From patchwork Mon Apr 15 12:58:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10900801 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D1886139A for ; Mon, 15 Apr 2019 13:01:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B25AF2893D for ; Mon, 15 Apr 2019 13:01:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A619228939; Mon, 15 Apr 2019 13:01:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5E6FF28958 for ; Mon, 15 Apr 2019 13:01:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BbkbflASnmDnFEzgJw3VID22So/NND8+VTw42Hrz5BQ=; b=AULP8tKPmLU+fi Lx3XL2R3lefeg60fTnOc7ir7PSc+lSC55GFNK1VaORHqzWc9wHPJiLPqTRLqHbv0HWo3p+KVQJ5RC AvI9JAbjiST8VwQ0ekJjcj06eArOtijCqGM9zJJbfJ7zj7nB88pZTzShESj4lmSWPXTbhND+MY1HK WDjbmZeQOhEsWIQRDRpZdvPjs1AGpqy6T/flxQATzKUeZb9G99N6VDqsEI7aGafoS3sfQvb08Ur60 FsEPxWApCc+GCqP9nooNDaHUVjgHE2fHI0a5xdfI6g0eDXZWPeY6Yy6jJ63GjnDBlZvh/Fslt7Sb7 IYLTjTgvA2r5Z2Z4mnQg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hG1EC-0001Q8-KO; Mon, 15 Apr 2019 13:00:52 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hG1DD-0007aU-Aw; Mon, 15 Apr 2019 13:00:21 +0000 X-UUID: e265da3e322b4f9881cdde762d0a7650-20190415 X-UUID: e265da3e322b4f9881cdde762d0a7650-20190415 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1506551423; Mon, 15 Apr 2019 04:58:52 -0800 Received: from MTKMBS01N1.mediatek.inc (172.21.101.68) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 15 Apr 2019 05:58:51 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 15 Apr 2019 20:58:36 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 15 Apr 2019 20:58:35 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v4 01/12] dt-binding: gce: remove thread-num property Date: Mon, 15 Apr 2019 20:58:22 +0800 Message-ID: <20190415125833.38704-2-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190415125833.38704-1-bibby.hsieh@mediatek.com> References: <20190415125833.38704-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190415_055951_998402_5EC71D10 X-CRM114-Status: UNSURE ( 8.74 ) X-CRM114-Notice: Please train this message. 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Signed-off-by: Bibby Hsieh Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/mailbox/mtk-gce.txt | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt index 7d72b21c9e94..cfe40b01d164 100644 --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt @@ -39,7 +39,6 @@ Example: interrupts = ; clocks = <&infracfg CLK_INFRA_GCE>; clock-names = "gce"; - thread-num = CMDQ_THR_MAX_COUNT; #mbox-cells = <3>; }; From patchwork Mon Apr 15 12:58:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10900831 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 93FB71390 for ; Mon, 15 Apr 2019 13:14:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 741162842B for ; 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Mon, 15 Apr 2019 04:58:52 -0800 Received: from MTKMBS01N1.mediatek.inc (172.21.101.68) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 15 Apr 2019 05:58:52 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 15 Apr 2019 20:58:36 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 15 Apr 2019 20:58:37 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v4 02/12] dt-binding: gce: add gce header file for mt8183 Date: Mon, 15 Apr 2019 20:58:23 +0800 Message-ID: <20190415125833.38704-3-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190415125833.38704-1-bibby.hsieh@mediatek.com> References: <20190415125833.38704-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190415_060025_855413_D2C42BFF X-CRM114-Status: GOOD ( 12.32 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , kendrick.hsu@mediatek.com, linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Frederic Chen , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add documentation for the mt8183 gce. Add gce header file defined the gce hardware event, subsys number and constant for mt8183. Signed-off-by: Bibby Hsieh Reviewed-by: Rob Herring --- .../devicetree/bindings/mailbox/mtk-gce.txt | 6 +- include/dt-bindings/gce/mt8183-gce.h | 177 ++++++++++++++++++ 2 files changed, 180 insertions(+), 3 deletions(-) create mode 100644 include/dt-bindings/gce/mt8183-gce.h diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt index cfe40b01d164..1f7f8f2a3f49 100644 --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt @@ -9,7 +9,7 @@ CMDQ driver uses mailbox framework for communication. Please refer to mailbox.txt for generic information about mailbox device-tree bindings. Required properties: -- compatible: Must be "mediatek,mt8173-gce" +- compatible: can be "mediatek,mt8173-gce" or "mediatek,mt8183-gce" - reg: Address range of the GCE unit - interrupts: The interrupt signal from the GCE block - clock: Clocks according to the common clock binding @@ -28,8 +28,8 @@ Required properties for a client device: - mediatek,gce-subsys: u32, specify the sub-system id which is corresponding to the register address. -Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'. Such as -sub-system ids, thread priority, event ids. +Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h' +or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids. Example: diff --git a/include/dt-bindings/gce/mt8183-gce.h b/include/dt-bindings/gce/mt8183-gce.h new file mode 100644 index 000000000000..aeb95154fac2 --- /dev/null +++ b/include/dt-bindings/gce/mt8183-gce.h @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Bibby Hsieh + * + */ + +#ifndef _DT_BINDINGS_GCE_MT8183_H +#define _DT_BINDINGS_GCE_MT8183_H + +#define CMDQ_NO_TIMEOUT 0xffffffff + +#define CMDQ_THR_MAX_COUNT 24 + +/* GCE HW thread priority */ +#define CMDQ_THR_PRIO_LOWEST 0 +#define CMDQ_THR_PRIO_HIGHEST 1 + +/* GCE SUBSYS */ +#define SUBSYS_1300XXXX 0 +#define SUBSYS_1400XXXX 1 +#define SUBSYS_1401XXXX 2 +#define SUBSYS_1402XXXX 3 +#define SUBSYS_1502XXXX 4 +#define SUBSYS_1880XXXX 5 +#define SUBSYS_1881XXXX 6 +#define SUBSYS_1882XXXX 7 +#define SUBSYS_1883XXXX 8 +#define SUBSYS_1884XXXX 9 +#define SUBSYS_1000XXXX 10 +#define SUBSYS_1001XXXX 11 +#define SUBSYS_1002XXXX 12 +#define SUBSYS_1003XXXX 13 +#define SUBSYS_1004XXXX 14 +#define SUBSYS_1005XXXX 15 +#define SUBSYS_1020XXXX 16 +#define SUBSYS_1028XXXX 17 +#define SUBSYS_1700XXXX 18 +#define SUBSYS_1701XXXX 19 +#define SUBSYS_1702XXXX 20 +#define SUBSYS_1703XXXX 21 +#define SUBSYS_1800XXXX 22 +#define SUBSYS_1801XXXX 23 +#define SUBSYS_1802XXXX 24 +#define SUBSYS_1804XXXX 25 +#define SUBSYS_1805XXXX 26 +#define SUBSYS_1808XXXX 27 +#define SUBSYS_180aXXXX 28 +#define SUBSYS_180bXXXX 29 + +#define CMDQ_EVENT_DISP_RDMA0_SOF 0 +#define CMDQ_EVENT_DISP_RDMA1_SOF 1 +#define CMDQ_EVENT_MDP_RDMA0_SOF 2 +#define CMDQ_EVENT_MDP_RSZ0_SOF 4 +#define CMDQ_EVENT_MDP_RSZ1_SOF 5 +#define CMDQ_EVENT_MDP_TDSHP_SOF 6 +#define CMDQ_EVENT_MDP_WROT0_SOF 7 +#define CMDQ_EVENT_MDP_WDMA0_SOF 8 +#define CMDQ_EVENT_DISP_OVL0_SOF 9 +#define CMDQ_EVENT_DISP_OVL0_2L_SOF 10 +#define CMDQ_EVENT_DISP_OVL1_2L_SOF 11 +#define CMDQ_EVENT_DISP_WDMA0_SOF 12 +#define CMDQ_EVENT_DISP_COLOR0_SOF 13 +#define CMDQ_EVENT_DISP_CCORR0_SOF 14 +#define CMDQ_EVENT_DISP_AAL0_SOF 15 +#define CMDQ_EVENT_DISP_GAMMA0_SOF 16 +#define CMDQ_EVENT_DISP_DITHER0_SOF 17 +#define CMDQ_EVENT_DISP_PWM0_SOF 18 +#define CMDQ_EVENT_DISP_DSI0_SOF 19 +#define CMDQ_EVENT_DISP_DPI0_SOF 20 +#define CMDQ_EVENT_DISP_RSZ_SOF 22 +#define CMDQ_EVENT_MDP_AAL_SOF 23 +#define CMDQ_EVENT_MDP_CCORR_SOF 24 +#define CMDQ_EVENT_DISP_DBI_SOF 25 +#define CMDQ_EVENT_DISP_RDMA0_EOF 26 +#define CMDQ_EVENT_DISP_RDMA1_EOF 27 +#define CMDQ_EVENT_MDP_RDMA0_EOF 28 +#define CMDQ_EVENT_MDP_RSZ0_EOF 30 +#define CMDQ_EVENT_MDP_RSZ1_EOF 31 +#define CMDQ_EVENT_MDP_TDSHP_EOF 32 +#define CMDQ_EVENT_MDP_WROT0_EOF 33 +#define CMDQ_EVENT_MDP_WDMA0_EOF 34 +#define CMDQ_EVENT_DISP_OVL0_EOF 35 +#define CMDQ_EVENT_DISP_OVL0_2L_EOF 36 +#define CMDQ_EVENT_DISP_OVL1_2L_EOF 37 +#define CMDQ_EVENT_DISP_WDMA0_EOF 38 +#define CMDQ_EVENT_DISP_COLOR0_EOF 39 +#define CMDQ_EVENT_DISP_CCORR0_EOF 40 +#define CMDQ_EVENT_DISP_AAL0_EOF 41 +#define CMDQ_EVENT_DISP_GAMMA0_EOF 42 +#define CMDQ_EVENT_DISP_DITHER0_EOF 43 +#define CMDQ_EVENT_DSI0_EOF 44 +#define CMDQ_EVENT_DPI0_EOF 45 +#define CMDQ_EVENT_DISP_RSZ_EOF 47 +#define CMDQ_EVENT_MDP_AAL_EOF 48 +#define CMDQ_EVENT_MDP_CCORR_EOF 49 +#define CMDQ_EVENT_DBI_EOF 50 +#define CMDQ_EVENT_MUTEX_STREAM_DONE0 130 +#define CMDQ_EVENT_MUTEX_STREAM_DONE1 131 +#define CMDQ_EVENT_MUTEX_STREAM_DONE2 132 +#define CMDQ_EVENT_MUTEX_STREAM_DONE3 133 +#define CMDQ_EVENT_MUTEX_STREAM_DONE4 134 +#define CMDQ_EVENT_MUTEX_STREAM_DONE5 135 +#define CMDQ_EVENT_MUTEX_STREAM_DONE6 136 +#define CMDQ_EVENT_MUTEX_STREAM_DONE7 137 +#define CMDQ_EVENT_MUTEX_STREAM_DONE8 138 +#define CMDQ_EVENT_MUTEX_STREAM_DONE9 139 +#define CMDQ_EVENT_MUTEX_STREAM_DONE10 140 +#define CMDQ_EVENT_MUTEX_STREAM_DONE11 141 +#define CMDQ_EVENT_DISP_RDMA0_BUF_UNDERRUN_EVEN 142 +#define CMDQ_EVENT_DISP_RDMA1_BUF_UNDERRUN_EVEN 143 +#define CMDQ_EVENT_DSI0_TE_EVENT 144 +#define CMDQ_EVENT_DSI0_IRQ_EVENT 145 +#define CMDQ_EVENT_DSI0_DONE_EVENT 146 +#define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE 150 +#define CMDQ_EVENT_MDP_WDMA_SW_RST_DONE 151 +#define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE 152 +#define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE 154 +#define CMDQ_EVENT_DISP_OVL0_FRAME_RST_DONE_PULE 155 +#define CMDQ_EVENT_DISP_OVL0_2L_FRAME_RST_DONE_ULSE 156 +#define CMDQ_EVENT_DISP_OVL1_2L_FRAME_RST_DONE_ULSE 157 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_0 257 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_1 258 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_2 259 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_3 260 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_4 261 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_5 262 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_6 263 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_7 264 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_8 265 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_9 266 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_10 267 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_11 268 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_12 269 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_13 270 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_14 271 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_15 272 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_16 273 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_17 274 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_18 275 +#define CMDQ_EVENT_AMD_FRAME_DONE 276 +#define CMDQ_EVENT_DVE_DONE 277 +#define CMDQ_EVENT_WMFE_DONE 278 +#define CMDQ_EVENT_RSC_DONE 279 +#define CMDQ_EVENT_MFB_DONE 280 +#define CMDQ_EVENT_WPE_A_DONE 281 +#define CMDQ_EVENT_SPE_B_DONE 282 +#define CMDQ_EVENT_OCC_DONE 283 +#define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 289 +#define CMDQ_EVENT_JPG_ENC_CMDQ_DONE 290 +#define CMDQ_EVENT_JPG_DEC_CMDQ_DONE 291 +#define CMDQ_EVENT_VENC_CMDQ_MB_DONE 292 +#define CMDQ_EVENT_VENC_CMDQ_128BYTE_DONE 293 +#define CMDQ_EVENT_ISP_FRAME_DONE_A 321 +#define CMDQ_EVENT_ISP_FRAME_DONE_B 322 +#define CMDQ_EVENT_CAMSV0_PASS1_DONE 323 +#define CMDQ_EVENT_CAMSV1_PASS1_DONE 324 +#define CMDQ_EVENT_CAMSV2_PASS1_DONE 325 +#define CMDQ_EVENT_TSF_DONE 326 +#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 327 +#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 328 +#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 329 +#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 330 +#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 331 +#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 332 +#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 333 +#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 334 +#define CMDQ_EVENT_IPU_CORE0_DONE0 353 +#define CMDQ_EVENT_IPU_CORE0_DONE1 354 +#define CMDQ_EVENT_IPU_CORE0_DONE2 355 +#define CMDQ_EVENT_IPU_CORE0_DONE3 356 +#define CMDQ_EVENT_IPU_CORE1_DONE0 385 +#define CMDQ_EVENT_IPU_CORE1_DONE1 386 +#define CMDQ_EVENT_IPU_CORE1_DONE2 387 +#define CMDQ_EVENT_IPU_CORE1_DONE3 388 + +#endif From patchwork Mon Apr 15 12:58:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10900777 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4A908922 for ; Mon, 15 Apr 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esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hG1C8-0006HV-E6; Mon, 15 Apr 2019 12:58:46 +0000 X-UUID: 9e5443cdfd8e462e8b853309fcd13fa2-20190415 X-UUID: 9e5443cdfd8e462e8b853309fcd13fa2-20190415 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 631558064; Mon, 15 Apr 2019 04:58:40 -0800 Received: from MTKMBS02N1.mediatek.inc (172.21.101.77) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 15 Apr 2019 05:58:39 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 15 Apr 2019 20:58:37 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 15 Apr 2019 20:58:37 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v4 03/12] dt-binding: gce: add binding for gce event property Date: Mon, 15 Apr 2019 20:58:24 +0800 Message-ID: <20190415125833.38704-4-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190415125833.38704-1-bibby.hsieh@mediatek.com> References: <20190415125833.38704-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190415_055844_474263_233EEA0E X-CRM114-Status: GOOD ( 10.92 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , kendrick.hsu@mediatek.com, linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Frederic Chen , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Client hardware would send event to GCE hardware, so #event-cells, mediatek,gce-event-names, mediatek,gce-events. present the event. Signed-off-by: Bibby Hsieh --- .../devicetree/bindings/mailbox/mtk-gce.txt | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt index 1f7f8f2a3f49..2f175d6b296d 100644 --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt @@ -21,12 +21,21 @@ Required properties: priority: Priority of GCE thread. atomic_exec: GCE processing continuous packets of commands in atomic way. +- #event-cells: Should be 1. + <&phandle event_number> + phandle: Label name of a gce node. + event_number: the event number defined in 'dt-bindings/gce/mt8173-gce.h' + or 'dt-binding/gce/mt8183-gce.h'. Required properties for a client device: - mboxes: Client use mailbox to communicate with GCE, it should have this property and list of phandle, mailbox specifiers. - mediatek,gce-subsys: u32, specify the sub-system id which is corresponding to the register address. +Optional propertier for a client device: +- mediatek,gce-event-names: the event name can be defined by user. +- mediatek,gce-events: u32, the event number defined in + 'dt-bindings/gce/mt8173-gce.h' or 'dt-binding/gce/mt8183-gce.h'. Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h' or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids. @@ -40,6 +49,7 @@ Example: clocks = <&infracfg CLK_INFRA_GCE>; clock-names = "gce"; #mbox-cells = <3>; + #event-cells = <1>; }; Example for a client device: @@ -49,8 +59,9 @@ Example for a client device: mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>, <&gce 1 CMDQ_THR_PRIO_LOWEST 1>; mediatek,gce-subsys = ; - mutex-event-eof = ; - + mediatek,gce-event-names = "rdma0_sof", + "rsz0_sof"; + mediatek,gce-events = <&gce CMDQ_EVENT_MDP_RDMA0_SOF>, + <&gce CMDQ_EVENT_MDP_RSZ0_SOF>; ... }; From patchwork Mon Apr 15 12:58:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10900781 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 26D42161F for ; Mon, 15 Apr 2019 12:59:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 07DFD28899 for ; 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Mon, 15 Apr 2019 04:58:39 -0800 Received: from MTKMBS01N2.mediatek.inc (172.21.101.79) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 15 Apr 2019 05:58:38 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 15 Apr 2019 20:58:37 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 15 Apr 2019 20:58:37 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v4 04/12] dt-binding: gce: add binding for gce subsys property Date: Mon, 15 Apr 2019 20:58:25 +0800 Message-ID: <20190415125833.38704-5-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190415125833.38704-1-bibby.hsieh@mediatek.com> References: <20190415125833.38704-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: E274F94B400CB943FFAD893F16360ABA0A9DEA9CB464F4414A5EF11BEDA06E542000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190415_055846_252428_9CA4D1B8 X-CRM114-Status: GOOD ( 10.97 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , kendrick.hsu@mediatek.com, linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Frederic Chen , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP cmdq driver provide a function that get the relationship of sub system number from device node for client. add specification for #subsys-cells, mediatek,gce-subsys. Signed-off-by: Bibby Hsieh --- .../devicetree/bindings/mailbox/mtk-gce.txt | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt index 2f175d6b296d..755b30fd6041 100644 --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt @@ -26,13 +26,20 @@ Required properties: phandle: Label name of a gce node. event_number: the event number defined in 'dt-bindings/gce/mt8173-gce.h' or 'dt-binding/gce/mt8183-gce.h'. +- #subsys-cells: Should be 3. + <&phandle subsys_number start_offset size> + phandle: Label name of a gce node. + subsys_number: specify the sub-system id which is corresponding + to the register address. + start_offset: the start offset of register address that GCE can access. + size: the total size of register address that GCE can access. Required properties for a client device: - mboxes: Client use mailbox to communicate with GCE, it should have this property and list of phandle, mailbox specifiers. -- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding - to the register address. Optional propertier for a client device: +- mediatek,gce-client-reg: u32, specify the sub-system id which is corresponding + to the register address. - mediatek,gce-event-names: the event name can be defined by user. - mediatek,gce-events: u32, the event number defined in 'dt-bindings/gce/mt8173-gce.h' or 'dt-binding/gce/mt8183-gce.h'. @@ -50,6 +57,7 @@ Example: clock-names = "gce"; #mbox-cells = <3>; #event-cells = <1>; + #subsys-cells = <3>; }; Example for a client device: @@ -58,7 +66,8 @@ Example for a client device: compatible = "mediatek,mt8173-mmsys"; mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>, <&gce 1 CMDQ_THR_PRIO_LOWEST 1>; - mediatek,gce-subsys = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>, + <&gce SUBSYS_1401XXXX 0x2000 0x100>; mediatek,gce-event-names = "rdma0_sof", "rsz0_sof"; mediatek,gce-events = <&gce CMDQ_EVENT_MDP_RDMA0_SOF>, From patchwork Mon Apr 15 12:58:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10900857 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 91CD914DB for ; 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Mon, 15 Apr 2019 13:00:04 +0000 X-UUID: 5a10cc65f66c4eae9ebbe19482a28252-20190415 X-UUID: 5a10cc65f66c4eae9ebbe19482a28252-20190415 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 2036898321; Mon, 15 Apr 2019 04:58:54 -0800 Received: from MTKMBS01N1.mediatek.inc (172.21.101.68) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 15 Apr 2019 05:58:52 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 15 Apr 2019 20:58:37 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 15 Apr 2019 20:58:37 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v4 05/12] soc: mediatek: cmdq: move the CMDQ_IRQ_MASK into cmdq driver data Date: Mon, 15 Apr 2019 20:58:26 +0800 Message-ID: <20190415125833.38704-6-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190415125833.38704-1-bibby.hsieh@mediatek.com> References: <20190415125833.38704-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190415_090002_944685_1EA6ED3A X-CRM114-Status: GOOD ( 13.09 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , kendrick.hsu@mediatek.com, linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Frederic Chen , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The interrupt mask and thread number has positive correlation, so we move the CMDQ_IRQ_MASK into cmdq driver data and calculate it by thread number. Signed-off-by: Bibby Hsieh Reviewed-by: CK Hu --- drivers/mailbox/mtk-cmdq-mailbox.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index 22811784dc7d..87617dc7504d 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -17,7 +17,6 @@ #include #define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT) -#define CMDQ_IRQ_MASK 0xffff #define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE) #define CMDQ_CURR_IRQ_STATUS 0x10 @@ -71,6 +70,7 @@ struct cmdq { void __iomem *base; u32 irq; u32 thread_nr; + u32 irq_mask; struct cmdq_thread *thread; struct clk *clock; bool suspended; @@ -284,11 +284,11 @@ static irqreturn_t cmdq_irq_handler(int irq, void *dev) unsigned long irq_status, flags = 0L; int bit; - irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & CMDQ_IRQ_MASK; - if (!(irq_status ^ CMDQ_IRQ_MASK)) + irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask; + if (!(irq_status ^ cmdq->irq_mask)) return IRQ_NONE; - for_each_clear_bit(bit, &irq_status, fls(CMDQ_IRQ_MASK)) { + for_each_clear_bit(bit, &irq_status, cmdq->thread_nr) { struct cmdq_thread *thread = &cmdq->thread[bit]; spin_lock_irqsave(&thread->chan->lock, flags); @@ -472,6 +472,9 @@ static int cmdq_probe(struct platform_device *pdev) dev_err(dev, "failed to get irq\n"); return -EINVAL; } + + cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev); + cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0); err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, "mtk_cmdq", cmdq); if (err < 0) { @@ -488,7 +491,6 @@ static int cmdq_probe(struct platform_device *pdev) return PTR_ERR(cmdq->clock); } - cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev); cmdq->mbox.dev = dev; cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr, sizeof(*cmdq->mbox.chans), GFP_KERNEL); From patchwork Mon Apr 15 12:58:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10900849 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CB19E14DB for ; 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Mon, 15 Apr 2019 13:00:04 +0000 X-UUID: a27ef570d68b480da5fec30afc1f2526-20190415 X-UUID: a27ef570d68b480da5fec30afc1f2526-20190415 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 465758842; Mon, 15 Apr 2019 04:58:54 -0800 Received: from MTKMBS01N1.mediatek.inc (172.21.101.68) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 15 Apr 2019 05:58:53 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 15 Apr 2019 20:58:37 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 15 Apr 2019 20:58:37 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v4 06/12] soc: mediatek: cmdq: support mt8183 gce function Date: Mon, 15 Apr 2019 20:58:27 +0800 Message-ID: <20190415125833.38704-7-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190415125833.38704-1-bibby.hsieh@mediatek.com> References: <20190415125833.38704-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190415_090003_872950_D9B4E436 X-CRM114-Status: GOOD ( 11.39 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , kendrick.hsu@mediatek.com, linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Frederic Chen , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP add mt8183 compatible name for supporting gce function Signed-off-by: Bibby Hsieh Reviewed-by: CK Hu --- drivers/mailbox/mtk-cmdq-mailbox.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index 87617dc7504d..6db1e2dd2dea 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -538,6 +538,7 @@ static const struct dev_pm_ops cmdq_pm_ops = { static const struct of_device_id cmdq_of_ids[] = { {.compatible = "mediatek,mt8173-gce", .data = (void *)16}, + {.compatible = "mediatek,mt8183-gce", .data = (void *)24}, {} }; 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Mon, 15 Apr 2019 20:58:38 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v4 07/12] soc: mediatek: cmdq: clear the event in cmdq initial flow Date: Mon, 15 Apr 2019 20:58:28 +0800 Message-ID: <20190415125833.38704-8-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190415125833.38704-1-bibby.hsieh@mediatek.com> References: <20190415125833.38704-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: E39EB341F9CD88EE65EB3D7D02B45E4225B9BD1C27D86467322F13BDB356BFB12000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190415_055849_198856_2F90ACD0 X-CRM114-Status: GOOD ( 10.29 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , kendrick.hsu@mediatek.com, linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Frederic Chen , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP GCE hardware stored event information in own internal sysram, if the initial value in those sysram is not zero value it will cause a situation that gce can wait the event immediately after client ask gce to wait event but not really trigger the corresponding hardware. In order to make sure that the wait event function is exactly correct, we need to clear the sysram value in cmdq initial flow. Fixes: 623a6143a845 ("mailbox: mediatek: Add Mediatek CMDQ driver") Signed-off-by: Bibby Hsieh Reviewed-by: CK Hu --- drivers/mailbox/mtk-cmdq-mailbox.c | 5 +++++ include/linux/mailbox/mtk-cmdq-mailbox.h | 2 ++ include/linux/soc/mediatek/mtk-cmdq.h | 3 --- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index 6db1e2dd2dea..4e744cf2c3fb 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -33,6 +33,7 @@ #define CMDQ_THR_END_ADDR 0x24 #define CMDQ_THR_WAIT_TOKEN 0x30 #define CMDQ_THR_PRIORITY 0x40 +#define CMDQ_SYNC_TOKEN_UPDATE 0x68 #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 #define CMDQ_THR_ENABLED 0x1 @@ -103,8 +104,12 @@ static void cmdq_thread_resume(struct cmdq_thread *thread) static void cmdq_init(struct cmdq *cmdq) { + int i; + WARN_ON(clk_enable(cmdq->clock) < 0); writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); + for (i = 0; i <= CMDQ_MAX_EVENT; i++) + writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); clk_disable(cmdq->clock); } diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h index ccb73422c2fa..911475da7a53 100644 --- a/include/linux/mailbox/mtk-cmdq-mailbox.h +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h @@ -19,6 +19,8 @@ #define CMDQ_WFE_UPDATE BIT(31) #define CMDQ_WFE_WAIT BIT(15) #define CMDQ_WFE_WAIT_VALUE 0x1 +/** cmdq event maximum */ +#define CMDQ_MAX_EVENT 0x3ff /* * CMDQ_CODE_MASK: diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 54ade13a9b15..4e8899972db4 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -13,9 +13,6 @@ #define CMDQ_NO_TIMEOUT 0xffffffffu -/** cmdq event maximum */ -#define CMDQ_MAX_EVENT 0x3ff - struct cmdq_pkt; struct cmdq_client { From patchwork Mon Apr 15 12:58:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10900793 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CB910139A for ; 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Mon, 15 Apr 2019 12:59:00 +0000 X-UUID: ebc09a406d8245529ff366c1d3597288-20190415 X-UUID: ebc09a406d8245529ff366c1d3597288-20190415 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1565778561; Mon, 15 Apr 2019 04:58:42 -0800 Received: from MTKMBS01N2.mediatek.inc (172.21.101.79) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 15 Apr 2019 05:58:41 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 15 Apr 2019 20:58:37 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 15 Apr 2019 20:58:38 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v4 08/12] soc: mediatek: cmdq: add packet encoder function Date: Mon, 15 Apr 2019 20:58:29 +0800 Message-ID: <20190415125833.38704-9-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190415125833.38704-1-bibby.hsieh@mediatek.com> References: <20190415125833.38704-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 0F82B3937C00B849BD51EC249A7FD755991FEB51B4669E767AF4D6AC580E698C2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190415_055852_393252_CD6061BF X-CRM114-Status: GOOD ( 14.26 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , kendrick.hsu@mediatek.com, linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Frederic Chen , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Implement a function can encode the GCE instructions Signed-off-by: Bibby Hsieh --- drivers/soc/mediatek/mtk-cmdq-helper.c | 125 ++++++++++++++++------- include/linux/mailbox/mtk-cmdq-mailbox.h | 2 + include/linux/soc/mediatek/mtk-cmdq.h | 14 +-- 3 files changed, 99 insertions(+), 42 deletions(-) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index ff9fef5a032b..d3873ab21db3 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -9,11 +9,43 @@ #include #include -#define CMDQ_ARG_A_WRITE_MASK 0xffff +#define CMDQ_GET_ARG_B(arg) (((arg) & GENMASK(31, 16)) >> 16) +#define CMDQ_GET_ARG_C(arg) ((arg) & GENMASK(15, 0)) #define CMDQ_WRITE_ENABLE_MASK BIT(0) #define CMDQ_EOC_IRQ_EN BIT(0) #define CMDQ_EOC_CMD ((u64)((CMDQ_CODE_EOC << CMDQ_OP_CODE_SHIFT)) \ << 32 | CMDQ_EOC_IRQ_EN) +#define CMDQ_IMMEDIATE_VALUE 0 +#define CMDQ_REG_TYPE 1 + +struct cmdq_instruction { + s16 arg_c:16; + s16 arg_b:16; + s16 arg_a:16; + u8 s_op:5; + u8 arg_c_type:1; + u8 arg_b_type:1; + u8 arg_a_type:1; + u8 op:8; +}; + +static void cmdq_pkt_instr_encoder(struct cmdq_pkt *pkt, s16 arg_c, s16 arg_b, + s16 arg_a, u8 s_op, u8 arg_c_type, + u8 arg_b_type, u8 arg_a_type, u8 op) +{ + struct cmdq_instruction *cmdq_inst; + + cmdq_inst = pkt->va_base + pkt->cmd_buf_size; + cmdq_inst->op = op; + cmdq_inst->arg_a_type = arg_a_type; + cmdq_inst->arg_b_type = arg_b_type; + cmdq_inst->arg_c_type = arg_c_type; + cmdq_inst->s_op = s_op; + cmdq_inst->arg_a = arg_a; + cmdq_inst->arg_b = arg_b; + cmdq_inst->arg_c = arg_c; + pkt->cmd_buf_size += CMDQ_INST_SIZE; +} static void cmdq_client_timeout(struct timer_list *t) { @@ -110,10 +142,11 @@ void cmdq_pkt_destroy(struct cmdq_pkt *pkt) } EXPORT_SYMBOL(cmdq_pkt_destroy); -static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code, - u32 arg_a, u32 arg_b) +static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, s16 arg_c, s16 arg_b, + s16 arg_a, u8 s_op, u8 arg_c_type, + u8 arg_b_type, u8 arg_a_type, + enum cmdq_code code) { - u64 *cmd_ptr; if (unlikely(pkt->cmd_buf_size + CMDQ_INST_SIZE > pkt->buf_size)) { /* @@ -129,65 +162,72 @@ static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code, __func__, (u32)pkt->buf_size); return -ENOMEM; } - cmd_ptr = pkt->va_base + pkt->cmd_buf_size; - (*cmd_ptr) = (u64)((code << CMDQ_OP_CODE_SHIFT) | arg_a) << 32 | arg_b; - pkt->cmd_buf_size += CMDQ_INST_SIZE; + cmdq_pkt_instr_encoder(pkt, arg_c, arg_b, arg_a, s_op, arg_c_type, + arg_b_type, arg_a_type, code); return 0; } -int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value, u32 subsys, u32 offset) +int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value) { - u32 arg_a = (offset & CMDQ_ARG_A_WRITE_MASK) | - (subsys << CMDQ_SUBSYS_SHIFT); - - return cmdq_pkt_append_command(pkt, CMDQ_CODE_WRITE, arg_a, value); + return cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(value), + CMDQ_GET_ARG_B(value), offset, subsys, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, CMDQ_CODE_WRITE); } EXPORT_SYMBOL(cmdq_pkt_write); -int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value, - u32 subsys, u32 offset, u32 mask) +int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys, u16 offset, + u32 value, u32 mask) { u32 offset_mask = offset; int err = 0; if (mask != 0xffffffff) { - err = cmdq_pkt_append_command(pkt, CMDQ_CODE_MASK, 0, ~mask); + err = cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(~mask), + CMDQ_GET_ARG_B(~mask), + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_CODE_MASK); offset_mask |= CMDQ_WRITE_ENABLE_MASK; } - err |= cmdq_pkt_write(pkt, value, subsys, offset_mask); + err |= cmdq_pkt_write(pkt, subsys, offset_mask, value); return err; } EXPORT_SYMBOL(cmdq_pkt_write_mask); -int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event) +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event) { - u32 arg_b; - if (event >= CMDQ_MAX_EVENT) return -EINVAL; - /* - * WFE arg_b - * bit 0-11: wait value - * bit 15: 1 - wait, 0 - no wait - * bit 16-27: update value - * bit 31: 1 - update, 0 - no update - */ - arg_b = CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE; - - return cmdq_pkt_append_command(pkt, CMDQ_CODE_WFE, event, arg_b); + return cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(CMDQ_WFE_OPTION), + CMDQ_GET_ARG_B(CMDQ_WFE_OPTION), event, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_CODE_WFE); } EXPORT_SYMBOL(cmdq_pkt_wfe); -int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u32 event) +int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event) { if (event >= CMDQ_MAX_EVENT) return -EINVAL; - return cmdq_pkt_append_command(pkt, CMDQ_CODE_WFE, event, - CMDQ_WFE_UPDATE); + return cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(CMDQ_WFE_UPDATE), + CMDQ_GET_ARG_B(CMDQ_WFE_UPDATE), event, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_CODE_WFE); } EXPORT_SYMBOL(cmdq_pkt_clear_event); @@ -196,10 +236,25 @@ static int cmdq_pkt_finalize(struct cmdq_pkt *pkt) int err; /* insert EOC and generate IRQ for each command iteration */ - err = cmdq_pkt_append_command(pkt, CMDQ_CODE_EOC, 0, CMDQ_EOC_IRQ_EN); - + err = cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(CMDQ_EOC_IRQ_EN), + CMDQ_GET_ARG_B(CMDQ_EOC_IRQ_EN), + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_CODE_EOC); + if (err < 0) + return err; /* JUMP to end */ - err |= cmdq_pkt_append_command(pkt, CMDQ_CODE_JUMP, 0, CMDQ_JUMP_PASS); + err = cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(CMDQ_JUMP_PASS), + CMDQ_GET_ARG_B(CMDQ_JUMP_PASS), + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_CODE_JUMP); return err; } diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h index 911475da7a53..f21801d32a3a 100644 --- a/include/linux/mailbox/mtk-cmdq-mailbox.h +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h @@ -19,6 +19,8 @@ #define CMDQ_WFE_UPDATE BIT(31) #define CMDQ_WFE_WAIT BIT(15) #define CMDQ_WFE_WAIT_VALUE 0x1 +#define CMDQ_WFE_OPTION (CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | \ + CMDQ_WFE_WAIT_VALUE) /** cmdq event maximum */ #define CMDQ_MAX_EVENT 0x3ff diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 4e8899972db4..52f69c8db8de 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -60,26 +60,26 @@ void cmdq_pkt_destroy(struct cmdq_pkt *pkt); /** * cmdq_pkt_write() - append write command to the CMDQ packet * @pkt: the CMDQ packet - * @value: the specified target register value * @subsys: the CMDQ sub system code * @offset: register offset from CMDQ sub system + * @value: the specified target register value * * Return: 0 for success; else the error code is returned */ -int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value, u32 subsys, u32 offset); +int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value); /** * cmdq_pkt_write_mask() - append write command with mask to the CMDQ packet * @pkt: the CMDQ packet - * @value: the specified target register value * @subsys: the CMDQ sub system code * @offset: register offset from CMDQ sub system + * @value: the specified target register value * @mask: the specified target register mask * * Return: 0 for success; else the error code is returned */ -int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value, - u32 subsys, u32 offset, u32 mask); +int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys, u16 offset, + u32 value, u32 mask); /** * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet @@ -88,7 +88,7 @@ int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value, * * Return: 0 for success; else the error code is returned */ -int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event); +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event); /** * cmdq_pkt_clear_event() - append clear event command to the CMDQ packet @@ -97,7 +97,7 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event); * * Return: 0 for success; else the error code is returned */ -int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u32 event); +int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event); /** * cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ From patchwork Mon Apr 15 12:58:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10900811 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0CAC4139A for ; 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Mon, 15 Apr 2019 13:00:26 +0000 X-UUID: 60e620c4fed0439a93af6aa3c4d7ae28-20190415 X-UUID: 60e620c4fed0439a93af6aa3c4d7ae28-20190415 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 532278854; Mon, 15 Apr 2019 04:58:54 -0800 Received: from MTKMBS02N2.mediatek.inc (172.21.101.101) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 15 Apr 2019 05:58:53 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 15 Apr 2019 20:58:38 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 15 Apr 2019 20:58:38 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v4 09/12] soc: mediatek: cmdq: add polling function Date: Mon, 15 Apr 2019 20:58:30 +0800 Message-ID: <20190415125833.38704-10-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190415125833.38704-1-bibby.hsieh@mediatek.com> References: <20190415125833.38704-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 5D93F1FD5E2961F2281EE69481537788D33C48AD105743452147FA19D363ED0B2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190415_060021_411416_762DB41B X-CRM114-Status: GOOD ( 12.21 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , kendrick.hsu@mediatek.com, linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Frederic Chen , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP add polling function in cmdq helper functions Signed-off-by: Bibby Hsieh --- drivers/soc/mediatek/mtk-cmdq-helper.c | 30 ++++++++++++++++++++++++ include/linux/mailbox/mtk-cmdq-mailbox.h | 1 + include/linux/soc/mediatek/mtk-cmdq.h | 15 ++++++++++++ 3 files changed, 46 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index d3873ab21db3..80856b8c2385 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -231,6 +231,36 @@ int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event) } EXPORT_SYMBOL(cmdq_pkt_clear_event); +int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys, + u16 offset, u32 value, u32 mask) +{ + int err; + + if (mask != 0xffffffff) { + err = cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(~mask), + CMDQ_GET_ARG_B(~mask), + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_CODE_MASK); + + if (err != 0) + return err; + } + offset = offset | 0x1; + + return cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(value), + CMDQ_GET_ARG_B(value), + offset, subsys, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_IMMEDIATE_VALUE, + CMDQ_CODE_POLL); +} +EXPORT_SYMBOL(cmdq_pkt_poll); + static int cmdq_pkt_finalize(struct cmdq_pkt *pkt) { int err; diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h index f21801d32a3a..1dfd5ed5c8c5 100644 --- a/include/linux/mailbox/mtk-cmdq-mailbox.h +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h @@ -46,6 +46,7 @@ enum cmdq_code { CMDQ_CODE_MASK = 0x02, CMDQ_CODE_WRITE = 0x04, + CMDQ_CODE_POLL = 0x08, CMDQ_CODE_JUMP = 0x10, CMDQ_CODE_WFE = 0x20, CMDQ_CODE_EOC = 0x40, diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 52f69c8db8de..0651a0bffa54 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -99,6 +99,21 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event); */ int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event); +/** + * cmdq_pkt_poll() - Append polling command to the CMDQ packet, ask GCE to + * execute an instruction that wait for a specified hardware + * register to check for the value. All GCE hardware + * threads will be blocked by this instruction. + * @pkt: the CMDQ packet + * @subsys: the CMDQ sub system code + * @offset: register offset from CMDQ sub system + * @value: the specified target register value + * @mask: the specified target register mask + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys, + u16 offset, u32 value, u32 mask); /** * cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ * packet and call back at the end of done packet From patchwork Mon Apr 15 12:58:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10900797 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E33C9139A for ; Mon, 15 Apr 2019 13:00:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C10B828948 for ; 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Mon, 15 Apr 2019 04:58:54 -0800 Received: from mtkmbs08n1.mediatek.inc (172.21.101.55) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 15 Apr 2019 05:58:52 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 15 Apr 2019 20:58:38 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 15 Apr 2019 20:58:38 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v4 10/12] soc: mediatek: cmdq: add cmdq_dev_get_subsys function Date: Mon, 15 Apr 2019 20:58:31 +0800 Message-ID: <20190415125833.38704-11-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190415125833.38704-1-bibby.hsieh@mediatek.com> References: <20190415125833.38704-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190415_055951_154810_65E1BADC X-CRM114-Status: GOOD ( 10.45 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , kendrick.hsu@mediatek.com, linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Frederic Chen , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP GCE cannot know the register base address, this function can help cmdq client to get the relationship of subsys and register base address. Signed-off-by: Bibby Hsieh --- drivers/soc/mediatek/mtk-cmdq-helper.c | 25 +++++++++++++++++++++++++ include/linux/soc/mediatek/mtk-cmdq.h | 18 ++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index 80856b8c2385..d86f800d40dc 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -47,6 +47,31 @@ static void cmdq_pkt_instr_encoder(struct cmdq_pkt *pkt, s16 arg_c, s16 arg_b, pkt->cmd_buf_size += CMDQ_INST_SIZE; } +struct cmdq_subsys *cmdq_dev_get_subsys(struct device *dev, int idx) +{ + struct cmdq_subsys *subsys; + struct of_phandle_args spec; + + subsys = devm_kzalloc(dev, sizeof(*subsys), GFP_KERNEL); + if (!subsys) + return NULL; + + if (of_parse_phandle_with_args(dev->of_node, "mediatek,gce-client-reg", + "#subsys-cells", idx, &spec)) { + dev_err(dev, "can't parse gce-client-reg property"); + + return (struct cmdq_subsys *)-ENODEV; + } + + subsys->id = spec.args[0]; + subsys->offset = spec.args[1]; + subsys->size = spec.args[2]; + of_node_put(spec.np); + + return subsys; +} +EXPORT_SYMBOL(cmdq_dev_get_subsys); + static void cmdq_client_timeout(struct timer_list *t) { struct cmdq_client *client = from_timer(client, t, timer); diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 0651a0bffa54..574006c5cd76 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -15,6 +15,12 @@ struct cmdq_pkt; +struct cmdq_subsys { + u8 id; + u16 offset; + u16 size; +}; + struct cmdq_client { spinlock_t lock; u32 pkt_cnt; @@ -142,4 +148,16 @@ int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb, */ int cmdq_pkt_flush(struct cmdq_pkt *pkt); +/** + * cmdq_dev_get_subsys() - parse sub system from the device node of CMDQ client + * @dev: device of CMDQ mailbox client + * @idx: the index of desired subsys + * + * Return: CMDQ subsys pointer + * + * Help CMDQ client pasing the sub system number + * from the device node of CMDQ client. + */ +struct cmdq_subsys *cmdq_dev_get_subsys(struct device *dev, int idx); + #endif /* __MTK_CMDQ_H__ */ From patchwork Mon Apr 15 12:58:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10900803 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6A55F922 for ; Mon, 15 Apr 2019 13:01:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4D83A28913 for ; Mon, 15 Apr 2019 13:01:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4166428956; Mon, 15 Apr 2019 13:01:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D3F4528913 for ; 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Mon, 15 Apr 2019 20:58:38 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v4 11/12] soc: mediatek: cmdq: add cmdq_dev_get_event function Date: Mon, 15 Apr 2019 20:58:32 +0800 Message-ID: <20190415125833.38704-12-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190415125833.38704-1-bibby.hsieh@mediatek.com> References: <20190415125833.38704-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190415_060019_131139_EBE2A541 X-CRM114-Status: GOOD ( 10.03 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , kendrick.hsu@mediatek.com, linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Frederic Chen , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP When client ask gce to clear or wait for event, client need to pass event number to the API. We suggest client store the event information in device node, so we provide an API for client parse the event property. Signed-off-by: Bibby Hsieh --- drivers/soc/mediatek/mtk-cmdq-helper.c | 32 ++++++++++++++++++++++++++ include/linux/soc/mediatek/mtk-cmdq.h | 12 ++++++++++ 2 files changed, 44 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index d86f800d40dc..bc8e10121f9b 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -72,6 +72,38 @@ struct cmdq_subsys *cmdq_dev_get_subsys(struct device *dev, int idx) } EXPORT_SYMBOL(cmdq_dev_get_subsys); +s32 cmdq_dev_get_event(struct device *dev, const char *name) +{ + s32 index = 0; + struct of_phandle_args spec; + s32 result; + + if (!dev) + return -EINVAL; + + index = of_property_match_string(dev->of_node, + "mediatek,gce-event-names", name); + if (index < 0) { + dev_err(dev, "no gce-event-names property or no such event:%s", + name); + + return index; + } + + if (of_parse_phandle_with_args(dev->of_node, "mediatek,gce-events", + "#event-cells", index, &spec)) { + dev_err(dev, "can't parse gce-events property"); + + return -ENODEV; + } + + result = spec.args[0]; + of_node_put(spec.np); + + return result; +} +EXPORT_SYMBOL(cmdq_dev_get_event); + static void cmdq_client_timeout(struct timer_list *t) { struct cmdq_client *client = from_timer(client, t, timer); diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 574006c5cd76..15884354af20 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -160,4 +160,16 @@ int cmdq_pkt_flush(struct cmdq_pkt *pkt); */ struct cmdq_subsys *cmdq_dev_get_subsys(struct device *dev, int idx); +/** + * cmdq_dev_get_event() - parse event from the device node of CMDQ client + * @dev: device of CMDQ mailbox client + * @name: the name of desired event + * + * Return: CMDQ event number + * + * Help CMDQ client pasing the event number + * from the device node of CMDQ client. + */ +s32 cmdq_dev_get_event(struct device *dev, const char *name); + #endif /* __MTK_CMDQ_H__ */ From patchwork Mon Apr 15 12:58:33 2019 Content-Type: text/plain; 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Mon, 15 Apr 2019 20:58:38 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v4 12/12] arm64: dts: add gce node for mt8183 Date: Mon, 15 Apr 2019 20:58:33 +0800 Message-ID: <20190415125833.38704-13-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190415125833.38704-1-bibby.hsieh@mediatek.com> References: <20190415125833.38704-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 364474C44978AA6ED83000E763EDAF2B5EF95E53C214EBB3345E5CCAD1DE3D4D2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190415_055849_281676_895CE8EF X-CRM114-Status: UNSURE ( 9.60 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , kendrick.hsu@mediatek.com, linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Frederic Chen , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP add gce device node for mt8183 Signed-off-by: Bibby Hsieh --- This patch is based on v5.1-rc1 and these patches: https://patchwork.kernel.org/patch/10856987/ https://patchwork.kernel.org/patch/10839021/ https://patchwork.kernel.org/patch/10879015/ https://patchwork.kernel.org/patch/10878999/ https://patchwork.kernel.org/patch/10858941/ https://patchwork.kernel.org/patch/10846685/ https://patchwork.kernel.org/patch/10893519/ --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index b36e37fcdfe3..60809490a74b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include "mt8183-pinfunc.h" / { compatible = "mediatek,mt8183"; @@ -293,6 +294,17 @@ clock-names = "spi", "wrap"; }; + gce: gce@10238000 { + compatible = "mediatek,mt8183-gce"; + reg = <0 0x10238000 0 0x4000>; + interrupts = ; + #mbox-cells = <3>; + #gce-event-cells = <1>; + #gce-subsys-cells = <3>; + clocks = <&infracfg CLK_INFRA_GCE>; + clock-names = "gce"; + }; + uart0: serial@11002000 { compatible = "mediatek,mt8183-uart", "mediatek,mt6577-uart";