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Fri, 19 Apr 2019 15:18:41 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id a3sm8162536pfn.182.2019.04.19.15.18.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Apr 2019 15:18:40 -0700 (PDT) From: Douglas Anderson To: Russell King Subject: [PATCH 1/2] ARM: errata: Workaround errata A12 857271 / A17 857272 Date: Fri, 19 Apr 2019 15:18:02 -0700 Message-Id: <20190419221803.99322-1-dianders@chromium.org> X-Mailer: git-send-email 2.21.0.593.g511ec345e18-goog MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190419_151842_641039_0BA6A218 X-CRM114-Status: GOOD ( 13.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, Douglas Anderson , heiko@sntech.de, Tony Lindgren , Palmer Dabbelt , will.deacon@arm.com, bbatacha@arm.com, Masahiro Yamada , Florian Fainelli , linux-rockchip@lists.infradead.org, mka@chromium.org, Geert Uytterhoeven , Salva.Climent@arm.com, Arnd Bergmann , Marc Zyngier , sonnyrao@chromium.org, linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , linux-kernel@vger.kernel.org, Paul Burton , Andrew Morton , robin.murphy@arm.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sonny Rao This adds support for working around errata A12 857271 / A17 857272. These errata were causing hangs on rk3288-based Chromebooks and it was confirmed that this workaround fixed the problems. In the Chrome OS 3.14 kernel [1] this erratum was known as ERRATA_FOOBAR due to lack of an official number from ARM (though the workaround of setting chicken bit 10 came from ARM). In the meantime ARM came up with official errata numbers but never published the workaround upstream. Let's actually get the workaround landed. [1] https://crrev.com/c/342753 Signed-off-by: Sonny Rao Signed-off-by: Douglas Anderson --- arch/arm/Kconfig | 19 +++++++++++++++++++ arch/arm/mm/proc-v7.S | 10 ++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b509cd338219..4376fe74f95e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1172,6 +1172,15 @@ config ARM_ERRATA_825619 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable and Device/Strongly-Ordered loads and stores might cause deadlock +config ARM_ERRATA_857271 + bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" + depends on CPU_V7 + help + This option enables the workaround for the 857271 Cortex-A12 + (all revs) erratum. Under very rare timing conditions, the CPU might + hang. The workaround is expected to have a negligible performance + impact. + config ARM_ERRATA_852421 bool "ARM errata: A17: DMB ST might fail to create order between stores" depends on CPU_V7 @@ -1193,6 +1202,16 @@ config ARM_ERRATA_852423 config option from the A12 erratum due to the way errata are checked for and handled. +config ARM_ERRATA_857272 + bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" + depends on CPU_V7 + help + This option enables the workaround for the 857272 Cortex-A17 erratum. + This erratum is not known to be fixed in any A17 revision. + This is identical to Cortex-A12 erratum 857271. It is a separate + config option from the A12 erratum due to the way errata are checked + for and handled. + endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 339eb17c9808..cd2accbab844 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -391,6 +391,11 @@ __ca12_errata: mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register orr r10, r10, #1 << 24 @ set bit #24 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif +#ifdef CONFIG_ARM_ERRATA_857271 + mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register + orr r10, r10, #1 << 10 @ set bit #10 + mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register #endif b __errata_finish @@ -406,6 +411,11 @@ __ca17_errata: mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register orrle r10, r10, #1 << 12 @ set bit #12 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif +#ifdef CONFIG_ARM_ERRATA_857272 + mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register + orr r10, r10, #1 << 10 @ set bit #10 + mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register #endif b __errata_finish From patchwork Fri Apr 19 22:18:03 2019 Content-Type: text/plain; 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The exact set of instruction needed to trigger this errata is not totaly known but we have a high level of confidence that the problem is fixed by setting chicken bit 11. All details are in http://crbug.com/711784 This erratum has no known number and thus I have tagged it CR711784 (after the Chrome OS bug number). I have created separate A12 / A17 configs to match how the rest of the A12 / A17 errata is handled. Signed-off-by: Douglas Anderson --- arch/arm/Kconfig | 18 ++++++++++++++++++ arch/arm/mm/proc-v7.S | 10 ++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4376fe74f95e..34ec9039206b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1181,6 +1181,13 @@ config ARM_ERRATA_857271 hang. The workaround is expected to have a negligible performance impact. +config ARM_ERRATA_CR711784_A12 + bool "ARM errata: A12: conditional instructions can lead to a CPU hang" + depends on CPU_V7 + help + This option enables the workaround for a Cortex-A12 erratum without a + number. The problems are best described in https://crbug.com/711784 + config ARM_ERRATA_852421 bool "ARM errata: A17: DMB ST might fail to create order between stores" depends on CPU_V7 @@ -1212,6 +1219,17 @@ config ARM_ERRATA_857272 config option from the A12 erratum due to the way errata are checked for and handled. +config ARM_ERRATA_CR711784_A17 + bool "ARM errata: A17: conditional instructions can lead to a CPU hang" + depends on CPU_V7 + help + This option enables the workaround for a Cortex-A17 erratum without a + number. The problems are best described in https://crbug.com/711784 + This erratum is not known to be fixed in any A17 revision. + This is identical to Cortex-A12 erratum CR711784. It is a separate + config option from the A12 erratum due to the way errata are checked + for and handled. + endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index cd2accbab844..a5156ea734ee 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -396,6 +396,11 @@ __ca12_errata: mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register orr r10, r10, #1 << 10 @ set bit #10 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif +#ifdef CONFIG_ARM_ERRATA_CR711784_A12 + mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register + orr r10, r10, #1 << 11 @ set bit #11 + mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register #endif b __errata_finish @@ -416,6 +421,11 @@ __ca17_errata: mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register orr r10, r10, #1 << 10 @ set bit #10 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif +#ifdef CONFIG_ARM_ERRATA_CR711784_A17 + mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register + orr r10, r10, #1 << 11 @ set bit #11 + mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register #endif b __errata_finish