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[73.69.118.222]) by smtp.gmail.com with ESMTPSA id 6sm11296020qtt.8.2019.04.23.13.38.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Apr 2019 13:38:45 -0700 (PDT) From: Pavel Tatashin To: pasha.tatashin@soleen.com, jmorris@namei.org, sashal@kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-nvdimm@lists.01.org, akpm@linux-foundation.org, mhocko@suse.com, dave.hansen@linux.intel.com, dan.j.williams@intel.com, keith.busch@intel.com, vishal.l.verma@intel.com, dave.jiang@intel.com, zwisler@kernel.org, thomas.lendacky@amd.com, ying.huang@intel.com, fengguang.wu@intel.com, bp@suse.de, bhelgaas@google.com, baiyaowei@cmss.chinamobile.com, tiwai@suse.de, jglisse@redhat.com, catalin.marinas@arm.com, will.deacon@arm.com, rppt@linux.vnet.ibm.com, ard.biesheuvel@linaro.org, andrew.murray@arm.com, james.morse@arm.com, marc.zyngier@arm.com, sboyd@kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH] arm64: configurable sparsemem section size Date: Tue, 23 Apr 2019 16:38:43 -0400 Message-Id: <20190423203843.2898-1-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190423_133848_949404_12A38695 X-CRM114-Status: GOOD ( 13.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP sparsemem section size determines the maximum size and alignment that is allowed to offline/online memory block. The bigger the size the less the clutter in /sys/devices/system/memory/*. On the other hand, however, there is less flexability in what granules of memory can be added and removed. Recently, it was enabled in Linux to hotadd persistent memory that can be either real NV device, or reserved from regular System RAM and has identity of devdax. The problem is that because ARM64's section size is 1G, and devdax must have 2M label section, the first 1G is always missed when device is attached, because it is not 1G aligned. Allow, better flexibility by making section size configurable. Signed-off-by: Pavel Tatashin --- arch/arm64/Kconfig | 10 ++++++++++ arch/arm64/include/asm/sparsemem.h | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index b5d8cf57e220..a0c5b9d13a7f 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -801,6 +801,16 @@ config ARM64_PA_BITS default 48 if ARM64_PA_BITS_48 default 52 if ARM64_PA_BITS_52 +config ARM64_SECTION_SIZE_BITS + int "sparsemem section size shift" + range 27 30 + default "30" + depends on SPARSEMEM + help + Specify section size in bits. Section size determines the hotplug + hotremove granularity. The current size can be determined from + /sys/devices/system/memory/block_size_bytes + config CPU_BIG_ENDIAN bool "Build big-endian kernel" help diff --git a/arch/arm64/include/asm/sparsemem.h b/arch/arm64/include/asm/sparsemem.h index b299929fe56c..810db34d7038 100644 --- a/arch/arm64/include/asm/sparsemem.h +++ b/arch/arm64/include/asm/sparsemem.h @@ -18,7 +18,7 @@ #ifdef CONFIG_SPARSEMEM #define MAX_PHYSMEM_BITS CONFIG_ARM64_PA_BITS -#define SECTION_SIZE_BITS 30 +#define SECTION_SIZE_BITS CONFIG_ARM64_SECTION_SIZE_BITS #endif #endif