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Wed, 24 Apr 2019 14:21:40 +0000 Received: from MA1PR01MB3770.INDPRD01.PROD.OUTLOOK.COM ([fe80::f0fa:29f3:9933:7d7a]) by MA1PR01MB3770.INDPRD01.PROD.OUTLOOK.COM ([fe80::f0fa:29f3:9933:7d7a%3]) with mapi id 15.20.1835.010; Wed, 24 Apr 2019 14:21:40 +0000 From: Matt Redfearn To: Andrzej Hajda , Laurent Pinchart , Philippe Cornu Subject: [PATCH] drm/bridge/synopsys: dsi: Wait for all active lanes to reach stop Thread-Topic: [PATCH] drm/bridge/synopsys: dsi: Wait for all active lanes to reach stop Thread-Index: AQHU+qkIdYdzVBhVUEOlClcEU/eg/w== Date: Wed, 24 Apr 2019 14:21:40 +0000 Message-ID: <20190424142124.25776-1-matt.redfearn@thinci.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: DB6P193CA0016.EURP193.PROD.OUTLOOK.COM (2603:10a6:6:29::26) To MA1PR01MB3770.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:7b::22) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [87.242.198.86] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 820878b5-bf5f-426d-8f70-08d6c8c02b17 x-microsoft-antispam: BCL:0; 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a=rsa-sha256; c=relaxed/relaxed; d=thinciit.onmicrosoft.com; s=selector1-thinci-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VSwHz5rve35WG41Mz2OaqLjLAqNFp1GP2l3kfXM3f9s=; b=Kbe3qpoy4CqLypceIMa9Wdo4uhesWGOJavmCQ9nMJksBCEpXAU7vZqgaNJdlETFpO5Wtu9YD8tvTDC5yPXLZg35R5lsW8T2YE4AuNZEsVAjpwlmd4nblk52hjjJWSg0ox+lwxnZjxac3aHvjrFyXzVZig22y2FrTEVa68Qj7w9w= X-Mailman-Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=matthew.redfearn@thinci.com; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Archit Taneja , David Airlie , "linux-kernel@vger.kernel.org" , Matthew Redfearn , Nickey Yang , "dri-devel@lists.freedesktop.org" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The Synopsys manual states that software should wait for all active lanes to reach stop state (User manual section 3.1.5). Currently the driver only waits for / checks that the clock lane is in stop state. Fix this by waiting for the mask of PHY STATUS bits corresponding to the active lanes to be set. Signed-off-by: Matt Redfearn Reviewed-by: Laurent Pinchart --- drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index bd15c21a177..38e88071363 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -189,6 +189,10 @@ #define DSI_PHY_TX_TRIGGERS 0xac #define DSI_PHY_STATUS 0xb0 +#define PHY_STOP_STATE_LANE_3 BIT(11) +#define PHY_STOP_STATE_LANE_2 BIT(9) +#define PHY_STOP_STATE_LANE_1 BIT(7) +#define PHY_STOP_STATE_LANE_0 BIT(4) #define PHY_STOP_STATE_CLK_LANE BIT(2) #define PHY_LOCK BIT(0) @@ -752,7 +756,7 @@ static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi) static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi) { - u32 val; + u32 val, mask; int ret; dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | @@ -763,11 +767,16 @@ static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi) if (ret) DRM_DEBUG_DRIVER("failed to wait phy lock state\n"); + mask = PHY_STOP_STATE_CLK_LANE | PHY_STOP_STATE_LANE_0; + mask |= (dsi->lanes >= 2) ? PHY_STOP_STATE_LANE_1 : 0; + mask |= (dsi->lanes >= 3) ? PHY_STOP_STATE_LANE_2 : 0; + mask |= (dsi->lanes == 4) ? PHY_STOP_STATE_LANE_3 : 0; + ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, - val, val & PHY_STOP_STATE_CLK_LANE, 1000, + val, (val & mask) == mask, 1000, PHY_STATUS_TIMEOUT_US); if (ret) - DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n"); + DRM_DEBUG_DRIVER("failed to wait phy stop state\n"); } static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)