From patchwork Thu Apr 25 09:17:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien DESSENNE X-Patchwork-Id: 10916377 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6AC3F14DB for ; Thu, 25 Apr 2019 09:18:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5A5F528BB7 for ; Thu, 25 Apr 2019 09:18:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4EE0F28C2B; Thu, 25 Apr 2019 09:18:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EC73228BB7 for ; Thu, 25 Apr 2019 09:18:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727940AbfDYJRs (ORCPT ); Thu, 25 Apr 2019 05:17:48 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:37911 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726887AbfDYJRr (ORCPT ); Thu, 25 Apr 2019 05:17:47 -0400 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x3P91Rgv023616; Thu, 25 Apr 2019 11:17:31 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=YxS1CmFL4QUjGza2F9ElVAd/BnjMK/K8FnWYOu39aEY=; b=CKcL4ouOzvK6j6Z3lB1aJDZeXhk4CLwcPkktnry9uxvq8ZSdCogCTERnNiXRgcYvfP9g 0iqjMC35nMDV07nmBhN2ohR2ojdU9n6gAu8DFGh8/4OCj3q9VRh/jqnxlfWVTLb9lf7m Wo7oN4OEVSwrh+V8xq1zjUOu+XD0Pch9JJxhdwb9haN1XcXJdn7/XoRI91Hrj6xBfNXn kI1OTQ3gBBG3XFsQrcjv1b0G0Wcjytpb38/Ui80xMl1EROsRVrnwlkyJe+uQNFBVbmdO MfOYhQ+hg/HhZoCwUIrRvNeE0Y038caYMUb1ajdKQNbmOKo+4LUTpkep0fNmY3YZa/Td +w== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2rys6s2m27-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 25 Apr 2019 11:17:31 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0A91334; Thu, 25 Apr 2019 09:17:31 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D0A791615; Thu, 25 Apr 2019 09:17:30 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 25 Apr 2019 11:17:30 +0200 Received: from localhost (10.201.23.25) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 25 Apr 2019 11:17:30 +0200 From: Fabien Dessenne To: Ohad Ben-Cohen , Bjorn Andersson , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue , Jonathan Corbet , , , , , , CC: Fabien Dessenne , Benjamin Gaignard Subject: [PATCH v2 1/6] dt-bindings: hwlock: add support of shared locks Date: Thu, 25 Apr 2019 11:17:18 +0200 Message-ID: <1556183843-28033-2-git-send-email-fabien.dessenne@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556183843-28033-1-git-send-email-fabien.dessenne@st.com> References: <1556183843-28033-1-git-send-email-fabien.dessenne@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.25] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-04-25_08:,, signatures=0 Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use #hwlock-cells value to define whether the locks can be shared by several users. Signed-off-by: Fabien Dessenne Reviewed-by: Rob Herring --- .../devicetree/bindings/hwlock/hwlock.txt | 27 ++++++++++++++++------ 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/hwlock/hwlock.txt b/Documentation/devicetree/bindings/hwlock/hwlock.txt index 085d1f5..e98088a 100644 --- a/Documentation/devicetree/bindings/hwlock/hwlock.txt +++ b/Documentation/devicetree/bindings/hwlock/hwlock.txt @@ -13,7 +13,7 @@ hwlock providers: Required properties: - #hwlock-cells: Specifies the number of cells needed to represent a - specific lock. + specific lock. Shall be 1 or 2 (see hwlocks below). hwlock users: ============= @@ -27,6 +27,11 @@ Required properties: #hwlock-cells. The list can have just a single hwlock or multiple hwlocks, with each hwlock represented by a phandle and a corresponding args specifier. + If #hwlock-cells is 1, all of the locks are exclusive + (cannot be used by several users). + If #hwlock-cells is 2, the value of the second cell + defines whether the lock is for exclusive usage (0) or + shared (1) i.e. can be used by several users. Optional properties: - hwlock-names: List of hwlock name strings defined in the same order @@ -46,14 +51,22 @@ of length 1. ... }; -2. Example of a node using multiple specific hwlocks: +2. Example of nodes using multiple and shared specific hwlocks: -The following example has a node requesting two hwlocks, a hwlock within -the hwlock device node 'hwlock1' with #hwlock-cells value of 1, and another -hwlock within the hwlock device node 'hwlock2' with #hwlock-cells value of 2. +The following example has a nodeA requesting two hwlocks: +- an exclusive one (#hwlock-cells = 1) within the hwlock device node 'hwlock1' +- a shared one (#hwlock-cells = 2, second cell = 1) within the hwlock device + node 'hwlock2'. +The shared lock is also be used by nodeB. - node { + nodeA { ... - hwlocks = <&hwlock1 2>, <&hwlock2 0 3>; + hwlocks = <&hwlock1 2>, <&hwlock2 0 1>; ... }; + + nodeB { + ... + hwlocks = <&hwlock2 0 1>; + ... + }; \ No newline at end of file From patchwork Thu Apr 25 09:17:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien DESSENNE X-Patchwork-Id: 10916365 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3D21D14DB for ; Thu, 25 Apr 2019 09:18:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2C5CE28BB7 for ; Thu, 25 Apr 2019 09:18:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 20FD428C4D; Thu, 25 Apr 2019 09:18:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 52AE028BBD for ; Thu, 25 Apr 2019 09:18:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728195AbfDYJRz (ORCPT ); Thu, 25 Apr 2019 05:17:55 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:3488 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728164AbfDYJRx (ORCPT ); Thu, 25 Apr 2019 05:17:53 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x3P8uclB024832; Thu, 25 Apr 2019 11:17:33 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=E4OJ6ruljLisNJcmxAqdZd1iuQsXRd0SslgNNjwngII=; b=q1nfNOEFe/6X4IJLbWKg1HhuBNbSMtH2biDzpp7yIBnl8i1GOA3F5RcCLlkZU84mGCGB 4nnppOHP+7ZLSnOarBixjtGzdHnuCwLtpKR2jUiUDezh8ES89P4UEQaszfmmtfKB0bkW 9jEuYsEfz0QH5ImrRlZa4YoSGC9PE0WyzmrdQi32jdbabx4aaq5i1mDKnSU90V9vfx/P v096XvoXZ1cWay+xTinjLkCI+66VwE7UzsmhBLs6g77tWDLOWG3/qE8xtVbZarhoQ5Lm 8aap77lN7fq8H9Q8RPIW8J/ZuoJ4s8etmfZ/dDY65hAMy0SZGf2vGMb3X+jXtP7xwSdB tg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2ryrvxjq4c-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 25 Apr 2019 11:17:33 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8C67F31; Thu, 25 Apr 2019 09:17:32 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas24.st.com [10.75.90.94]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5894D1615; Thu, 25 Apr 2019 09:17:32 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by Safex1hubcas24.st.com (10.75.90.94) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 25 Apr 2019 11:17:31 +0200 Received: from localhost (10.201.23.25) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 25 Apr 2019 11:17:31 +0200 From: Fabien Dessenne To: Ohad Ben-Cohen , Bjorn Andersson , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue , Jonathan Corbet , , , , , , CC: Fabien Dessenne , Benjamin Gaignard Subject: [PATCH v2 2/6] hwspinlock: allow sharing of hwspinlocks Date: Thu, 25 Apr 2019 11:17:19 +0200 Message-ID: <1556183843-28033-3-git-send-email-fabien.dessenne@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556183843-28033-1-git-send-email-fabien.dessenne@st.com> References: <1556183843-28033-1-git-send-email-fabien.dessenne@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.25] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-04-25_08:,, signatures=0 Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The current implementation does not allow different devices to use a common hwspinlock. Offer the possibility to use the same hwspinlock by several users. If a device registers to the framework with #hwlock-cells = 2, then the second parameter of the 'hwlocks' DeviceTree property defines whether an hwlock is requested for an exclusive or a shared usage. If a device registers with #hwlock-cells = 1, then all the hwlocks are for an exclusive usage. Signed-off-by: Fabien Dessenne --- Documentation/hwspinlock.txt | 10 ++-- drivers/hwspinlock/hwspinlock_core.c | 82 +++++++++++++++++++++++++------- drivers/hwspinlock/hwspinlock_internal.h | 2 + 3 files changed, 73 insertions(+), 21 deletions(-) diff --git a/Documentation/hwspinlock.txt b/Documentation/hwspinlock.txt index ed640a2..e6ce2dd 100644 --- a/Documentation/hwspinlock.txt +++ b/Documentation/hwspinlock.txt @@ -54,9 +54,11 @@ Should be called from a process context (might sleep). struct hwspinlock *hwspin_lock_request_specific(unsigned int id); Assign a specific hwspinlock id and return its address, or NULL -if that hwspinlock is already in use. Usually board code will -be calling this function in order to reserve specific hwspinlock -ids for predefined purposes. +if that hwspinlock is already in use and not shared. If that specific +hwspinlock is declared as shared, it can be requested and used by +several users. +Usually board code will be calling this function in order to reserve +specific hwspinlock ids for predefined purposes. Should be called from a process context (might sleep). @@ -368,11 +370,13 @@ of which represents a single hardware lock:: * struct hwspinlock - this struct represents a single hwspinlock instance * @bank: the hwspinlock_device structure which owns this lock * @lock: initialized and used by hwspinlock core + * @refcount: number of users (when shared) * @priv: private data, owned by the underlying platform-specific hwspinlock drv */ struct hwspinlock { struct hwspinlock_device *bank; spinlock_t lock; + unsigned int refcount; void *priv; }; diff --git a/drivers/hwspinlock/hwspinlock_core.c b/drivers/hwspinlock/hwspinlock_core.c index 2bad40d..53afdeb 100644 --- a/drivers/hwspinlock/hwspinlock_core.c +++ b/drivers/hwspinlock/hwspinlock_core.c @@ -25,6 +25,8 @@ /* radix tree tags */ #define HWSPINLOCK_UNUSED (0) /* tags an hwspinlock as unused */ +#define HWSPINLOCK_EXCLUSIVE (1) /* tags an hwspinlock as exclusive */ +#define HWSPINLOCK_SHARED (2) /* tags an hwspinlock as shared */ /* * A radix tree is used to maintain the available hwspinlock instances. @@ -291,7 +293,7 @@ EXPORT_SYMBOL_GPL(__hwspin_unlock); * @hwlock_spec: hwlock specifier as found in the device tree * * This is a simple translation function, suitable for hwspinlock platform - * drivers that only has a lock specifier length of 1. + * drivers that only has a lock specifier length of 1 or 2. * * Returns a relative index of the lock within a specified bank on success, * or -EINVAL on invalid specifier cell count. @@ -299,7 +301,8 @@ EXPORT_SYMBOL_GPL(__hwspin_unlock); static inline int of_hwspin_lock_simple_xlate(const struct of_phandle_args *hwlock_spec) { - if (WARN_ON(hwlock_spec->args_count != 1)) + if (WARN_ON(hwlock_spec->args_count != 1 && + hwlock_spec->args_count != 2)) return -EINVAL; return hwlock_spec->args[0]; @@ -322,11 +325,12 @@ of_hwspin_lock_simple_xlate(const struct of_phandle_args *hwlock_spec) int of_hwspin_lock_get_id(struct device_node *np, int index) { struct of_phandle_args args; - struct hwspinlock *hwlock; + struct hwspinlock *hwlock, *tmp; struct radix_tree_iter iter; void **slot; int id; int ret; + unsigned int tag; ret = of_parse_phandle_with_args(np, "hwlocks", "#hwlock-cells", index, &args); @@ -361,6 +365,37 @@ int of_hwspin_lock_get_id(struct device_node *np, int index) } id += hwlock->bank->base_id; + /* Set the EXCLUSIVE / SHARED tag */ + if (args.args_count == 2 && args.args[1]) { + /* Tag SHARED unless already tagged EXCLUSIVE */ + if (radix_tree_tag_get(&hwspinlock_tree, id, + HWSPINLOCK_EXCLUSIVE)) { + ret = -EINVAL; + goto out; + } + tag = HWSPINLOCK_SHARED; + } else { + /* Tag EXCLUSIVE unless already tagged SHARED */ + if (radix_tree_tag_get(&hwspinlock_tree, id, + HWSPINLOCK_SHARED)) { + ret = -EINVAL; + goto out; + } + tag = HWSPINLOCK_EXCLUSIVE; + } + + /* mark this hwspinlock */ + hwlock = radix_tree_lookup(&hwspinlock_tree, id); + if (!hwlock) { + ret = -EINVAL; + goto out; + } + + tmp = radix_tree_tag_set(&hwspinlock_tree, id, tag); + + /* self-sanity check which should never fail */ + WARN_ON(tmp != hwlock); + out: of_node_put(args.np); return ret ? ret : id; @@ -483,6 +518,7 @@ int hwspin_lock_register(struct hwspinlock_device *bank, struct device *dev, spin_lock_init(&hwlock->lock); hwlock->bank = bank; + hwlock->refcount = 0; ret = hwspin_lock_register_single(hwlock, base_id + i); if (ret) @@ -625,7 +661,7 @@ static int __hwspin_lock_request(struct hwspinlock *hwlock) { struct device *dev = hwlock->bank->dev; struct hwspinlock *tmp; - int ret; + int ret, id; /* prevent underlying implementation from being removed */ if (!try_module_get(dev->driver->owner)) { @@ -642,13 +678,18 @@ static int __hwspin_lock_request(struct hwspinlock *hwlock) return ret; } + /* update shareable refcount */ + id = hwlock_to_id(hwlock); + if (radix_tree_tag_get(&hwspinlock_tree, id, HWSPINLOCK_SHARED) && + hwlock->refcount++) + goto out; + /* mark hwspinlock as used, should not fail */ - tmp = radix_tree_tag_clear(&hwspinlock_tree, hwlock_to_id(hwlock), - HWSPINLOCK_UNUSED); + tmp = radix_tree_tag_clear(&hwspinlock_tree, id, HWSPINLOCK_UNUSED); /* self-sanity check that should never fail */ WARN_ON(tmp != hwlock); - +out: return ret; } @@ -742,9 +783,9 @@ struct hwspinlock *hwspin_lock_request_specific(unsigned int id) /* sanity check (this shouldn't happen) */ WARN_ON(hwlock_to_id(hwlock) != id); - /* make sure this hwspinlock is unused */ - ret = radix_tree_tag_get(&hwspinlock_tree, id, HWSPINLOCK_UNUSED); - if (ret == 0) { + /* make sure this hwspinlock is unused or shareable */ + if (!radix_tree_tag_get(&hwspinlock_tree, id, HWSPINLOCK_SHARED) && + !radix_tree_tag_get(&hwspinlock_tree, id, HWSPINLOCK_UNUSED)) { pr_warn("hwspinlock %u is already in use\n", id); hwlock = NULL; goto out; @@ -777,7 +818,7 @@ int hwspin_lock_free(struct hwspinlock *hwlock) { struct device *dev; struct hwspinlock *tmp; - int ret; + int ret, id; if (!hwlock) { pr_err("invalid hwlock\n"); @@ -788,30 +829,35 @@ int hwspin_lock_free(struct hwspinlock *hwlock) mutex_lock(&hwspinlock_tree_lock); /* make sure the hwspinlock is used */ - ret = radix_tree_tag_get(&hwspinlock_tree, hwlock_to_id(hwlock), - HWSPINLOCK_UNUSED); + id = hwlock_to_id(hwlock); + ret = radix_tree_tag_get(&hwspinlock_tree, id, HWSPINLOCK_UNUSED); if (ret == 1) { dev_err(dev, "%s: hwlock is already free\n", __func__); dump_stack(); ret = -EINVAL; - goto out; + goto unlock; } /* notify the underlying device that power is not needed */ ret = pm_runtime_put(dev); if (ret < 0) - goto out; + goto unlock; + + /* update shareable refcount */ + if (radix_tree_tag_get(&hwspinlock_tree, id, HWSPINLOCK_SHARED) && + --hwlock->refcount) + goto put; /* mark this hwspinlock as available */ - tmp = radix_tree_tag_set(&hwspinlock_tree, hwlock_to_id(hwlock), - HWSPINLOCK_UNUSED); + tmp = radix_tree_tag_set(&hwspinlock_tree, id, HWSPINLOCK_UNUSED); /* sanity check (this shouldn't happen) */ WARN_ON(tmp != hwlock); +put: module_put(dev->driver->owner); -out: +unlock: mutex_unlock(&hwspinlock_tree_lock); return ret; } diff --git a/drivers/hwspinlock/hwspinlock_internal.h b/drivers/hwspinlock/hwspinlock_internal.h index 9eb6bd0..c808e11 100644 --- a/drivers/hwspinlock/hwspinlock_internal.h +++ b/drivers/hwspinlock/hwspinlock_internal.h @@ -35,11 +35,13 @@ struct hwspinlock_ops { * struct hwspinlock - this struct represents a single hwspinlock instance * @bank: the hwspinlock_device structure which owns this lock * @lock: initialized and used by hwspinlock core + * @refcount: number of users (when shared) * @priv: private data, owned by the underlying platform-specific hwspinlock drv */ struct hwspinlock { struct hwspinlock_device *bank; spinlock_t lock; + unsigned int refcount; void *priv; }; From patchwork Thu Apr 25 09:17:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien DESSENNE X-Patchwork-Id: 10916367 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5E3CB161F for ; Thu, 25 Apr 2019 09:18:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4F97228BBD for ; Thu, 25 Apr 2019 09:18:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4310928BB7; Thu, 25 Apr 2019 09:18:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E557128C2B for ; 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Thu, 25 Apr 2019 11:17:39 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id AE53731; Thu, 25 Apr 2019 09:17:33 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas22.st.com [10.75.90.92]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 91F4C1615; Thu, 25 Apr 2019 09:17:33 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by Safex1hubcas22.st.com (10.75.90.92) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 25 Apr 2019 11:17:33 +0200 Received: from localhost (10.201.23.25) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 25 Apr 2019 11:17:32 +0200 From: Fabien Dessenne To: Ohad Ben-Cohen , Bjorn Andersson , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue , Jonathan Corbet , , , , , , CC: Fabien Dessenne , Benjamin Gaignard Subject: [PATCH v2 3/6] dt-bindings: hwlock: update STM32 #hwlock-cells value Date: Thu, 25 Apr 2019 11:17:20 +0200 Message-ID: <1556183843-28033-4-git-send-email-fabien.dessenne@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556183843-28033-1-git-send-email-fabien.dessenne@st.com> References: <1556183843-28033-1-git-send-email-fabien.dessenne@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.25] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-04-25_08:,, signatures=0 Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use a value of 2, so users can share hwlocks. Signed-off-by: Fabien Dessenne Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt index adf4f000..60a3716 100644 --- a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt +++ b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt @@ -4,8 +4,8 @@ STM32 Hardware Spinlock Device Binding Required properties : - compatible : should be "st,stm32-hwspinlock". - reg : the register address of hwspinlock. -- #hwlock-cells : hwlock users only use the hwlock id to represent a specific - hwlock, so the number of cells should be <1> here. +- #hwlock-cells : should be <2> so the hwlock users use the hwlock id to + represent a specific hwlock and define its shared / exclusive attribute. - clock-names : Must contain "hsem". - clocks : Must contain a phandle entry for the clock in clock-names, see the common clock bindings. @@ -16,7 +16,7 @@ Please look at the generic hwlock binding for usage information for consumers, Example of hwlock provider: hwspinlock@4c000000 { compatible = "st,stm32-hwspinlock"; - #hwlock-cells = <1>; + #hwlock-cells = <2>; reg = <0x4c000000 0x400>; clocks = <&rcc HSEM>; clock-names = "hsem"; From patchwork Thu Apr 25 09:17:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien DESSENNE X-Patchwork-Id: 10916375 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B4C9714DB for ; Thu, 25 Apr 2019 09:18:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A648E28BB7 for ; Thu, 25 Apr 2019 09:18:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9A9E928C2B; Thu, 25 Apr 2019 09:18:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 455A528BB7 for ; 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Thu, 25 Apr 2019 11:17:35 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E35DF38; Thu, 25 Apr 2019 09:17:34 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id BB303161B; Thu, 25 Apr 2019 09:17:34 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 25 Apr 2019 11:17:34 +0200 Received: from localhost (10.201.23.25) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 25 Apr 2019 11:17:34 +0200 From: Fabien Dessenne To: Ohad Ben-Cohen , Bjorn Andersson , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue , Jonathan Corbet , , , , , , CC: Fabien Dessenne , Benjamin Gaignard Subject: [PATCH v2 4/6] ARM: dts: stm32: Add hwspinlock node for stm32mp157 SoC Date: Thu, 25 Apr 2019 11:17:21 +0200 Message-ID: <1556183843-28033-5-git-send-email-fabien.dessenne@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556183843-28033-1-git-send-email-fabien.dessenne@st.com> References: <1556183843-28033-1-git-send-email-fabien.dessenne@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.25] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-04-25_08:,, signatures=0 Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Declare hwspinlock device for stm32mp157 SoC Signed-off-by: Fabien Dessenne --- arch/arm/boot/dts/stm32mp157c.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 105e21f..824d7e1 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -886,6 +886,14 @@ status = "disabled"; }; + hsem: hwspinlock@4c000000 { + compatible = "st,stm32-hwspinlock"; + #hwlock-cells = <2>; + reg = <0x4c000000 0x400>; + clocks = <&rcc HSEM>; + clock-names = "hsem"; + }; + ipcc: mailbox@4c001000 { compatible = "st,stm32mp1-ipcc"; #mbox-cells = <1>; From patchwork Thu Apr 25 09:17:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien DESSENNE X-Patchwork-Id: 10916363 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AEB43161F for ; Thu, 25 Apr 2019 09:18:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9E85328BB7 for ; Thu, 25 Apr 2019 09:18:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9294E28C42; Thu, 25 Apr 2019 09:18:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4AFA328BB7 for ; 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Thu, 25 Apr 2019 11:17:39 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 02F443F; Thu, 25 Apr 2019 09:17:36 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas22.st.com [10.75.90.92]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D8C7D1615; Thu, 25 Apr 2019 09:17:35 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by Safex1hubcas22.st.com (10.75.90.92) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 25 Apr 2019 11:17:35 +0200 Received: from localhost (10.201.23.25) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 25 Apr 2019 11:17:35 +0200 From: Fabien Dessenne To: Ohad Ben-Cohen , Bjorn Andersson , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue , Jonathan Corbet , , , , , , CC: Fabien Dessenne , Benjamin Gaignard Subject: [PATCH v2 5/6] ARM: dts: stm32: Add hwlock for irqchip on stm32mp157 Date: Thu, 25 Apr 2019 11:17:22 +0200 Message-ID: <1556183843-28033-6-git-send-email-fabien.dessenne@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556183843-28033-1-git-send-email-fabien.dessenne@st.com> References: <1556183843-28033-1-git-send-email-fabien.dessenne@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.25] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-04-25_08:,, signatures=0 Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Define a hwspinlock to be used by the irq controller driver and the syscon driver. Signed-off-by: Fabien Dessenne --- arch/arm/boot/dts/stm32mp157c.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 824d7e1..417bdf7 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -921,6 +921,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x5000d000 0x400>; + hwlocks = <&hsem 1 1>; }; syscfg: syscon@50020000 { From patchwork Thu Apr 25 09:17:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien DESSENNE X-Patchwork-Id: 10916371 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AD20F1805 for ; Thu, 25 Apr 2019 09:18:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9E70C28BB7 for ; Thu, 25 Apr 2019 09:18:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9220828BBD; Thu, 25 Apr 2019 09:18:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3D5D528C4D for ; Thu, 25 Apr 2019 09:18:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728122AbfDYJRv (ORCPT ); Thu, 25 Apr 2019 05:17:51 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:11406 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726887AbfDYJRu (ORCPT ); Thu, 25 Apr 2019 05:17:50 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x3P98EbV001148; Thu, 25 Apr 2019 11:17:38 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=TB3BkgmyReUhhLwwZP6E0LuWO4jA3RAmt5KETLnSFmk=; b=erSsRncWHfTfgt1hSBbJVJkg4qpjxVOYOW155egY+s/7bfch9x6ovQd99jhKgW32hzAp iOo04rFy+9NpvhSA9Bf/HKtFOxlYSA8oxTdfiL8j/uxo5sACisdBXQdSJ0p30mfZ6xTn D9EeRrmLENOkU5ioixzzmPYz2VR8+ds33mPOZsUKLDNKl4Hd+k3MZNdxfanzD0GxcgI5 2PO4ZJhyLNtwEsD8Smktfsyc7kGm6g9leXkczQgnbzNqBLYB/7mTMtZ/Nb5qJTJ/Mp0k rVx+HW3073yt3Vd3rTX3lc5HvKjjpxRAifn/qO7b66qn2Pk4g4EFysbtejs/sZi7K0wv BQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2ryrj6cabb-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 25 Apr 2019 11:17:37 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2B9B83A; Thu, 25 Apr 2019 09:17:37 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0B409161E; Thu, 25 Apr 2019 09:17:37 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 25 Apr 2019 11:17:36 +0200 Received: from localhost (10.201.23.25) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 25 Apr 2019 11:17:36 +0200 From: Fabien Dessenne To: Ohad Ben-Cohen , Bjorn Andersson , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue , Jonathan Corbet , , , , , , CC: Fabien Dessenne , Benjamin Gaignard Subject: [PATCH v2 6/6] ARM: dts: stm32: hwlocks for GPIO for stm32mp157 Date: Thu, 25 Apr 2019 11:17:23 +0200 Message-ID: <1556183843-28033-7-git-send-email-fabien.dessenne@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556183843-28033-1-git-send-email-fabien.dessenne@st.com> References: <1556183843-28033-1-git-send-email-fabien.dessenne@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.25] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-04-25_08:,, signatures=0 Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Declare a shared hwlock to be used by all gpio / pin controllers. Signed-off-by: Fabien Dessenne --- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index 6b3a9c6..9fd562a 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -14,6 +14,7 @@ ranges = <0 0x50002000 0xa400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; + hwlocks = <&hsem 0 1>; pins-are-numbered; gpioa: gpio@50002000 { @@ -424,6 +425,7 @@ pins-are-numbered; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; + hwlocks = <&hsem 0 1>; gpioz: gpio@54004000 { gpio-controller;