From patchwork Mon May 13 15:36:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941225 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4070D933 for ; Mon, 13 May 2019 15:37:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 311A4283A6 for ; Mon, 13 May 2019 15:37:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 255F5283E7; Mon, 13 May 2019 15:37:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8DB86283A6 for ; Mon, 13 May 2019 15:37:26 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 56974E55; Mon, 13 May 2019 15:37:26 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id D4F0ED85 for ; Mon, 13 May 2019 15:37:24 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 7B11B875 for ; Mon, 13 May 2019 15:37:22 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810545" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:37:21 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 84C75401BBEF; Tue, 14 May 2019 00:37:20 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:26 +0100 Message-Id: <1557761837-24993-2-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 01/52] ARM: shmobile: r8a77470: basic SoC support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit 0c1d543b75f242f08b08e7fb63a1df2ada025903 upstream. Add minimal support for the RZ/G1C (R8A77470) SoC. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman Signed-off-by: Fabrizio Castro --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ arch/arm/mach-shmobile/Kconfig | 4 ++++ arch/arm/mach-shmobile/pm-rcar-gen2.c | 2 ++ arch/arm/mach-shmobile/setup-rcar-gen2.c | 2 ++ 4 files changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index e27b38e..3b51d7e 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -17,6 +17,8 @@ SoCs: compatible = "renesas,r8a7743" - RZ/G1E (R8A77450) compatible = "renesas,r8a7745" + - RZ/G1C (R8A77470) + compatible = "renesas,r8a77470" - R-Car M1A (R8A77781) compatible = "renesas,r8a7778" - R-Car H1 (R8A77790) diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 602fc2d..31549b7 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -72,6 +72,10 @@ config ARCH_R8A7745 bool "RZ/G1E (R8A77450)" select ARCH_RCAR_GEN2 +config ARCH_R8A77470 + bool "RZ/G1C (R8A77470)" + select ARCH_RCAR_GEN2 + config ARCH_R8A7778 bool "R-Car M1A (R8A77781)" select ARCH_RCAR_GEN1 diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c b/arch/arm/mach-shmobile/pm-rcar-gen2.c index 0054561..419575e 100644 --- a/arch/arm/mach-shmobile/pm-rcar-gen2.c +++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c @@ -101,6 +101,8 @@ void __init rcar_gen2_pm_init(void) syscier = 0x00101003; else if (of_machine_is_compatible("renesas,r8a7745")) syscier = 0x00300060; + else if (of_machine_is_compatible("renesas,r8a77470")) + syscier = 0x00300060; np = of_find_compatible_node(NULL, NULL, "renesas,smp-sram"); if (!np) { diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c index 50d7438..6e0c0ce 100644 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c @@ -61,6 +61,7 @@ void __init rcar_gen2_timer_init(void) shmobile_init_cntvoff(); if (of_machine_is_compatible("renesas,r8a7745") || + of_machine_is_compatible("renesas,r8a77470") || of_machine_is_compatible("renesas,r8a7794")) { freq = 260000000 / 8; /* ZS / 8 */ } else { @@ -208,6 +209,7 @@ MACHINE_END static const char * const rz_g1_boards_compat_dt[] __initconst = { "renesas,r8a7743", "renesas,r8a7745", + "renesas,r8a77470", NULL, }; From patchwork Mon May 13 15:36:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941227 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8EDF3933 for ; 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Mon, 13 May 2019 15:37:25 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 85CA727B for ; Mon, 13 May 2019 15:37:24 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608146" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:37:23 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 3EAD6401BA41; Tue, 14 May 2019 00:37:22 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:27 +0100 Message-Id: <1557761837-24993-3-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 02/52] clk: shmobile: rcar-gen2: Add quirks for the RZ/G1C X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds a quirk for clocks "sd0" and "sd1" for the RZ/G1C (a.k.a. r8a77470) SoC, similarly to what has been done upstream with commit: 5bf2fbbef50c ("clk: renesas: cpg-mssr: Add r8a77470 support") and also customizes the settings for the PLLs. Signed-off-by: Fabrizio Castro --- drivers/clk/shmobile/clk-rcar-gen2.c | 39 +++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c index 6ab0199..3f7d331 100644 --- a/drivers/clk/shmobile/clk-rcar-gen2.c +++ b/drivers/clk/shmobile/clk-rcar-gen2.c @@ -268,6 +268,24 @@ static struct clk * __init cpg_adsp_clk_register(struct rcar_gen2_cpg *cpg) #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ (((md) & BIT(13)) >> 12) | \ (((md) & BIT(19)) >> 19)) + +/* + * This table is only valid for the RZ/G1C + * + * MD EXTAL PLL0 PLL1 PLL3 + * 14 13 (MHz) *1 *2 + *--------------------------------------------------- + * 0 0 20 / 1 x80 x78 x50 + * 0 1 26 / 1 x60 x60 x56 + * 1 0 Prohibited setting + * 1 1 30 / 1 x52 x52 x50 + * + * *1 : Table 7.4 indicates VCO output (PLL0 = VCO) + * *2 : Table 7.4 indicates VCO output (PLL1 = VCO) + */ +#define CPG_PLL_CONFIG_INDEX_RZG1C(md) ((((md) & BIT(14)) >> 13) | \ + (((md) & BIT(13)) >> 13)) + struct cpg_pll_config { unsigned int extal_div; unsigned int pll1_mult; @@ -282,6 +300,14 @@ static const struct cpg_pll_config cpg_pll_configs[8] __initconst = { { 2, 208, 106, 200 }, { 2, 208, 88, 200 }, }; +static const struct cpg_pll_config cpg_pll_configs_rzg1c[4] __initconst = { + /* EXTAL div PLL1 mult x2 PLL3 mult */ + { 1, 156, 50, }, + { 1, 120, 56, }, + { /* Invalid*/ }, + { 1, 104, 50, }, +}; + /* SDHI divisors */ static const struct clk_div_table cpg_sdh_div_table[] = { { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, @@ -308,6 +334,8 @@ static const char * const pll0_mult_match[] = { NULL }; +static const char *r8a77470_compat = "renesas,r8a77470-cpg-clocks"; + static struct clk * __init rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg, const struct cpg_pll_config *config, @@ -357,10 +385,16 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg, } else if (!strcmp(name, "sd0")) { parent_name = "pll1"; table = cpg_sd01_div_table; + if (of_device_is_compatible(np, r8a77470_compat)) + table++; + shift = 4; } else if (!strcmp(name, "sd1")) { parent_name = "pll1"; table = cpg_sd01_div_table; + if (of_device_is_compatible(np, r8a77470_compat)) + table++; + shift = 0; } else if (!strcmp(name, "z")) { return cpg_z_clk_register(cpg); @@ -414,7 +448,10 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np) if (WARN_ON(cpg->reg == NULL)) return; - config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; + if (of_device_is_compatible(np, r8a77470_compat)) + config = &cpg_pll_configs_rzg1c[CPG_PLL_CONFIG_INDEX_RZG1C(cpg_mode)]; + else + config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; for (i = 0; i < num_clks; ++i) { const char *name; From patchwork Mon May 13 15:36:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941231 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C4994933 for ; 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Mon, 13 May 2019 15:37:25 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 63F6327B for ; Mon, 13 May 2019 15:37:25 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810548" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:37:25 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id E381C401B9F5; Tue, 14 May 2019 00:37:23 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:28 +0100 Message-Id: <1557761837-24993-4-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 03/52] clk: shmobile: Compile clk-rcar-gen2.c when using the r8a77470 X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP This patch makes sure clk-rcar-gen2,c gets compiled when CONFIG_ARCH_R8A77470 is selected, similarly to what done by commit: 7bac4ad3e40f ("CIP: Build essential clock driver for Renesas RZ/G1 platforms") Signed-off-by: Fabrizio Castro --- drivers/clk/shmobile/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile index b339c0b..2412eb9 100644 --- a/drivers/clk/shmobile/Makefile +++ b/drivers/clk/shmobile/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o obj-$(CONFIG_ARCH_R8A7743) += clk-rcar-gen2.o obj-$(CONFIG_ARCH_R8A7745) += clk-rcar-gen2.o +obj-$(CONFIG_ARCH_R8A77470) += clk-rcar-gen2.o obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o From patchwork Mon May 13 15:36:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941233 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7C904933 for ; Mon, 13 May 2019 15:37:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6DAA5283A6 for ; Mon, 13 May 2019 15:37:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 62382283B1; Mon, 13 May 2019 15:37:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id EFAC4283A6 for ; Mon, 13 May 2019 15:37:41 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id B971EE71; Mon, 13 May 2019 15:37:28 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id D7181E52 for ; Mon, 13 May 2019 15:37:27 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 1940883A for ; Mon, 13 May 2019 15:37:26 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608149" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:37:26 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 93E07401B9F5; Tue, 14 May 2019 00:37:25 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:29 +0100 Message-Id: <1557761837-24993-5-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 04/52] ARM: shmobile: r8a77470: Add clock index macros for DT sources X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP Add macros usable by device tree sources to reference the r8a77470 clocks by index. Signed-off-by: Fabrizio Castro --- include/dt-bindings/clock/r8a77470-clock.h | 140 +++++++++++++++++++++++++++++ 1 file changed, 140 insertions(+) create mode 100644 include/dt-bindings/clock/r8a77470-clock.h diff --git a/include/dt-bindings/clock/r8a77470-clock.h b/include/dt-bindings/clock/r8a77470-clock.h new file mode 100644 index 0000000..2f20bcc --- /dev/null +++ b/include/dt-bindings/clock/r8a77470-clock.h @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2019 Renesas Electronics Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A77470_H__ +#define __DT_BINDINGS_CLOCK_R8A77470_H__ + +/* CPG */ +#define R8A77470_CLK_MAIN 0 +#define R8A77470_CLK_PLL0 1 +#define R8A77470_CLK_PLL1 2 +#define R8A77470_CLK_PLL3 3 +#define R8A77470_CLK_LB 4 +#define R8A77470_CLK_QSPI 5 +#define R8A77470_CLK_SDH 6 +#define R8A77470_CLK_SD0 7 +#define R8A77470_CLK_SD1 8 +#define R8A77470_CLK_RCAN 9 + +/* MSTP0 */ +#define R8A77470_CLK_MSIOF0 0 + +/* MSTP1 */ +#define R8A77470_CLK_VCP0 1 +#define R8A77470_CLK_VPC0 3 +#define R8A77470_CLK_STB 4 +#define R8A77470_CLK_TMU1 11 +#define R8A77470_CLK_3DG 12 +#define R8A77470_CLK_2DDMAC 15 +#define R8A77470_CLK_FDP1_0 19 +#define R8A77470_CLK_TMU3 21 +#define R8A77470_CLK_TMU2 22 +#define R8A77470_CLK_CMT0 24 +#define R8A77470_CLK_VSP1DU0 28 +#define R8A77470_CLK_VSP1_SY 31 + +/* MSTP2 */ +#define R8A77470_CLK_MSIOF2 5 +#define R8A77470_CLK_MSIOF1 8 +#define R8A77470_CLK_SYS_DMAC1 18 +#define R8A77470_CLK_SYS_DMAC0 19 + +/* MSTP3 */ +#define R8A77470_CLK_SDHI2 12 +#define R8A77470_CLK_SDHI1 13 +#define R8A77470_CLK_SDHI0 14 +#define R8A77470_CLK_USBHS_DMAC0_CH1 26 +#define R8A77470_CLK_USBHS_DMAC1_CH1 27 +#define R8A77470_CLK_CMT1 29 +#define R8A77470_CLK_USBHS_DMAC0_CH0 30 +#define R8A77470_CLK_USBHS_DMAC1_CH0 31 + +/* MSTP4 */ +#define R8A77470_CLK_RWDT 2 +#define R8A77470_CLK_USB_DDM0 6 +#define R8A77470_CLK_IRQC 7 +#define R8A77470_CLK_INTC_SYS 8 +#define R8A77470_CLK_USB_DDM1 9 + +/* MSTP5 */ +#define R8A77470_CLK_AUDIO_DMAC0 2 +#define R8A77470_CLK_PWM 23 +#define R8A77470_CLK_BOOT_ROM 30 + +/* MSTP7 */ +#define R8A77470_CLK_USB_EHCI_0 3 +#define R8A77470_CLK_USBHS0 4 +#define R8A77470_CLK_USB_EHCI_1 5 +#define R8A77470_CLK_USBHS1 6 +#define R8A77470_CLK_HSCIF2 13 +#define R8A77470_CLK_SCIF5 14 +#define R8A77470_CLK_SCIF4 15 +#define R8A77470_CLK_HSCIF1 16 +#define R8A77470_CLK_HSCIF0 17 +#define R8A77470_CLK_SCIF3 18 +#define R8A77470_CLK_SCIF2 19 +#define R8A77470_CLK_SCIF1 20 +#define R8A77470_CLK_SCIF0 21 +#define R8A77470_CLK_DU1 23 +#define R8A77470_CLK_DU0 24 +#define R8A77470_CLK_LVDS 26 +#define R8A77470_CLK_DVE 27 + +/* MSTP8 */ +#define R8A77470_CLK_IPMMU_SGX 0 +#define R8A77470_CLK_DVD 1 +#define R8A77470_CLK_VIN1 10 +#define R8A77470_CLK_VIN0 11 +#define R8A77470_CLK_ETHERAVB 12 +#define R8A77470_CLK_ETHER 13 + +/* MSTP9 */ +#define R8A77470_CLK_IR_RECEIVER 3 +#define R8A77470_CLK_GPIO5 7 +#define R8A77470_CLK_GPIO4 8 +#define R8A77470_CLK_GPIO3 9 +#define R8A77470_CLK_GPIO2 10 +#define R8A77470_CLK_GPIO1 11 +#define R8A77470_CLK_GPIO0 12 +#define R8A77470_CLK_CAN1 15 +#define R8A77470_CLK_CAN0 16 +#define R8A77470_CLK_QUAD_SPI1 17 +#define R8A77470_CLK_QUAD_SPI0 18 +#define R8A77470_CLK_ADG 22 +#define R8A77470_CLK_I2C4 27 +#define R8A77470_CLK_I2C3 28 +#define R8A77470_CLK_I2C2 29 +#define R8A77470_CLK_I2C1 30 +#define R8A77470_CLK_I2C0 31 + +/* MSTP10 */ +#define R8A77470_CLK_SSI_ALL 5 +#define R8A77470_CLK_SSI9 6 +#define R8A77470_CLK_SSI8 7 +#define R8A77470_CLK_SSI7 8 +#define R8A77470_CLK_SSI6 9 +#define R8A77470_CLK_SSI5 10 +#define R8A77470_CLK_SSI4 11 +#define R8A77470_CLK_SSI3 12 +#define R8A77470_CLK_SSI2 13 +#define R8A77470_CLK_SSI1 14 +#define R8A77470_CLK_SSI0 15 +#define R8A77470_CLK_SCU_ALL 17 +#define R8A77470_CLK_SCU_DVC1 18 +#define R8A77470_CLK_SCU_DVC0 19 +#define R8A77470_CLK_SCU_CTU1_MIX1 20 +#define R8A77470_CLK_SCU_CTU0_MIX0 21 +#define R8A77470_CLK_SCU_SRC6 25 +#define R8A77470_CLK_SCU_SRC5 26 +#define R8A77470_CLK_SCU_SRC4 27 +#define R8A77470_CLK_SCU_SRC3 28 +#define R8A77470_CLK_SCU_SRC2 29 +#define R8A77470_CLK_SCU_SRC1 30 + +#endif /* __DT_BINDINGS_CLOCK_R8A77470_H__ */ From patchwork Mon May 13 15:36:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941239 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0D0D1933 for ; Mon, 13 May 2019 15:38:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E832F283A6 for ; Mon, 13 May 2019 15:38:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DBEFC283AF; Mon, 13 May 2019 15:38:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,UPPERCASE_50_75 autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id F1817283A6 for ; Mon, 13 May 2019 15:37:59 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 25493E84; Mon, 13 May 2019 15:37:37 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id AC16CE84 for ; Mon, 13 May 2019 15:37:35 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 954D527B for ; Mon, 13 May 2019 15:37:29 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608152" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:37:29 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 43C64401B9F5; Tue, 14 May 2019 00:37:27 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:30 +0100 Message-Id: <1557761837-24993-6-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 05/52] pinctrl: sh-pfc: Add r8a77470 PFC support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit 73dacc3403436fc246258c0933e35b6e809640ac upstream. Add PFC support for the R8A77470 SoC including pin groups for some on-chip devices such as SCIF and MMC. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Signed-off-by: Geert Uytterhoeven Signed-off-by: Linus Walleij (fab: moved r8a77470_pinmux_info declaration from sh_pfc.h to core.h, in pfc-r8a77470.c: added #include "core.h", removed #include "sh_pfc.h", and added a few missing macro definitions) Signed-off-by: Fabrizio Castro --- drivers/pinctrl/sh-pfc/Kconfig | 5 + drivers/pinctrl/sh-pfc/Makefile | 1 + drivers/pinctrl/sh-pfc/core.c | 6 + drivers/pinctrl/sh-pfc/core.h | 1 + drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 2368 +++++++++++++++++++++++++++++++++ 5 files changed, 2381 insertions(+) create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a77470.c diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 2ba6d55..ab15d19 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -45,6 +45,11 @@ config PINCTRL_PFC_R8A7745 depends on ARCH_R8A7745 select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A77470 + def_bool y + depends on ARCH_R8A77470 + select PINCTRL_SH_PFC + config PINCTRL_PFC_R8A7778 def_bool y depends on ARCH_R8A7778 diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 7fd3bea..e9ef2cc 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o obj-$(CONFIG_PINCTRL_PFC_R8A7743) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7745) += pfc-r8a7794.o +obj-$(CONFIG_PINCTRL_PFC_R8A77470) += pfc-r8a77470.o obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 0cd07df..c3a3283 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -465,6 +465,12 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a7745_pinmux_info, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A77470 + { + .compatible = "renesas,pfc-r8a77470", + .data = &r8a77470_pinmux_info, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A7778 { .compatible = "renesas,pfc-r8a7778", diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index 0822d9fe..37acc88 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -71,6 +71,7 @@ extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; extern const struct sh_pfc_soc_info r8a7740_pinmux_info; extern const struct sh_pfc_soc_info r8a7743_pinmux_info; extern const struct sh_pfc_soc_info r8a7745_pinmux_info; +extern const struct sh_pfc_soc_info r8a77470_pinmux_info; extern const struct sh_pfc_soc_info r8a7778_pinmux_info; extern const struct sh_pfc_soc_info r8a7779_pinmux_info; extern const struct sh_pfc_soc_info r8a7790_pinmux_info; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c new file mode 100644 index 0000000..8973f61 --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -0,0 +1,2368 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R8A77470 processor support - PFC hardware block. + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +#include + +#include "core.h" + +#define PINMUX_IPSR_GPSR(ipsr, fn) \ + PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr) + +#define PORT_GP_17(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ + PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ + PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ + PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ + PORT_GP_1(bank, 16, fn, sfx) + +#define PORT_GP_23(bank, fn, sfx) \ + PORT_GP_17(bank, fn, sfx), \ + PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ + PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ + PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 22, fn, sfx) + +#define PORT_GP_26(bank, fn, sfx) \ + PORT_GP_23(bank, fn, sfx), \ + PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ + PORT_GP_1(bank, 25, fn, sfx) + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_23(0, fn, sfx), \ + PORT_GP_23(1, fn, sfx), \ + PORT_GP_32(2, fn, sfx), \ + PORT_GP_17(3, fn, sfx), \ + PORT_GP_1(3, 27, fn, sfx), \ + PORT_GP_1(3, 28, fn, sfx), \ + PORT_GP_1(3, 29, fn, sfx), \ + PORT_GP_26(4, fn, sfx), \ + PORT_GP_32(5, fn, sfx) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, FN_CLKOUT, + FN_IP0_3_0, FN_IP0_7_4, FN_IP0_11_8, FN_IP0_15_12, FN_IP0_19_16, + FN_IP0_23_20, FN_IP0_27_24, FN_IP0_31_28, FN_MMC0_CLK_SDHI1_CLK, + FN_MMC0_CMD_SDHI1_CMD, FN_MMC0_D0_SDHI1_D0, FN_MMC0_D1_SDHI1_D1, + FN_MMC0_D2_SDHI1_D2, FN_MMC0_D3_SDHI1_D3, FN_IP1_3_0, + FN_IP1_7_4, FN_MMC0_D6, FN_MMC0_D7, + + /* GPSR1 */ + FN_IP1_11_8, FN_IP1_15_12, FN_IP1_19_16, FN_IP1_23_20, FN_IP1_27_24, + FN_IP1_31_28, FN_IP2_3_0, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12, + FN_IP2_19_16, FN_IP2_23_20, FN_IP2_27_24, FN_IP2_31_28, FN_IP3_3_0, + FN_IP3_7_4, FN_IP3_11_8, FN_IP3_15_12, FN_IP3_19_16, FN_IP3_23_20, + FN_IP3_27_24, FN_IP3_31_28, FN_IP4_3_0, + + /* GPSR2 */ + FN_IP4_7_4, FN_IP4_11_8, FN_IP4_15_12, FN_IP4_19_16, FN_IP4_23_20, + FN_IP4_27_24, FN_IP4_31_28, FN_IP5_3_0, FN_IP5_7_4, FN_IP5_11_8, + FN_IP5_15_12, FN_IP5_19_16, FN_IP5_23_20, FN_IP5_27_24, FN_IP5_31_28, + FN_IP6_3_0, FN_IP6_7_4, FN_IP6_11_8, FN_IP6_15_12, FN_IP6_19_16, + FN_IP6_23_20, FN_IP6_27_24, FN_IP6_31_28, FN_IP7_3_0, FN_IP7_7_4, + FN_IP7_11_8, FN_IP7_15_12, FN_IP7_19_16, FN_IP7_23_20, FN_IP7_27_24, + FN_IP7_31_28, FN_IP8_3_0, + + /* GPSR3 */ + FN_IP8_7_4, FN_IP8_11_8, FN_IP8_15_12, FN_IP8_19_16, FN_IP8_23_20, + FN_IP8_27_24, FN_IP8_31_28, FN_IP9_3_0, FN_IP9_7_4, FN_IP9_11_8, + FN_IP9_15_12, FN_IP9_19_16, FN_IP9_23_20, FN_IP9_27_24, FN_IP9_31_28, + FN_IP10_3_0, FN_IP10_7_4, FN_IP10_11_8, FN_IP10_15_12, FN_IP10_19_16, + + /* GPSR4 */ + FN_IP10_23_20, FN_IP10_27_24, FN_IP10_31_28, FN_IP11_3_0, FN_IP11_7_4, + FN_IP11_11_8, FN_IP11_15_12, FN_IP11_19_16, FN_IP11_23_20, + FN_IP11_27_24, FN_IP11_31_28, FN_IP12_3_0, FN_IP12_7_4, FN_IP12_11_8, + FN_IP12_15_12, FN_IP12_19_16, FN_IP12_23_20, FN_IP12_27_24, + FN_IP12_31_28, FN_IP13_3_0, FN_IP13_7_4, FN_IP13_11_8, FN_IP13_15_12, + FN_IP13_19_16, FN_IP13_23_20, FN_IP13_27_24, + + /* GPSR5 */ + FN_IP13_31_28, FN_IP14_3_0, FN_IP14_7_4, FN_IP14_11_8, FN_IP14_15_12, + FN_IP14_19_16, FN_IP14_23_20, FN_IP14_27_24, FN_IP14_31_28, + FN_IP15_3_0, FN_IP15_7_4, FN_IP15_11_8, FN_IP15_15_12, FN_IP15_19_16, + FN_IP15_23_20, FN_IP15_27_24, FN_IP15_31_28, FN_IP16_3_0, FN_IP16_7_4, + FN_IP16_11_8, FN_IP16_15_12, FN_IP16_19_16, FN_IP16_23_20, + FN_IP16_27_24, FN_IP16_31_28, FN_IP17_3_0, FN_IP17_7_4, FN_IP17_11_8, + FN_IP17_15_12, FN_IP17_19_16, FN_IP17_23_20, FN_IP17_27_24, + + /* IPSR0 */ + FN_SD0_CLK, FN_SSI_SCK1_C, FN_RX3_C, + FN_SD0_CMD, FN_SSI_WS1_C, FN_TX3_C, + FN_SD0_DAT0, FN_SSI_SDATA1_C, FN_RX4_E, + FN_SD0_DAT1, FN_SSI_SCK0129_B, FN_TX4_E, + FN_SD0_DAT2, FN_SSI_WS0129_B, FN_RX5_E, + FN_SD0_DAT3, FN_SSI_SDATA0_B, FN_TX5_E, + FN_SD0_CD, FN_CAN0_RX_A, + FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, + + /* IPSR1 */ + FN_MMC0_D4, FN_SD1_CD, + FN_MMC0_D5, FN_SD1_WP, + FN_D0, FN_SCL3_B, FN_RX5_B, FN_IRQ4, FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B, + FN_D1, FN_SDA3_B, FN_TX5_B, FN_MSIOF2_TXD_C, FN_SSI_WS5_B, + FN_D2, FN_RX4_B, FN_SCL0_D, FN_PWM1_C, FN_MSIOF2_SCK_C, FN_SSI_SCK5_B, + FN_D3, FN_TX4_B, FN_SDA0_D, FN_PWM0_A, FN_MSIOF2_SYNC_C, + FN_D4, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C, + FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, + + /* IPSR2 */ + FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, + FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C, + FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C, + FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D, + FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B, + FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B, + FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, FN_CAN_CLK_C, + FN_D13, FN_MSIOF2_SYNC_A, FN_RX4_C, + + /* IPSR3 */ + FN_D14, FN_MSIOF2_SS1, FN_TX4_C, FN_CAN1_RX_B, FN_AVB_AVTP_CAPTURE_A, + FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, FN_CAN1_TX_B, FN_IRQ2, FN_AVB_AVTP_MATCH_A, + FN_QSPI0_SPCLK, FN_WE0_N, + FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N, + FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N, + FN_QSPI0_IO2, FN_CS0_N, + FN_QSPI0_IO3, FN_RD_N, + FN_QSPI0_SSL, FN_WE1_N, + + /* IPSR4 */ + FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, + FN_DU0_DR0, FN_RX5_C, FN_SCL2_D, FN_A0, + FN_DU0_DR1, FN_TX5_C, FN_SDA2_D, FN_A1, + FN_DU0_DR2, FN_RX0_D, FN_SCL0_E, FN_A2, + FN_DU0_DR3, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, FN_A3, + FN_DU0_DR4, FN_RX1_D, FN_A4, + FN_DU0_DR5, FN_TX1_D, FN_PWM1_B, FN_A5, + FN_DU0_DR6, FN_RX2_C, FN_A6, + + /* IPSR5 */ + FN_DU0_DR7, FN_TX2_C, FN_PWM2_B, FN_A7, + FN_DU0_DG0, FN_RX3_B, FN_SCL3_D, FN_A8, + FN_DU0_DG1, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, FN_A9, + FN_DU0_DG2, FN_RX4_D, FN_A10, + FN_DU0_DG3, FN_TX4_D, FN_PWM4_B, FN_A11, + FN_DU0_DG4, FN_HRX0_A, FN_A12, + FN_DU0_DG5, FN_HTX0_A, FN_PWM5_B, FN_A13, + FN_DU0_DG6, FN_HRX1_C, FN_A14, + + /* IPSR6 */ + FN_DU0_DG7, FN_HTX1_C, FN_PWM6_B, FN_A15, + FN_DU0_DB0, FN_SCL4_D, FN_CAN0_RX_C, FN_A16, + FN_DU0_DB1, FN_SDA4_D, FN_CAN0_TX_C, FN_A17, + FN_DU0_DB2, FN_HCTS0_N, FN_A18, + FN_DU0_DB3, FN_HRTS0_N, FN_A19, + FN_DU0_DB4, FN_HCTS1_N_C, FN_A20, + FN_DU0_DB5, FN_HRTS1_N_C, FN_A21, + FN_DU0_DB6, FN_A22, + + /* IPSR7 */ + FN_DU0_DB7, FN_A23, + FN_DU0_DOTCLKIN, FN_A24, + FN_DU0_DOTCLKOUT0, FN_A25, + FN_DU0_DOTCLKOUT1, FN_MSIOF2_RXD_B, FN_CS1_N_A26, + FN_DU0_EXHSYNC_DU0_HSYNC, FN_MSIOF2_TXD_B, FN_DREQ0_N, + FN_DU0_EXVSYNC_DU0_VSYNC, FN_MSIOF2_SYNC_B, FN_DACK0, + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_MSIOF2_SCK_B, FN_DRACK0, + FN_DU0_DISP, FN_CAN1_RX_C, + + /* IPSR8 */ + FN_DU0_CDE, FN_CAN1_TX_C, + FN_VI1_CLK, FN_AVB_RX_CLK, FN_ETH_REF_CLK, + FN_VI1_DATA0, FN_AVB_RX_DV, FN_ETH_CRS_DV, + FN_VI1_DATA1, FN_AVB_RXD0, FN_ETH_RXD0, + FN_VI1_DATA2, FN_AVB_RXD1, FN_ETH_RXD1, + FN_VI1_DATA3, FN_AVB_RXD2, FN_ETH_MDIO, + FN_VI1_DATA4, FN_AVB_RXD3, FN_ETH_RX_ER, + FN_VI1_DATA5, FN_AVB_RXD4, FN_ETH_LINK, + + /* IPSR9 */ + FN_VI1_DATA6, FN_AVB_RXD5, FN_ETH_TXD1, + FN_VI1_DATA7, FN_AVB_RXD6, FN_ETH_TX_EN, + FN_VI1_CLKENB, FN_SCL3_A, FN_AVB_RXD7, FN_ETH_MAGIC, + FN_VI1_FIELD, FN_SDA3_A, FN_AVB_RX_ER, FN_ETH_TXD0, + FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, FN_AVB_GTXREFCLK, FN_ETH_MDC, + FN_VI1_VSYNC_N, FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_CLK, + FN_VI1_DATA8, FN_SCL2_B, FN_AVB_TX_EN, + FN_VI1_DATA9, FN_SDA2_B, FN_AVB_TXD0, + + /* IPSR10 */ + FN_VI1_DATA10, FN_CAN0_RX_B, FN_AVB_TXD1, + FN_VI1_DATA11, FN_CAN0_TX_B, FN_AVB_TXD2, + FN_AVB_TXD3, FN_AUDIO_CLKA_B, FN_SSI_SCK1_D, FN_RX5_F, FN_MSIOF0_RXD_B, + FN_AVB_TXD4, FN_AUDIO_CLKB_B, FN_SSI_WS1_D, FN_TX5_F, FN_MSIOF0_TXD_B, + FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, FN_SSI_SDATA1_D, FN_MSIOF0_SCK_B, + FN_SCL0_A, FN_RX0_C, FN_PWM5_A, FN_TCLK1_B, FN_AVB_TXD6, FN_CAN1_RX_D, FN_MSIOF0_SYNC_B, + FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK, FN_CAN1_TX_D, FN_DVC_MUTE, + FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, FN_SSI_SCK6_B, FN_VI0_G0, + + /* IPSR11 */ + FN_SDA1_A, FN_TX4_A, FN_DU1_DR1, FN_SSI_WS6_B, FN_VI0_G1, + FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2, + FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3, + FN_MSIOF0_SCK_A, FN_IRQ0, FN_DU1_DR4, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4, + FN_MSIOF0_SYNC_A, FN_PWM1_A, FN_DU1_DR5, FN_QSPI1_IO2, FN_SSI_SDATA7_B, + FN_MSIOF0_SS1_A, FN_DU1_DR6, FN_QSPI1_IO3, FN_SSI_SDATA8_B, + FN_MSIOF0_SS2_A, FN_DU1_DR7, FN_QSPI1_SSL, + FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, + + /* IPSR12 */ + FN_HTX1_A, FN_SDA4_A, FN_DU1_DG1, FN_TX0_A, + FN_HCTS1_N_A, FN_PWM2_A, FN_DU1_DG2, FN_REMOCON_B, + FN_HRTS1_N_A, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1, + FN_SD2_CLK, FN_HSCK1, FN_DU1_DG4, FN_SSI_SCK1_B, + FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5, FN_SSI_SCK2_B, FN_PWM3_A, + FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6, FN_SSI_SDATA1_B, + FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B, + FN_SD2_DAT2, FN_RX2_A, FN_DU1_DB0, FN_SSI_SDATA2_B, + + /* IPSR13 */ + FN_SD2_DAT3, FN_TX2_A, FN_DU1_DB1, FN_SSI_WS9_B, + FN_SD2_CD, FN_SCIF2_SCK_A, FN_DU1_DB2, FN_SSI_SCK9_B, + FN_SD2_WP, FN_SCIF3_SCK, FN_DU1_DB3, FN_SSI_SDATA9_B, + FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4, FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B, + FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B, + FN_SCL2_A, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C, FN_SSI_SCK4_B, + FN_SDA2_A, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, + FN_SSI_SCK5_A, FN_DU1_DOTCLKOUT1, + + /* IPSR14 */ + FN_SSI_WS5_A, FN_SCL3_C, FN_DU1_DOTCLKIN, + FN_SSI_SDATA5_A, FN_SDA3_C, FN_DU1_DOTCLKOUT0, + FN_SSI_SCK6_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, + FN_SSI_WS6_A, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC, + FN_SSI_SDATA6_A, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC, + FN_SSI_SCK78_A, FN_SDA4_E, FN_DU1_DISP, + FN_SSI_WS78_A, FN_SCL4_E, FN_DU1_CDE, + FN_SSI_SDATA7_A, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_VI0_G5, + + /* IPSR15 */ + FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, FN_VI0_G6, + FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, FN_VI0_G7, + FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, FN_VI0_R0, + FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, FN_DACK1, FN_VI0_R1, + FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, FN_CAN1_RX_A, FN_DREQ1_N, FN_VI0_R2, + FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, FN_CAN1_TX_A, FN_DREQ2_N, FN_VI0_R3, + FN_SSI_SCK4_A, FN_AVB_MAGIC, FN_VI0_R4, + FN_SSI_WS4_A, FN_AVB_PHY_INT, FN_VI0_R5, + + /* IPSR16 */ + FN_SSI_SDATA4_A, FN_AVB_CRS, FN_VI0_R6, + FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A, FN_DACK2, FN_VI0_CLK, FN_AVB_COL, + FN_SSI_SDATA8_A, FN_RX1_B, FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7, + FN_SSI_WS1_A, FN_TX1_B, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0, + FN_SSI_SDATA1_A, FN_HRX1_B, FN_VI0_DATA1_VI0_B1, + FN_SSI_SCK2_A, FN_HTX1_B, FN_AVB_TXD7, FN_VI0_DATA2_VI0_B2, + FN_SSI_WS2_A, FN_HCTS1_N_B, FN_AVB_TX_ER, FN_VI0_DATA3_VI0_B3, + FN_SSI_SDATA2_A, FN_HRTS1_N_B, FN_VI0_DATA4_VI0_B4, + + /* IPSR17 */ + FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, FN_EX_WAIT1, FN_VI0_DATA5_VI0_B5, + FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, FN_VI0_DATA6_VI0_B6, + FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, FN_VI0_DATA7_VI0_B7, + FN_AUDIO_CLKA_A, FN_SCL0_B, FN_VI0_CLKENB, + FN_AUDIO_CLKB_A, FN_SDA0_B, FN_VI0_FIELD, + FN_AUDIO_CLKC_A, FN_SCL4_B, FN_VI0_HSYNC_N, + FN_AUDIO_CLKOUT_A, FN_SDA4_B, FN_VI0_VSYNC_N, + + /* MOD_SEL0 */ + FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3, + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, FN_SEL_I2C04_4, + FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, FN_SEL_I2C03_4, + FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, + FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, + FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, FN_SEL_I2C00_4, + FN_SEL_AVB_0, FN_SEL_AVB_1, + + /* MOD_SEL1 */ + FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, FN_SEL_SCIF5_4, FN_SEL_SCIF5_5, + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, FN_SEL_SCIF4_4, + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, + FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1, + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2, + FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, + FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1, + FN_SEL_RCN_0, FN_SEL_RCN_1, + FN_SEL_TMU2_0, FN_SEL_TMU2_1, + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, + + /* MOD_SEL2 */ + FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2, + FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2, + FN_SEL_SSI9_0, FN_SEL_SSI9_1, + FN_SEL_SSI8_0, FN_SEL_SSI8_1, + FN_SEL_SSI7_0, FN_SEL_SSI7_1, + FN_SEL_SSI6_0, FN_SEL_SSI6_1, + FN_SEL_SSI5_0, FN_SEL_SSI5_1, + FN_SEL_SSI4_0, FN_SEL_SSI4_1, + FN_SEL_SSI2_0, FN_SEL_SSI2_1, + FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3, + FN_SEL_SSI0_0, FN_SEL_SSI0_1, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK, + CLKOUT_MARK, MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK, + MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK, + MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, MMC0_D6_MARK, + MMC0_D7_MARK, + + /* IPSR0 */ + SD0_CLK_MARK, SSI_SCK1_C_MARK, RX3_C_MARK, + SD0_CMD_MARK, SSI_WS1_C_MARK, TX3_C_MARK, + SD0_DAT0_MARK, SSI_SDATA1_C_MARK, RX4_E_MARK, + SD0_DAT1_MARK, SSI_SCK0129_B_MARK, TX4_E_MARK, + SD0_DAT2_MARK, SSI_WS0129_B_MARK, RX5_E_MARK, + SD0_DAT3_MARK, SSI_SDATA0_B_MARK, TX5_E_MARK, + SD0_CD_MARK, CAN0_RX_A_MARK, + SD0_WP_MARK, IRQ7_MARK, CAN0_TX_A_MARK, + + /* IPSR1 */ + MMC0_D4_MARK, SD1_CD_MARK, + MMC0_D5_MARK, SD1_WP_MARK, + D0_MARK, SCL3_B_MARK, RX5_B_MARK, IRQ4_MARK, MSIOF2_RXD_C_MARK, SSI_SDATA5_B_MARK, + D1_MARK, SDA3_B_MARK, TX5_B_MARK, MSIOF2_TXD_C_MARK, SSI_WS5_B_MARK, + D2_MARK, RX4_B_MARK, SCL0_D_MARK, PWM1_C_MARK, MSIOF2_SCK_C_MARK, SSI_SCK5_B_MARK, + D3_MARK, TX4_B_MARK, SDA0_D_MARK, PWM0_A_MARK, MSIOF2_SYNC_C_MARK, + D4_MARK, IRQ3_MARK, TCLK1_A_MARK, PWM6_C_MARK, + D5_MARK, HRX2_MARK, SCL1_B_MARK, PWM2_C_MARK, TCLK2_B_MARK, + + /* IPSR2 */ + D6_MARK, HTX2_MARK, SDA1_B_MARK, PWM4_C_MARK, + D7_MARK, HSCK2_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK, + D8_MARK, HCTS2_N_MARK, RX1_C_MARK, SCL1_D_MARK, PWM3_C_MARK, + D9_MARK, HRTS2_N_MARK, TX1_C_MARK, SDA1_D_MARK, + D10_MARK, MSIOF2_RXD_A_MARK, HRX0_B_MARK, + D11_MARK, MSIOF2_TXD_A_MARK, HTX0_B_MARK, + D12_MARK, MSIOF2_SCK_A_MARK, HSCK0_MARK, CAN_CLK_C_MARK, + D13_MARK, MSIOF2_SYNC_A_MARK, RX4_C_MARK, + + /* IPSR3 */ + D14_MARK, MSIOF2_SS1_MARK, TX4_C_MARK, CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_A_MARK, + D15_MARK, MSIOF2_SS2_MARK, PWM4_A_MARK, CAN1_TX_B_MARK, IRQ2_MARK, AVB_AVTP_MATCH_A_MARK, + QSPI0_SPCLK_MARK, WE0_N_MARK, + QSPI0_MOSI_QSPI0_IO0_MARK, BS_N_MARK, + QSPI0_MISO_QSPI0_IO1_MARK, RD_WR_N_MARK, + QSPI0_IO2_MARK, CS0_N_MARK, + QSPI0_IO3_MARK, RD_N_MARK, + QSPI0_SSL_MARK, WE1_N_MARK, + + /* IPSR4 */ + EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_A_MARK, + DU0_DR0_MARK, RX5_C_MARK, SCL2_D_MARK, A0_MARK, + DU0_DR1_MARK, TX5_C_MARK, SDA2_D_MARK, A1_MARK, + DU0_DR2_MARK, RX0_D_MARK, SCL0_E_MARK, A2_MARK, + DU0_DR3_MARK, TX0_D_MARK, SDA0_E_MARK, PWM0_B_MARK, A3_MARK, + DU0_DR4_MARK, RX1_D_MARK, A4_MARK, + DU0_DR5_MARK, TX1_D_MARK, PWM1_B_MARK, A5_MARK, + DU0_DR6_MARK, RX2_C_MARK, A6_MARK, + + /* IPSR5 */ + DU0_DR7_MARK, TX2_C_MARK, PWM2_B_MARK, A7_MARK, + DU0_DG0_MARK, RX3_B_MARK, SCL3_D_MARK, A8_MARK, + DU0_DG1_MARK, TX3_B_MARK, SDA3_D_MARK, PWM3_B_MARK, A9_MARK, + DU0_DG2_MARK, RX4_D_MARK, A10_MARK, + DU0_DG3_MARK, TX4_D_MARK, PWM4_B_MARK, A11_MARK, + DU0_DG4_MARK, HRX0_A_MARK, A12_MARK, + DU0_DG5_MARK, HTX0_A_MARK, PWM5_B_MARK, A13_MARK, + DU0_DG6_MARK, HRX1_C_MARK, A14_MARK, + + /* IPSR6 */ + DU0_DG7_MARK, HTX1_C_MARK, PWM6_B_MARK, A15_MARK, + DU0_DB0_MARK, SCL4_D_MARK, CAN0_RX_C_MARK, A16_MARK, + DU0_DB1_MARK, SDA4_D_MARK, CAN0_TX_C_MARK, A17_MARK, + DU0_DB2_MARK, HCTS0_N_MARK, A18_MARK, + DU0_DB3_MARK, HRTS0_N_MARK, A19_MARK, + DU0_DB4_MARK, HCTS1_N_C_MARK, A20_MARK, + DU0_DB5_MARK, HRTS1_N_C_MARK, A21_MARK, + DU0_DB6_MARK, A22_MARK, + + /* IPSR7 */ + DU0_DB7_MARK, A23_MARK, + DU0_DOTCLKIN_MARK, A24_MARK, + DU0_DOTCLKOUT0_MARK, A25_MARK, + DU0_DOTCLKOUT1_MARK, MSIOF2_RXD_B_MARK, CS1_N_A26_MARK, + DU0_EXHSYNC_DU0_HSYNC_MARK, MSIOF2_TXD_B_MARK, DREQ0_N_MARK, + DU0_EXVSYNC_DU0_VSYNC_MARK, MSIOF2_SYNC_B_MARK, DACK0_MARK, + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, MSIOF2_SCK_B_MARK, DRACK0_MARK, + DU0_DISP_MARK, CAN1_RX_C_MARK, + + /* IPSR8 */ + DU0_CDE_MARK, CAN1_TX_C_MARK, + VI1_CLK_MARK, AVB_RX_CLK_MARK, ETH_REF_CLK_MARK, + VI1_DATA0_MARK, AVB_RX_DV_MARK, ETH_CRS_DV_MARK, + VI1_DATA1_MARK, AVB_RXD0_MARK, ETH_RXD0_MARK, + VI1_DATA2_MARK, AVB_RXD1_MARK, ETH_RXD1_MARK, + VI1_DATA3_MARK, AVB_RXD2_MARK, ETH_MDIO_MARK, + VI1_DATA4_MARK, AVB_RXD3_MARK, ETH_RX_ER_MARK, + VI1_DATA5_MARK, AVB_RXD4_MARK, ETH_LINK_MARK, + + /* IPSR9 */ + VI1_DATA6_MARK, AVB_RXD5_MARK, ETH_TXD1_MARK, + VI1_DATA7_MARK, AVB_RXD6_MARK, ETH_TX_EN_MARK, + VI1_CLKENB_MARK, SCL3_A_MARK, AVB_RXD7_MARK, ETH_MAGIC_MARK, + VI1_FIELD_MARK, SDA3_A_MARK, AVB_RX_ER_MARK, ETH_TXD0_MARK, + VI1_HSYNC_N_MARK, RX0_B_MARK, SCL0_C_MARK, AVB_GTXREFCLK_MARK, ETH_MDC_MARK, + VI1_VSYNC_N_MARK, TX0_B_MARK, SDA0_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_CLK_MARK, + VI1_DATA8_MARK, SCL2_B_MARK, AVB_TX_EN_MARK, + VI1_DATA9_MARK, SDA2_B_MARK, AVB_TXD0_MARK, + + /* IPSR10 */ + VI1_DATA10_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, + VI1_DATA11_MARK, CAN0_TX_B_MARK, AVB_TXD2_MARK, + AVB_TXD3_MARK, AUDIO_CLKA_B_MARK, SSI_SCK1_D_MARK, RX5_F_MARK, MSIOF0_RXD_B_MARK, + AVB_TXD4_MARK, AUDIO_CLKB_B_MARK, SSI_WS1_D_MARK, TX5_F_MARK, MSIOF0_TXD_B_MARK, + AVB_TXD5_MARK, SCIF_CLK_B_MARK, AUDIO_CLKC_B_MARK, SSI_SDATA1_D_MARK, MSIOF0_SCK_B_MARK, + SCL0_A_MARK, RX0_C_MARK, PWM5_A_MARK, TCLK1_B_MARK, AVB_TXD6_MARK, CAN1_RX_D_MARK, MSIOF0_SYNC_B_MARK, + SDA0_A_MARK, TX0_C_MARK, IRQ5_MARK, CAN_CLK_A_MARK, AVB_GTX_CLK_MARK, CAN1_TX_D_MARK, DVC_MUTE_MARK, + SCL1_A_MARK, RX4_A_MARK, PWM5_D_MARK, DU1_DR0_MARK, SSI_SCK6_B_MARK, VI0_G0_MARK, + + /* IPSR11 */ + SDA1_A_MARK, TX4_A_MARK, DU1_DR1_MARK, SSI_WS6_B_MARK, VI0_G1_MARK, + MSIOF0_RXD_A_MARK, RX5_A_MARK, SCL2_C_MARK, DU1_DR2_MARK, QSPI1_MOSI_QSPI1_IO0_MARK, SSI_SDATA6_B_MARK, VI0_G2_MARK, + MSIOF0_TXD_A_MARK, TX5_A_MARK, SDA2_C_MARK, DU1_DR3_MARK, QSPI1_MISO_QSPI1_IO1_MARK, SSI_WS78_B_MARK, VI0_G3_MARK, + MSIOF0_SCK_A_MARK, IRQ0_MARK, DU1_DR4_MARK, QSPI1_SPCLK_MARK, SSI_SCK78_B_MARK, VI0_G4_MARK, + MSIOF0_SYNC_A_MARK, PWM1_A_MARK, DU1_DR5_MARK, QSPI1_IO2_MARK, SSI_SDATA7_B_MARK, + MSIOF0_SS1_A_MARK, DU1_DR6_MARK, QSPI1_IO3_MARK, SSI_SDATA8_B_MARK, + MSIOF0_SS2_A_MARK, DU1_DR7_MARK, QSPI1_SSL_MARK, + HRX1_A_MARK, SCL4_A_MARK, PWM6_A_MARK, DU1_DG0_MARK, RX0_A_MARK, + + /* IPSR12 */ + HTX1_A_MARK, SDA4_A_MARK, DU1_DG1_MARK, TX0_A_MARK, + HCTS1_N_A_MARK, PWM2_A_MARK, DU1_DG2_MARK, REMOCON_B_MARK, + HRTS1_N_A_MARK, DU1_DG3_MARK, SSI_WS1_B_MARK, IRQ1_MARK, + SD2_CLK_MARK, HSCK1_MARK, DU1_DG4_MARK, SSI_SCK1_B_MARK, + SD2_CMD_MARK, SCIF1_SCK_A_MARK, TCLK2_A_MARK, DU1_DG5_MARK, SSI_SCK2_B_MARK, PWM3_A_MARK, + SD2_DAT0_MARK, RX1_A_MARK, SCL1_E_MARK, DU1_DG6_MARK, SSI_SDATA1_B_MARK, + SD2_DAT1_MARK, TX1_A_MARK, SDA1_E_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK, + SD2_DAT2_MARK, RX2_A_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK, + + /* IPSR13 */ + SD2_DAT3_MARK, TX2_A_MARK, DU1_DB1_MARK, SSI_WS9_B_MARK, + SD2_CD_MARK, SCIF2_SCK_A_MARK, DU1_DB2_MARK, SSI_SCK9_B_MARK, + SD2_WP_MARK, SCIF3_SCK_MARK, DU1_DB3_MARK, SSI_SDATA9_B_MARK, + RX3_A_MARK, SCL1_C_MARK, MSIOF1_RXD_B_MARK, DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SDATA4_B_MARK, + TX3_A_MARK, SDA1_C_MARK, MSIOF1_TXD_B_MARK, DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, + SCL2_A_MARK, MSIOF1_SCK_B_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK, SSI_SCK4_B_MARK, + SDA2_A_MARK, MSIOF1_SYNC_B_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, + SSI_SCK5_A_MARK, DU1_DOTCLKOUT1_MARK, + + /* IPSR14 */ + SSI_WS5_A_MARK, SCL3_C_MARK, DU1_DOTCLKIN_MARK, + SSI_SDATA5_A_MARK, SDA3_C_MARK, DU1_DOTCLKOUT0_MARK, + SSI_SCK6_A_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, + SSI_WS6_A_MARK, SCL4_C_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, + SSI_SDATA6_A_MARK, SDA4_C_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, + SSI_SCK78_A_MARK, SDA4_E_MARK, DU1_DISP_MARK, + SSI_WS78_A_MARK, SCL4_E_MARK, DU1_CDE_MARK, + SSI_SDATA7_A_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, VI0_G5_MARK, + + /* IPSR15 */ + SSI_SCK0129_A_MARK, MSIOF1_RXD_A_MARK, RX5_D_MARK, VI0_G6_MARK, + SSI_WS0129_A_MARK, MSIOF1_TXD_A_MARK, TX5_D_MARK, VI0_G7_MARK, + SSI_SDATA0_A_MARK, MSIOF1_SYNC_A_MARK, PWM0_C_MARK, VI0_R0_MARK, + SSI_SCK34_MARK, MSIOF1_SCK_A_MARK, AVB_MDC_MARK, DACK1_MARK, VI0_R1_MARK, + SSI_WS34_MARK, MSIOF1_SS1_A_MARK, AVB_MDIO_MARK, CAN1_RX_A_MARK, DREQ1_N_MARK, VI0_R2_MARK, + SSI_SDATA3_MARK, MSIOF1_SS2_A_MARK, AVB_LINK_MARK, CAN1_TX_A_MARK, DREQ2_N_MARK, VI0_R3_MARK, + SSI_SCK4_A_MARK, AVB_MAGIC_MARK, VI0_R4_MARK, + SSI_WS4_A_MARK, AVB_PHY_INT_MARK, VI0_R5_MARK, + + /* IPSR16 */ + SSI_SDATA4_A_MARK, AVB_CRS_MARK, VI0_R6_MARK, + SSI_SCK1_A_MARK, SCIF1_SCK_B_MARK, PWM1_D_MARK, IRQ9_MARK, REMOCON_A_MARK, DACK2_MARK, VI0_CLK_MARK, AVB_COL_MARK, + SSI_SDATA8_A_MARK, RX1_B_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_B_MARK, VI0_R7_MARK, + SSI_WS1_A_MARK, TX1_B_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_B_MARK, VI0_DATA0_VI0_B0_MARK, + SSI_SDATA1_A_MARK, HRX1_B_MARK, VI0_DATA1_VI0_B1_MARK, + SSI_SCK2_A_MARK, HTX1_B_MARK, AVB_TXD7_MARK, VI0_DATA2_VI0_B2_MARK, + SSI_WS2_A_MARK, HCTS1_N_B_MARK, AVB_TX_ER_MARK, VI0_DATA3_VI0_B3_MARK, + SSI_SDATA2_A_MARK, HRTS1_N_B_MARK, VI0_DATA4_VI0_B4_MARK, + + /* IPSR17 */ + SSI_SCK9_A_MARK, RX2_B_MARK, SCL3_E_MARK, EX_WAIT1_MARK, VI0_DATA5_VI0_B5_MARK, + SSI_WS9_A_MARK, TX2_B_MARK, SDA3_E_MARK, VI0_DATA6_VI0_B6_MARK, + SSI_SDATA9_A_MARK, SCIF2_SCK_B_MARK, PWM2_D_MARK, VI0_DATA7_VI0_B7_MARK, + AUDIO_CLKA_A_MARK, SCL0_B_MARK, VI0_CLKENB_MARK, + AUDIO_CLKB_A_MARK, SDA0_B_MARK, VI0_FIELD_MARK, + AUDIO_CLKC_A_MARK, SCL4_B_MARK, VI0_HSYNC_N_MARK, + AUDIO_CLKOUT_A_MARK, SDA4_B_MARK, VI0_VSYNC_N_MARK, + + PINMUX_MARK_END, +}; + +static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_SINGLE(USB0_PWEN), + PINMUX_SINGLE(USB0_OVC), + PINMUX_SINGLE(USB1_PWEN), + PINMUX_SINGLE(USB1_OVC), + PINMUX_SINGLE(CLKOUT), + PINMUX_SINGLE(MMC0_CLK_SDHI1_CLK), + PINMUX_SINGLE(MMC0_CMD_SDHI1_CMD), + PINMUX_SINGLE(MMC0_D0_SDHI1_D0), + PINMUX_SINGLE(MMC0_D1_SDHI1_D1), + PINMUX_SINGLE(MMC0_D2_SDHI1_D2), + PINMUX_SINGLE(MMC0_D3_SDHI1_D3), + PINMUX_SINGLE(MMC0_D6), + PINMUX_SINGLE(MMC0_D7), + + /* IPSR0 */ + PINMUX_IPSR_GPSR(IP0_3_0, SD0_CLK), + PINMUX_IPSR_MSEL(IP0_3_0, SSI_SCK1_C, SEL_SSI1_2), + PINMUX_IPSR_MSEL(IP0_3_0, RX3_C, SEL_SCIF3_2), + PINMUX_IPSR_GPSR(IP0_7_4, SD0_CMD), + PINMUX_IPSR_MSEL(IP0_7_4, SSI_WS1_C, SEL_SSI1_2), + PINMUX_IPSR_MSEL(IP0_7_4, TX3_C, SEL_SCIF3_2), + PINMUX_IPSR_GPSR(IP0_11_8, SD0_DAT0), + PINMUX_IPSR_MSEL(IP0_11_8, SSI_SDATA1_C, SEL_SSI1_2), + PINMUX_IPSR_MSEL(IP0_11_8, RX4_E, SEL_SCIF4_4), + PINMUX_IPSR_GPSR(IP0_15_12, SD0_DAT1), + PINMUX_IPSR_MSEL(IP0_15_12, SSI_SCK0129_B, SEL_SSI0_1), + PINMUX_IPSR_MSEL(IP0_15_12, TX4_E, SEL_SCIF4_4), + PINMUX_IPSR_GPSR(IP0_19_16, SD0_DAT2), + PINMUX_IPSR_MSEL(IP0_19_16, SSI_WS0129_B, SEL_SSI0_1), + PINMUX_IPSR_MSEL(IP0_19_16, RX5_E, SEL_SCIF5_4), + PINMUX_IPSR_GPSR(IP0_23_20, SD0_DAT3), + PINMUX_IPSR_MSEL(IP0_23_20, SSI_SDATA0_B, SEL_SSI0_1), + PINMUX_IPSR_MSEL(IP0_23_20, TX5_E, SEL_SCIF5_4), + PINMUX_IPSR_GPSR(IP0_27_24, SD0_CD), + PINMUX_IPSR_MSEL(IP0_27_24, CAN0_RX_A, SEL_CAN0_0), + PINMUX_IPSR_GPSR(IP0_31_28, SD0_WP), + PINMUX_IPSR_GPSR(IP0_31_28, IRQ7), + PINMUX_IPSR_MSEL(IP0_31_28, CAN0_TX_A, SEL_CAN0_0), + + /* IPSR1 */ + PINMUX_IPSR_GPSR(IP1_3_0, MMC0_D4), + PINMUX_IPSR_GPSR(IP1_3_0, SD1_CD), + PINMUX_IPSR_GPSR(IP1_7_4, MMC0_D5), + PINMUX_IPSR_GPSR(IP1_7_4, SD1_WP), + PINMUX_IPSR_GPSR(IP1_11_8, D0), + PINMUX_IPSR_MSEL(IP1_11_8, SCL3_B, SEL_I2C03_1), + PINMUX_IPSR_MSEL(IP1_11_8, RX5_B, SEL_SCIF5_1), + PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), + PINMUX_IPSR_MSEL(IP1_11_8, MSIOF2_RXD_C, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL(IP1_11_8, SSI_SDATA5_B, SEL_SSI5_1), + PINMUX_IPSR_GPSR(IP1_15_12, D1), + PINMUX_IPSR_MSEL(IP1_15_12, SDA3_B, SEL_I2C03_1), + PINMUX_IPSR_MSEL(IP1_15_12, TX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MSEL(IP1_15_12, MSIOF2_TXD_C, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL(IP1_15_12, SSI_WS5_B, SEL_SSI5_1), + PINMUX_IPSR_GPSR(IP1_19_16, D2), + PINMUX_IPSR_MSEL(IP1_19_16, RX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MSEL(IP1_19_16, SCL0_D, SEL_I2C00_3), + PINMUX_IPSR_GPSR(IP1_19_16, PWM1_C), + PINMUX_IPSR_MSEL(IP1_19_16, MSIOF2_SCK_C, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL(IP1_19_16, SSI_SCK5_B, SEL_SSI5_1), + PINMUX_IPSR_GPSR(IP1_23_20, D3), + PINMUX_IPSR_MSEL(IP1_23_20, TX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MSEL(IP1_23_20, SDA0_D, SEL_I2C00_3), + PINMUX_IPSR_GPSR(IP1_23_20, PWM0_A), + PINMUX_IPSR_MSEL(IP1_23_20, MSIOF2_SYNC_C, SEL_MSIOF2_2), + PINMUX_IPSR_GPSR(IP1_27_24, D4), + PINMUX_IPSR_GPSR(IP1_27_24, IRQ3), + PINMUX_IPSR_MSEL(IP1_27_24, TCLK1_A, SEL_TMU1_0), + PINMUX_IPSR_GPSR(IP1_27_24, PWM6_C), + PINMUX_IPSR_GPSR(IP1_31_28, D5), + PINMUX_IPSR_GPSR(IP1_31_28, HRX2), + PINMUX_IPSR_MSEL(IP1_31_28, SCL1_B, SEL_I2C01_1), + PINMUX_IPSR_GPSR(IP1_31_28, PWM2_C), + PINMUX_IPSR_MSEL(IP1_31_28, TCLK2_B, SEL_TMU2_1), + + /* IPSR2 */ + PINMUX_IPSR_GPSR(IP2_3_0, D6), + PINMUX_IPSR_GPSR(IP2_3_0, HTX2), + PINMUX_IPSR_MSEL(IP2_3_0, SDA1_B, SEL_I2C01_1), + PINMUX_IPSR_GPSR(IP2_3_0, PWM4_C), + PINMUX_IPSR_GPSR(IP2_7_4, D7), + PINMUX_IPSR_GPSR(IP2_7_4, HSCK2), + PINMUX_IPSR_MSEL(IP2_7_4, SCIF1_SCK_C, SEL_SCIF1_2), + PINMUX_IPSR_GPSR(IP2_7_4, IRQ6), + PINMUX_IPSR_GPSR(IP2_7_4, PWM5_C), + PINMUX_IPSR_GPSR(IP2_11_8, D8), + PINMUX_IPSR_GPSR(IP2_11_8, HCTS2_N), + PINMUX_IPSR_MSEL(IP2_11_8, RX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP2_11_8, SCL1_D, SEL_I2C01_3), + PINMUX_IPSR_GPSR(IP2_11_8, PWM3_C), + PINMUX_IPSR_GPSR(IP2_15_12, D9), + PINMUX_IPSR_GPSR(IP2_15_12, HRTS2_N), + PINMUX_IPSR_MSEL(IP2_15_12, TX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP2_15_12, SDA1_D, SEL_I2C01_3), + PINMUX_IPSR_GPSR(IP2_19_16, D10), + PINMUX_IPSR_MSEL(IP2_19_16, MSIOF2_RXD_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP2_19_16, HRX0_B, SEL_HSCIF0_1), + PINMUX_IPSR_GPSR(IP2_23_20, D11), + PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_TXD_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP2_23_20, HTX0_B, SEL_HSCIF0_1), + PINMUX_IPSR_GPSR(IP2_27_24, D12), + PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SCK_A, SEL_MSIOF2_0), + PINMUX_IPSR_GPSR(IP2_27_24, HSCK0), + PINMUX_IPSR_MSEL(IP2_27_24, CAN_CLK_C, SEL_CANCLK_2), + PINMUX_IPSR_GPSR(IP2_31_28, D13), + PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP2_31_28, RX4_C, SEL_SCIF4_2), + + /* IPSR3 */ + PINMUX_IPSR_GPSR(IP3_3_0, D14), + PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SS1), + PINMUX_IPSR_MSEL(IP3_3_0, TX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP3_3_0, CAN1_RX_B, SEL_CAN1_1), + PINMUX_IPSR_MSEL(IP3_3_0, AVB_AVTP_CAPTURE_A, SEL_AVB_0), + PINMUX_IPSR_GPSR(IP3_7_4, D15), + PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_SS2), + PINMUX_IPSR_GPSR(IP3_7_4, PWM4_A), + PINMUX_IPSR_MSEL(IP3_7_4, CAN1_TX_B, SEL_CAN1_1), + PINMUX_IPSR_GPSR(IP3_7_4, IRQ2), + PINMUX_IPSR_MSEL(IP3_7_4, AVB_AVTP_MATCH_A, SEL_AVB_0), + PINMUX_IPSR_GPSR(IP3_11_8, QSPI0_SPCLK), + PINMUX_IPSR_GPSR(IP3_11_8, WE0_N), + PINMUX_IPSR_GPSR(IP3_15_12, QSPI0_MOSI_QSPI0_IO0), + PINMUX_IPSR_GPSR(IP3_15_12, BS_N), + PINMUX_IPSR_GPSR(IP3_19_16, QSPI0_MISO_QSPI0_IO1), + PINMUX_IPSR_GPSR(IP3_19_16, RD_WR_N), + PINMUX_IPSR_GPSR(IP3_23_20, QSPI0_IO2), + PINMUX_IPSR_GPSR(IP3_23_20, CS0_N), + PINMUX_IPSR_GPSR(IP3_27_24, QSPI0_IO3), + PINMUX_IPSR_GPSR(IP3_27_24, RD_N), + PINMUX_IPSR_GPSR(IP3_31_28, QSPI0_SSL), + PINMUX_IPSR_GPSR(IP3_31_28, WE1_N), + + /* IPSR4 */ + PINMUX_IPSR_GPSR(IP4_3_0, EX_WAIT0), + PINMUX_IPSR_MSEL(IP4_3_0, CAN_CLK_B, SEL_CANCLK_1), + PINMUX_IPSR_MSEL(IP4_3_0, SCIF_CLK_A, SEL_SCIFCLK_0), + PINMUX_IPSR_GPSR(IP4_7_4, DU0_DR0), + PINMUX_IPSR_MSEL(IP4_7_4, RX5_C, SEL_SCIF5_2), + PINMUX_IPSR_MSEL(IP4_7_4, SCL2_D, SEL_I2C02_3), + PINMUX_IPSR_GPSR(IP4_7_4, A0), + PINMUX_IPSR_GPSR(IP4_11_8, DU0_DR1), + PINMUX_IPSR_MSEL(IP4_11_8, TX5_C, SEL_SCIF5_2), + PINMUX_IPSR_MSEL(IP4_11_8, SDA2_D, SEL_I2C02_3), + PINMUX_IPSR_GPSR(IP4_11_8, A1), + PINMUX_IPSR_GPSR(IP4_15_12, DU0_DR2), + PINMUX_IPSR_MSEL(IP4_15_12, RX0_D, SEL_SCIF0_3), + PINMUX_IPSR_MSEL(IP4_15_12, SCL0_E, SEL_I2C00_4), + PINMUX_IPSR_GPSR(IP4_15_12, A2), + PINMUX_IPSR_GPSR(IP4_19_16, DU0_DR3), + PINMUX_IPSR_MSEL(IP4_19_16, TX0_D, SEL_SCIF0_3), + PINMUX_IPSR_MSEL(IP4_19_16, SDA0_E, SEL_I2C00_4), + PINMUX_IPSR_GPSR(IP4_19_16, PWM0_B), + PINMUX_IPSR_GPSR(IP4_19_16, A3), + PINMUX_IPSR_GPSR(IP4_23_20, DU0_DR4), + PINMUX_IPSR_MSEL(IP4_23_20, RX1_D, SEL_SCIF1_3), + PINMUX_IPSR_GPSR(IP4_23_20, A4), + PINMUX_IPSR_GPSR(IP4_27_24, DU0_DR5), + PINMUX_IPSR_MSEL(IP4_27_24, TX1_D, SEL_SCIF1_3), + PINMUX_IPSR_GPSR(IP4_27_24, PWM1_B), + PINMUX_IPSR_GPSR(IP4_27_24, A5), + PINMUX_IPSR_GPSR(IP4_31_28, DU0_DR6), + PINMUX_IPSR_MSEL(IP4_31_28, RX2_C, SEL_SCIF2_2), + PINMUX_IPSR_GPSR(IP4_31_28, A6), + + /* IPSR5 */ + PINMUX_IPSR_GPSR(IP5_3_0, DU0_DR7), + PINMUX_IPSR_MSEL(IP5_3_0, TX2_C, SEL_SCIF2_2), + PINMUX_IPSR_GPSR(IP5_3_0, PWM2_B), + PINMUX_IPSR_GPSR(IP5_3_0, A7), + PINMUX_IPSR_GPSR(IP5_7_4, DU0_DG0), + PINMUX_IPSR_MSEL(IP5_7_4, RX3_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP5_7_4, SCL3_D, SEL_I2C03_3), + PINMUX_IPSR_GPSR(IP5_7_4, A8), + PINMUX_IPSR_GPSR(IP5_11_8, DU0_DG1), + PINMUX_IPSR_MSEL(IP5_11_8, TX3_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP5_11_8, SDA3_D, SEL_I2C03_3), + PINMUX_IPSR_GPSR(IP5_11_8, PWM3_B), + PINMUX_IPSR_GPSR(IP5_11_8, A9), + PINMUX_IPSR_GPSR(IP5_15_12, DU0_DG2), + PINMUX_IPSR_MSEL(IP5_15_12, RX4_D, SEL_SCIF4_3), + PINMUX_IPSR_GPSR(IP5_15_12, A10), + PINMUX_IPSR_GPSR(IP5_19_16, DU0_DG3), + PINMUX_IPSR_MSEL(IP5_19_16, TX4_D, SEL_SCIF4_3), + PINMUX_IPSR_GPSR(IP5_19_16, PWM4_B), + PINMUX_IPSR_GPSR(IP5_19_16, A11), + PINMUX_IPSR_GPSR(IP5_23_20, DU0_DG4), + PINMUX_IPSR_MSEL(IP5_23_20, HRX0_A, SEL_HSCIF0_0), + PINMUX_IPSR_GPSR(IP5_23_20, A12), + PINMUX_IPSR_GPSR(IP5_27_24, DU0_DG5), + PINMUX_IPSR_MSEL(IP5_27_24, HTX0_A, SEL_HSCIF0_0), + PINMUX_IPSR_GPSR(IP5_27_24, PWM5_B), + PINMUX_IPSR_GPSR(IP5_27_24, A13), + PINMUX_IPSR_GPSR(IP5_31_28, DU0_DG6), + PINMUX_IPSR_MSEL(IP5_31_28, HRX1_C, SEL_HSCIF1_2), + PINMUX_IPSR_GPSR(IP5_31_28, A14), + + /* IPSR6 */ + PINMUX_IPSR_GPSR(IP6_3_0, DU0_DG7), + PINMUX_IPSR_MSEL(IP6_3_0, HTX1_C, SEL_HSCIF1_2), + PINMUX_IPSR_GPSR(IP6_3_0, PWM6_B), + PINMUX_IPSR_GPSR(IP6_3_0, A15), + PINMUX_IPSR_GPSR(IP6_7_4, DU0_DB0), + PINMUX_IPSR_MSEL(IP6_7_4, SCL4_D, SEL_I2C04_3), + PINMUX_IPSR_MSEL(IP6_7_4, CAN0_RX_C, SEL_CAN0_2), + PINMUX_IPSR_GPSR(IP6_7_4, A16), + PINMUX_IPSR_GPSR(IP6_11_8, DU0_DB1), + PINMUX_IPSR_MSEL(IP6_11_8, SDA4_D, SEL_I2C04_3), + PINMUX_IPSR_MSEL(IP6_11_8, CAN0_TX_C, SEL_CAN0_2), + PINMUX_IPSR_GPSR(IP6_11_8, A17), + PINMUX_IPSR_GPSR(IP6_15_12, DU0_DB2), + PINMUX_IPSR_GPSR(IP6_15_12, HCTS0_N), + PINMUX_IPSR_GPSR(IP6_15_12, A18), + PINMUX_IPSR_GPSR(IP6_19_16, DU0_DB3), + PINMUX_IPSR_GPSR(IP6_19_16, HRTS0_N), + PINMUX_IPSR_GPSR(IP6_19_16, A19), + PINMUX_IPSR_GPSR(IP6_23_20, DU0_DB4), + PINMUX_IPSR_MSEL(IP6_23_20, HCTS1_N_C, SEL_HSCIF1_2), + PINMUX_IPSR_GPSR(IP6_23_20, A20), + PINMUX_IPSR_GPSR(IP6_27_24, DU0_DB5), + PINMUX_IPSR_MSEL(IP6_27_24, HRTS1_N_C, SEL_HSCIF1_2), + PINMUX_IPSR_GPSR(IP6_27_24, A21), + PINMUX_IPSR_GPSR(IP6_31_28, DU0_DB6), + PINMUX_IPSR_GPSR(IP6_31_28, A22), + + /* IPSR7 */ + PINMUX_IPSR_GPSR(IP7_3_0, DU0_DB7), + PINMUX_IPSR_GPSR(IP7_3_0, A23), + PINMUX_IPSR_GPSR(IP7_7_4, DU0_DOTCLKIN), + PINMUX_IPSR_GPSR(IP7_7_4, A24), + PINMUX_IPSR_GPSR(IP7_11_8, DU0_DOTCLKOUT0), + PINMUX_IPSR_GPSR(IP7_11_8, A25), + PINMUX_IPSR_GPSR(IP7_15_12, DU0_DOTCLKOUT1), + PINMUX_IPSR_MSEL(IP7_15_12, MSIOF2_RXD_B, SEL_MSIOF2_1), + PINMUX_IPSR_GPSR(IP7_15_12, CS1_N_A26), + PINMUX_IPSR_GPSR(IP7_19_16, DU0_EXHSYNC_DU0_HSYNC), + PINMUX_IPSR_MSEL(IP7_19_16, MSIOF2_TXD_B, SEL_MSIOF2_1), + PINMUX_IPSR_GPSR(IP7_19_16, DREQ0_N), + PINMUX_IPSR_GPSR(IP7_23_20, DU0_EXVSYNC_DU0_VSYNC), + PINMUX_IPSR_MSEL(IP7_23_20, MSIOF2_SYNC_B, SEL_MSIOF2_1), + PINMUX_IPSR_GPSR(IP7_23_20, DACK0), + PINMUX_IPSR_GPSR(IP7_27_24, DU0_EXODDF_DU0_ODDF_DISP_CDE), + PINMUX_IPSR_MSEL(IP7_27_24, MSIOF2_SCK_B, SEL_MSIOF2_1), + PINMUX_IPSR_GPSR(IP7_27_24, DRACK0), + PINMUX_IPSR_GPSR(IP7_31_28, DU0_DISP), + PINMUX_IPSR_MSEL(IP7_31_28, CAN1_RX_C, SEL_CAN1_2), + + /* IPSR8 */ + PINMUX_IPSR_GPSR(IP8_3_0, DU0_CDE), + PINMUX_IPSR_MSEL(IP8_3_0, CAN1_TX_C, SEL_CAN1_2), + PINMUX_IPSR_GPSR(IP8_7_4, VI1_CLK), + PINMUX_IPSR_GPSR(IP8_7_4, AVB_RX_CLK), + PINMUX_IPSR_GPSR(IP8_7_4, ETH_REF_CLK), + PINMUX_IPSR_GPSR(IP8_11_8, VI1_DATA0), + PINMUX_IPSR_GPSR(IP8_11_8, AVB_RX_DV), + PINMUX_IPSR_GPSR(IP8_11_8, ETH_CRS_DV), + PINMUX_IPSR_GPSR(IP8_15_12, VI1_DATA1), + PINMUX_IPSR_GPSR(IP8_15_12, AVB_RXD0), + PINMUX_IPSR_GPSR(IP8_15_12, ETH_RXD0), + PINMUX_IPSR_GPSR(IP8_19_16, VI1_DATA2), + PINMUX_IPSR_GPSR(IP8_19_16, AVB_RXD1), + PINMUX_IPSR_GPSR(IP8_19_16, ETH_RXD1), + PINMUX_IPSR_GPSR(IP8_23_20, VI1_DATA3), + PINMUX_IPSR_GPSR(IP8_23_20, AVB_RXD2), + PINMUX_IPSR_GPSR(IP8_23_20, ETH_MDIO), + PINMUX_IPSR_GPSR(IP8_27_24, VI1_DATA4), + PINMUX_IPSR_GPSR(IP8_27_24, AVB_RXD3), + PINMUX_IPSR_GPSR(IP8_27_24, ETH_RX_ER), + PINMUX_IPSR_GPSR(IP8_31_28, VI1_DATA5), + PINMUX_IPSR_GPSR(IP8_31_28, AVB_RXD4), + PINMUX_IPSR_GPSR(IP8_31_28, ETH_LINK), + + /* IPSR9 */ + PINMUX_IPSR_GPSR(IP9_3_0, VI1_DATA6), + PINMUX_IPSR_GPSR(IP9_3_0, AVB_RXD5), + PINMUX_IPSR_GPSR(IP9_3_0, ETH_TXD1), + PINMUX_IPSR_GPSR(IP9_7_4, VI1_DATA7), + PINMUX_IPSR_GPSR(IP9_7_4, AVB_RXD6), + PINMUX_IPSR_GPSR(IP9_7_4, ETH_TX_EN), + PINMUX_IPSR_GPSR(IP9_11_8, VI1_CLKENB), + PINMUX_IPSR_MSEL(IP9_11_8, SCL3_A, SEL_I2C03_0), + PINMUX_IPSR_GPSR(IP9_11_8, AVB_RXD7), + PINMUX_IPSR_GPSR(IP9_11_8, ETH_MAGIC), + PINMUX_IPSR_GPSR(IP9_15_12, VI1_FIELD), + PINMUX_IPSR_MSEL(IP9_15_12, SDA3_A, SEL_I2C03_0), + PINMUX_IPSR_GPSR(IP9_15_12, AVB_RX_ER), + PINMUX_IPSR_GPSR(IP9_15_12, ETH_TXD0), + PINMUX_IPSR_GPSR(IP9_19_16, VI1_HSYNC_N), + PINMUX_IPSR_MSEL(IP9_19_16, RX0_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP9_19_16, SCL0_C, SEL_I2C00_2), + PINMUX_IPSR_GPSR(IP9_19_16, AVB_GTXREFCLK), + PINMUX_IPSR_GPSR(IP9_19_16, ETH_MDC), + PINMUX_IPSR_GPSR(IP9_23_20, VI1_VSYNC_N), + PINMUX_IPSR_MSEL(IP9_23_20, TX0_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP9_23_20, SDA0_C, SEL_I2C00_2), + PINMUX_IPSR_GPSR(IP9_23_20, AUDIO_CLKOUT_B), + PINMUX_IPSR_GPSR(IP9_23_20, AVB_TX_CLK), + PINMUX_IPSR_GPSR(IP9_27_24, VI1_DATA8), + PINMUX_IPSR_MSEL(IP9_27_24, SCL2_B, SEL_I2C02_1), + PINMUX_IPSR_GPSR(IP9_27_24, AVB_TX_EN), + PINMUX_IPSR_GPSR(IP9_31_28, VI1_DATA9), + PINMUX_IPSR_MSEL(IP9_31_28, SDA2_B, SEL_I2C02_1), + PINMUX_IPSR_GPSR(IP9_31_28, AVB_TXD0), + + /* IPSR10 */ + PINMUX_IPSR_GPSR(IP10_3_0, VI1_DATA10), + PINMUX_IPSR_MSEL(IP10_3_0, CAN0_RX_B, SEL_CAN0_1), + PINMUX_IPSR_GPSR(IP10_3_0, AVB_TXD1), + PINMUX_IPSR_GPSR(IP10_7_4, VI1_DATA11), + PINMUX_IPSR_MSEL(IP10_7_4, CAN0_TX_B, SEL_CAN0_1), + PINMUX_IPSR_GPSR(IP10_7_4, AVB_TXD2), + PINMUX_IPSR_GPSR(IP10_11_8, AVB_TXD3), + PINMUX_IPSR_MSEL(IP10_11_8, AUDIO_CLKA_B, SEL_ADGA_1), + PINMUX_IPSR_MSEL(IP10_11_8, SSI_SCK1_D, SEL_SSI1_3), + PINMUX_IPSR_MSEL(IP10_11_8, RX5_F, SEL_SCIF5_5), + PINMUX_IPSR_MSEL(IP10_11_8, MSIOF0_RXD_B, SEL_MSIOF0_1), + PINMUX_IPSR_GPSR(IP10_15_12, AVB_TXD4), + PINMUX_IPSR_MSEL(IP10_15_12, AUDIO_CLKB_B, SEL_ADGB_1), + PINMUX_IPSR_MSEL(IP10_15_12, SSI_WS1_D, SEL_SSI1_3), + PINMUX_IPSR_MSEL(IP10_15_12, TX5_F, SEL_SCIF5_5), + PINMUX_IPSR_MSEL(IP10_15_12, MSIOF0_TXD_B, SEL_MSIOF0_1), + PINMUX_IPSR_GPSR(IP10_19_16, AVB_TXD5), + PINMUX_IPSR_MSEL(IP10_19_16, SCIF_CLK_B, SEL_SCIFCLK_1), + PINMUX_IPSR_MSEL(IP10_19_16, AUDIO_CLKC_B, SEL_ADGC_1), + PINMUX_IPSR_MSEL(IP10_19_16, SSI_SDATA1_D, SEL_SSI1_3), + PINMUX_IPSR_MSEL(IP10_19_16, MSIOF0_SCK_B, SEL_MSIOF0_1), + PINMUX_IPSR_MSEL(IP10_23_20, SCL0_A, SEL_I2C00_0), + PINMUX_IPSR_MSEL(IP10_23_20, RX0_C, SEL_SCIF0_2), + PINMUX_IPSR_GPSR(IP10_23_20, PWM5_A), + PINMUX_IPSR_MSEL(IP10_23_20, TCLK1_B, SEL_TMU1_1), + PINMUX_IPSR_GPSR(IP10_23_20, AVB_TXD6), + PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_D, SEL_CAN1_3), + PINMUX_IPSR_MSEL(IP10_23_20, MSIOF0_SYNC_B, SEL_MSIOF0_1), + PINMUX_IPSR_MSEL(IP10_27_24, SDA0_A, SEL_I2C00_0), + PINMUX_IPSR_MSEL(IP10_27_24, TX0_C, SEL_SCIF0_2), + PINMUX_IPSR_GPSR(IP10_27_24, IRQ5), + PINMUX_IPSR_MSEL(IP10_27_24, CAN_CLK_A, SEL_CANCLK_0), + PINMUX_IPSR_GPSR(IP10_27_24, AVB_GTX_CLK), + PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_D, SEL_CAN1_3), + PINMUX_IPSR_GPSR(IP10_27_24, DVC_MUTE), + PINMUX_IPSR_MSEL(IP10_31_28, SCL1_A, SEL_I2C01_0), + PINMUX_IPSR_MSEL(IP10_31_28, RX4_A, SEL_SCIF4_0), + PINMUX_IPSR_GPSR(IP10_31_28, PWM5_D), + PINMUX_IPSR_GPSR(IP10_31_28, DU1_DR0), + PINMUX_IPSR_MSEL(IP10_31_28, SSI_SCK6_B, SEL_SSI6_1), + PINMUX_IPSR_GPSR(IP10_31_28, VI0_G0), + + /* IPSR11 */ + PINMUX_IPSR_MSEL(IP11_3_0, SDA1_A, SEL_I2C01_0), + PINMUX_IPSR_MSEL(IP11_3_0, TX4_A, SEL_SCIF4_0), + PINMUX_IPSR_GPSR(IP11_3_0, DU1_DR1), + PINMUX_IPSR_MSEL(IP11_3_0, SSI_WS6_B, SEL_SSI6_1), + PINMUX_IPSR_GPSR(IP11_3_0, VI0_G1), + PINMUX_IPSR_MSEL(IP11_7_4, MSIOF0_RXD_A, SEL_MSIOF0_0), + PINMUX_IPSR_MSEL(IP11_7_4, RX5_A, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP11_7_4, SCL2_C, SEL_I2C02_2), + PINMUX_IPSR_GPSR(IP11_7_4, DU1_DR2), + PINMUX_IPSR_GPSR(IP11_7_4, QSPI1_MOSI_QSPI1_IO0), + PINMUX_IPSR_MSEL(IP11_7_4, SSI_SDATA6_B, SEL_SSI6_1), + PINMUX_IPSR_GPSR(IP11_7_4, VI0_G2), + PINMUX_IPSR_MSEL(IP11_11_8, MSIOF0_TXD_A, SEL_MSIOF0_0), + PINMUX_IPSR_MSEL(IP11_11_8, TX5_A, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP11_11_8, SDA2_C, SEL_I2C02_2), + PINMUX_IPSR_GPSR(IP11_11_8, DU1_DR3), + PINMUX_IPSR_GPSR(IP11_11_8, QSPI1_MISO_QSPI1_IO1), + PINMUX_IPSR_MSEL(IP11_11_8, SSI_WS78_B, SEL_SSI7_1), + PINMUX_IPSR_GPSR(IP11_11_8, VI0_G3), + PINMUX_IPSR_MSEL(IP11_15_12, MSIOF0_SCK_A, SEL_MSIOF0_0), + PINMUX_IPSR_GPSR(IP11_15_12, IRQ0), + PINMUX_IPSR_GPSR(IP11_15_12, DU1_DR4), + PINMUX_IPSR_GPSR(IP11_15_12, QSPI1_SPCLK), + PINMUX_IPSR_MSEL(IP11_15_12, SSI_SCK78_B, SEL_SSI7_1), + PINMUX_IPSR_GPSR(IP11_15_12, VI0_G4), + PINMUX_IPSR_MSEL(IP11_19_16, MSIOF0_SYNC_A, SEL_MSIOF0_0), + PINMUX_IPSR_GPSR(IP11_19_16, PWM1_A), + PINMUX_IPSR_GPSR(IP11_19_16, DU1_DR5), + PINMUX_IPSR_GPSR(IP11_19_16, QSPI1_IO2), + PINMUX_IPSR_MSEL(IP11_19_16, SSI_SDATA7_B, SEL_SSI7_1), + PINMUX_IPSR_MSEL(IP11_23_20, MSIOF0_SS1_A, SEL_MSIOF0_0), + PINMUX_IPSR_GPSR(IP11_23_20, DU1_DR6), + PINMUX_IPSR_GPSR(IP11_23_20, QSPI1_IO3), + PINMUX_IPSR_MSEL(IP11_23_20, SSI_SDATA8_B, SEL_SSI8_1), + PINMUX_IPSR_MSEL(IP11_27_24, MSIOF0_SS2_A, SEL_MSIOF0_0), + PINMUX_IPSR_GPSR(IP11_27_24, DU1_DR7), + PINMUX_IPSR_GPSR(IP11_27_24, QSPI1_SSL), + PINMUX_IPSR_MSEL(IP11_31_28, HRX1_A, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP11_31_28, SCL4_A, SEL_I2C04_0), + PINMUX_IPSR_GPSR(IP11_31_28, PWM6_A), + PINMUX_IPSR_GPSR(IP11_31_28, DU1_DG0), + PINMUX_IPSR_MSEL(IP11_31_28, RX0_A, SEL_SCIF0_0), + + /* IPSR12 */ + PINMUX_IPSR_MSEL(IP12_3_0, HTX1_A, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP12_3_0, SDA4_A, SEL_I2C04_0), + PINMUX_IPSR_GPSR(IP12_3_0, DU1_DG1), + PINMUX_IPSR_MSEL(IP12_3_0, TX0_A, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_A, SEL_HSCIF1_0), + PINMUX_IPSR_GPSR(IP12_7_4, PWM2_A), + PINMUX_IPSR_GPSR(IP12_7_4, DU1_DG2), + PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_B, SEL_RCN_1), + PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_A, SEL_HSCIF1_0), + PINMUX_IPSR_GPSR(IP12_11_8, DU1_DG3), + PINMUX_IPSR_MSEL(IP12_11_8, SSI_WS1_B, SEL_SSI1_1), + PINMUX_IPSR_GPSR(IP12_11_8, IRQ1), + PINMUX_IPSR_GPSR(IP12_15_12, SD2_CLK), + PINMUX_IPSR_GPSR(IP12_15_12, HSCK1), + PINMUX_IPSR_GPSR(IP12_15_12, DU1_DG4), + PINMUX_IPSR_MSEL(IP12_15_12, SSI_SCK1_B, SEL_SSI1_1), + PINMUX_IPSR_GPSR(IP12_19_16, SD2_CMD), + PINMUX_IPSR_MSEL(IP12_19_16, SCIF1_SCK_A, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP12_19_16, TCLK2_A, SEL_TMU2_0), + PINMUX_IPSR_GPSR(IP12_19_16, DU1_DG5), + PINMUX_IPSR_MSEL(IP12_19_16, SSI_SCK2_B, SEL_SSI2_1), + PINMUX_IPSR_GPSR(IP12_19_16, PWM3_A), + PINMUX_IPSR_GPSR(IP12_23_20, SD2_DAT0), + PINMUX_IPSR_MSEL(IP12_23_20, RX1_A, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP12_23_20, SCL1_E, SEL_I2C01_4), + PINMUX_IPSR_GPSR(IP12_23_20, DU1_DG6), + PINMUX_IPSR_MSEL(IP12_23_20, SSI_SDATA1_B, SEL_SSI1_1), + PINMUX_IPSR_GPSR(IP12_27_24, SD2_DAT1), + PINMUX_IPSR_MSEL(IP12_27_24, TX1_A, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP12_27_24, SDA1_E, SEL_I2C01_4), + PINMUX_IPSR_GPSR(IP12_27_24, DU1_DG7), + PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS2_B, SEL_SSI2_1), + PINMUX_IPSR_GPSR(IP12_31_28, SD2_DAT2), + PINMUX_IPSR_MSEL(IP12_31_28, RX2_A, SEL_SCIF2_0), + PINMUX_IPSR_GPSR(IP12_31_28, DU1_DB0), + PINMUX_IPSR_MSEL(IP12_31_28, SSI_SDATA2_B, SEL_SSI2_1), + + /* IPSR13 */ + PINMUX_IPSR_GPSR(IP13_3_0, SD2_DAT3), + PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0), + PINMUX_IPSR_GPSR(IP13_3_0, DU1_DB1), + PINMUX_IPSR_MSEL(IP13_3_0, SSI_WS9_B, SEL_SSI9_1), + PINMUX_IPSR_GPSR(IP13_7_4, SD2_CD), + PINMUX_IPSR_MSEL(IP13_7_4, SCIF2_SCK_A, SEL_SCIF2_CLK_0), + PINMUX_IPSR_GPSR(IP13_7_4, DU1_DB2), + PINMUX_IPSR_MSEL(IP13_7_4, SSI_SCK9_B, SEL_SSI9_1), + PINMUX_IPSR_GPSR(IP13_11_8, SD2_WP), + PINMUX_IPSR_GPSR(IP13_11_8, SCIF3_SCK), + PINMUX_IPSR_GPSR(IP13_11_8, DU1_DB3), + PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA9_B, SEL_SSI9_1), + PINMUX_IPSR_MSEL(IP13_15_12, RX3_A, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP13_15_12, SCL1_C, SEL_I2C01_2), + PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_B, SEL_MSIOF1_1), + PINMUX_IPSR_GPSR(IP13_15_12, DU1_DB4), + PINMUX_IPSR_MSEL(IP13_15_12, AUDIO_CLKA_C, SEL_ADGA_2), + PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA4_B, SEL_SSI4_1), + PINMUX_IPSR_MSEL(IP13_19_16, TX3_A, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP13_19_16, SDA1_C, SEL_I2C01_2), + PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_B, SEL_MSIOF1_1), + PINMUX_IPSR_GPSR(IP13_19_16, DU1_DB5), + PINMUX_IPSR_MSEL(IP13_19_16, AUDIO_CLKB_C, SEL_ADGB_2), + PINMUX_IPSR_MSEL(IP13_19_16, SSI_WS4_B, SEL_SSI4_1), + PINMUX_IPSR_MSEL(IP13_23_20, SCL2_A, SEL_I2C02_0), + PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SCK_B, SEL_MSIOF1_1), + PINMUX_IPSR_GPSR(IP13_23_20, DU1_DB6), + PINMUX_IPSR_MSEL(IP13_23_20, AUDIO_CLKC_C, SEL_ADGC_2), + PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK4_B, SEL_SSI4_1), + PINMUX_IPSR_MSEL(IP13_27_24, SDA2_A, SEL_I2C02_0), + PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SYNC_B, SEL_MSIOF1_1), + PINMUX_IPSR_GPSR(IP13_27_24, DU1_DB7), + PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT_C), + PINMUX_IPSR_MSEL(IP13_31_28, SSI_SCK5_A, SEL_SSI5_0), + PINMUX_IPSR_GPSR(IP13_31_28, DU1_DOTCLKOUT1), + + /* IPSR14 */ + PINMUX_IPSR_MSEL(IP14_3_0, SSI_WS5_A, SEL_SSI5_0), + PINMUX_IPSR_MSEL(IP14_3_0, SCL3_C, SEL_I2C03_2), + PINMUX_IPSR_GPSR(IP14_3_0, DU1_DOTCLKIN), + PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA5_A, SEL_SSI5_0), + PINMUX_IPSR_MSEL(IP14_7_4, SDA3_C, SEL_I2C03_2), + PINMUX_IPSR_GPSR(IP14_7_4, DU1_DOTCLKOUT0), + PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK6_A, SEL_SSI6_0), + PINMUX_IPSR_GPSR(IP14_11_8, DU1_EXODDF_DU1_ODDF_DISP_CDE), + PINMUX_IPSR_MSEL(IP14_15_12, SSI_WS6_A, SEL_SSI6_0), + PINMUX_IPSR_MSEL(IP14_15_12, SCL4_C, SEL_I2C04_2), + PINMUX_IPSR_GPSR(IP14_15_12, DU1_EXHSYNC_DU1_HSYNC), + PINMUX_IPSR_MSEL(IP14_19_16, SSI_SDATA6_A, SEL_SSI6_0), + PINMUX_IPSR_MSEL(IP14_19_16, SDA4_C, SEL_I2C04_2), + PINMUX_IPSR_GPSR(IP14_19_16, DU1_EXVSYNC_DU1_VSYNC), + PINMUX_IPSR_MSEL(IP14_23_20, SSI_SCK78_A, SEL_SSI7_0), + PINMUX_IPSR_MSEL(IP14_23_20, SDA4_E, SEL_I2C04_4), + PINMUX_IPSR_GPSR(IP14_23_20, DU1_DISP), + PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS78_A, SEL_SSI7_0), + PINMUX_IPSR_MSEL(IP14_27_24, SCL4_E, SEL_I2C04_4), + PINMUX_IPSR_GPSR(IP14_27_24, DU1_CDE), + PINMUX_IPSR_MSEL(IP14_31_28, SSI_SDATA7_A, SEL_SSI7_0), + PINMUX_IPSR_GPSR(IP14_31_28, IRQ8), + PINMUX_IPSR_MSEL(IP14_31_28, AUDIO_CLKA_D, SEL_ADGA_3), + PINMUX_IPSR_MSEL(IP14_31_28, CAN_CLK_D, SEL_CANCLK_3), + PINMUX_IPSR_GPSR(IP14_31_28, VI0_G5), + + /* IPSR15 */ + PINMUX_IPSR_MSEL(IP15_3_0, SSI_SCK0129_A, SEL_SSI0_0), + PINMUX_IPSR_MSEL(IP15_3_0, MSIOF1_RXD_A, SEL_MSIOF1_0), + PINMUX_IPSR_MSEL(IP15_3_0, RX5_D, SEL_SCIF5_3), + PINMUX_IPSR_GPSR(IP15_3_0, VI0_G6), + PINMUX_IPSR_MSEL(IP15_7_4, SSI_WS0129_A, SEL_SSI0_0), + PINMUX_IPSR_MSEL(IP15_7_4, MSIOF1_TXD_A, SEL_MSIOF1_0), + PINMUX_IPSR_MSEL(IP15_7_4, TX5_D, SEL_SCIF5_3), + PINMUX_IPSR_GPSR(IP15_7_4, VI0_G7), + PINMUX_IPSR_MSEL(IP15_11_8, SSI_SDATA0_A, SEL_SSI0_0), + PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SYNC_A, SEL_MSIOF1_0), + PINMUX_IPSR_GPSR(IP15_11_8, PWM0_C), + PINMUX_IPSR_GPSR(IP15_11_8, VI0_R0), + PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK34), + PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_A, SEL_MSIOF1_0), + PINMUX_IPSR_GPSR(IP15_15_12, AVB_MDC), + PINMUX_IPSR_GPSR(IP15_15_12, DACK1), + PINMUX_IPSR_GPSR(IP15_15_12, VI0_R1), + PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS34), + PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SS1_A, SEL_MSIOF1_0), + PINMUX_IPSR_GPSR(IP15_19_16, AVB_MDIO), + PINMUX_IPSR_MSEL(IP15_19_16, CAN1_RX_A, SEL_CAN1_0), + PINMUX_IPSR_GPSR(IP15_19_16, DREQ1_N), + PINMUX_IPSR_GPSR(IP15_19_16, VI0_R2), + PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA3), + PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SS2_A, SEL_MSIOF1_0), + PINMUX_IPSR_GPSR(IP15_23_20, AVB_LINK), + PINMUX_IPSR_MSEL(IP15_23_20, CAN1_TX_A, SEL_CAN1_0), + PINMUX_IPSR_GPSR(IP15_23_20, DREQ2_N), + PINMUX_IPSR_GPSR(IP15_23_20, VI0_R3), + PINMUX_IPSR_MSEL(IP15_27_24, SSI_SCK4_A, SEL_SSI4_0), + PINMUX_IPSR_GPSR(IP15_27_24, AVB_MAGIC), + PINMUX_IPSR_GPSR(IP15_27_24, VI0_R4), + PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS4_A, SEL_SSI4_0), + PINMUX_IPSR_GPSR(IP15_31_28, AVB_PHY_INT), + PINMUX_IPSR_GPSR(IP15_31_28, VI0_R5), + + /* IPSR16 */ + PINMUX_IPSR_MSEL(IP16_3_0, SSI_SDATA4_A, SEL_SSI4_0), + PINMUX_IPSR_GPSR(IP16_3_0, AVB_CRS), + PINMUX_IPSR_GPSR(IP16_3_0, VI0_R6), + PINMUX_IPSR_MSEL(IP16_7_4, SSI_SCK1_A, SEL_SSI1_0), + PINMUX_IPSR_MSEL(IP16_7_4, SCIF1_SCK_B, SEL_SCIF1_1), + PINMUX_IPSR_GPSR(IP16_7_4, PWM1_D), + PINMUX_IPSR_GPSR(IP16_7_4, IRQ9), + PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_RCN_0), + PINMUX_IPSR_GPSR(IP16_7_4, DACK2), + PINMUX_IPSR_GPSR(IP16_7_4, VI0_CLK), + PINMUX_IPSR_GPSR(IP16_7_4, AVB_COL), + PINMUX_IPSR_MSEL(IP16_11_8, SSI_SDATA8_A, SEL_SSI8_0), + PINMUX_IPSR_MSEL(IP16_11_8, RX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP16_11_8, CAN0_RX_D, SEL_CAN0_3), + PINMUX_IPSR_MSEL(IP16_11_8, AVB_AVTP_CAPTURE_B, SEL_AVB_1), + PINMUX_IPSR_GPSR(IP16_11_8, VI0_R7), + PINMUX_IPSR_MSEL(IP16_15_12, SSI_WS1_A, SEL_SSI1_0), + PINMUX_IPSR_MSEL(IP16_15_12, TX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP16_15_12, CAN0_TX_D, SEL_CAN0_3), + PINMUX_IPSR_MSEL(IP16_15_12, AVB_AVTP_MATCH_B, SEL_AVB_1), + PINMUX_IPSR_GPSR(IP16_15_12, VI0_DATA0_VI0_B0), + PINMUX_IPSR_MSEL(IP16_19_16, SSI_SDATA1_A, SEL_SSI1_0), + PINMUX_IPSR_MSEL(IP16_19_16, HRX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_GPSR(IP16_19_16, VI0_DATA1_VI0_B1), + PINMUX_IPSR_MSEL(IP16_23_20, SSI_SCK2_A, SEL_SSI2_0), + PINMUX_IPSR_MSEL(IP16_23_20, HTX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_GPSR(IP16_23_20, AVB_TXD7), + PINMUX_IPSR_GPSR(IP16_23_20, VI0_DATA2_VI0_B2), + PINMUX_IPSR_MSEL(IP16_27_24, SSI_WS2_A, SEL_SSI2_0), + PINMUX_IPSR_MSEL(IP16_27_24, HCTS1_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_GPSR(IP16_27_24, AVB_TX_ER), + PINMUX_IPSR_GPSR(IP16_27_24, VI0_DATA3_VI0_B3), + PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA2_A, SEL_SSI2_0), + PINMUX_IPSR_MSEL(IP16_31_28, HRTS1_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_GPSR(IP16_31_28, VI0_DATA4_VI0_B4), + + /* IPSR17 */ + PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_A, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP17_3_0, RX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP17_3_0, SCL3_E, SEL_I2C03_4), + PINMUX_IPSR_GPSR(IP17_3_0, EX_WAIT1), + PINMUX_IPSR_GPSR(IP17_3_0, VI0_DATA5_VI0_B5), + PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_A, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP17_7_4, TX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP17_7_4, SDA3_E, SEL_I2C03_4), + PINMUX_IPSR_GPSR(IP17_7_4, VI0_DATA6_VI0_B6), + PINMUX_IPSR_MSEL(IP17_11_8, SSI_SDATA9_A, SEL_SSI9_0), + PINMUX_IPSR_GPSR(IP17_11_8, SCIF2_SCK_B), + PINMUX_IPSR_GPSR(IP17_11_8, PWM2_D), + PINMUX_IPSR_GPSR(IP17_11_8, VI0_DATA7_VI0_B7), + PINMUX_IPSR_MSEL(IP17_15_12, AUDIO_CLKA_A, SEL_ADGA_0), + PINMUX_IPSR_MSEL(IP17_15_12, SCL0_B, SEL_I2C00_1), + PINMUX_IPSR_GPSR(IP17_15_12, VI0_CLKENB), + PINMUX_IPSR_MSEL(IP17_19_16, AUDIO_CLKB_A, SEL_ADGB_0), + PINMUX_IPSR_MSEL(IP17_19_16, SDA0_B, SEL_I2C00_1), + PINMUX_IPSR_GPSR(IP17_19_16, VI0_FIELD), + PINMUX_IPSR_MSEL(IP17_23_20, AUDIO_CLKC_A, SEL_ADGC_0), + PINMUX_IPSR_MSEL(IP17_23_20, SCL4_B, SEL_I2C04_1), + PINMUX_IPSR_GPSR(IP17_23_20, VI0_HSYNC_N), + PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_A), + PINMUX_IPSR_MSEL(IP17_27_24, SDA4_B, SEL_I2C04_1), + PINMUX_IPSR_GPSR(IP17_27_24, VI0_VSYNC_N), +}; + +static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), +}; + +/* - MMC -------------------------------------------------------------------- */ +static const unsigned int mmc_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(0, 15), +}; +static const unsigned int mmc_data1_mux[] = { + MMC0_D0_SDHI1_D0_MARK, +}; +static const unsigned int mmc_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16), + RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18), +}; +static const unsigned int mmc_data4_mux[] = { + MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK, + MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, +}; +static const unsigned int mmc_data8_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16), + RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18), + RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), + RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22), +}; +static const unsigned int mmc_data8_mux[] = { + MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK, + MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, + MMC0_D4_MARK, MMC0_D5_MARK, + MMC0_D6_MARK, MMC0_D7_MARK, +}; +static const unsigned int mmc_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), +}; +static const unsigned int mmc_ctrl_mux[] = { + MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK, +}; +/* - SCIF0 ------------------------------------------------------------------ */ +static const unsigned int scif0_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), +}; +static const unsigned int scif0_data_a_mux[] = { + RX0_A_MARK, TX0_A_MARK, +}; +static const unsigned int scif0_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), +}; +static const unsigned int scif0_data_b_mux[] = { + RX0_B_MARK, TX0_B_MARK, +}; +static const unsigned int scif0_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), +}; +static const unsigned int scif0_data_c_mux[] = { + RX0_C_MARK, TX0_C_MARK, +}; +static const unsigned int scif0_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), +}; +static const unsigned int scif0_data_d_mux[] = { + RX0_D_MARK, TX0_D_MARK, +}; +/* - SCIF1 ------------------------------------------------------------------ */ +static const unsigned int scif1_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), +}; +static const unsigned int scif1_data_a_mux[] = { + RX1_A_MARK, TX1_A_MARK, +}; +static const unsigned int scif1_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 15), +}; +static const unsigned int scif1_clk_a_mux[] = { + SCIF1_SCK_A_MARK, +}; +static const unsigned int scif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20), +}; +static const unsigned int scif1_data_b_mux[] = { + RX1_B_MARK, TX1_B_MARK, +}; +static const unsigned int scif1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 18), +}; +static const unsigned int scif1_clk_b_mux[] = { + SCIF1_SCK_B_MARK, +}; +static const unsigned int scif1_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9), +}; +static const unsigned int scif1_data_c_mux[] = { + RX1_C_MARK, TX1_C_MARK, +}; +static const unsigned int scif1_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 7), +}; +static const unsigned int scif1_clk_c_mux[] = { + SCIF1_SCK_C_MARK, +}; +static const unsigned int scif1_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), +}; +static const unsigned int scif1_data_d_mux[] = { + RX1_D_MARK, TX1_D_MARK, +}; +/* - SCIF2 ------------------------------------------------------------------ */ +static const unsigned int scif2_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19), +}; +static const unsigned int scif2_data_a_mux[] = { + RX2_A_MARK, TX2_A_MARK, +}; +static const unsigned int scif2_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 20), +}; +static const unsigned int scif2_clk_a_mux[] = { + SCIF2_SCK_A_MARK, +}; +static const unsigned int scif2_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), +}; +static const unsigned int scif2_data_b_mux[] = { + RX2_B_MARK, TX2_B_MARK, +}; +static const unsigned int scif2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 27), +}; +static const unsigned int scif2_clk_b_mux[] = { + SCIF2_SCK_B_MARK, +}; +static const unsigned int scif2_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), +}; +static const unsigned int scif2_data_c_mux[] = { + RX2_C_MARK, TX2_C_MARK, +}; +/* - SCIF3 ------------------------------------------------------------------ */ +static const unsigned int scif3_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), +}; +static const unsigned int scif3_data_a_mux[] = { + RX3_A_MARK, TX3_A_MARK, +}; +static const unsigned int scif3_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 21), +}; +static const unsigned int scif3_clk_mux[] = { + SCIF3_SCK_MARK, +}; +static const unsigned int scif3_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), +}; +static const unsigned int scif3_data_b_mux[] = { + RX3_B_MARK, TX3_B_MARK, +}; +static const unsigned int scif3_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), +}; +static const unsigned int scif3_data_c_mux[] = { + RX3_C_MARK, TX3_C_MARK, +}; +/* - SCIF4 ------------------------------------------------------------------ */ +static const unsigned int scif4_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), +}; +static const unsigned int scif4_data_a_mux[] = { + RX4_A_MARK, TX4_A_MARK, +}; +static const unsigned int scif4_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), +}; +static const unsigned int scif4_data_b_mux[] = { + RX4_B_MARK, TX4_B_MARK, +}; +static const unsigned int scif4_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), +}; +static const unsigned int scif4_data_c_mux[] = { + RX4_C_MARK, TX4_C_MARK, +}; +static const unsigned int scif4_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), +}; +static const unsigned int scif4_data_d_mux[] = { + RX4_D_MARK, TX4_D_MARK, +}; +static const unsigned int scif4_data_e_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), +}; +static const unsigned int scif4_data_e_mux[] = { + RX4_E_MARK, TX4_E_MARK, +}; +/* - SCIF5 ------------------------------------------------------------------ */ +static const unsigned int scif5_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), +}; +static const unsigned int scif5_data_a_mux[] = { + RX5_A_MARK, TX5_A_MARK, +}; +static const unsigned int scif5_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), +}; +static const unsigned int scif5_data_b_mux[] = { + RX5_B_MARK, TX5_B_MARK, +}; +static const unsigned int scif5_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), +}; +static const unsigned int scif5_data_c_mux[] = { + RX5_C_MARK, TX5_C_MARK, +}; +static const unsigned int scif5_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), +}; +static const unsigned int scif5_data_d_mux[] = { + RX5_D_MARK, TX5_D_MARK, +}; +static const unsigned int scif5_data_e_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), +}; +static const unsigned int scif5_data_e_mux[] = { + RX5_E_MARK, TX5_E_MARK, +}; +static const unsigned int scif5_data_f_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), +}; +static const unsigned int scif5_data_f_mux[] = { + RX5_F_MARK, TX5_F_MARK, +}; +/* - SCIF Clock ------------------------------------------------------------- */ +static const unsigned int scif_clk_a_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(1, 22), +}; +static const unsigned int scif_clk_a_mux[] = { + SCIF_CLK_A_MARK, +}; +static const unsigned int scif_clk_b_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(3, 29), +}; +static const unsigned int scif_clk_b_mux[] = { + SCIF_CLK_B_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(mmc_data1), + SH_PFC_PIN_GROUP(mmc_data4), + SH_PFC_PIN_GROUP(mmc_data8), + SH_PFC_PIN_GROUP(mmc_ctrl), + SH_PFC_PIN_GROUP(scif0_data_a), + SH_PFC_PIN_GROUP(scif0_data_b), + SH_PFC_PIN_GROUP(scif0_data_c), + SH_PFC_PIN_GROUP(scif0_data_d), + SH_PFC_PIN_GROUP(scif1_data_a), + SH_PFC_PIN_GROUP(scif1_clk_a), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_clk_b), + SH_PFC_PIN_GROUP(scif1_data_c), + SH_PFC_PIN_GROUP(scif1_clk_c), + SH_PFC_PIN_GROUP(scif1_data_d), + SH_PFC_PIN_GROUP(scif2_data_a), + SH_PFC_PIN_GROUP(scif2_clk_a), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scif2_clk_b), + SH_PFC_PIN_GROUP(scif2_data_c), + SH_PFC_PIN_GROUP(scif3_data_a), + SH_PFC_PIN_GROUP(scif3_clk), + SH_PFC_PIN_GROUP(scif3_data_b), + SH_PFC_PIN_GROUP(scif3_data_c), + SH_PFC_PIN_GROUP(scif4_data_a), + SH_PFC_PIN_GROUP(scif4_data_b), + SH_PFC_PIN_GROUP(scif4_data_c), + SH_PFC_PIN_GROUP(scif4_data_d), + SH_PFC_PIN_GROUP(scif4_data_e), + SH_PFC_PIN_GROUP(scif5_data_a), + SH_PFC_PIN_GROUP(scif5_data_b), + SH_PFC_PIN_GROUP(scif5_data_c), + SH_PFC_PIN_GROUP(scif5_data_d), + SH_PFC_PIN_GROUP(scif5_data_e), + SH_PFC_PIN_GROUP(scif5_data_f), + SH_PFC_PIN_GROUP(scif_clk_a), + SH_PFC_PIN_GROUP(scif_clk_b), +}; + +static const char * const mmc_groups[] = { + "mmc_data1", + "mmc_data4", + "mmc_data8", + "mmc_ctrl", +}; + +static const char * const scif0_groups[] = { + "scif0_data_a", + "scif0_data_b", + "scif0_data_c", + "scif0_data_d", +}; + +static const char * const scif1_groups[] = { + "scif1_data_a", + "scif1_clk_a", + "scif1_data_b", + "scif1_clk_b", + "scif1_data_c", + "scif1_clk_c", + "scif1_data_d", +}; + +static const char * const scif2_groups[] = { + "scif2_data_a", + "scif2_clk_a", + "scif2_data_b", + "scif2_clk_b", + "scif2_data_c", +}; + +static const char * const scif3_groups[] = { + "scif3_data_a", + "scif3_clk", + "scif3_data_b", + "scif3_data_c", +}; + +static const char * const scif4_groups[] = { + "scif4_data_a", + "scif4_data_b", + "scif4_data_c", + "scif4_data_d", + "scif4_data_e", +}; + +static const char * const scif5_groups[] = { + "scif5_data_a", + "scif5_data_b", + "scif5_data_c", + "scif5_data_d", + "scif5_data_e", + "scif5_data_f", +}; + +static const char * const scif_clk_groups[] = { + "scif_clk_a", + "scif_clk_b", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(mmc), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif5), + SH_PFC_FUNCTION(scif_clk), +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_0_22_FN, FN_MMC0_D7, + GP_0_21_FN, FN_MMC0_D6, + GP_0_20_FN, FN_IP1_7_4, + GP_0_19_FN, FN_IP1_3_0, + GP_0_18_FN, FN_MMC0_D3_SDHI1_D3, + GP_0_17_FN, FN_MMC0_D2_SDHI1_D2, + GP_0_16_FN, FN_MMC0_D1_SDHI1_D1, + GP_0_15_FN, FN_MMC0_D0_SDHI1_D0, + GP_0_14_FN, FN_MMC0_CMD_SDHI1_CMD, + GP_0_13_FN, FN_MMC0_CLK_SDHI1_CLK, + GP_0_12_FN, FN_IP0_31_28, + GP_0_11_FN, FN_IP0_27_24, + GP_0_10_FN, FN_IP0_23_20, + GP_0_9_FN, FN_IP0_19_16, + GP_0_8_FN, FN_IP0_15_12, + GP_0_7_FN, FN_IP0_11_8, + GP_0_6_FN, FN_IP0_7_4, + GP_0_5_FN, FN_IP0_3_0, + GP_0_4_FN, FN_CLKOUT, + GP_0_3_FN, FN_USB1_OVC, + GP_0_2_FN, FN_USB1_PWEN, + GP_0_1_FN, FN_USB0_OVC, + GP_0_0_FN, FN_USB0_PWEN, } + }, + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_22_FN, FN_IP4_3_0, + GP_1_21_FN, FN_IP3_31_28, + GP_1_20_FN, FN_IP3_27_24, + GP_1_19_FN, FN_IP3_23_20, + GP_1_18_FN, FN_IP3_19_16, + GP_1_17_FN, FN_IP3_15_12, + GP_1_16_FN, FN_IP3_11_8, + GP_1_15_FN, FN_IP3_7_4, + GP_1_14_FN, FN_IP3_3_0, + GP_1_13_FN, FN_IP2_31_28, + GP_1_12_FN, FN_IP2_27_24, + GP_1_11_FN, FN_IP2_23_20, + GP_1_10_FN, FN_IP2_19_16, + GP_1_9_FN, FN_IP2_15_12, + GP_1_8_FN, FN_IP2_11_8, + GP_1_7_FN, FN_IP2_7_4, + GP_1_6_FN, FN_IP2_3_0, + GP_1_5_FN, FN_IP1_31_28, + GP_1_4_FN, FN_IP1_27_24, + GP_1_3_FN, FN_IP1_23_20, + GP_1_2_FN, FN_IP1_19_16, + GP_1_1_FN, FN_IP1_15_12, + GP_1_0_FN, FN_IP1_11_8, } + }, + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + GP_2_31_FN, FN_IP8_3_0, + GP_2_30_FN, FN_IP7_31_28, + GP_2_29_FN, FN_IP7_27_24, + GP_2_28_FN, FN_IP7_23_20, + GP_2_27_FN, FN_IP7_19_16, + GP_2_26_FN, FN_IP7_15_12, + GP_2_25_FN, FN_IP7_11_8, + GP_2_24_FN, FN_IP7_7_4, + GP_2_23_FN, FN_IP7_3_0, + GP_2_22_FN, FN_IP6_31_28, + GP_2_21_FN, FN_IP6_27_24, + GP_2_20_FN, FN_IP6_23_20, + GP_2_19_FN, FN_IP6_19_16, + GP_2_18_FN, FN_IP6_15_12, + GP_2_17_FN, FN_IP6_11_8, + GP_2_16_FN, FN_IP6_7_4, + GP_2_15_FN, FN_IP6_3_0, + GP_2_14_FN, FN_IP5_31_28, + GP_2_13_FN, FN_IP5_27_24, + GP_2_12_FN, FN_IP5_23_20, + GP_2_11_FN, FN_IP5_19_16, + GP_2_10_FN, FN_IP5_15_12, + GP_2_9_FN, FN_IP5_11_8, + GP_2_8_FN, FN_IP5_7_4, + GP_2_7_FN, FN_IP5_3_0, + GP_2_6_FN, FN_IP4_31_28, + GP_2_5_FN, FN_IP4_27_24, + GP_2_4_FN, FN_IP4_23_20, + GP_2_3_FN, FN_IP4_19_16, + GP_2_2_FN, FN_IP4_15_12, + GP_2_1_FN, FN_IP4_11_8, + GP_2_0_FN, FN_IP4_7_4, } + }, + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + 0, 0, + 0, 0, + GP_3_29_FN, FN_IP10_19_16, + GP_3_28_FN, FN_IP10_15_12, + GP_3_27_FN, FN_IP10_11_8, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_3_16_FN, FN_IP10_7_4, + GP_3_15_FN, FN_IP10_3_0, + GP_3_14_FN, FN_IP9_31_28, + GP_3_13_FN, FN_IP9_27_24, + GP_3_12_FN, FN_IP9_23_20, + GP_3_11_FN, FN_IP9_19_16, + GP_3_10_FN, FN_IP9_15_12, + GP_3_9_FN, FN_IP9_11_8, + GP_3_8_FN, FN_IP9_7_4, + GP_3_7_FN, FN_IP9_3_0, + GP_3_6_FN, FN_IP8_31_28, + GP_3_5_FN, FN_IP8_27_24, + GP_3_4_FN, FN_IP8_23_20, + GP_3_3_FN, FN_IP8_19_16, + GP_3_2_FN, FN_IP8_15_12, + GP_3_1_FN, FN_IP8_11_8, + GP_3_0_FN, FN_IP8_7_4, } + }, + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_4_25_FN, FN_IP13_27_24, + GP_4_24_FN, FN_IP13_23_20, + GP_4_23_FN, FN_IP13_19_16, + GP_4_22_FN, FN_IP13_15_12, + GP_4_21_FN, FN_IP13_11_8, + GP_4_20_FN, FN_IP13_7_4, + GP_4_19_FN, FN_IP13_3_0, + GP_4_18_FN, FN_IP12_31_28, + GP_4_17_FN, FN_IP12_27_24, + GP_4_16_FN, FN_IP12_23_20, + GP_4_15_FN, FN_IP12_19_16, + GP_4_14_FN, FN_IP12_15_12, + GP_4_13_FN, FN_IP12_11_8, + GP_4_12_FN, FN_IP12_7_4, + GP_4_11_FN, FN_IP12_3_0, + GP_4_10_FN, FN_IP11_31_28, + GP_4_9_FN, FN_IP11_27_24, + GP_4_8_FN, FN_IP11_23_20, + GP_4_7_FN, FN_IP11_19_16, + GP_4_6_FN, FN_IP11_15_12, + GP_4_5_FN, FN_IP11_11_8, + GP_4_4_FN, FN_IP11_7_4, + GP_4_3_FN, FN_IP11_3_0, + GP_4_2_FN, FN_IP10_31_28, + GP_4_1_FN, FN_IP10_27_24, + GP_4_0_FN, FN_IP10_23_20, } + }, + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + GP_5_31_FN, FN_IP17_27_24, + GP_5_30_FN, FN_IP17_23_20, + GP_5_29_FN, FN_IP17_19_16, + GP_5_28_FN, FN_IP17_15_12, + GP_5_27_FN, FN_IP17_11_8, + GP_5_26_FN, FN_IP17_7_4, + GP_5_25_FN, FN_IP17_3_0, + GP_5_24_FN, FN_IP16_31_28, + GP_5_23_FN, FN_IP16_27_24, + GP_5_22_FN, FN_IP16_23_20, + GP_5_21_FN, FN_IP16_19_16, + GP_5_20_FN, FN_IP16_15_12, + GP_5_19_FN, FN_IP16_11_8, + GP_5_18_FN, FN_IP16_7_4, + GP_5_17_FN, FN_IP16_3_0, + GP_5_16_FN, FN_IP15_31_28, + GP_5_15_FN, FN_IP15_27_24, + GP_5_14_FN, FN_IP15_23_20, + GP_5_13_FN, FN_IP15_19_16, + GP_5_12_FN, FN_IP15_15_12, + GP_5_11_FN, FN_IP15_11_8, + GP_5_10_FN, FN_IP15_7_4, + GP_5_9_FN, FN_IP15_3_0, + GP_5_8_FN, FN_IP14_31_28, + GP_5_7_FN, FN_IP14_27_24, + GP_5_6_FN, FN_IP14_23_20, + GP_5_5_FN, FN_IP14_19_16, + GP_5_4_FN, FN_IP14_15_12, + GP_5_3_FN, FN_IP14_11_8, + GP_5_2_FN, FN_IP14_7_4, + GP_5_1_FN, FN_IP14_3_0, + GP_5_0_FN, FN_IP13_31_28, } + }, + { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IP0_31_28 [4] */ + FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_27_24 [4] */ + FN_SD0_CD, 0, FN_CAN0_RX_A, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_23_20 [4] */ + FN_SD0_DAT3, 0, 0, FN_SSI_SDATA0_B, FN_TX5_E, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_19_16 [4] */ + FN_SD0_DAT2, 0, 0, FN_SSI_WS0129_B, FN_RX5_E, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_15_12 [4] */ + FN_SD0_DAT1, 0, 0, FN_SSI_SCK0129_B, FN_TX4_E, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_11_8 [4] */ + FN_SD0_DAT0, 0, 0, FN_SSI_SDATA1_C, FN_RX4_E, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_7_4 [4] */ + FN_SD0_CMD, 0, 0, FN_SSI_WS1_C, FN_TX3_C, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_3_0 [4] */ + FN_SD0_CLK, 0, 0, FN_SSI_SCK1_C, FN_RX3_C, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IP1_31_28 [4] */ + FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_27_24 [4] */ + FN_D4, 0, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_23_20 [4] */ + FN_D3, 0, FN_TX4_B, FN_SDA0_D, FN_PWM0_A, + FN_MSIOF2_SYNC_C, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_19_16 [4] */ + FN_D2, 0, FN_RX4_B, FN_SCL0_D, FN_PWM1_C, + FN_MSIOF2_SCK_C, FN_SSI_SCK5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_15_12 [4] */ + FN_D1, 0, FN_SDA3_B, FN_TX5_B, 0, FN_MSIOF2_TXD_C, + FN_SSI_WS5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_11_8 [4] */ + FN_D0, 0, FN_SCL3_B, FN_RX5_B, FN_IRQ4, + FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_7_4 [4] */ + FN_MMC0_D5, FN_SD1_WP, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_3_0 [4] */ + FN_MMC0_D4, FN_SD1_CD, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IP2_31_28 [4] */ + FN_D13, FN_MSIOF2_SYNC_A, 0, FN_RX4_C, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, + /* IP2_27_24 [4] */ + FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, 0, FN_CAN_CLK_C, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_23_20 [4] */ + FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, + /* IP2_19_16 [4] */ + FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, + /* IP2_15_12 [4] */ + FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_11_8 [4] */ + FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_7_4 [4] */ + FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_3_0 [4] */ + FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IP3_31_28 [4] */ + FN_QSPI0_SSL, FN_WE1_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, + /* IP3_27_24 [4] */ + FN_QSPI0_IO3, FN_RD_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, + /* IP3_23_20 [4] */ + FN_QSPI0_IO2, FN_CS0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, + /* IP3_19_16 [4] */ + FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, + /* IP3_15_12 [4] */ + FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, + /* IP3_11_8 [4] */ + FN_QSPI0_SPCLK, FN_WE0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, + /* IP3_7_4 [4] */ + FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, 0, FN_CAN1_TX_B, FN_IRQ2, + FN_AVB_AVTP_MATCH_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP3_3_0 [4] */ + FN_D14, FN_MSIOF2_SS1, 0, FN_TX4_C, FN_CAN1_RX_B, + 0, FN_AVB_AVTP_CAPTURE_A, + 0, 0, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IP4_31_28 [4] */ + FN_DU0_DR6, 0, FN_RX2_C, 0, 0, 0, FN_A6, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP4_27_24 [4] */ + FN_DU0_DR5, 0, FN_TX1_D, 0, FN_PWM1_B, 0, FN_A5, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP4_23_20 [4] */ + FN_DU0_DR4, 0, FN_RX1_D, 0, 0, 0, FN_A4, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + /* IP4_19_16 [4] */ + FN_DU0_DR3, 0, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, 0, + FN_A3, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP4_15_12 [4] */ + FN_DU0_DR2, 0, FN_RX0_D, FN_SCL0_E, 0, 0, FN_A2, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP4_11_8 [4] */ + FN_DU0_DR1, 0, FN_TX5_C, FN_SDA2_D, 0, 0, FN_A1, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP4_7_4 [4] */ + FN_DU0_DR0, 0, FN_RX5_C, FN_SCL2_D, 0, 0, FN_A0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP4_3_0 [4] */ + FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IP5_31_28 [4] */ + FN_DU0_DG6, 0, FN_HRX1_C, 0, 0, 0, FN_A14, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + /* IP5_27_24 [4] */ + FN_DU0_DG5, 0, FN_HTX0_A, 0, FN_PWM5_B, 0, FN_A13, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP5_23_20 [4] */ + FN_DU0_DG4, 0, FN_HRX0_A, 0, 0, 0, FN_A12, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + /* IP5_19_16 [4] */ + FN_DU0_DG3, 0, FN_TX4_D, 0, FN_PWM4_B, 0, FN_A11, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP5_15_12 [4] */ + FN_DU0_DG2, 0, FN_RX4_D, 0, 0, 0, FN_A10, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + /* IP5_11_8 [4] */ + FN_DU0_DG1, 0, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, 0, + FN_A9, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP5_7_4 [4] */ + FN_DU0_DG0, 0, FN_RX3_B, FN_SCL3_D, 0, 0, FN_A8, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP5_3_0 [4] */ + FN_DU0_DR7, 0, FN_TX2_C, 0, FN_PWM2_B, 0, FN_A7, 0, + 0, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IP6_31_28 [4] */ + FN_DU0_DB6, 0, 0, 0, 0, 0, FN_A22, 0, 0, + 0, 0, 0, 0, 0, 0, 0, + /* IP6_27_24 [4] */ + FN_DU0_DB5, 0, FN_HRTS1_N_C, 0, 0, 0, + FN_A21, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP6_23_20 [4] */ + FN_DU0_DB4, 0, FN_HCTS1_N_C, 0, 0, 0, + FN_A20, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP6_19_16 [4] */ + FN_DU0_DB3, 0, FN_HRTS0_N, 0, 0, 0, FN_A19, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + /* IP6_15_12 [4] */ + FN_DU0_DB2, 0, FN_HCTS0_N, 0, 0, 0, FN_A18, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + /* IP6_11_8 [4] */ + FN_DU0_DB1, 0, 0, FN_SDA4_D, FN_CAN0_TX_C, 0, FN_A17, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP6_7_4 [4] */ + FN_DU0_DB0, 0, 0, FN_SCL4_D, FN_CAN0_RX_C, 0, FN_A16, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP6_3_0 [4] */ + FN_DU0_DG7, 0, FN_HTX1_C, 0, FN_PWM6_B, 0, FN_A15, + 0, 0, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IP7_31_28 [4] */ + FN_DU0_DISP, 0, 0, 0, FN_CAN1_RX_C, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + /* IP7_27_24 [4] */ + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0, FN_MSIOF2_SCK_B, + 0, 0, 0, FN_DRACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP7_23_20 [4] */ + FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_MSIOF2_SYNC_B, 0, + 0, 0, FN_DACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP7_19_16 [4] */ + FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_MSIOF2_TXD_B, 0, + 0, 0, FN_DREQ0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP7_15_12 [4] */ + FN_DU0_DOTCLKOUT1, 0, FN_MSIOF2_RXD_B, 0, 0, 0, + FN_CS1_N_A26, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP7_11_8 [4] */ + FN_DU0_DOTCLKOUT0, 0, 0, 0, 0, 0, FN_A25, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + /* IP7_7_4 [4] */ + FN_DU0_DOTCLKIN, 0, 0, 0, 0, 0, FN_A24, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + /* IP7_3_0 [4] */ + FN_DU0_DB7, 0, 0, 0, 0, 0, FN_A23, 0, 0, + 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IP8_31_28 [4] */ + FN_VI1_DATA5, 0, 0, 0, FN_AVB_RXD4, FN_ETH_LINK, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + /* IP8_27_24 [4] */ + FN_VI1_DATA4, 0, 0, 0, FN_AVB_RXD3, FN_ETH_RX_ER, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + /* IP8_23_20 [4] */ + FN_VI1_DATA3, 0, 0, 0, FN_AVB_RXD2, FN_ETH_MDIO, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + /* IP8_19_16 [4] */ + FN_VI1_DATA2, 0, 0, 0, FN_AVB_RXD1, FN_ETH_RXD1, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + /* IP8_15_12 [4] */ + FN_VI1_DATA1, 0, 0, 0, FN_AVB_RXD0, FN_ETH_RXD0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + /* IP8_11_8 [4] */ + FN_VI1_DATA0, 0, 0, 0, FN_AVB_RX_DV, FN_ETH_CRS_DV, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, + /* IP8_7_4 [4] */ + FN_VI1_CLK, 0, 0, 0, FN_AVB_RX_CLK, FN_ETH_REF_CLK, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, + /* IP8_3_0 [4] */ + FN_DU0_CDE, 0, 0, 0, FN_CAN1_TX_C, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IP9_31_28 [4] */ + FN_VI1_DATA9, 0, 0, FN_SDA2_B, FN_AVB_TXD0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + /* IP9_27_24 [4] */ + FN_VI1_DATA8, 0, 0, FN_SCL2_B, FN_AVB_TX_EN, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + /* IP9_23_20 [4] */ + FN_VI1_VSYNC_N, FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B, + FN_AVB_TX_CLK, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP9_19_16 [4] */ + FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, 0, FN_AVB_GTXREFCLK, + FN_ETH_MDC, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP9_15_12 [4] */ + FN_VI1_FIELD, FN_SDA3_A, 0, 0, FN_AVB_RX_ER, FN_ETH_TXD0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP9_11_8 [4] */ + FN_VI1_CLKENB, FN_SCL3_A, 0, 0, FN_AVB_RXD7, FN_ETH_MAGIC, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP9_7_4 [4] */ + FN_VI1_DATA7, 0, 0, 0, FN_AVB_RXD6, FN_ETH_TX_EN, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + /* IP9_3_0 [4] */ + FN_VI1_DATA6, 0, 0, 0, FN_AVB_RXD5, FN_ETH_TXD1, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060068, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IP10_31_28 [4] */ + FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, 0, 0, + FN_SSI_SCK6_B, FN_VI0_G0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP10_27_24 [4] */ + FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK, + FN_CAN1_TX_D, FN_DVC_MUTE, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP10_23_20 [4] */ + FN_SCL0_A, FN_RX0_C, FN_PWM5_A, FN_TCLK1_B, FN_AVB_TXD6, + FN_CAN1_RX_D, FN_MSIOF0_SYNC_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP10_19_16 [4] */ + FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, 0, + FN_SSI_SDATA1_D, 0, FN_MSIOF0_SCK_B, 0, 0, 0, 0, 0, 0, 0, + 0, 0, + /* IP10_15_12 [4] */ + FN_AVB_TXD4, 0, FN_AUDIO_CLKB_B, 0, FN_SSI_WS1_D, FN_TX5_F, + FN_MSIOF0_TXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP10_11_8 [4] */ + FN_AVB_TXD3, 0, FN_AUDIO_CLKA_B, 0, FN_SSI_SCK1_D, FN_RX5_F, + FN_MSIOF0_RXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP10_7_4 [4] */ + FN_VI1_DATA11, 0, 0, FN_CAN0_TX_B, FN_AVB_TXD2, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, + /* IP10_3_0 [4] */ + FN_VI1_DATA10, 0, 0, FN_CAN0_RX_B, FN_AVB_TXD1, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR11", 0xE606006C, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IP11_31_28 [4] */ + FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP11_27_24 [4] */ + FN_MSIOF0_SS2_A, 0, 0, FN_DU1_DR7, 0, + FN_QSPI1_SSL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP11_23_20 [4] */ + FN_MSIOF0_SS1_A, 0, 0, FN_DU1_DR6, 0, + FN_QSPI1_IO3, FN_SSI_SDATA8_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP11_19_16 [4] */ + FN_MSIOF0_SYNC_A, FN_PWM1_A, 0, FN_DU1_DR5, + 0, FN_QSPI1_IO2, FN_SSI_SDATA7_B, 0, 0, 0, 0, 0, + 0, 0, 0, 0, + /* IP11_15_12 [4] */ + FN_MSIOF0_SCK_A, FN_IRQ0, 0, FN_DU1_DR4, + 0, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP11_11_8 [4] */ + FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, 0, + FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP11_7_4 [4] */ + FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, 0, + FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP11_3_0 [4] */ + FN_SDA1_A, FN_TX4_A, 0, FN_DU1_DR1, 0, 0, FN_SSI_WS6_B, + FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060070, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IP12_31_28 [4] */ + FN_SD2_DAT2, FN_RX2_A, 0, FN_DU1_DB0, FN_SSI_SDATA2_B, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP12_27_24 [4] */ + FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP12_23_20 [4] */ + FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6, + FN_SSI_SDATA1_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP12_19_16 [4] */ + FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5, + FN_SSI_SCK2_B, FN_PWM3_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP12_15_12 [4] */ + FN_SD2_CLK, FN_HSCK1, 0, FN_DU1_DG4, FN_SSI_SCK1_B, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP12_11_8 [4] */ + FN_HRTS1_N_A, 0, 0, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP12_7_4 [4] */ + FN_HCTS1_N_A, FN_PWM2_A, 0, FN_DU1_DG2, FN_REMOCON_B, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP12_3_0 [4] */ + FN_HTX1_A, FN_SDA4_A, 0, FN_DU1_DG1, FN_TX0_A, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060074, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IP13_31_28 [4] */ + FN_SSI_SCK5_A, 0, 0, FN_DU1_DOTCLKOUT1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + /* IP13_27_24 [4] */ + FN_SDA2_A, 0, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP13_23_20 [4] */ + FN_SCL2_A, 0, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C, + FN_SSI_SCK4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP13_19_16 [4] */ + FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5, + FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP13_15_12 [4] */ + FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4, + FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, + /* IP13_11_8 [4] */ + FN_SD2_WP, FN_SCIF3_SCK, 0, FN_DU1_DB3, FN_SSI_SDATA9_B, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP13_7_4 [4] */ + FN_SD2_CD, FN_SCIF2_SCK_A, 0, FN_DU1_DB2, FN_SSI_SCK9_B, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP13_3_0 [4] */ + FN_SD2_DAT3, FN_TX2_A, 0, FN_DU1_DB1, FN_SSI_WS9_B, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060078, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IP14_31_28 [4] */ + FN_SSI_SDATA7_A, 0, 0, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, + FN_VI0_G5, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP14_27_24 [4] */ + FN_SSI_WS78_A, 0, FN_SCL4_E, FN_DU1_CDE, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + /* IP14_23_20 [4] */ + FN_SSI_SCK78_A, 0, FN_SDA4_E, FN_DU1_DISP, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + /* IP14_19_16 [4] */ + FN_SSI_SDATA6_A, 0, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP14_15_12 [4] */ + FN_SSI_WS6_A, 0, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP14_11_8 [4] */ + FN_SSI_SCK6_A, 0, 0, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP14_7_4 [4] */ + FN_SSI_SDATA5_A, 0, FN_SDA3_C, FN_DU1_DOTCLKOUT0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP14_3_0 [4] */ + FN_SSI_WS5_A, 0, FN_SCL3_C, FN_DU1_DOTCLKIN, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR15", 0xE606007C, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IP15_31_28 [4] */ + FN_SSI_WS4_A, 0, FN_AVB_PHY_INT, 0, 0, 0, FN_VI0_R5, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + /* IP15_27_24 [4] */ + FN_SSI_SCK4_A, 0, FN_AVB_MAGIC, 0, 0, 0, FN_VI0_R4, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + /* IP15_23_20 [4] */ + FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, 0, FN_CAN1_TX_A, + FN_DREQ2_N, FN_VI0_R3, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP15_19_16 [4] */ + FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, 0, FN_CAN1_RX_A, + FN_DREQ1_N, FN_VI0_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP15_15_12 [4] */ + FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, 0, 0, FN_DACK1, + FN_VI0_R1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP15_11_8 [4] */ + FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, 0, 0, 0, + FN_VI0_R0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP15_7_4 [4] */ + FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, 0, 0, 0, + FN_VI0_G7, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP15_3_0 [4] */ + FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, 0, 0, 0, + FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060080, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IP16_31_28 [4] */ + FN_SSI_SDATA2_A, FN_HRTS1_N_B, 0, 0, 0, 0, + FN_VI0_DATA4_VI0_B4, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_27_24 [4] */ + FN_SSI_WS2_A, FN_HCTS1_N_B, 0, 0, 0, FN_AVB_TX_ER, + FN_VI0_DATA3_VI0_B3, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_23_20 [4] */ + FN_SSI_SCK2_A, FN_HTX1_B, 0, 0, 0, FN_AVB_TXD7, + FN_VI0_DATA2_VI0_B2, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_19_16 [4] */ + FN_SSI_SDATA1_A, FN_HRX1_B, 0, 0, 0, 0, FN_VI0_DATA1_VI0_B1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_15_12 [4] */ + FN_SSI_WS1_A, FN_TX1_B, 0, 0, FN_CAN0_TX_D, + FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, + /* IP16_11_8 [4] */ + FN_SSI_SDATA8_A, FN_RX1_B, 0, 0, FN_CAN0_RX_D, + FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_7_4 [4] */ + FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A, + FN_DACK2, FN_VI0_CLK, FN_AVB_COL, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_3_0 [4] */ + FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0, + 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IP17_31_28 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP17_27_24 [4] */ + FN_AUDIO_CLKOUT_A, FN_SDA4_B, 0, 0, 0, 0, + FN_VI0_VSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP17_23_20 [4] */ + FN_AUDIO_CLKC_A, FN_SCL4_B, 0, 0, 0, 0, + FN_VI0_HSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP17_19_16 [4] */ + FN_AUDIO_CLKB_A, FN_SDA0_B, 0, 0, 0, 0, + FN_VI0_FIELD, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP17_15_12 [4] */ + FN_AUDIO_CLKA_A, FN_SCL0_B, 0, 0, 0, 0, + FN_VI0_CLKENB, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP17_11_8 [4] */ + FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, 0, 0, 0, + FN_VI0_DATA7_VI0_B7, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP17_7_4 [4] */ + FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, 0, 0, 0, + FN_VI0_DATA6_VI0_B6, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP17_3_0 [4] */ + FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, 0, 0, FN_EX_WAIT1, + FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32, + 1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 2, 1, 3, 3, + 1, 2, 3, 3, 1) { + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* SEL_ADGA [2] */ + FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* SEL_CANCLK [2] */ + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, + FN_SEL_CANCLK_3, + /* SEL_CAN1 [2] */ + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, + /* SEL_CAN0 [2] */ + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + /* RESERVED [1] */ + 0, 0, + /* SEL_I2C04 [3] */ + FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, + FN_SEL_I2C04_4, 0, 0, 0, + /* SEL_I2C03 [3] */ + FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, + FN_SEL_I2C03_4, 0, 0, 0, + /* RESERVED [1] */ + 0, 0, + /* SEL_I2C02 [2] */ + FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, + /* SEL_I2C01 [3] */ + FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, + FN_SEL_I2C01_4, 0, 0, 0, + /* SEL_I2C00 [3] */ + FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, + FN_SEL_I2C00_4, 0, 0, 0, + /* SEL_AVB [1] */ + FN_SEL_AVB_0, FN_SEL_AVB_1, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32, + 1, 3, 3, 2, 2, 1, 2, 2, + 2, 1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 1) { + /* SEL_SCIFCLK [1] */ + FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, + /* SEL_SCIF5 [3] */ + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, + FN_SEL_SCIF5_4, FN_SEL_SCIF5_5, 0, 0, + /* SEL_SCIF4 [3] */ + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, + FN_SEL_SCIF4_4, 0, 0, 0, + /* SEL_SCIF3 [2] */ + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, 0, + /* SEL_SCIF2 [2] */ + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0, + /* SEL_SCIF2_CLK [1] */ + FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1, + /* SEL_SCIF1 [2] */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + /* SEL_SCIF0 [2] */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + /* SEL_MSIOF2 [2] */ + FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2, 0, + /* RESERVED [1] */ + 0, 0, + /* SEL_MSIOF1 [1] */ + FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, + /* RESERVED [1] */ + 0, 0, + /* SEL_MSIOF0 [1] */ + FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1, + /* SEL_RCN [1] */ + FN_SEL_RCN_0, FN_SEL_RCN_1, + /* RESERVED [2] */ + 0, 0, 0, 0, + /* SEL_TMU2 [1] */ + FN_SEL_TMU2_0, FN_SEL_TMU2_1, + /* SEL_TMU1 [1] */ + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + /* RESERVED [2] */ + 0, 0, 0, 0, + /* SEL_HSCIF1 [2] */ + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 0, + /* SEL_HSCIF0 [1] */ + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,} + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) { + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* SEL_ADGB [2] */ + FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2, 0, + /* SEL_ADGC [2] */ + FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2, 0, + /* SEL_SSI9 [2] */ + FN_SEL_SSI9_0, FN_SEL_SSI9_1, 0, 0, + /* SEL_SSI8 [2] */ + FN_SEL_SSI8_0, FN_SEL_SSI8_1, 0, 0, + /* SEL_SSI7 [2] */ + FN_SEL_SSI7_0, FN_SEL_SSI7_1, 0, 0, + /* SEL_SSI6 [2] */ + FN_SEL_SSI6_0, FN_SEL_SSI6_1, 0, 0, + /* SEL_SSI5 [2] */ + FN_SEL_SSI5_0, FN_SEL_SSI5_1, 0, 0, + /* SEL_SSI4 [2] */ + FN_SEL_SSI4_0, FN_SEL_SSI4_1, 0, 0, + /* SEL_SSI2 [2] */ + FN_SEL_SSI2_0, FN_SEL_SSI2_1, 0, 0, + /* SEL_SSI1 [2] */ + FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3, + /* SEL_SSI0 [2] */ + FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, } + }, + { }, +}; + +#ifdef CONFIG_PINCTRL_PFC_R8A77470 +const struct sh_pfc_soc_info r8a77470_pinmux_info = { + .name = "r8a77470_pfc", + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; +#endif From patchwork Mon May 13 15:36:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941235 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CB53176 for ; Mon, 13 May 2019 15:37:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BACE0283A6 for ; Mon, 13 May 2019 15:37:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AEFA2283AF; Mon, 13 May 2019 15:37:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 397CD283A6 for ; Mon, 13 May 2019 15:37:47 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id D684BE7D; Mon, 13 May 2019 15:37:33 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 8957AD85 for ; Mon, 13 May 2019 15:37:32 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id A7503875 for ; Mon, 13 May 2019 15:37:31 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608155" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:37:31 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id B6C07401BA41; Tue, 14 May 2019 00:37:29 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:31 +0100 Message-Id: <1557761837-24993-7-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 06/52] pinctrl: sh-pfc: r8a77470: Add EtherAVB pin groups X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit 491e9f585c97c857c52669244c2263cdc5e3e645 upstream. Add EtherAVB groups and functions definitions for R8A77470 SoC. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Simon Horman Signed-off-by: Geert Uytterhoeven Signed-off-by: Fabrizio Castro --- drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 133 ++++++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index 8973f61..4526b0f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -1118,6 +1118,110 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), }; +/* - AVB -------------------------------------------------------------------- */ +static const unsigned int avb_col_pins[] = { + RCAR_GP_PIN(5, 18), +}; +static const unsigned int avb_col_mux[] = { + AVB_COL_MARK, +}; +static const unsigned int avb_crs_pins[] = { + RCAR_GP_PIN(5, 17), +}; +static const unsigned int avb_crs_mux[] = { + AVB_CRS_MARK, +}; +static const unsigned int avb_link_pins[] = { + RCAR_GP_PIN(5, 14), +}; +static const unsigned int avb_link_mux[] = { + AVB_LINK_MARK, +}; +static const unsigned int avb_magic_pins[] = { + RCAR_GP_PIN(5, 15), +}; +static const unsigned int avb_magic_mux[] = { + AVB_MAGIC_MARK, +}; +static const unsigned int avb_phy_int_pins[] = { + RCAR_GP_PIN(5, 16), +}; +static const unsigned int avb_phy_int_mux[] = { + AVB_PHY_INT_MARK, +}; +static const unsigned int avb_mdio_pins[] = { + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), +}; +static const unsigned int avb_mdio_mux[] = { + AVB_MDC_MARK, AVB_MDIO_MARK, +}; +static const unsigned int avb_mii_tx_rx_pins[] = { + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), + RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 13), + + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 1), + RCAR_GP_PIN(3, 10), +}; +static const unsigned int avb_mii_tx_rx_mux[] = { + AVB_TX_CLK_MARK, AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, + AVB_TXD3_MARK, AVB_TX_EN_MARK, + + AVB_RX_CLK_MARK, AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, + AVB_RXD3_MARK, AVB_RX_DV_MARK, AVB_RX_ER_MARK, +}; +static const unsigned int avb_mii_tx_er_pins[] = { + RCAR_GP_PIN(5, 23), +}; +static const unsigned int avb_mii_tx_er_mux[] = { + AVB_TX_ER_MARK, +}; +static const unsigned int avb_gmii_tx_rx_pins[] = { + RCAR_GP_PIN(4, 1), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), + RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(3, 13), + RCAR_GP_PIN(5, 23), + + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), + RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 10), +}; +static const unsigned int avb_gmii_tx_rx_mux[] = { + AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, AVB_TX_CLK_MARK, AVB_TXD0_MARK, + AVB_TXD1_MARK, AVB_TXD2_MARK, AVB_TXD3_MARK, AVB_TXD4_MARK, + AVB_TXD5_MARK, AVB_TXD6_MARK, AVB_TXD7_MARK, AVB_TX_EN_MARK, + AVB_TX_ER_MARK, + + AVB_RX_CLK_MARK, AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, + AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, AVB_RXD6_MARK, + AVB_RXD7_MARK, AVB_RX_DV_MARK, AVB_RX_ER_MARK, +}; +static const unsigned int avb_avtp_match_a_pins[] = { + RCAR_GP_PIN(1, 15), +}; +static const unsigned int avb_avtp_match_a_mux[] = { + AVB_AVTP_MATCH_A_MARK, +}; +static const unsigned int avb_avtp_capture_a_pins[] = { + RCAR_GP_PIN(1, 14), +}; +static const unsigned int avb_avtp_capture_a_mux[] = { + AVB_AVTP_CAPTURE_A_MARK, +}; +static const unsigned int avb_avtp_match_b_pins[] = { + RCAR_GP_PIN(5, 20), +}; +static const unsigned int avb_avtp_match_b_mux[] = { + AVB_AVTP_MATCH_B_MARK, +}; +static const unsigned int avb_avtp_capture_b_pins[] = { + RCAR_GP_PIN(5, 19), +}; +static const unsigned int avb_avtp_capture_b_mux[] = { + AVB_AVTP_CAPTURE_B_MARK, +}; /* - MMC -------------------------------------------------------------------- */ static const unsigned int mmc_data1_pins[] = { /* D0 */ @@ -1395,6 +1499,19 @@ static const unsigned int scif_clk_b_mux[] = { }; static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(avb_col), + SH_PFC_PIN_GROUP(avb_crs), + SH_PFC_PIN_GROUP(avb_link), + SH_PFC_PIN_GROUP(avb_magic), + SH_PFC_PIN_GROUP(avb_phy_int), + SH_PFC_PIN_GROUP(avb_mdio), + SH_PFC_PIN_GROUP(avb_mii_tx_rx), + SH_PFC_PIN_GROUP(avb_mii_tx_er), + SH_PFC_PIN_GROUP(avb_gmii_tx_rx), + SH_PFC_PIN_GROUP(avb_avtp_match_a), + SH_PFC_PIN_GROUP(avb_avtp_capture_a), + SH_PFC_PIN_GROUP(avb_avtp_match_b), + SH_PFC_PIN_GROUP(avb_avtp_capture_b), SH_PFC_PIN_GROUP(mmc_data1), SH_PFC_PIN_GROUP(mmc_data4), SH_PFC_PIN_GROUP(mmc_data8), @@ -1434,6 +1551,21 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif_clk_b), }; +static const char * const avb_groups[] = { + "avb_col", + "avb_crs", + "avb_link", + "avb_magic", + "avb_phy_int", + "avb_mdio", + "avb_mii_tx_rx", + "avb_mii_tx_er", + "avb_gmii_tx_rx", + "avb_avtp_match_a", + "avb_avtp_capture_a", + "avb_avtp_match_b", + "avb_avtp_capture_b", +}; static const char * const mmc_groups[] = { "mmc_data1", "mmc_data4", @@ -1496,6 +1628,7 @@ static const char * const scif_clk_groups[] = { }; static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), From patchwork Mon May 13 15:36:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941237 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 21B3614DB for ; Mon, 13 May 2019 15:37:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0EA9D283A6 for ; Mon, 13 May 2019 15:37:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F4101283AF; Mon, 13 May 2019 15:37:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A36F3283A6 for ; Mon, 13 May 2019 15:37:52 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 0E1F2E81; Mon, 13 May 2019 15:37:35 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 85302D85 for ; Mon, 13 May 2019 15:37:33 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id E72F6878 for ; Mon, 13 May 2019 15:37:32 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608159" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:37:32 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 681BD401BA41; Tue, 14 May 2019 00:37:31 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:32 +0100 Message-Id: <1557761837-24993-8-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 07/52] pinctrl: sh-pfc: r8a77470: Add I2C4 pin groups X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP commit e34ebe5a6b8318eb6d99d5476072e4eddf5c46f2 upstream. Add I2C4 pin groups and function to the R8A77470 SoC. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 51 +++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index 4526b0f..dd54e99 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -1222,6 +1222,42 @@ static const unsigned int avb_avtp_capture_b_pins[] = { static const unsigned int avb_avtp_capture_b_mux[] = { AVB_AVTP_CAPTURE_B_MARK, }; +/* - I2C4 ------------------------------------------------------------------- */ +static const unsigned int i2c4_a_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), +}; +static const unsigned int i2c4_a_mux[] = { + SCL4_A_MARK, SDA4_A_MARK, +}; +static const unsigned int i2c4_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 31), +}; +static const unsigned int i2c4_b_mux[] = { + SCL4_B_MARK, SDA4_B_MARK, +}; +static const unsigned int i2c4_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), +}; +static const unsigned int i2c4_c_mux[] = { + SCL4_C_MARK, SDA4_C_MARK, +}; +static const unsigned int i2c4_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), +}; +static const unsigned int i2c4_d_mux[] = { + SCL4_D_MARK, SDA4_D_MARK, +}; +static const unsigned int i2c4_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 6), +}; +static const unsigned int i2c4_e_mux[] = { + SCL4_E_MARK, SDA4_E_MARK, +}; /* - MMC -------------------------------------------------------------------- */ static const unsigned int mmc_data1_pins[] = { /* D0 */ @@ -1512,6 +1548,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_avtp_capture_a), SH_PFC_PIN_GROUP(avb_avtp_match_b), SH_PFC_PIN_GROUP(avb_avtp_capture_b), + SH_PFC_PIN_GROUP(i2c4_a), + SH_PFC_PIN_GROUP(i2c4_b), + SH_PFC_PIN_GROUP(i2c4_c), + SH_PFC_PIN_GROUP(i2c4_d), + SH_PFC_PIN_GROUP(i2c4_e), SH_PFC_PIN_GROUP(mmc_data1), SH_PFC_PIN_GROUP(mmc_data4), SH_PFC_PIN_GROUP(mmc_data8), @@ -1566,6 +1607,15 @@ static const char * const avb_groups[] = { "avb_avtp_match_b", "avb_avtp_capture_b", }; + +static const char * const i2c4_groups[] = { + "i2c4_a", + "i2c4_b", + "i2c4_c", + "i2c4_d", + "i2c4_e", +}; + static const char * const mmc_groups[] = { "mmc_data1", "mmc_data4", @@ -1629,6 +1679,7 @@ static const char * const scif_clk_groups[] = { static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), From patchwork Mon May 13 15:36:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941241 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 49C4276 for ; Mon, 13 May 2019 15:38:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3ADAC283A6 for ; Mon, 13 May 2019 15:38:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2F58D283AF; Mon, 13 May 2019 15:38:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B6A39283A6 for ; Mon, 13 May 2019 15:38:05 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 55CB7E8F; Mon, 13 May 2019 15:37:37 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id C50F1E89 for ; Mon, 13 May 2019 15:37:35 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id F0BE4878 for ; Mon, 13 May 2019 15:37:34 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810554" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:37:34 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 1F21D401B9F5; Tue, 14 May 2019 00:37:32 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:33 +0100 Message-Id: <1557761837-24993-9-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 08/52] pinctrl: sh-pfc: r8a77470: Add DU0 pin groups X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP commit 469c1e97dcce926f4c41e438c75ac064a7cbf042 upstream. Add DU0 pin groups and function to the R8A77470 SoC. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 109 ++++++++++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index dd54e99..a1eb68b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -1222,6 +1222,93 @@ static const unsigned int avb_avtp_capture_b_pins[] = { static const unsigned int avb_avtp_capture_b_mux[] = { AVB_AVTP_CAPTURE_B_MARK, }; +/* - DU --------------------------------------------------------------------- */ +static const unsigned int du0_rgb666_pins[] = { + /* R[7:2], G[7:2], B[7:2] */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), + RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21), + RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18), +}; +static const unsigned int du0_rgb666_mux[] = { + DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, + DU0_DR3_MARK, DU0_DR2_MARK, + DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK, + DU0_DG3_MARK, DU0_DG2_MARK, + DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK, + DU0_DB3_MARK, DU0_DB2_MARK, +}; +static const unsigned int du0_rgb888_pins[] = { + /* R[7:0], G[7:0], B[7:0] */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 0), + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), + RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8), + RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21), + RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16), +}; +static const unsigned int du0_rgb888_mux[] = { + DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, + DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK, + DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK, + DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK, + DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK, + DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK, +}; +static const unsigned int du0_clk0_out_pins[] = { + /* DOTCLKOUT0 */ + RCAR_GP_PIN(2, 25), +}; +static const unsigned int du0_clk0_out_mux[] = { + DU0_DOTCLKOUT0_MARK +}; +static const unsigned int du0_clk1_out_pins[] = { + /* DOTCLKOUT1 */ + RCAR_GP_PIN(2, 26), +}; +static const unsigned int du0_clk1_out_mux[] = { + DU0_DOTCLKOUT1_MARK +}; +static const unsigned int du0_clk_in_pins[] = { + /* CLKIN */ + RCAR_GP_PIN(2, 24), +}; +static const unsigned int du0_clk_in_mux[] = { + DU0_DOTCLKIN_MARK +}; +static const unsigned int du0_sync_pins[] = { + /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ + RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27), +}; +static const unsigned int du0_sync_mux[] = { + DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK +}; +static const unsigned int du0_oddf_pins[] = { + /* EXODDF/ODDF/DISP/CDE */ + RCAR_GP_PIN(2, 29), +}; +static const unsigned int du0_oddf_mux[] = { + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, +}; +static const unsigned int du0_cde_pins[] = { + /* CDE */ + RCAR_GP_PIN(2, 31), +}; +static const unsigned int du0_cde_mux[] = { + DU0_CDE_MARK, +}; +static const unsigned int du0_disp_pins[] = { + /* DISP */ + RCAR_GP_PIN(2, 30), +}; +static const unsigned int du0_disp_mux[] = { + DU0_DISP_MARK +}; /* - I2C4 ------------------------------------------------------------------- */ static const unsigned int i2c4_a_pins[] = { /* SCL, SDA */ @@ -1548,6 +1635,15 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_avtp_capture_a), SH_PFC_PIN_GROUP(avb_avtp_match_b), SH_PFC_PIN_GROUP(avb_avtp_capture_b), + SH_PFC_PIN_GROUP(du0_rgb666), + SH_PFC_PIN_GROUP(du0_rgb888), + SH_PFC_PIN_GROUP(du0_clk0_out), + SH_PFC_PIN_GROUP(du0_clk1_out), + SH_PFC_PIN_GROUP(du0_clk_in), + SH_PFC_PIN_GROUP(du0_sync), + SH_PFC_PIN_GROUP(du0_oddf), + SH_PFC_PIN_GROUP(du0_cde), + SH_PFC_PIN_GROUP(du0_disp), SH_PFC_PIN_GROUP(i2c4_a), SH_PFC_PIN_GROUP(i2c4_b), SH_PFC_PIN_GROUP(i2c4_c), @@ -1608,6 +1704,18 @@ static const char * const avb_groups[] = { "avb_avtp_capture_b", }; +static const char * const du0_groups[] = { + "du0_rgb666", + "du0_rgb888", + "du0_clk0_out", + "du0_clk1_out", + "du0_clk_in", + "du0_sync", + "du0_oddf", + "du0_cde", + "du0_disp", +}; + static const char * const i2c4_groups[] = { "i2c4_a", "i2c4_b", @@ -1679,6 +1787,7 @@ static const char * const scif_clk_groups[] = { static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(scif0), From patchwork Mon May 13 15:36:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941243 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B8ABD933 for ; Mon, 13 May 2019 15:38:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AAAAE28358 for ; Mon, 13 May 2019 15:38:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9F03D283A8; Mon, 13 May 2019 15:38:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4E8DA28358 for ; Mon, 13 May 2019 15:38:11 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id A2130E6C; Mon, 13 May 2019 15:37:38 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 512A6E8E for ; Mon, 13 May 2019 15:37:37 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id B282E27B for ; Mon, 13 May 2019 15:37:36 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608162" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:37:36 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id C78A5401B9F5; Tue, 14 May 2019 00:37:34 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:34 +0100 Message-Id: <1557761837-24993-10-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 09/52] pinctrl: sh-pfc: r8a77470: Add QSPI0 pin groups X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP commit e5984d0576fbcd756a3c03f1d3136fdc46b30c74 upstream. Add QSPI0 pin groups and function to the R8A77470 SoC. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index a1eb68b..77e8b59 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -1382,6 +1382,30 @@ static const unsigned int mmc_ctrl_pins[] = { static const unsigned int mmc_ctrl_mux[] = { MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK, }; +/* - QSPI ------------------------------------------------------------------- */ +static const unsigned int qspi0_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 21), +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), +}; +static const unsigned int qspi0_data2_mux[] = { + QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK, +}; +static const unsigned int qspi0_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), + RCAR_GP_PIN(1, 20), +}; +static const unsigned int qspi0_data4_mux[] = { + QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK, +}; /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_a_pins[] = { /* RX, TX */ @@ -1653,6 +1677,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc_data4), SH_PFC_PIN_GROUP(mmc_data8), SH_PFC_PIN_GROUP(mmc_ctrl), + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP(qspi0_data2), + SH_PFC_PIN_GROUP(qspi0_data4), SH_PFC_PIN_GROUP(scif0_data_a), SH_PFC_PIN_GROUP(scif0_data_b), SH_PFC_PIN_GROUP(scif0_data_c), @@ -1731,6 +1758,12 @@ static const char * const mmc_groups[] = { "mmc_ctrl", }; +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + static const char * const scif0_groups[] = { "scif0_data_a", "scif0_data_b", @@ -1790,6 +1823,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(mmc), + SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), From patchwork Mon May 13 15:36:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941245 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F34A6933 for ; Mon, 13 May 2019 15:38:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E16B528358 for ; Mon, 13 May 2019 15:38:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D369D283A8; Mon, 13 May 2019 15:38:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7CF8B28358 for ; Mon, 13 May 2019 15:38:19 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id BAA4BE96; Mon, 13 May 2019 15:37:39 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 83859E8B for ; Mon, 13 May 2019 15:37:38 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id EEE2583A for ; Mon, 13 May 2019 15:37:37 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608165" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:37:37 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 776F9401B9F5; Tue, 14 May 2019 00:37:36 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:35 +0100 Message-Id: <1557761837-24993-11-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 10/52] pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP commit df9c71694fcf84f4956b07750afa8608cc0a84ad upstream. Add SDHI2 pin groups and functions to the R8A77470 SoC. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 51 +++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index 77e8b59..a103740 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -1644,6 +1644,43 @@ static const unsigned int scif_clk_b_pins[] = { static const unsigned int scif_clk_b_mux[] = { SCIF_CLK_B_MARK, }; +/* - SDHI2 ------------------------------------------------------------------ */ +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(4, 16), +}; +static const unsigned int sdhi2_data1_mux[] = { + SD2_DAT0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), + RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19), +}; +static const unsigned int sdhi2_data4_mux[] = { + SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SD2_CLK_MARK, SD2_CMD_MARK, +}; +static const unsigned int sdhi2_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(4, 20), +}; +static const unsigned int sdhi2_cd_mux[] = { + SD2_CD_MARK, +}; +static const unsigned int sdhi2_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(4, 21), +}; +static const unsigned int sdhi2_wp_mux[] = { + SD2_WP_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_col), @@ -1713,6 +1750,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_data_f), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd), + SH_PFC_PIN_GROUP(sdhi2_wp), }; static const char * const avb_groups[] = { @@ -1818,6 +1860,14 @@ static const char * const scif_clk_groups[] = { "scif_clk_b", }; +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_ctrl", + "sdhi2_cd", + "sdhi2_wp", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(du0), @@ -1831,6 +1881,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi2), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { From patchwork Mon May 13 15:36:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941247 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3E90D76 for ; Mon, 13 May 2019 15:38:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 305D5283A6 for ; Mon, 13 May 2019 15:38:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 24936283AF; Mon, 13 May 2019 15:38:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C86F7283A6 for ; Mon, 13 May 2019 15:38:24 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id D0F16E98; Mon, 13 May 2019 15:37:40 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 2FA0CE98 for ; Mon, 13 May 2019 15:37:40 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id A1F3383A for ; Mon, 13 May 2019 15:37:39 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608168" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:37:39 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 2B3ED401BA41; Tue, 14 May 2019 00:37:37 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:36 +0100 Message-Id: <1557761837-24993-12-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 11/52] pinctrl: sh-pfc: r8a77470: Add USB pin groups X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP commit 8faa0754ec246bb40034c6d8afca72afef54bd10 upstream. Add USB[01] pin groups and functions to the R8A77470 SoC. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index a103740..283217f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -1681,6 +1681,24 @@ static const unsigned int sdhi2_wp_pins[] = { static const unsigned int sdhi2_wp_mux[] = { SD2_WP_MARK, }; +/* - USB0 ------------------------------------------------------------------- */ +static const unsigned int usb0_pins[] = { + RCAR_GP_PIN(0, 0), /* PWEN */ + RCAR_GP_PIN(0, 1), /* OVC */ +}; +static const unsigned int usb0_mux[] = { + USB0_PWEN_MARK, + USB0_OVC_MARK, +}; +/* - USB1 ------------------------------------------------------------------- */ +static const unsigned int usb1_pins[] = { + RCAR_GP_PIN(0, 2), /* PWEN */ + RCAR_GP_PIN(0, 3), /* OVC */ +}; +static const unsigned int usb1_mux[] = { + USB1_PWEN_MARK, + USB1_OVC_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_col), @@ -1755,6 +1773,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd), SH_PFC_PIN_GROUP(sdhi2_wp), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb1), }; static const char * const avb_groups[] = { @@ -1868,6 +1888,14 @@ static const char * const sdhi2_groups[] = { "sdhi2_wp", }; +static const char * const usb0_groups[] = { + "usb0", +}; + +static const char * const usb1_groups[] = { + "usb1", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(du0), @@ -1882,6 +1910,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif5), SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { From patchwork Mon May 13 15:36:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941249 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1C3D8933 for ; Mon, 13 May 2019 15:38:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0D356283A6 for ; Mon, 13 May 2019 15:38:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 017DD283AF; Mon, 13 May 2019 15:38:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 77E77283A6 for ; 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Tue, 14 May 2019 00:37:39 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:37 +0100 Message-Id: <1557761837-24993-13-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 12/52] pinctrl: sh-pfc: r8a77470: Add remaining I2C pin groups X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP commit 80ef7d09104424120c5a9e531f6c41ecb14b023c upstream. This patch adds I2C[0123] groups and functions to the RZ/G1C (a.k.a. R8A77470) pinctrl driver. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Simon Horman Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 191 ++++++++++++++++++++++++++++++++++ 1 file changed, 191 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index 283217f..3ca236a 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -1309,6 +1309,143 @@ static const unsigned int du0_disp_pins[] = { static const unsigned int du0_disp_mux[] = { DU0_DISP_MARK }; +/* - I2C0 ------------------------------------------------------------------- */ +static const unsigned int i2c0_a_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), +}; +static const unsigned int i2c0_a_mux[] = { + SCL0_A_MARK, SDA0_A_MARK, +}; +static const unsigned int i2c0_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29), +}; +static const unsigned int i2c0_b_mux[] = { + SCL0_B_MARK, SDA0_B_MARK, +}; +static const unsigned int i2c0_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), +}; +static const unsigned int i2c0_c_mux[] = { + SCL0_C_MARK, SDA0_C_MARK, +}; +static const unsigned int i2c0_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), +}; +static const unsigned int i2c0_d_mux[] = { + SCL0_D_MARK, SDA0_D_MARK, +}; +static const unsigned int i2c0_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), +}; +static const unsigned int i2c0_e_mux[] = { + SCL0_E_MARK, SDA0_E_MARK, +}; +/* - I2C1 ------------------------------------------------------------------- */ +static const unsigned int i2c1_a_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), +}; +static const unsigned int i2c1_a_mux[] = { + SCL1_A_MARK, SDA1_A_MARK, +}; +static const unsigned int i2c1_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), +}; +static const unsigned int i2c1_b_mux[] = { + SCL1_B_MARK, SDA1_B_MARK, +}; +static const unsigned int i2c1_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), +}; +static const unsigned int i2c1_c_mux[] = { + SCL1_C_MARK, SDA1_C_MARK, +}; +static const unsigned int i2c1_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9), +}; +static const unsigned int i2c1_d_mux[] = { + SCL1_D_MARK, SDA1_D_MARK, +}; +static const unsigned int i2c1_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), +}; +static const unsigned int i2c1_e_mux[] = { + SCL1_E_MARK, SDA1_E_MARK, +}; +/* - I2C2 ------------------------------------------------------------------- */ +static const unsigned int i2c2_a_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25), +}; +static const unsigned int i2c2_a_mux[] = { + SCL2_A_MARK, SDA2_A_MARK, +}; +static const unsigned int i2c2_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), +}; +static const unsigned int i2c2_b_mux[] = { + SCL2_B_MARK, SDA2_B_MARK, +}; +static const unsigned int i2c2_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), +}; +static const unsigned int i2c2_c_mux[] = { + SCL2_C_MARK, SDA2_C_MARK, +}; +static const unsigned int i2c2_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), +}; +static const unsigned int i2c2_d_mux[] = { + SCL2_D_MARK, SDA2_D_MARK, +}; +/* - I2C3 ------------------------------------------------------------------- */ +static const unsigned int i2c3_a_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), +}; +static const unsigned int i2c3_a_mux[] = { + SCL3_A_MARK, SDA3_A_MARK, +}; +static const unsigned int i2c3_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), +}; +static const unsigned int i2c3_b_mux[] = { + SCL3_B_MARK, SDA3_B_MARK, +}; +static const unsigned int i2c3_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; +static const unsigned int i2c3_c_mux[] = { + SCL3_C_MARK, SDA3_C_MARK, +}; +static const unsigned int i2c3_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), +}; +static const unsigned int i2c3_d_mux[] = { + SCL3_D_MARK, SDA3_D_MARK, +}; +static const unsigned int i2c3_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), +}; +static const unsigned int i2c3_e_mux[] = { + SCL3_E_MARK, SDA3_E_MARK, +}; /* - I2C4 ------------------------------------------------------------------- */ static const unsigned int i2c4_a_pins[] = { /* SCL, SDA */ @@ -1723,6 +1860,25 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du0_oddf), SH_PFC_PIN_GROUP(du0_cde), SH_PFC_PIN_GROUP(du0_disp), + SH_PFC_PIN_GROUP(i2c0_a), + SH_PFC_PIN_GROUP(i2c0_b), + SH_PFC_PIN_GROUP(i2c0_c), + SH_PFC_PIN_GROUP(i2c0_d), + SH_PFC_PIN_GROUP(i2c0_e), + SH_PFC_PIN_GROUP(i2c1_a), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c1_c), + SH_PFC_PIN_GROUP(i2c1_d), + SH_PFC_PIN_GROUP(i2c1_e), + SH_PFC_PIN_GROUP(i2c2_a), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c2_c), + SH_PFC_PIN_GROUP(i2c2_d), + SH_PFC_PIN_GROUP(i2c3_a), + SH_PFC_PIN_GROUP(i2c3_b), + SH_PFC_PIN_GROUP(i2c3_c), + SH_PFC_PIN_GROUP(i2c3_d), + SH_PFC_PIN_GROUP(i2c3_e), SH_PFC_PIN_GROUP(i2c4_a), SH_PFC_PIN_GROUP(i2c4_b), SH_PFC_PIN_GROUP(i2c4_c), @@ -1805,6 +1961,37 @@ static const char * const du0_groups[] = { "du0_disp", }; +static const char * const i2c0_groups[] = { + "i2c0_a", + "i2c0_b", + "i2c0_c", + "i2c0_d", + "i2c0_e", +}; + +static const char * const i2c1_groups[] = { + "i2c1_a", + "i2c1_b", + "i2c1_c", + "i2c1_d", + "i2c1_e", +}; + +static const char * const i2c2_groups[] = { + "i2c2_a", + "i2c2_b", + "i2c2_c", + "i2c2_d", +}; + +static const char * const i2c3_groups[] = { + "i2c3_a", + "i2c3_b", + "i2c3_c", + "i2c3_d", + "i2c3_e", +}; + static const char * const i2c4_groups[] = { "i2c4_a", "i2c4_b", @@ -1899,6 +2086,10 @@ static const char * const usb1_groups[] = { static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(du0), + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(qspi0), From patchwork Mon May 13 15:36:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941251 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1556B76 for ; Mon, 13 May 2019 15:38:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0719B283A6 for ; Mon, 13 May 2019 15:38:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EFC27283AF; Mon, 13 May 2019 15:38:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 82A42283A6 for ; Mon, 13 May 2019 15:38:34 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 1CC8FEA3; Mon, 13 May 2019 15:37:45 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id CA7BBE8D for ; Mon, 13 May 2019 15:37:43 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 1A71927B for ; Mon, 13 May 2019 15:37:42 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810564" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:37:42 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 933C0401BA41; Tue, 14 May 2019 00:37:41 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:38 +0100 Message-Id: <1557761837-24993-14-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 13/52] pinctrl: sh-pfc: r8a77470: Add DU1 pin groups X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP commit 5c9258bca9ace0a25614b635fc1c2836ee4d8c96 upstream. Add DU1 pin groups and function to the RZ/G1C (a.k.a. R8A77470) pinctrl driver. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Simon Horman Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 108 ++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index 3ca236a..81ef3af 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -1309,6 +1309,92 @@ static const unsigned int du0_disp_pins[] = { static const unsigned int du0_disp_mux[] = { DU0_DISP_MARK }; +static const unsigned int du1_rgb666_pins[] = { + /* R[7:2], G[7:2], B[7:2] */ + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7), + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4), + RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15), + RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12), + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23), + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), +}; +static const unsigned int du1_rgb666_mux[] = { + DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, + DU1_DR3_MARK, DU1_DR2_MARK, + DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, + DU1_DG3_MARK, DU1_DG2_MARK, + DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, + DU1_DB3_MARK, DU1_DB2_MARK, +}; +static const unsigned int du1_rgb888_pins[] = { + /* R[7:0], G[7:0], B[7:0] */ + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7), + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4), + RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), + RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15), + RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12), + RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10), + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23), + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), + RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18), +}; +static const unsigned int du1_rgb888_mux[] = { + DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, + DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK, + DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, + DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK, + DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, + DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK, +}; +static const unsigned int du1_clk0_out_pins[] = { + /* DOTCLKOUT0 */ + RCAR_GP_PIN(5, 2), +}; +static const unsigned int du1_clk0_out_mux[] = { + DU1_DOTCLKOUT0_MARK +}; +static const unsigned int du1_clk1_out_pins[] = { + /* DOTCLKOUT1 */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int du1_clk1_out_mux[] = { + DU1_DOTCLKOUT1_MARK +}; +static const unsigned int du1_clk_in_pins[] = { + /* DOTCLKIN */ + RCAR_GP_PIN(5, 1), +}; +static const unsigned int du1_clk_in_mux[] = { + DU1_DOTCLKIN_MARK +}; +static const unsigned int du1_sync_pins[] = { + /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 4), +}; +static const unsigned int du1_sync_mux[] = { + DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK +}; +static const unsigned int du1_oddf_pins[] = { + /* EXODDF/ODDF/DISP/CDE */ + RCAR_GP_PIN(5, 3), +}; +static const unsigned int du1_oddf_mux[] = { + DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, +}; +static const unsigned int du1_cde_pins[] = { + /* CDE */ + RCAR_GP_PIN(5, 7), +}; +static const unsigned int du1_cde_mux[] = { + DU1_CDE_MARK +}; +static const unsigned int du1_disp_pins[] = { + /* DISP */ + RCAR_GP_PIN(5, 6), +}; +static const unsigned int du1_disp_mux[] = { + DU1_DISP_MARK +}; /* - I2C0 ------------------------------------------------------------------- */ static const unsigned int i2c0_a_pins[] = { /* SCL, SDA */ @@ -1860,6 +1946,15 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du0_oddf), SH_PFC_PIN_GROUP(du0_cde), SH_PFC_PIN_GROUP(du0_disp), + SH_PFC_PIN_GROUP(du1_rgb666), + SH_PFC_PIN_GROUP(du1_rgb888), + SH_PFC_PIN_GROUP(du1_clk0_out), + SH_PFC_PIN_GROUP(du1_clk1_out), + SH_PFC_PIN_GROUP(du1_clk_in), + SH_PFC_PIN_GROUP(du1_sync), + SH_PFC_PIN_GROUP(du1_oddf), + SH_PFC_PIN_GROUP(du1_cde), + SH_PFC_PIN_GROUP(du1_disp), SH_PFC_PIN_GROUP(i2c0_a), SH_PFC_PIN_GROUP(i2c0_b), SH_PFC_PIN_GROUP(i2c0_c), @@ -1961,6 +2056,18 @@ static const char * const du0_groups[] = { "du0_disp", }; +static const char * const du1_groups[] = { + "du1_rgb666", + "du1_rgb888", + "du1_clk0_out", + "du1_clk1_out", + "du1_clk_in", + "du1_sync", + "du1_oddf", + "du1_cde", + "du1_disp", +}; + static const char * const i2c0_groups[] = { "i2c0_a", "i2c0_b", @@ -2086,6 +2193,7 @@ static const char * const usb1_groups[] = { static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(du0), + SH_PFC_FUNCTION(du1), SH_PFC_FUNCTION(i2c0), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), From patchwork Mon May 13 15:36:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941253 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 95C6276 for ; Mon, 13 May 2019 15:38:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 87065283A6 for ; Mon, 13 May 2019 15:38:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7B885283AF; Mon, 13 May 2019 15:38:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id F3A8B283A6 for ; Mon, 13 May 2019 15:38:41 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 33739EB0; Mon, 13 May 2019 15:37:47 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id A6A70EA8 for ; Mon, 13 May 2019 15:37:45 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id BDCED27B for ; Mon, 13 May 2019 15:37:44 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608174" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:37:44 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 439F6401B9F5; Tue, 14 May 2019 00:37:43 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:39 +0100 Message-Id: <1557761837-24993-15-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 14/52] pinctrl: sh-pfc: r8a77470: Add VIN pin groups X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP commit 610d662ac3d38ef0acad2c1128e6a9a547fd8c0f upstream. Add VIN[01] pin groups and functions to the RZ/G1C (a.k.a. R8A77470) pinctrl driver. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Simon Horman Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 184 ++++++++++++++++++++++++++++++++++ 1 file changed, 184 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index 81ef3af..f23042e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -1922,6 +1922,146 @@ static const unsigned int usb1_mux[] = { USB1_PWEN_MARK, USB1_OVC_MARK, }; +/* - VIN0 ------------------------------------------------------------------- */ +static const union vin_data vin0_data_pins = { + .data24 = { + /* B */ + RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), + RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), + RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), + RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), + /* G */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8), + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), + /* R */ + RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12), + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), + RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19), + }, +}; +static const union vin_data vin0_data_mux = { + .data24 = { + /* B */ + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G0_MARK, VI0_G1_MARK, + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R0_MARK, VI0_R1_MARK, + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, + }, +}; +static const unsigned int vin0_data18_pins[] = { + /* B */ + RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), + RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), + RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), + /* G */ + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8), + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), + /* R */ + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), + RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19), +}; +static const unsigned int vin0_data18_mux[] = { + /* B */ + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, +}; +static const unsigned int vin0_sync_pins[] = { + RCAR_GP_PIN(5, 30), /* HSYNC */ + RCAR_GP_PIN(5, 31), /* VSYNC */ +}; +static const unsigned int vin0_sync_mux[] = { + VI0_HSYNC_N_MARK, + VI0_VSYNC_N_MARK, +}; +static const unsigned int vin0_field_pins[] = { + RCAR_GP_PIN(5, 29), +}; +static const unsigned int vin0_field_mux[] = { + VI0_FIELD_MARK, +}; +static const unsigned int vin0_clkenb_pins[] = { + RCAR_GP_PIN(5, 28), +}; +static const unsigned int vin0_clkenb_mux[] = { + VI0_CLKENB_MARK, +}; +static const unsigned int vin0_clk_pins[] = { + RCAR_GP_PIN(5, 18), +}; +static const unsigned int vin0_clk_mux[] = { + VI0_CLK_MARK, +}; +/* - VIN1 ------------------------------------------------------------------- */ +static const union vin_data vin1_data_pins = { + .data12 = { + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), + RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), + RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), + }, +}; +static const union vin_data vin1_data_mux = { + .data12 = { + VI1_DATA0_MARK, VI1_DATA1_MARK, + VI1_DATA2_MARK, VI1_DATA3_MARK, + VI1_DATA4_MARK, VI1_DATA5_MARK, + VI1_DATA6_MARK, VI1_DATA7_MARK, + VI1_DATA8_MARK, VI1_DATA9_MARK, + VI1_DATA10_MARK, VI1_DATA11_MARK, + }, +}; +static const unsigned int vin1_sync_pins[] = { + RCAR_GP_PIN(3, 11), /* HSYNC */ + RCAR_GP_PIN(3, 12), /* VSYNC */ +}; +static const unsigned int vin1_sync_mux[] = { + VI1_HSYNC_N_MARK, + VI1_VSYNC_N_MARK, +}; +static const unsigned int vin1_field_pins[] = { + RCAR_GP_PIN(3, 10), +}; +static const unsigned int vin1_field_mux[] = { + VI1_FIELD_MARK, +}; +static const unsigned int vin1_clkenb_pins[] = { + RCAR_GP_PIN(3, 9), +}; +static const unsigned int vin1_clkenb_mux[] = { + VI1_CLKENB_MARK, +}; +static const unsigned int vin1_clk_pins[] = { + RCAR_GP_PIN(3, 0), +}; +static const unsigned int vin1_clk_mux[] = { + VI1_CLK_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_col), @@ -2026,6 +2166,24 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi2_wp), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), + VIN_DATA_PIN_GROUP(vin0_data, 24), + VIN_DATA_PIN_GROUP(vin0_data, 20), + SH_PFC_PIN_GROUP(vin0_data18), + VIN_DATA_PIN_GROUP(vin0_data, 16), + VIN_DATA_PIN_GROUP(vin0_data, 12), + VIN_DATA_PIN_GROUP(vin0_data, 10), + VIN_DATA_PIN_GROUP(vin0_data, 8), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin0_field), + SH_PFC_PIN_GROUP(vin0_clkenb), + SH_PFC_PIN_GROUP(vin0_clk), + VIN_DATA_PIN_GROUP(vin1_data, 12), + VIN_DATA_PIN_GROUP(vin1_data, 10), + VIN_DATA_PIN_GROUP(vin1_data, 8), + SH_PFC_PIN_GROUP(vin1_sync), + SH_PFC_PIN_GROUP(vin1_field), + SH_PFC_PIN_GROUP(vin1_clkenb), + SH_PFC_PIN_GROUP(vin1_clk), }; static const char * const avb_groups[] = { @@ -2190,6 +2348,30 @@ static const char * const usb1_groups[] = { "usb1", }; +static const char * const vin0_groups[] = { + "vin0_data24", + "vin0_data20", + "vin0_data18", + "vin0_data16", + "vin0_data12", + "vin0_data10", + "vin0_data8", + "vin0_sync", + "vin0_field", + "vin0_clkenb", + "vin0_clk", +}; + +static const char * const vin1_groups[] = { + "vin1_data12", + "vin1_data10", + "vin1_data8", + "vin1_sync", + "vin1_field", + "vin1_clkenb", + "vin1_clk", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(du0), @@ -2211,6 +2393,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { From patchwork Mon May 13 15:36:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941255 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E596F933 for ; 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Mon, 13 May 2019 15:37:47 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 6EBBA27B for ; Mon, 13 May 2019 15:37:46 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810568" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:37:46 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id E76DA401B9F5; Tue, 14 May 2019 00:37:44 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:40 +0100 Message-Id: <1557761837-24993-16-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 15/52] pinctrl: sh-pfc: r8a77470: Add QSPI1 pin groups X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP commit f743f017b739e27601fec7d3eab29840c5e95b37 upstream. Add QSPI1 pin groups and function to the RZ/G1C (a.k.a. R8A77470) pinctrl driver. Signed-off-by: Fabrizio Castro Reviewed-by: Fabrizio Castro Reviewed-by: Simon Horman Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index f23042e..395d1fd 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -1629,6 +1629,29 @@ static const unsigned int qspi0_data4_mux[] = { QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK, QSPI0_IO2_MARK, QSPI0_IO3_MARK, }; +static const unsigned int qspi1_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 9), +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), +}; +static const unsigned int qspi1_data2_mux[] = { + QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK, +}; +static const unsigned int qspi1_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7), + RCAR_GP_PIN(4, 8), +}; +static const unsigned int qspi1_data4_mux[] = { + QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK, +}; /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_a_pins[] = { /* RX, TX */ @@ -2126,6 +2149,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(qspi0_ctrl), SH_PFC_PIN_GROUP(qspi0_data2), SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP(qspi1_data2), + SH_PFC_PIN_GROUP(qspi1_data4), SH_PFC_PIN_GROUP(scif0_data_a), SH_PFC_PIN_GROUP(scif0_data_b), SH_PFC_PIN_GROUP(scif0_data_c), @@ -2278,6 +2304,12 @@ static const char * const qspi0_groups[] = { "qspi0_data4", }; +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + static const char * const scif0_groups[] = { "scif0_data_a", "scif0_data_b", @@ -2383,6 +2415,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), From patchwork Mon May 13 15:36:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941257 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D4949933 for ; Mon, 13 May 2019 15:38:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C4C85283A6 for ; Mon, 13 May 2019 15:38:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B9872283AF; Mon, 13 May 2019 15:38:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 624A0283A6 for ; Mon, 13 May 2019 15:38:51 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 68418EB8; Mon, 13 May 2019 15:37:50 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id AE355E71 for ; Mon, 13 May 2019 15:37:48 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 243F327B for ; Mon, 13 May 2019 15:37:48 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810571" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:37:47 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 9A3EC401BA41; Tue, 14 May 2019 00:37:46 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:41 +0100 Message-Id: <1557761837-24993-17-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 16/52] soc: renesas: rcar-rst: Add support for RZ/G1C X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit a3a9033f1193842c6e0b518db196ade0f882cf78 upstream. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman Signed-off-by: Fabrizio Castro --- Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 + drivers/soc/renesas/rcar-rst.c | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt index fff2e8e..fb5f68e 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rst.txt +++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt @@ -8,6 +8,7 @@ Required properties: Examples with soctypes are: - "renesas,r8a7743-rst" (RZ/G1M) - "renesas,r8a7745-rst" (RZ/G1E) + - "renesas,r8a77470-rst" (RZ/G1C) - "renesas,r8a7790-rst" (R-Car H2) - "renesas,r8a7791-rst" (R-Car M2-W) - "renesas,r8a7792-rst" (R-Car V2H diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c index 0622006..caaa029 100644 --- a/drivers/soc/renesas/rcar-rst.c +++ b/drivers/soc/renesas/rcar-rst.c @@ -34,6 +34,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = { /* RZ/G is handled like R-Car Gen2 */ { .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 }, { .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 }, + { .compatible = "renesas,r8a77470-rst", .data = &rcar_rst_gen2 }, /* R-Car Gen2 */ { .compatible = "renesas,r8a7790-rst", .data = &rcar_rst_gen2 }, { .compatible = "renesas,r8a7791-rst", .data = &rcar_rst_gen2 }, From patchwork Mon May 13 15:36:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941259 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 05D4F76 for ; Mon, 13 May 2019 15:38:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EB1DF283A6 for ; Mon, 13 May 2019 15:38:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DFDFD283AF; Mon, 13 May 2019 15:38:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8D33A283A6 for ; Mon, 13 May 2019 15:38:56 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 83E12EAF; Mon, 13 May 2019 15:37:51 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 5D203EAF for ; Mon, 13 May 2019 15:37:50 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id C6A6627B for ; Mon, 13 May 2019 15:37:49 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810574" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:37:49 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 4E1BE401B9F5; Tue, 14 May 2019 00:37:48 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:42 +0100 Message-Id: <1557761837-24993-18-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 17/52] ARM: debug-ll: Add support for r8a77470 X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit 2f095c261a0fe15aacf1c3b2958b4d23a4735b4e upstream. Enable low-level debugging support for RZ/G1C (r8a77470). RZ/G1C uses SCIF1 for the debug console. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman Signed-off-by: Fabrizio Castro --- arch/arm/Kconfig.debug | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index c84f87b..e5c9e93 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -824,6 +824,13 @@ choice via SCIF0 on Renesas RZ/G1M (R8A7743), R-Car H2 (R8A7790), M2-W (R8A7791), or M2-N (R8A7793). + config DEBUG_RCAR_GEN2_SCIF1 + bool "Kernel low-level debugging messages via SCIF1 on R8A77470" + depends on ARCH_R8A77470 + help + Say Y here if you want kernel low-level debugging support + via SCIF1 on Renesas RZ/G1C (R8A77470). + config DEBUG_RCAR_GEN2_SCIF2 bool "Kernel low-level debugging messages via SCIF2 on R8A7794" depends on ARCH_R8A7794 @@ -1340,6 +1347,7 @@ config DEBUG_LL_INCLUDE default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF0 default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF2 default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF0 + default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF1 default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF2 default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF4 default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA0 @@ -1442,6 +1450,7 @@ config DEBUG_UART_PHYS default 0xe6c80000 if DEBUG_RMOBILE_SCIFA4 default 0xe6e58000 if DEBUG_RCAR_GEN2_SCIF2 default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0 + default 0xe6e68000 if DEBUG_RCAR_GEN2_SCIF1 default 0xe6ee0000 if DEBUG_RCAR_GEN2_SCIF4 default 0xe8008000 if DEBUG_R7S72100_SCIF2 default 0xf0000be0 if ARCH_EBSA110 @@ -1475,8 +1484,8 @@ config DEBUG_UART_PHYS DEBUG_NETX_UART || \ DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \ DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \ - DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF2 || \ - DEBUG_RCAR_GEN2_SCIF4 || \ + DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF1 || \ + DEBUG_RCAR_GEN2_SCIF2 || DEBUG_RCAR_GEN2_SCIF4 || \ DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \ DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \ DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \ From patchwork Mon May 13 15:36:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941261 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 32566933 for ; Mon, 13 May 2019 15:39:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 21F3E283A6 for ; Mon, 13 May 2019 15:39:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 16709283AF; Mon, 13 May 2019 15:39:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B57B1283A6 for ; Mon, 13 May 2019 15:39:01 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id AB5E1EC2; Mon, 13 May 2019 15:37:53 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 7AEAEEC0 for ; Mon, 13 May 2019 15:37:52 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id E148227B for ; Mon, 13 May 2019 15:37:51 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608185" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:37:51 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id F1DF2401B9F5; Tue, 14 May 2019 00:37:49 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:43 +0100 Message-Id: <1557761837-24993-19-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 18/52] gpiolib: Extract mask allocation into subroutine X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Stephen Boyd commit e4371f6e079294369ecb4cfa03aaeb60831e8b91 upstream. We're going to use similar code to allocate and set all the bits in a mask for valid gpios to use. Extract the code from the irqchip version so it can be reused. Signed-off-by: Stephen Boyd Tested-by: Timur Tabi Reviewed-by: Andy Shevchenko Signed-off-by: Linus Walleij [fab: removed change from function gpiochip_irqchip_init_valid_mask] Signed-off-by: Fabrizio Castro --- drivers/gpio/gpiolib.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 827510d..0e4e753 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -279,6 +279,20 @@ static int gpiochip_set_desc_names(struct gpio_chip *gc) return 0; } +static unsigned long *gpiochip_allocate_mask(struct gpio_chip *chip) +{ + unsigned long *p; + + p = kcalloc(BITS_TO_LONGS(chip->ngpio), sizeof(long), GFP_KERNEL); + if (!p) + return NULL; + + /* Assume by default all GPIOs are valid */ + bitmap_fill(p, chip->ngpio); + + return p; +} + /** * gpiochip_add_data() - register a gpio_chip * @chip: the chip to register, with chip->base initialized From patchwork Mon May 13 15:36:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941263 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5D43F933 for ; Mon, 13 May 2019 15:39:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 46CB4283A6 for ; Mon, 13 May 2019 15:39:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 39A72283AF; Mon, 13 May 2019 15:39:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B32A6283A6 for ; Mon, 13 May 2019 15:39:08 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id C13F5ED0; Mon, 13 May 2019 15:37:54 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 1111BEB7 for ; Mon, 13 May 2019 15:37:54 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 2C2F927B for ; Mon, 13 May 2019 15:37:53 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810578" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:37:52 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id A6A76401BBEF; Tue, 14 May 2019 00:37:51 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:44 +0100 Message-Id: <1557761837-24993-20-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 19/52] gpiolib: Support 'gpio-reserved-ranges' property X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Stephen Boyd commit 726cb3ba49692bdae6caff457755e7cdb432efa4 upstream. Some qcom platforms make some GPIOs or pins unavailable for use by non-secure operating systems, and thus reading or writing the registers for those pins will cause access control issues. Add support for a DT property to describe the set of GPIOs that are available for use so that higher level OSes are able to know what pins to avoid reading/writing. Non-DT platforms can add support by directly updating the chip->valid_mask. Signed-off-by: Stephen Boyd Signed-off-by: Stephen Boyd Tested-by: Timur Tabi Reviewed-by: Andy Shevchenko Signed-off-by: Linus Walleij [fab: replaced chip->of_node with chip->dev->of_node, and removed err_remove_irqchip_mask] Signed-off-by: Fabrizio Castro --- drivers/gpio/gpiolib-of.c | 24 ++++++++++++++++++++++++ drivers/gpio/gpiolib.c | 43 +++++++++++++++++++++++++++++++++++++++++++ include/linux/gpio/driver.h | 18 ++++++++++++++++++ 3 files changed, 85 insertions(+) diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c index 5fe34a9d..ec642bf 100644 --- a/drivers/gpio/gpiolib-of.c +++ b/drivers/gpio/gpiolib-of.c @@ -334,6 +334,28 @@ void of_mm_gpiochip_remove(struct of_mm_gpio_chip *mm_gc) } EXPORT_SYMBOL(of_mm_gpiochip_remove); +static void of_gpiochip_init_valid_mask(struct gpio_chip *chip) +{ + int len, i; + u32 start, count; + struct device_node *np = chip->dev->of_node; + + len = of_property_count_u32_elems(np, "gpio-reserved-ranges"); + if (len < 0 || len % 2 != 0) + return; + + for (i = 0; i < len; i += 2) { + of_property_read_u32_index(np, "gpio-reserved-ranges", + i, &start); + of_property_read_u32_index(np, "gpio-reserved-ranges", + i + 1, &count); + if (start >= chip->ngpio || start + count >= chip->ngpio) + continue; + + bitmap_clear(chip->valid_mask, start, count); + } +}; + #ifdef CONFIG_PINCTRL static int of_gpiochip_add_pin_range(struct gpio_chip *chip) { @@ -434,6 +456,8 @@ int of_gpiochip_add(struct gpio_chip *chip) chip->of_xlate = of_gpio_simple_xlate; } + of_gpiochip_init_valid_mask(chip); + status = of_gpiochip_add_pin_range(chip); if (status) return status; diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 0e4e753..d2b0386 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -293,6 +293,43 @@ static unsigned long *gpiochip_allocate_mask(struct gpio_chip *chip) return p; } +static int gpiochip_init_valid_mask(struct gpio_chip *gpiochip) +{ +#ifdef CONFIG_OF_GPIO + int size; + struct device_node *np = gpiochip->dev->of_node; + + size = of_property_count_u32_elems(np, "gpio-reserved-ranges"); + if (size > 0 && size % 2 == 0) + gpiochip->need_valid_mask = true; +#endif + + if (!gpiochip->need_valid_mask) + return 0; + + gpiochip->valid_mask = gpiochip_allocate_mask(gpiochip); + if (!gpiochip->valid_mask) + return -ENOMEM; + + return 0; +} + +static void gpiochip_free_valid_mask(struct gpio_chip *gpiochip) +{ + kfree(gpiochip->valid_mask); + gpiochip->valid_mask = NULL; +} + +bool gpiochip_line_is_valid(const struct gpio_chip *gpiochip, + unsigned int offset) +{ + /* No mask means all valid */ + if (likely(!gpiochip->valid_mask)) + return true; + return test_bit(offset, gpiochip->valid_mask); +} +EXPORT_SYMBOL_GPL(gpiochip_line_is_valid); + /** * gpiochip_add_data() - register a gpio_chip * @chip: the chip to register, with chip->base initialized @@ -371,6 +408,10 @@ int gpiochip_add_data(struct gpio_chip *chip, void *data) if (status) goto err_remove_from_list; + status = gpiochip_init_valid_mask(chip); + if (status) + goto err_remove_from_list; + status = of_gpiochip_add(chip); if (status) goto err_remove_chip; @@ -391,6 +432,7 @@ err_remove_chip: acpi_gpiochip_remove(chip); gpiochip_free_hogs(chip); of_gpiochip_remove(chip); + gpiochip_free_valid_mask(chip); err_remove_from_list: spin_lock_irqsave(&gpio_lock, flags); list_del(&chip->list); @@ -428,6 +470,7 @@ void gpiochip_remove(struct gpio_chip *chip) gpiochip_remove_pin_ranges(chip); gpiochip_free_hogs(chip); of_gpiochip_remove(chip); + gpiochip_free_valid_mask(chip); spin_lock_irqsave(&gpio_lock, flags); for (id = 0; id < chip->ngpio; id++) { diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index de502c7..c0fc8ef 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -143,6 +143,21 @@ struct gpio_chip { struct lock_class_key *lock_key; #endif + /** + * @need_valid_mask: + * + * If set core allocates @valid_mask with all bits set to one. + */ + bool need_valid_mask; + + /** + * @valid_mask: + * + * If not %NULL holds bitmask of GPIOs which are valid to be used + * from the chip. + */ + unsigned long *valid_mask; + #if defined(CONFIG_OF_GPIO) /* * If CONFIG_OF is enabled, then all GPIO controllers described in the @@ -185,6 +200,9 @@ extern struct gpio_chip *gpiochip_find(void *data, int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset); void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset); +/* */ +bool gpiochip_line_is_valid(const struct gpio_chip *chip, unsigned int offset); + /* get driver data */ static inline void *gpiochip_get_data(struct gpio_chip *chip) { From patchwork Mon May 13 15:36:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941265 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 983B476 for ; Mon, 13 May 2019 15:39:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 88FB2283A6 for ; Mon, 13 May 2019 15:39:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7DB3D283AF; Mon, 13 May 2019 15:39:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2F44A283A6 for ; Mon, 13 May 2019 15:39:14 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id DC602EF5; Mon, 13 May 2019 15:37:55 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 69B73EF5 for ; Mon, 13 May 2019 15:37:55 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id CD3E8875 for ; Mon, 13 May 2019 15:37:54 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608192" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:37:54 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 56158401BA41; Tue, 14 May 2019 00:37:53 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:45 +0100 Message-Id: <1557761837-24993-21-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 20/52] gpiolib: Avoid calling chip->request() for unused gpios X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit 3789f5acb9bbe088f70779002f32e7c6a64000bc upstream. Add a check for unused gpios to avoid chip->request() call to client driver for unused gpios. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Linus Walleij [fab: moved changes from gpiod_request_commit to __gpiod_request] Signed-off-by: Fabrizio Castro --- drivers/gpio/gpiolib.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index d2b0386..7dd3468 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -1025,6 +1025,7 @@ static int __gpiod_request(struct gpio_desc *desc, const char *label) struct gpio_chip *chip = desc->chip; int status; unsigned long flags; + unsigned offset; spin_lock_irqsave(&gpio_lock, flags); @@ -1043,7 +1044,11 @@ static int __gpiod_request(struct gpio_desc *desc, const char *label) if (chip->request) { /* chip->request may sleep */ spin_unlock_irqrestore(&gpio_lock, flags); - status = chip->request(chip, gpio_chip_hwgpio(desc)); + offset = gpio_chip_hwgpio(desc); + if (gpiochip_line_is_valid(chip, offset)) + status = chip->request(chip, offset); + else + status = -EINVAL; spin_lock_irqsave(&gpio_lock, flags); if (status < 0) { From patchwork Mon May 13 15:36:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941267 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9B96476 for ; Mon, 13 May 2019 15:39:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8D236283A6 for ; Mon, 13 May 2019 15:39:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 819D4283AF; Mon, 13 May 2019 15:39:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AE4CD283A6 for ; Mon, 13 May 2019 15:39:19 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 00B4CEC0; Mon, 13 May 2019 15:37:59 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id B04BCEFC for ; Mon, 13 May 2019 15:37:57 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 7D48F27B for ; Mon, 13 May 2019 15:37:56 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608197" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:37:56 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 03D25401B9F5; Tue, 14 May 2019 00:37:54 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:46 +0100 Message-Id: <1557761837-24993-22-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 21/52] gpio: rcar: Implement gpiochip.set_multiple() X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Geert Uytterhoeven commit dbb763b8ea5d8eb0ce3e45e289969f6f1f418921 upstream. This allows to set multiple outputs using a single register write. Signed-off-by: Geert Uytterhoeven Signed-off-by: Linus Walleij Signed-off-by: Fabrizio Castro --- drivers/gpio/gpio-rcar.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index c0fd5a5..411e93b 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -349,6 +349,25 @@ static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value) spin_unlock_irqrestore(&p->lock, flags); } +static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask, + unsigned long *bits) +{ + struct gpio_rcar_priv *p = gpiochip_get_data(chip); + unsigned long flags; + u32 val, bankmask; + + bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0); + if (!bankmask) + return; + + spin_lock_irqsave(&p->lock, flags); + val = gpio_rcar_read(p, OUTDT); + val &= ~bankmask; + val |= (bankmask & bits[0]); + gpio_rcar_write(p, OUTDT, val); + spin_unlock_irqrestore(&p->lock, flags); +} + static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset, int value) { @@ -500,6 +519,7 @@ static int gpio_rcar_probe(struct platform_device *pdev) gpio_chip->get = gpio_rcar_get; gpio_chip->direction_output = gpio_rcar_direction_output; gpio_chip->set = gpio_rcar_set; + gpio_chip->set_multiple = gpio_rcar_set_multiple; gpio_chip->label = name; gpio_chip->dev = dev; gpio_chip->owner = THIS_MODULE; From patchwork Mon May 13 15:36:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941269 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C1C3914DB for ; Mon, 13 May 2019 15:39:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B1BBA283AF for ; Mon, 13 May 2019 15:39:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A5C40283E7; Mon, 13 May 2019 15:39:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 595F5283AF for ; Mon, 13 May 2019 15:39:24 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 15E2EEFC; Mon, 13 May 2019 15:38:00 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id A2B5CEC0 for ; Mon, 13 May 2019 15:37:58 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 2CA6127B for ; Mon, 13 May 2019 15:37:58 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810586" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:37:57 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id A8942401B9F5; Tue, 14 May 2019 00:37:56 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:47 +0100 Message-Id: <1557761837-24993-23-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 22/52] gpio: rcar: Add GPIO hole support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit 496069b87eea631274c2c35fb6f8c45ad838436b upstream. GPIO hole is present in RZ/G1C SoC. Valid GPIO pins on bank3 are in the range GP3_0 to GP3_16 and GP3_27 to GP3_29. The GPIO pins between GP3_17 to GP3_26 are unused. Add support for handling unused GPIO's. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Linus Walleij [fab: removed change from gpio_rcar_resume] Signed-off-by: Fabrizio Castro --- drivers/gpio/gpio-rcar.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index 411e93b..e829f11 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -357,6 +357,9 @@ static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask, u32 val, bankmask; bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0); + if (chip->valid_mask) + bankmask &= chip->valid_mask[0]; + if (!bankmask) return; From patchwork Mon May 13 15:36:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941271 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BB5B576 for ; Mon, 13 May 2019 15:39:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A5CDE283AF for ; Mon, 13 May 2019 15:39:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 98AC5283E7; Mon, 13 May 2019 15:39:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 22FC6283AF for ; Mon, 13 May 2019 15:39:29 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 2C82BF02; Mon, 13 May 2019 15:38:01 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 7D74CF02 for ; Mon, 13 May 2019 15:38:00 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id CBE5327B for ; Mon, 13 May 2019 15:37:59 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608203" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:37:59 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 558F9401B9F5; Tue, 14 May 2019 00:37:58 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:48 +0100 Message-Id: <1557761837-24993-24-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 23/52] dt-bindings: gpio: Add a gpio-reserved-ranges property X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Stephen Boyd commit b9c725ed73b7cecc7c9bc4b752ab3eb975ef9330 upstream. Some qcom platforms make some GPIOs or pins unavailable for use by non-secure operating systems, and thus reading or writing the registers for those pins will cause access control issues. Introduce a DT property to describe the set of GPIOs that are available for use so that higher level OSes are able to know what pins to avoid reading/writing. Cc: Grant Likely Cc: Signed-off-by: Stephen Boyd Signed-off-by: Stephen Boyd Reviewed-by: Rob Herring Tested-by: Timur Tabi Reviewed-by: Andy Shevchenko Signed-off-by: Linus Walleij Signed-off-by: Fabrizio Castro --- Documentation/devicetree/bindings/gpio/gpio.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index 069cdf6..6550775 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt @@ -141,9 +141,9 @@ in a lot of designs, some using all 32 bits, some using 18 and some using first 18 GPIOs, at local offset 0 .. 17, are in use. If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an -additional bitmask is needed to specify which GPIOs are actually in use, -and which are dummies. The bindings for this case has not yet been -specified, but should be specified if/when such hardware appears. +additional set of tuples is needed to specify which GPIOs are unusable, with +the gpio-reserved-ranges binding. This property indicates the start and size +of the GPIOs that can't be used. Example: @@ -153,6 +153,7 @@ gpio-controller@00000000 { gpio-controller; #gpio-cells = <2>; ngpios = <18>; + gpio-reserved-ranges = <0 4>, <12 2>; } The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism From patchwork Mon May 13 15:36:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941273 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CDA68933 for ; Mon, 13 May 2019 15:39:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BC37F283AF for ; Mon, 13 May 2019 15:39:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A6E4A283E7; Mon, 13 May 2019 15:39:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4A368283AF for ; Mon, 13 May 2019 15:39:33 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 45320F07; Mon, 13 May 2019 15:38:03 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 40789F06 for ; Mon, 13 May 2019 15:38:02 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 7E9C027B for ; Mon, 13 May 2019 15:38:01 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608207" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:38:01 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 05725401B9F5; Tue, 14 May 2019 00:37:59 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:49 +0100 Message-Id: <1557761837-24993-25-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 24/52] dt-bindings: gpio: rcar: Add gpio-reserved-ranges support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit c0f6afad46a8ed2c0a2053ec720b1e6da80cf69a upstream. Update the DT bindings documentation with the optional gpio-reserved-ranges properties. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring Signed-off-by: Linus Walleij [fab: reworked example to make it fit v4.4 implementation] Signed-off-by: Fabrizio Castro --- .../devicetree/bindings/gpio/renesas,gpio-rcar.txt | 43 +++++++++++++--------- 1 file changed, 25 insertions(+), 18 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt index 68eb3a8..7163b19e 100644 --- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt @@ -30,7 +30,7 @@ Required Properties: - #gpio-cells: Should be 2. The first cell is the GPIO number and the second cell specifies GPIO flags, as defined in . Only the GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. - - gpio-ranges: Range of pins managed by the GPIO controller. + - gpio-ranges: See gpio.txt. Optional properties: @@ -38,35 +38,42 @@ Optional properties: mandatory if the hardware implements a controllable functional clock for the GPIO instance. -Please refer to gpio.txt in this directory for details of gpio-ranges property -and the common GPIO bindings used by client devices. + - gpio-reserved-ranges: See gpio.txt. + +Please refer to gpio.txt in this directory for the common GPIO bindings used by +client devices. The GPIO controller also acts as an interrupt controller. It uses the default two cells specifier as described in Documentation/devicetree/bindings/ interrupt-controller/interrupts.txt. -Example: R8A7779 (R-Car H1) GPIO controller nodes +Example: R8A77470 (RZ/G1C) GPIO controller nodes - gpio0: gpio@ffc40000 { - compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; - reg = <0xffc40000 0x2c>; - interrupt-parent = <&gic>; - interrupts = <0 141 0x4>; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a77470", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; #gpio-cells = <2>; gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - interrupt-controller; + gpio-ranges = <&pfc 0 0 23>; #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A77470_CLK_GPIO0>; + power-domains = <&cpg_clocks>; }; ... - gpio6: gpio@ffc46000 { - compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; - reg = <0xffc46000 0x2c>; - interrupt-parent = <&gic>; - interrupts = <0 147 0x4>; + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a77470", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; #gpio-cells = <2>; gpio-controller; - gpio-ranges = <&pfc 0 192 9>; - interrupt-controller; + gpio-ranges = <&pfc 0 96 30>; + gpio-reserved-ranges = <17 10>; #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A77470_CLK_GPIO3>; + power-domains = <&cpg_clocks>; }; From patchwork Mon May 13 15:36:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941275 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6A7F0933 for ; Mon, 13 May 2019 15:39:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5B94E283AF for ; Mon, 13 May 2019 15:39:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4E6F0283E7; Mon, 13 May 2019 15:39:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E3C5C283AF for ; Mon, 13 May 2019 15:39:37 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 6BC63F09; Mon, 13 May 2019 15:38:05 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 7A779E89 for ; Mon, 13 May 2019 15:38:04 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 3181827B for ; Mon, 13 May 2019 15:38:03 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810594" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:38:02 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id AE64C401BA41; Tue, 14 May 2019 00:38:01 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:50 +0100 Message-Id: <1557761837-24993-26-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 25/52] ARM: shmobile: defconfig: Enable r8a77470 SoC X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit f794fa1e8f0f7e308edae8eaef2f9cd59aa62bc6 upstream. Enable recently added r8a77470 (RZ/G1C) SoC. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman Signed-off-by: Fabrizio Castro --- arch/arm/configs/shmobile_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index 223fbc8..4770cd8 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_R8A73A4=y CONFIG_ARCH_R8A7740=y CONFIG_ARCH_R8A7743=y CONFIG_ARCH_R8A7745=y +CONFIG_ARCH_R8A77470=y CONFIG_ARCH_R8A7778=y CONFIG_ARCH_R8A7779=y CONFIG_ARCH_R8A7790=y From patchwork Mon May 13 15:36:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941277 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 88F8576 for ; Mon, 13 May 2019 15:39:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 78A2C283B1 for ; Mon, 13 May 2019 15:39:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6D40E283F9; Mon, 13 May 2019 15:39:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 21DFC283B1 for ; Mon, 13 May 2019 15:39:45 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 8485AF0D; Mon, 13 May 2019 15:38:06 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 5D866E89 for ; Mon, 13 May 2019 15:38:05 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id DA50127B for ; Mon, 13 May 2019 15:38:04 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810598" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:38:04 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 5D16F401BBFB; Tue, 14 May 2019 00:38:03 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:51 +0100 Message-Id: <1557761837-24993-27-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 26/52] ARM: multi_v7_defconfig: Enable r8a77470 SoC X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit d588298a309050ef0f2bd52ff86f2f39dd39ff4d upstream. Enable recently added r8a77470 (RZ/G1C) SoC. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman Signed-off-by: Fabrizio Castro --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 47f98eb..cfaf564 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -82,6 +82,7 @@ CONFIG_ARCH_R8A73A4=y CONFIG_ARCH_R8A7740=y CONFIG_ARCH_R8A7743=y CONFIG_ARCH_R8A7745=y +CONFIG_ARCH_R8A77470=y CONFIG_ARCH_R8A7778=y CONFIG_ARCH_R8A7779=y CONFIG_ARCH_R8A7790=y From patchwork Mon May 13 15:36:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941279 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D8AB7933 for ; Mon, 13 May 2019 15:39:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CB03B283AF for ; Mon, 13 May 2019 15:39:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BFE1F283E7; Mon, 13 May 2019 15:39:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6B3B2283AF for ; Mon, 13 May 2019 15:39:49 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 9DB08E7C; Mon, 13 May 2019 15:38:08 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 14D65F06 for ; Mon, 13 May 2019 15:38:07 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 8CFA183A for ; Mon, 13 May 2019 15:38:06 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608215" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:38:06 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 11A27401BBFB; Tue, 14 May 2019 00:38:04 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:52 +0100 Message-Id: <1557761837-24993-28-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 27/52] serial: sh-sci: Document r8a77470 bindings X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit ef9604b622ce3b77e0ec6b566a016ddd64c5deb0 upstream. RZ/G1C (R8A77470) SoC also has the R-Car gen2 compatible SCIF and HSCIF ports, so document the SoC specific bindings. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Reviewed-by: Rob Herring Signed-off-by: Greg Kroah-Hartman Signed-off-by: Fabrizio Castro --- Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index 211f193..3772d4c 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -17,6 +17,8 @@ Required properties: - "renesas,scifa-r8a7745" for R8A7745 (RZ/G1E) SCIFA compatible UART. - "renesas,scifb-r8a7745" for R8A7745 (RZ/G1E) SCIFB compatible UART. - "renesas,hscif-r8a7745" for R8A7745 (RZ/G1E) HSCIF compatible UART. + - "renesas,scif-r8a77470" for R8A77470 (RZ/G1C) SCIF compatible UART. + - "renesas,hscif-r8a77470" for R8A77470 (RZ/G1C) HSCIF compatible UART. - "renesas,scif-r8a7778" for R8A7778 (R-Car M1) SCIF compatible UART. - "renesas,scif-r8a7779" for R8A7779 (R-Car H1) SCIF compatible UART. - "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART. From patchwork Mon May 13 15:36:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941281 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0E6F976 for ; Mon, 13 May 2019 15:39:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F269F283AF for ; Mon, 13 May 2019 15:39:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E55E5283E7; Mon, 13 May 2019 15:39:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 98DFD283AF for ; Mon, 13 May 2019 15:39:53 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id BAABEF23; Mon, 13 May 2019 15:38:10 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id BE4CAF23 for ; Mon, 13 May 2019 15:38:08 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 3D84027B for ; Mon, 13 May 2019 15:38:08 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810603" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:38:08 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id BA8E6401BA41; Tue, 14 May 2019 00:38:06 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:53 +0100 Message-Id: <1557761837-24993-29-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 28/52] dt-bindings: sram: Document renesas, smp-sram X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Geert Uytterhoeven commit d5f2ac6ae9931227d8ccd71c12182e547ec28c21 upstream. Document reserved SRAM for the SMP jump stub on Renesas R-Car Gen2 and RZ/G1 SoCs. Signed-off-by: Geert Uytterhoeven Acked-by: Rob Herring Signed-off-by: Simon Horman Signed-off-by: Fabrizio Castro --- .../devicetree/bindings/sram/renesas,smp-sram.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/sram/renesas,smp-sram.txt diff --git a/Documentation/devicetree/bindings/sram/renesas,smp-sram.txt b/Documentation/devicetree/bindings/sram/renesas,smp-sram.txt new file mode 100644 index 0000000..712d05e --- /dev/null +++ b/Documentation/devicetree/bindings/sram/renesas,smp-sram.txt @@ -0,0 +1,27 @@ +* Renesas SMP SRAM + +Renesas R-Car Gen2 and RZ/G1 SoCs need a small piece of SRAM for the jump stub +for secondary CPU bringup and CPU hotplug. +This memory is reserved by adding a child node to a "mmio-sram" node, cfr. +Documentation/devicetree/bindings/sram/sram.txt. + +Required child node properties: + - compatible: Must be "renesas,smp-sram", + - reg: Address and length of the reserved SRAM. + The full physical (bus) address must be aligned to a 256 KiB boundary. + + +Example: + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x10>; + }; + }; From patchwork Mon May 13 15:36:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941283 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CBB1B933 for ; Mon, 13 May 2019 15:39:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B658A1FE8B for ; Mon, 13 May 2019 15:39:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A873620121; Mon, 13 May 2019 15:39:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3D6A71FE8B for ; Mon, 13 May 2019 15:39:58 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id D4382F29; Mon, 13 May 2019 15:38:12 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 4C7C1F29 for ; Mon, 13 May 2019 15:38:11 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id EC24C27B for ; Mon, 13 May 2019 15:38:09 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608218" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:38:09 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 6BF78401BA41; Tue, 14 May 2019 00:38:08 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:54 +0100 Message-Id: <1557761837-24993-30-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 29/52] ARM: dts: r8a77470: Initial SoC device tree X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit 6929dfc5918049272e07653b1760b0b305f098e6 upstream. The initial R8A77470 SoC device tree including CPU0, GIC, timer, SYSC, RST, CPG, and the required clock descriptions. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman [fab: replaced renesas-cpg-mssr.h with r8a77470-clock.h, taken out clocks, clock-names, power-domains, and resets properties, and also taken out cpg, prr, and sysc nodes] Signed-off-by: Fabrizio Castro --- arch/arm/boot/dts/r8a77470.dtsi | 121 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 arch/arm/boot/dts/r8a77470.dtsi diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi new file mode 100644 index 0000000..a126bf5 --- /dev/null +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a77470 SoC + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +#include +#include +#include + +/ { + compatible = "renesas,r8a77470"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + clock-frequency = <1000000000>; + next-level-cache = <&L2_CA7>; + }; + + + L2_CA7: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77470-rst"; + reg = <0 0xe6160000 0 0x100>; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x100>; + }; + }; + + icram2: sram@e6300000 { + compatible = "mmio-sram"; + reg = <0 0xe6300000 0 0x20000>; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a77470", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = ; + status = "disabled"; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; +}; From patchwork Mon May 13 15:36:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941285 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6EFE776 for ; Mon, 13 May 2019 15:40:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5AC2927FC0 for ; Mon, 13 May 2019 15:40:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4A63C282E8; Mon, 13 May 2019 15:40:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0E1A227FC0 for ; Mon, 13 May 2019 15:40:03 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id EECFEEA2; Mon, 13 May 2019 15:38:13 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id D4BBDF2A for ; Mon, 13 May 2019 15:38:12 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id A2D0927B for ; Mon, 13 May 2019 15:38:11 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810607" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:38:11 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 2612F401BBF3; Tue, 14 May 2019 00:38:09 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:55 +0100 Message-Id: <1557761837-24993-31-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 30/52] clk: shmobile: Document r8a77470 CPG clock support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP Document r8a77470 CPG clock support. Signed-off-by: Fabrizio Castro --- Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt index a75c26a..ba321bc 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt @@ -10,6 +10,7 @@ Required Properties: - compatible: Must be one of - "renesas,r8a7743-cpg-clocks" for the r8a7743 CPG - "renesas,r8a7745-cpg-clocks" for the r8a7745 CPG + - "renesas,r8a77470-cpg-clocks" for the r8a77470 CPG - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG From patchwork Mon May 13 15:36:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941287 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 69DE776 for ; Mon, 13 May 2019 15:40:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5B5D827FC0 for ; Mon, 13 May 2019 15:40:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4F689282E8; Mon, 13 May 2019 15:40:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0E89427FC0 for ; Mon, 13 May 2019 15:40:08 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 139E3F33; Mon, 13 May 2019 15:38:14 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id BF729E6C for ; Mon, 13 May 2019 15:38:13 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 4DF8E27B for ; Mon, 13 May 2019 15:38:13 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810610" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:38:13 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id CC546401BA41; Tue, 14 May 2019 00:38:11 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:56 +0100 Message-Id: <1557761837-24993-32-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 31/52] clk: shmobile: Document r8a77470 CPG DIV6 clock support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP Document r8a77470 CPG DIV6 clock support. Signed-off-by: Fabrizio Castro --- Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt index feb9ab5..3a05843 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt @@ -11,6 +11,7 @@ Required Properties: - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks - "renesas,r8a7743-div6-clock" for R8A7743 (RZ/G1M) DIV6 clocks - "renesas,r8a7745-div6-clock" for R8A7745 (RZ/G1E) DIV6 clocks + - "renesas,r8a77470-div6-clock" for R8A77470 (RZ/G1C) DIV6 clocks - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks From patchwork Mon May 13 15:36:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941289 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 412C2933 for ; Mon, 13 May 2019 15:40:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 32C4E27FC0 for ; Mon, 13 May 2019 15:40:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 26BD2282E8; Mon, 13 May 2019 15:40:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E0E9327FC0 for ; Mon, 13 May 2019 15:40:12 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 38600F4D; Mon, 13 May 2019 15:38:16 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 6C54FF37 for ; Mon, 13 May 2019 15:38:15 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id F1C3B27B for ; Mon, 13 May 2019 15:38:14 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608222" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:38:14 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 7A92F401BBF3; Tue, 14 May 2019 00:38:13 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:57 +0100 Message-Id: <1557761837-24993-33-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 32/52] clk: shmobile: Document r8a77470 MSTP clock support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP Document r8a77470 MSTP clock support. Signed-off-by: Fabrizio Castro --- Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt index 6e2c6ae..a9d2e65 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt @@ -15,6 +15,7 @@ Required Properties: - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks - "renesas,r8a7743-mstp-clocks" for R8A7743 (RZ/G1M) MSTP gate clocks - "renesas,r8a7745-mstp-clocks" for R8A7745 (RZ/G1E) MSTP gate clocks + - "renesas,r8a77470-mstp-clocks" for R8A77470 (RZ/G1C) MSTP gate clocks - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks From patchwork Mon May 13 15:36:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941291 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 766F9933 for ; Mon, 13 May 2019 15:40:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 66C8C2807B for ; Mon, 13 May 2019 15:40:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5B2E728382; Mon, 13 May 2019 15:40:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 97D182807B for ; Mon, 13 May 2019 15:40:18 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 5DB01F39; Mon, 13 May 2019 15:38:19 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 30C01F3A for ; Mon, 13 May 2019 15:38:18 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id BE9E2875 for ; Mon, 13 May 2019 15:38:16 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810613" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:38:16 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 2D8A8401BA41; Tue, 14 May 2019 00:38:14 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:58 +0100 Message-Id: <1557761837-24993-34-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 33/52] ARM: dts: r8a77470: Add clocks X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP Declare all core clocks, DIV6 clocks, and MSTP clocks. Also, hook up clocks within cpu0, scif1, and gic nodes. Signed-off-by: Fabrizio Castro --- arch/arm/boot/dts/r8a77470.dtsi | 384 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 384 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index a126bf5..09c4d66 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -23,6 +23,7 @@ compatible = "arm,cortex-a7"; reg = <0>; clock-frequency = <1000000000>; + clocks = <&z2_clk>; next-level-cache = <&L2_CA7>; }; @@ -90,6 +91,10 @@ compatible = "renesas,scif-r8a77470", "renesas,scif"; reg = <0 0xe6e68000 0 0x40>; interrupts = ; + clocks = <&mstp7_clks R8A77470_CLK_SCIF1>, + <&zs_clk>, <&scif_clk>; + clock-names = "sci_ick", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -101,6 +106,385 @@ reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = ; + clocks = <&mstp4_clks R8A77470_CLK_INTC_SYS>; + clock-names = "clk"; + power-domains = <&cpg_clocks>; + }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a77470-cpg-clocks", + "renesas,rcar-gen2-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk &usb_extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", + "pll3", "lb", "qspi", + "sdh", "sd0", "sd1", + "rcan"; + #power-domain-cells = <0>; + }; + + /* Variable factor clocks */ + sd2_clk: sd2_clk@e6150078 { + compatible = "renesas,r8a77470-div6-clock", + "renesas,cpg-div6-clock"; + reg = <0 0xe6150078 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sd2"; + }; + + /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A77470_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "pll1_div2"; + }; + z2_clk: z2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A77470_CLK_PLL0>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "z2"; + }; + zx_clk: zx_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A77470_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "zx"; + }; + zs_clk: zs_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A77470_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + clock-output-names = "zs"; + }; + hp_clk: hp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A77470_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "hp"; + }; + b_clk: b_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A77470_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "b"; + }; + p_clk: p_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A77470_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <24>; + clock-mult = <1>; + clock-output-names = "p"; + }; + cl_clk: cl_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A77470_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <48>; + clock-mult = <1>; + clock-output-names = "cl"; + }; + cp_clk: cp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A77470_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <48>; + clock-mult = <1>; + clock-output-names = "cp"; + }; + m2_clk: m2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A77470_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "m2"; + }; + zb3_clk: zb3_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A77470_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "zb3"; + }; + mp_clk: mp_clk { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <15>; + clock-mult = <1>; + clock-output-names = "mp"; + }; + cpex_clk: cpex_clk { + compatible = "fixed-factor-clock"; + clocks = <&extal_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "cpex"; + }; + rclk_clk: rclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A77470_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(48 * 1024)>; + clock-mult = <1>; + clock-output-names = "rclk"; + }; + oscclk_clk: oscclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A77470_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(12 * 1024)>; + clock-mult = <1>; + clock-output-names = "oscclk"; + }; + + /* Gate clocks */ + mstp0_clks: mstp0_clks@e6150130 { + compatible = "renesas,r8a77470-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; + clocks = <&mp_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "msiof0"; + }; + mstp1_clks: mstp1_clks@e6150134 { + compatible = "renesas,r8a77470-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; + clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, + <&zs_clk>, <&zs_clk>, <&zs_clk>, + <&p_clk>, <&p_clk>, <&rclk_clk>, + <&zs_clk>, <&zs_clk>; + #clock-cells = <1>; + clock-indices = < + R8A77470_CLK_VCP0 R8A77470_CLK_VPC0 + R8A77470_CLK_TMU1 R8A77470_CLK_3DG + R8A77470_CLK_2DDMAC R8A77470_CLK_FDP1_0 + R8A77470_CLK_TMU3 R8A77470_CLK_TMU2 + R8A77470_CLK_CMT0 R8A77470_CLK_VSP1DU0 + R8A77470_CLK_VSP1_SY + >; + clock-output-names = + "vcp0", "vpc0", "tmu1", + "3dg", "2d-dmac", "fdp1-0", + "tmu3", "tmu2", "cmt0", + "vsp1du0", "vsp1-sy"; + }; + mstp2_clks: mstp2_clks@e6150138 { + compatible = "renesas,r8a77470-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, + <&zs_clk>; + #clock-cells = <1>; + clock-indices = < + R8A77470_CLK_MSIOF2 + R8A77470_CLK_MSIOF1 + R8A77470_CLK_SYS_DMAC1 + R8A77470_CLK_SYS_DMAC0 + >; + clock-output-names = + "msiof2", "msiof1", "sys-dmac1", + "sys-dmac0"; + }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a77470-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&sd2_clk>, + <&cpg_clocks R8A77470_CLK_SD1>, + <&cpg_clocks R8A77470_CLK_SD0>, + <&hp_clk>, <&hp_clk>, <&rclk_clk>, + <&hp_clk>, <&hp_clk>; + #clock-cells = <1>; + clock-indices = < + R8A77470_CLK_SDHI2 + R8A77470_CLK_SDHI1 + R8A77470_CLK_SDHI0 + R8A77470_CLK_USBHS_DMAC0_CH1 + R8A77470_CLK_USBHS_DMAC1_CH1 + R8A77470_CLK_CMT1 + R8A77470_CLK_USBHS_DMAC0_CH0 + R8A77470_CLK_USBHS_DMAC1_CH0 + >; + clock-output-names = + "sdhi2", "sdhi1", "sdhi0", + "usbhs-dmac0-ch1", "usbhs-dmac1-ch1", + "cmt1", "usbhs-dmac0-ch0", + "usbhs-dmac1-ch0"; + }; + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,r8a77470-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; + clocks = <&rclk_clk>, <&cp_clk>, <&zs_clk>; + #clock-cells = <1>; + clock-indices = < + R8A77470_CLK_RWDT R8A77470_CLK_IRQC + R8A77470_CLK_INTC_SYS + >; + clock-output-names = "rwdt", "irqc", "intc-sys"; + }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,r8a77470-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; + clocks = <&hp_clk>, <&p_clk>; + #clock-cells = <1>; + clock-indices = < + R8A77470_CLK_AUDIO_DMAC0 + R8A77470_CLK_PWM + >; + clock-output-names = "audio-dmac0", "pwm"; + }; + mstp7_clks: mstp7_clks@e615014c { + compatible = "renesas,r8a77470-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; + clocks = <&mp_clk>, <&hp_clk>, <&mp_clk>, + <&hp_clk>, <&zs_clk>, <&p_clk>, + <&p_clk>, <&zs_clk>, <&zs_clk>, + <&p_clk>, <&p_clk>, <&p_clk>, + <&p_clk>, <&zx_clk>, <&zx_clk>; + #clock-cells = <1>; + clock-indices = < + R8A77470_CLK_USB_EHCI_0 + R8A77470_CLK_USBHS0 + R8A77470_CLK_USB_EHCI_1 + R8A77470_CLK_USBHS1 R8A77470_CLK_HSCIF2 + R8A77470_CLK_SCIF5 R8A77470_CLK_SCIF4 + R8A77470_CLK_HSCIF1 R8A77470_CLK_HSCIF0 + R8A77470_CLK_SCIF3 R8A77470_CLK_SCIF2 + R8A77470_CLK_SCIF1 R8A77470_CLK_SCIF0 + R8A77470_CLK_DU1 R8A77470_CLK_DU0 + >; + clock-output-names = + "usb-ehci-0", "usbhs-0", "usb-ehci-1", + "usbhs-1", "hscif2", "scif5", "scif4", + "hscif1", "hscif0", "scif3", "scif2", + "scif1", "scif0", "du1", "du0"; + }; + mstp8_clks: mstp8_clks@e6150990 { + compatible = "renesas,r8a77470-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; + clocks = <&zx_clk>, <&hp_clk>, <&p_clk>; + #clock-cells = <1>; + clock-indices = < + R8A77470_CLK_IPMMU_SGX + R8A77470_CLK_ETHERAVB R8A77470_CLK_ETHER + >; + clock-output-names = + "ipmmu-sgx", "etheravb", "ether"; + }; + mstp9_clks: mstp9_clks@e6150994 { + compatible = "renesas,r8a77470-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; + clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, + <&cp_clk>, <&cp_clk>, <&cp_clk>, + <&p_clk>, <&p_clk>, + <&cpg_clocks R8A77470_CLK_QSPI>, + <&cpg_clocks R8A77470_CLK_QSPI>, + <&hp_clk>, <&hp_clk>, <&hp_clk>, + <&hp_clk>, <&hp_clk>; + #clock-cells = <1>; + clock-indices = < + R8A77470_CLK_GPIO5 R8A77470_CLK_GPIO4 + R8A77470_CLK_GPIO3 R8A77470_CLK_GPIO2 + R8A77470_CLK_GPIO1 R8A77470_CLK_GPIO0 + R8A77470_CLK_CAN1 R8A77470_CLK_CAN0 + R8A77470_CLK_QUAD_SPI1 + R8A77470_CLK_QUAD_SPI0 + R8A77470_CLK_I2C4 R8A77470_CLK_I2C3 + R8A77470_CLK_I2C2 R8A77470_CLK_I2C1 + R8A77470_CLK_I2C0 + >; + clock-output-names = + "gpio5", "gpio4", "gpio3", "gpio2", + "gpio1", "gpio0", "can1", "can0", + "qspi_mod-1", "qspi_mod-0", "i2c4", + "i2c3", "i2c2", "i2c1", "i2c0"; + }; + mstp10_clks: mstp10_clks@e6150998 { + compatible = "renesas,r8a77470-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; + clocks = <&p_clk>, + <&mstp10_clks R8A77470_CLK_SSI_ALL>, + <&mstp10_clks R8A77470_CLK_SSI_ALL>, + <&mstp10_clks R8A77470_CLK_SSI_ALL>, + <&mstp10_clks R8A77470_CLK_SSI_ALL>, + <&mstp10_clks R8A77470_CLK_SSI_ALL>, + <&mstp10_clks R8A77470_CLK_SSI_ALL>, + <&mstp10_clks R8A77470_CLK_SSI_ALL>, + <&mstp10_clks R8A77470_CLK_SSI_ALL>, + <&mstp10_clks R8A77470_CLK_SSI_ALL>, + <&mstp10_clks R8A77470_CLK_SSI_ALL>, + <&p_clk>, + <&mstp10_clks R8A77470_CLK_SCU_ALL>, + <&mstp10_clks R8A77470_CLK_SCU_ALL>, + <&mstp10_clks R8A77470_CLK_SCU_ALL>, + <&mstp10_clks R8A77470_CLK_SCU_ALL>, + <&mstp10_clks R8A77470_CLK_SCU_ALL>, + <&mstp10_clks R8A77470_CLK_SCU_ALL>, + <&mstp10_clks R8A77470_CLK_SCU_ALL>, + <&mstp10_clks R8A77470_CLK_SCU_ALL>, + <&mstp10_clks R8A77470_CLK_SCU_ALL>, + <&mstp10_clks R8A77470_CLK_SCU_ALL>; + #clock-cells = <1>; + clock-indices = < + R8A77470_CLK_SSI_ALL R8A77470_CLK_SSI9 + R8A77470_CLK_SSI8 R8A77470_CLK_SSI7 + R8A77470_CLK_SSI6 R8A77470_CLK_SSI5 + R8A77470_CLK_SSI4 R8A77470_CLK_SSI3 + R8A77470_CLK_SSI2 R8A77470_CLK_SSI1 + R8A77470_CLK_SSI0 R8A77470_CLK_SCU_ALL + R8A77470_CLK_SCU_DVC1 + R8A77470_CLK_SCU_DVC0 + R8A77470_CLK_SCU_CTU1_MIX1 + R8A77470_CLK_SCU_CTU0_MIX0 + R8A77470_CLK_SCU_SRC6 + R8A77470_CLK_SCU_SRC5 + R8A77470_CLK_SCU_SRC4 + R8A77470_CLK_SCU_SRC3 + R8A77470_CLK_SCU_SRC2 + R8A77470_CLK_SCU_SRC1 + >; + clock-output-names = + "ssi-all", "ssi9", "ssi8", "ssi7", + "ssi6", "ssi5", "ssi4", "ssi3", "ssi2", + "ssi1", "ssi0", "scu-all", "scu-dvc1", + "scu-dvc0", "scu-ctu1-mix1", + "scu-ctu0-mix0", "scu-src6", "scu-src5", + "scu-src4", "scu-src3", "scu-src2", + "scu-src1"; + }; }; }; From patchwork Mon May 13 15:36:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941293 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D3D6C76 for ; Mon, 13 May 2019 15:40:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C4B6A282E8 for ; Mon, 13 May 2019 15:40:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B63A128382; Mon, 13 May 2019 15:40:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6FBA5282E8 for ; Mon, 13 May 2019 15:40:25 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 76331F9E; Mon, 13 May 2019 15:38:20 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id EA8D4F3A for ; Mon, 13 May 2019 15:38:18 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 72E5483A for ; Mon, 13 May 2019 15:38:18 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608225" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:38:18 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id EC968401BBF3; Tue, 14 May 2019 00:38:16 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:59 +0100 Message-Id: <1557761837-24993-35-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 34/52] dt-bindings: arm: Document iW-RainboW-G23S single board computer X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit 7625f03be3177d63cc6e5763b0c2dfecc371ca95 upstream. Document the iW-RainboW-G23S single board computer device tree bindings, listing it as a supported board. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman Signed-off-by: Fabrizio Castro --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 3b51d7e..423575a 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -51,6 +51,8 @@ Boards: compatible = "renesas,gose", "renesas,r8a7793" - Henninger compatible = "renesas,henninger", "renesas,r8a7791" + - iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S) + compatible = "iwave,g23s", "renesas,r8a77470" - iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D) compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745" - iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM) From patchwork Mon May 13 15:37:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941295 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C98DE76 for ; Mon, 13 May 2019 15:40:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B89DD283C8 for ; Mon, 13 May 2019 15:40:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ACB0D283E7; Mon, 13 May 2019 15:40:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5819B283C8 for ; Mon, 13 May 2019 15:40:30 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 8EBD7FA9; Mon, 13 May 2019 15:38:23 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id A81CBFA9 for ; Mon, 13 May 2019 15:38:20 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 21E5483A for ; Mon, 13 May 2019 15:38:20 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810616" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:38:19 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 9E9EA401BA41; Tue, 14 May 2019 00:38:18 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:37:00 +0100 Message-Id: <1557761837-24993-36-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 35/52] ARM: dts: iwg23s-sbc: Add support for iWave G23S-SBC based on RZ/G1C X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit f922fb5af1584c35bcd8bf661738b16dd4f65441 upstream. Add support for iWave iW-RainboW-G23S single board computer based on RZ/G1C. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman Signed-off-by: Fabrizio Castro --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 35 +++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9871a7f..28fbcdb 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -548,6 +548,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ r8a7743-iwg20d-q7-dbcm-ca.dtb \ r8a7745-iwg22d-sodimm.dtb \ r8a7745-iwg22d-sodimm-dbhd-ca.dtb \ + r8a77470-iwg23s-sbc.dtb \ r8a7778-bockw.dtb \ r8a7779-marzen.dtb \ r8a7790-lager.dtb \ diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts new file mode 100644 index 0000000..d21baad --- /dev/null +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave-RZ/G1C single board computer + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a77470.dtsi" +/ { + model = "iWave iW-RainboW-G23S single board computer based on RZ/G1C"; + compatible = "iwave,g23s", "renesas,r8a77470"; + + aliases { + serial1 = &scif1; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial1:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x20000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&scif1 { + status = "okay"; +}; From patchwork Mon May 13 15:37:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941297 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AC84B933 for ; Mon, 13 May 2019 15:40:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9CFCA283C8 for ; Mon, 13 May 2019 15:40:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8E839283E7; Mon, 13 May 2019 15:40:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3F3A3283C8 for ; Mon, 13 May 2019 15:40:35 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id A571CF37; Mon, 13 May 2019 15:38:24 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 24EBAFAE for ; Mon, 13 May 2019 15:38:23 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id CAC3C875 for ; Mon, 13 May 2019 15:38:21 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810619" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:38:21 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 4F898401BBF3; Tue, 14 May 2019 00:38:20 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:37:01 +0100 Message-Id: <1557761837-24993-37-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 36/52] dt-bindings: pinctrl: sh-pfc: Document r8a77470 PFC support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit 98c1c1f08adfda0d24f3bef9614a7117ef0c5495 upstream. Document PFC support for the R8A77470 SoC. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Rob Herring Signed-off-by: Geert Uytterhoeven Signed-off-by: Linus Walleij Signed-off-by: Fabrizio Castro --- Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index cf28bd4..b2264d9 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -15,6 +15,7 @@ Required Properties: - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller. - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller. - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller. + - "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller. - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller. - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. From patchwork Mon May 13 15:37:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941299 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6C52D933 for ; Mon, 13 May 2019 15:40:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5D410283C8 for ; Mon, 13 May 2019 15:40:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 51675283E7; Mon, 13 May 2019 15:40:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 09327283C8 for ; Mon, 13 May 2019 15:40:40 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id BC0D6FE7; Mon, 13 May 2019 15:38:25 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id E9811FC2 for ; Mon, 13 May 2019 15:38:23 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 763EF27B for ; Mon, 13 May 2019 15:38:23 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608230" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:38:23 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 00615401BA41; Tue, 14 May 2019 00:38:21 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:37:02 +0100 Message-Id: <1557761837-24993-38-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 37/52] ARM: dts: r8a77470: Add PFC support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit 0ea1a4d2c92a65aea6acc2397938cd01b053bc38 upstream. Define the generic R8A77470 part of the PFC device node. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman Signed-off-by: Fabrizio Castro --- arch/arm/boot/dts/r8a77470.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 09c4d66..e971b5e 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -59,6 +59,11 @@ #size-cells = <2>; ranges; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a77470"; + reg = <0 0xe6060000 0 0x118>; + }; + rst: reset-controller@e6160000 { compatible = "renesas,r8a77470-rst"; reg = <0 0xe6160000 0 0x100>; From patchwork Mon May 13 15:37:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941301 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DD62576 for ; Mon, 13 May 2019 15:40:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CBDA0283C8 for ; Mon, 13 May 2019 15:40:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BFD86283E7; Mon, 13 May 2019 15:40:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 787C5283C8 for ; Mon, 13 May 2019 15:40:44 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id E3BCCFE6; Mon, 13 May 2019 15:38:25 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id A46A0F3B for ; Mon, 13 May 2019 15:38:25 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 238E3875 for ; Mon, 13 May 2019 15:38:25 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608233" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:38:24 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id A23AB401BBF3; Tue, 14 May 2019 00:38:23 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:37:03 +0100 Message-Id: <1557761837-24993-39-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 38/52] dt-bindings: gpio: rcar: Add r8a77470 (RZ/G1C) support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit 856ac1d26b5d64fcf3b9d6d889ec1a61fd745a8e upstream. Renesas RZ/G1C (R8A77470) SoC GPIO blocks are identical to the R-Car Gen2 family. Add support for its GPIO controllers. Signed-off-by: Biju Das Reviewed-by: Chris Paterson Reviewed-by: Simon Horman Reviewed-by: Geert Uytterhoeven Signed-off-by: Linus Walleij Signed-off-by: Fabrizio Castro --- Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt index 7163b19e..8addadf7 100644 --- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt @@ -5,6 +5,7 @@ Required Properties: - compatible: should contain one or more of the following: - "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO controller. - "renesas,gpio-r8a7745": for R8A7745 (RZ/G1E) compatible GPIO controller. + - "renesas,gpio-r8a77470": for R8A77470 (RZ/G1C) compatible GPIO controller. - "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller. - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller. - "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller. From patchwork Mon May 13 15:37:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941303 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2222F933 for ; Mon, 13 May 2019 15:40:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1312F283C8 for ; Mon, 13 May 2019 15:40:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 07A3A283E7; Mon, 13 May 2019 15:40:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A554A283C8 for ; Mon, 13 May 2019 15:40:51 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 0705AE98; Mon, 13 May 2019 15:38:28 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 87324E98 for ; Mon, 13 May 2019 15:38:27 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id CA1D4878 for ; Mon, 13 May 2019 15:38:26 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810623" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:38:26 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 4E818401BBF3; Tue, 14 May 2019 00:38:25 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:37:04 +0100 Message-Id: <1557761837-24993-40-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 39/52] ARM: dts: r8a77470: Add GPIO support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit 5fcd4bfe03913301bab34e2934c838eb4173a475 upstream. Describe GPIO blocks in the R8A77470 device tree. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman [fab: reworked clocks and power-domains properties, removed resets proporties] Signed-off-by: Fabrizio Castro --- arch/arm/boot/dts/r8a77470.dtsi | 85 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index e971b5e..d9a89fa 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -59,6 +59,91 @@ #size-cells = <2>; ranges; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a77470", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 23>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A77470_CLK_GPIO0>; + power-domains = <&cpg_clocks>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a77470", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 23>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A77470_CLK_GPIO1>; + power-domains = <&cpg_clocks>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a77470", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A77470_CLK_GPIO2>; + power-domains = <&cpg_clocks>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a77470", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 30>; + gpio-reserved-ranges = <17 10>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A77470_CLK_GPIO3>; + power-domains = <&cpg_clocks>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a77470", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A77470_CLK_GPIO4>; + power-domains = <&cpg_clocks>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a77470", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A77470_CLK_GPIO5>; + power-domains = <&cpg_clocks>; + }; + pfc: pin-controller@e6060000 { compatible = "renesas,pfc-r8a77470"; reg = <0 0xe6060000 0 0x118>; From patchwork Mon May 13 15:37:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941305 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ECC6C933 for ; Mon, 13 May 2019 15:40:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DB438283C8 for ; Mon, 13 May 2019 15:40:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CE8D7283E7; Mon, 13 May 2019 15:40:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 76B06283C8 for ; Mon, 13 May 2019 15:40:56 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 1EF4DFEB; Mon, 13 May 2019 15:38:30 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 4429CFFC for ; Mon, 13 May 2019 15:38:29 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 8944D875 for ; Mon, 13 May 2019 15:38:28 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608236" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:38:28 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 01DAD401BA41; Tue, 14 May 2019 00:38:26 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:37:05 +0100 Message-Id: <1557761837-24993-41-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 40/52] ARM: dts: r8a77470: Add SCIF support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit 8cdb8f1ab7efbd88868d3067ec1f211ff289bc01 upstream. Describe SCIF ports in the R8A77470 device tree. Also it fixes the CPG clock index ZS from 6 to 5. Fixes: 6929dfc5918049 ("ARM: dts: r8a77470: Initial SoC device tree") Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman [fab: reworked to make it fit 4.4.y-cip definitions, like include files, and properties like clocks, clock-names, and power-domains. Also, removed resets properties as not applicable here. Finally, the fix for the ZS clock index is not applicable to this version] Signed-off-by: Fabrizio Castro --- arch/arm/boot/dts/r8a77470.dtsi | 56 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index d9a89fa..2d542b3 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -177,6 +177,17 @@ reg = <0 0xe6300000 0 0x20000>; }; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a77470", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = ; + clocks = <&mstp7_clks R8A77470_CLK_SCIF0>, + <&zs_clk>, <&scif_clk>; + clock-names = "sci_ick", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + scif1: serial@e6e68000 { compatible = "renesas,scif-r8a77470", "renesas,scif"; reg = <0 0xe6e68000 0 0x40>; @@ -188,6 +199,51 @@ status = "disabled"; }; + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a77470", "renesas,scif"; + reg = <0 0xe6e58000 0 0x40>; + interrupts = ; + clocks = <&mstp7_clks R8A77470_CLK_SCIF2>, + <&zs_clk>, <&scif_clk>; + clock-names = "sci_ick", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a77470", "renesas,scif"; + reg = <0 0xe6ea8000 0 0x40>; + interrupts = ; + clocks = <&mstp7_clks R8A77470_CLK_SCIF3>, + <&zs_clk>, <&scif_clk>; + clock-names = "sci_ick", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a77470", "renesas,scif"; + reg = <0 0xe6ee0000 0 0x40>; + interrupts = ; + clocks = <&mstp7_clks R8A77470_CLK_SCIF4>, + <&zs_clk>, <&scif_clk>; + clock-names = "sci_ick", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a77470", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 0x40>; + interrupts = ; + clocks = <&mstp7_clks R8A77470_CLK_SCIF5>, + <&zs_clk>, <&scif_clk>; + clock-names = "sci_ick", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; From patchwork Mon May 13 15:37:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941307 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A372D76 for ; Mon, 13 May 2019 15:41:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 95328283C8 for ; Mon, 13 May 2019 15:41:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 89942283E7; Mon, 13 May 2019 15:41:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3F2A6283C8 for ; Mon, 13 May 2019 15:41:01 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 370D8E90; Mon, 13 May 2019 15:38:32 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id B54EAE90 for ; Mon, 13 May 2019 15:38:30 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 3B52C27B for ; Mon, 13 May 2019 15:38:30 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810627" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:38:30 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id B7AED401BA41; Tue, 14 May 2019 00:38:28 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:37:06 +0100 Message-Id: <1557761837-24993-42-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 41/52] dt-bindings: irqchip: renesas-irqc: Document r8a77470 support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit dcbabbbd2618991d349b3b4f75e6b2eb4fad37df upstream. Renesas RZ/G SoC have the R-Car gen2 compatible IRQC interrupt controllers. Document RZ/G1C (also known as R8A77470) SoC bindings. Reviewed-by: Fabrizio Castro Reviewed-by: Simon Horman Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das Signed-off-by: Marc Zyngier Signed-off-by: Fabrizio Castro --- Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt index e3f052d..1ed382e 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt @@ -7,6 +7,7 @@ Required properties: - "renesas,irqc-r8a73a4" (R-Mobile APE6) - "renesas,irqc-r8a7743" (RZ/G1M) - "renesas,irqc-r8a7745" (RZ/G1E) + - "renesas,irqc-r8a77470" (RZ/G1C) - "renesas,irqc-r8a7790" (R-Car H2) - "renesas,irqc-r8a7791" (R-Car M2-W) - "renesas,irqc-r8a7792" (R-Car V2H) From patchwork Mon May 13 15:37:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941309 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 96448933 for ; Mon, 13 May 2019 15:41:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 87BB6283C8 for ; Mon, 13 May 2019 15:41:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7C1EF283E7; Mon, 13 May 2019 15:41:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2AD47283C8 for ; Mon, 13 May 2019 15:41:06 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 4E338E9C; Mon, 13 May 2019 15:38:33 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 6D7611025 for ; Mon, 13 May 2019 15:38:32 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id E7D0383A for ; Mon, 13 May 2019 15:38:31 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608239" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:38:31 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 694EF401BA41; Tue, 14 May 2019 00:38:30 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:37:07 +0100 Message-Id: <1557761837-24993-43-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 42/52] ARM: dts: r8a77470: Add IRQC support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit 141fb10294e3ba5ee2d34d464ddc8a9952bd3372 upstream. Describe the IRQC interrupt controller in the R8A77470 device tree. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman [fab: reworked clocks and power-domains properties. Removed resets property] Signed-off-by: Fabrizio Castro --- arch/arm/boot/dts/r8a77470.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 2d542b3..1325dae 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -154,6 +154,25 @@ reg = <0 0xe6160000 0 0x100>; }; + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a77470", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&mstp4_clks R8A77470_CLK_IRQC>; + power-domains = <&cpg_clocks>; + }; + icram0: sram@e63a0000 { compatible = "mmio-sram"; reg = <0 0xe63a0000 0 0x12000>; From patchwork Mon May 13 15:37:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941311 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0D90B933 for ; Mon, 13 May 2019 15:41:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F2F65283CA for ; Mon, 13 May 2019 15:41:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E66EC283F9; Mon, 13 May 2019 15:41:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A7DF0283CA for ; Mon, 13 May 2019 15:41:10 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 655121074; Mon, 13 May 2019 15:38:35 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 16262104F for ; Mon, 13 May 2019 15:38:34 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 93EE183A for ; Mon, 13 May 2019 15:38:33 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608242" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:38:33 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 1C671401BA41; Tue, 14 May 2019 00:38:31 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:37:08 +0100 Message-Id: <1557761837-24993-44-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 43/52] ARM: dts: iwg23s-sbc: Add pinctl support for scif1 X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit 01a12d4975fb09c10f64cb551d4903dacd032b79 upstream. Adding pinctrl support for scif1 interface. Signed-off-by: Biju Das Reviewed-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman Signed-off-by: Fabrizio Castro --- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts index d21baad..48821dd 100644 --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -30,6 +30,16 @@ clock-frequency = <20000000>; }; +&pfc { + scif1_pins: scif1 { + groups = "scif1_data_b"; + function = "scif1"; + }; +}; + &scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + status = "okay"; }; From patchwork Mon May 13 15:37:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941313 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E2F0E76 for ; Mon, 13 May 2019 15:41:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D1844283C8 for ; Mon, 13 May 2019 15:41:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C5C95283E7; Mon, 13 May 2019 15:41:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7A7D6283C8 for ; Mon, 13 May 2019 15:41:15 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 80D8B1082; Mon, 13 May 2019 15:38:37 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 5A9E41075 for ; Mon, 13 May 2019 15:38:36 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 48195878 for ; Mon, 13 May 2019 15:38:35 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810631" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:38:35 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id C1DD6401BA41; Tue, 14 May 2019 00:38:33 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:37:09 +0100 Message-Id: <1557761837-24993-45-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> MIME-Version: 1.0 Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 44/52] dt-bindings: rcar-dmac: Document missing error interrupt X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Geert Uytterhoeven commit 5466c34f8425ccd24124ebdae6e3b6552195956d upstream. The documentation for the "interrupt-names" property only mentions the per-channel interrupts, while the error interrupt has always been mandatory, too. Fixes: 10f5c8438475909a ("dmaengine: rcar-dmac: Add device tree bindings documentation") Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Signed-off-by: Vinod Koul Signed-off-by: Fabrizio Castro --- Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt index 5f2ce66..471fcc2 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt @@ -29,8 +29,9 @@ Required Properties: - interrupts: interrupt specifiers for the DMAC, one for each entry in interrupt-names. -- interrupt-names: one entry per channel, named "ch%u", where %u is the - channel number ranging from zero to the number of channels minus one. +- interrupt-names: one entry for the error interrupt, named "error", plus one + entry per channel, named "ch%u", where %u is the channel number ranging from + zero to the number of channels minus one. - clock-names: "fck" for the functional clock - clocks: a list of phandle + clock-specifier pairs, one for each entry From patchwork Mon May 13 15:37:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941315 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7B5FC933 for ; Mon, 13 May 2019 15:41:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6CB02283CA for ; Mon, 13 May 2019 15:41:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 61056283E8; Mon, 13 May 2019 15:41:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0FEBF283CA for ; Mon, 13 May 2019 15:41:20 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id A9A1B1081; Mon, 13 May 2019 15:38:38 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 71AA21077 for ; Mon, 13 May 2019 15:38:37 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id EDF1427B for ; Mon, 13 May 2019 15:38:36 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810634" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:38:36 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 744D8401BBF3; Tue, 14 May 2019 00:38:35 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:37:10 +0100 Message-Id: <1557761837-24993-46-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 45/52] dt-bindings: rcar-dmac: Document r8a77470 support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit a0b007e1ef1cb5b7f8d4be296beeb0a097af57ac upstream. Renesas RZ/G SoC also have the R-Car gen2/3 compatible DMA controllers. Document RZ/G1C (also known as R8A77470) SoC bindings. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Simon Horman Reviewed-by: Geert Uytterhoeven Signed-off-by: Vinod Koul Signed-off-by: Fabrizio Castro --- Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt index 471fcc2..5954b05 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt @@ -18,6 +18,7 @@ Required Properties: Examples with soctypes are: - "renesas,dmac-r8a7743" (RZ/G1M) - "renesas,dmac-r8a7745" (RZ/G1E) + - "renesas,dmac-r8a77470" (RZ/G1C) - "renesas,dmac-r8a7790" (R-Car H2) - "renesas,dmac-r8a7791" (R-Car M2-W) - "renesas,dmac-r8a7792" (R-Car V2H) From patchwork Mon May 13 15:37:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941317 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 96747933 for ; Mon, 13 May 2019 15:41:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8517B283CA for ; Mon, 13 May 2019 15:41:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 78764283E8; Mon, 13 May 2019 15:41:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1ECDF283CA for ; Mon, 13 May 2019 15:41:27 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id C1A46108B; Mon, 13 May 2019 15:38:40 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 58C691085 for ; Mon, 13 May 2019 15:38:39 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 9FD5927B for ; Mon, 13 May 2019 15:38:38 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810638" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:38:38 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 242E7401BA41; Tue, 14 May 2019 00:38:36 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:37:11 +0100 Message-Id: <1557761837-24993-47-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 46/52] ARM: dts: r8a77470: Add SYS-DMAC support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit 2e5775e3fd0667f7140a00748465af1c3d0aa5bb upstream. Describe SYS-DMAC0/1 in the R8A77470 device tree. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman [fab: reworked clocks and power-domains properties. Removed resets properties] Signed-off-by: Fabrizio Castro --- arch/arm/boot/dts/r8a77470.dtsi | 64 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 1325dae..0daa451 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -196,6 +196,70 @@ reg = <0 0xe6300000 0 0x20000>; }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a77470", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A77470_CLK_SYS_DMAC0>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a77470", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A77470_CLK_SYS_DMAC1>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <15>; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a77470", "renesas,scif"; reg = <0 0xe6e60000 0 0x40>; From patchwork Mon May 13 15:37:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941319 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 09F5C76 for ; Mon, 13 May 2019 15:41:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EE14B283CA for ; Mon, 13 May 2019 15:41:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E22C0283E8; Mon, 13 May 2019 15:41:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 91987283CA for ; Mon, 13 May 2019 15:41:32 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id DC4E01084; Mon, 13 May 2019 15:38:43 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 1F0A91078 for ; Mon, 13 May 2019 15:38:42 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 5605E27B for ; Mon, 13 May 2019 15:38:40 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810641" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:38:40 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id CACE2401BA41; Tue, 14 May 2019 00:38:38 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:37:12 +0100 Message-Id: <1557761837-24993-48-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 47/52] ARM: dts: r8a77470: Add SCIF DMA support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit e4696122205634f40e26f9c33359a71823d1e68c upstream. Add SCIF DMA support for R8A77470 SoC. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman Signed-off-by: Fabrizio Castro --- arch/arm/boot/dts/r8a77470.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 0daa451..6f5fd91 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -267,6 +267,9 @@ clocks = <&mstp7_clks R8A77470_CLK_SCIF0>, <&zs_clk>, <&scif_clk>; clock-names = "sci_ick", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -278,6 +281,9 @@ clocks = <&mstp7_clks R8A77470_CLK_SCIF1>, <&zs_clk>, <&scif_clk>; clock-names = "sci_ick", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -289,6 +295,9 @@ clocks = <&mstp7_clks R8A77470_CLK_SCIF2>, <&zs_clk>, <&scif_clk>; clock-names = "sci_ick", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -300,6 +309,9 @@ clocks = <&mstp7_clks R8A77470_CLK_SCIF3>, <&zs_clk>, <&scif_clk>; clock-names = "sci_ick", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -311,6 +323,9 @@ clocks = <&mstp7_clks R8A77470_CLK_SCIF4>, <&zs_clk>, <&scif_clk>; clock-names = "sci_ick", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -323,6 +338,9 @@ clocks = <&mstp7_clks R8A77470_CLK_SCIF5>, <&zs_clk>, <&scif_clk>; clock-names = "sci_ick", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; From patchwork Mon May 13 15:37:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941321 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 31CA7933 for ; Mon, 13 May 2019 15:41:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 232A2283CA for ; Mon, 13 May 2019 15:41:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 17C70283F9; Mon, 13 May 2019 15:41:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 88836283E7 for ; Mon, 13 May 2019 15:41:37 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 0322CEB0; Mon, 13 May 2019 15:38:45 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 12C211078 for ; Mon, 13 May 2019 15:38:43 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 585A927B for ; Mon, 13 May 2019 15:38:42 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810644" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:38:41 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 84963401BA41; Tue, 14 May 2019 00:38:40 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:37:13 +0100 Message-Id: <1557761837-24993-49-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 48/52] dt-bindings: net: renesas-ravb: Add support for r8a77470 SoC X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit 9b85756341c53fd13b4b5e25104c22849274cd0d upstream. Add a new compatible string for the RZ/G1C (R8A77470) SoC. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Acked-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: David S. Miller Signed-off-by: Fabrizio Castro --- Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt index 9a22b1e..b289f61 100644 --- a/Documentation/devicetree/bindings/net/renesas,ravb.txt +++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt @@ -7,6 +7,7 @@ Required properties: - compatible: Must contain one or more of the following: - "renesas,etheravb-r8a7743" for the R8A7743 SoC. - "renesas,etheravb-r8a7745" for the R8A7745 SoC. + - "renesas,etheravb-r8a77470" for the R8A77470 SoC. - "renesas,etheravb-r8a7790" for the R8A7790 SoC. - "renesas,etheravb-r8a7794" for the R8A7794 SoC. - "renesas,etheravb-rcar-gen2" as a fallback for the above From patchwork Mon May 13 15:37:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941323 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 93DC0933 for ; Mon, 13 May 2019 15:41:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8511E283CA for ; Mon, 13 May 2019 15:41:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 796EB283E8; Mon, 13 May 2019 15:41:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2FFC4283CA for ; Mon, 13 May 2019 15:41:42 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 1C6F8EFA; Mon, 13 May 2019 15:38:46 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 891C3EB0 for ; Mon, 13 May 2019 15:38:44 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 13CAF83A for ; Mon, 13 May 2019 15:38:43 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608251" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:38:43 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 361CA401BA41; Tue, 14 May 2019 00:38:42 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:37:14 +0100 Message-Id: <1557761837-24993-50-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 49/52] ARM: dts: r8a77470: Add EtherAVB support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit f70b0958c044a73188056a231d40a8af55c04dd2 upstream. Define the generic R8A77470 part of the EtherAVB device node. Signed-off-by: Biju Das Reviewed-by: Chris Paterson Signed-off-by: Simon Horman [fab: reworked clocks and power-domains properties, removed resets property] Signed-off-by: Fabrizio Castro --- arch/arm/boot/dts/r8a77470.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 6f5fd91..3542678 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -260,6 +260,18 @@ dma-channels = <15>; }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a77470", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&mstp8_clks R8A77470_CLK_ETHERAVB>; + power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a77470", "renesas,scif"; reg = <0 0xe6e60000 0 0x40>; From patchwork Mon May 13 15:37:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941325 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 011AE76 for ; Mon, 13 May 2019 15:41:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E67B2283CA for ; Mon, 13 May 2019 15:41:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DAD46283E8; Mon, 13 May 2019 15:41:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9DFAC283CA for ; Mon, 13 May 2019 15:41:46 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 3398F109C; Mon, 13 May 2019 15:38:47 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id D8A2CEFA for ; Mon, 13 May 2019 15:38:45 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 623CF83A for ; Mon, 13 May 2019 15:38:45 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608254" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:38:45 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id DED5F401BA41; Tue, 14 May 2019 00:38:43 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:37:15 +0100 Message-Id: <1557761837-24993-51-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 50/52] ARM: dts: iwg23s-sbc: Add EtherAVB support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit b6ef074bcadf9f89295bc7ee19424714b6ffc4c8 upstream. Define the iW-RainboW-G23S board dependent part of the EtherAVB device node. Signed-off-by: Biju Das Reviewed-by: Chris Paterson Signed-off-by: Simon Horman Signed-off-by: Fabrizio Castro --- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts index 48821dd..56182ee 100644 --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -12,11 +12,12 @@ compatible = "iwave,g23s", "renesas,r8a77470"; aliases { + ethernet0 = &avb; serial1 = &scif1; }; chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial1:115200n8"; }; @@ -26,6 +27,18 @@ }; }; +&avb { + phy-handle = <&phy3>; + phy-mode = "gmii"; + renesas,no-ether-link; + status = "okay"; + + phy3: ethernet-phy@3 { + reg = <3>; + micrel,led-mode = <1>; + }; +}; + &extal_clk { clock-frequency = <20000000>; }; From patchwork Mon May 13 15:37:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941327 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BFE6476 for ; Mon, 13 May 2019 15:41:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B1C79283CA for ; Mon, 13 May 2019 15:41:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A59F6283E8; Mon, 13 May 2019 15:41:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5B2A5283CA for ; Mon, 13 May 2019 15:41:51 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 4C04210A5; Mon, 13 May 2019 15:38:49 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id E882F10A5 for ; Mon, 13 May 2019 15:38:47 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 77BD227B for ; Mon, 13 May 2019 15:38:47 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15810648" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 May 2019 00:38:46 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 8E01A401BA41; Tue, 14 May 2019 00:38:45 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:37:16 +0100 Message-Id: <1557761837-24993-52-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 51/52] ARM: dts: iwg23s-sbc: specify EtherAVB PHY IRQ X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit 938fbd1ae2aca6e0547411687f0cc32d18427eae upstream. Specify EtherAVB PHY IRQ in the board specific device tree, now that we have GPIO support. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman Signed-off-by: Fabrizio Castro --- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts index 56182ee..22da819 100644 --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -35,6 +35,8 @@ phy3: ethernet-phy@3 { reg = <3>; + interrupt-parent = <&gpio5>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; micrel,led-mode = <1>; }; }; From patchwork Mon May 13 15:37:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10941329 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 457FF933 for ; Mon, 13 May 2019 15:41:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 33C94283CA for ; Mon, 13 May 2019 15:41:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 27045283E8; Mon, 13 May 2019 15:41:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D0D3E283CA for ; Mon, 13 May 2019 15:41:55 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 67100F6D; Mon, 13 May 2019 15:38:52 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 3A8A8EB2 for ; Mon, 13 May 2019 15:38:49 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id B804127B for ; Mon, 13 May 2019 15:38:48 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,465,1549897200"; d="scan'208";a="15608257" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 May 2019 00:38:48 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 3EB13401BA41; Tue, 14 May 2019 00:38:47 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:37:17 +0100 Message-Id: <1557761837-24993-53-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y 52/52] ARM: dts: iwg23s-sbc: Add pinctl support for EtherAVB X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit 976a5ccb808da21f77a3bb1123a9e5df6f2d9564 upstream. Adding pinctrl support for EtherAVB interface. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts index 22da819..4ceff9c 100644 --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -28,6 +28,9 @@ }; &avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + phy-handle = <&phy3>; phy-mode = "gmii"; renesas,no-ether-link; @@ -46,6 +49,11 @@ }; &pfc { + avb_pins: avb { + groups = "avb_mdio", "avb_gmii_tx_rx"; + function = "avb"; + }; + scif1_pins: scif1 { groups = "scif1_data_b"; function = "scif1";