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[180.57.220.11]) by smtp.gmail.com with ESMTPSA id 194sm5687959pgd.33.2019.05.17.07.43.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 17 May 2019 07:43:15 -0700 (PDT) From: Yoshihiro Kaneko To: linux-renesas-soc@vger.kernel.org Cc: Simon Horman , Geert Uytterhoeven , Magnus Damm , linux-arm-kernel@lists.infradead.org Subject: [PATCH/RFT] arm: dts: renesas: r7s9210-rza2mevb: sort nodes of rza2mevb board Date: Fri, 17 May 2019 23:43:07 +0900 Message-Id: <1558104187-2842-1-git-send-email-ykaneko0929@gmail.com> X-Mailer: git-send-email 1.9.1 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch sorts the nodes of arch/arm/boot/dts/r7s9210-rza2mevb.dts. * Sort subnodes of root ("/") node alphabetically * Sort following top-level nodes alphabetically * Sort subnodes of pinctrl alphabetically Signed-off-by: Yoshihiro Kaneko Signed-off-by: Yoshihiro Kaneko Signed-off-by: Simon Horman --- This patch is based on the devel branch of Simon Horman's renesas tree. arch/arm/boot/dts/r7s9210-rza2mevb.dts | 92 +++++++++++++++++----------------- 1 file changed, 46 insertions(+), 46 deletions(-) diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts index fa44e35..71808ce 100644 --- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts +++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts @@ -26,11 +26,6 @@ stdout-path = "serial0:115200n8"; }; - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x00800000>; /* HyperRAM */ - }; - lbsc { #address-cells = <1>; #size-cells = <1>; @@ -46,6 +41,33 @@ gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>; }; }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x00800000>; /* HyperRAM */ + }; +}; + +ðer0 { + pinctrl-names = "default"; + pinctrl-0 = <ð0_pins>; + status = "okay"; + renesas,no-ether-link; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +ðer1 { + pinctrl-names = "default"; + pinctrl-0 = <ð1_pins>; + status = "okay"; + renesas,no-ether-link; + phy-handle = <&phy1>; + phy1: ethernet-phy@1 { + reg = <0>; + }; }; /* EXTAL */ @@ -53,23 +75,16 @@ clock-frequency = <24000000>; /* 24MHz */ }; -/* RTC_X1 */ -&rtc_x1_clk { - clock-frequency = <32768>; +/* High resolution System tick timers */ +&ostm0 { + status = "okay"; }; -/* USB_X1 */ -&usb_x1_clk { - clock-frequency = <48000000>; +&ostm1 { + status = "okay"; }; &pinctrl { - /* Serial Console */ - scif4_pins: serial4 { - pinmux = , /* TxD4 */ - ; /* RxD4 */ - }; - eth0_pins: eth0 { pinmux = , /* REF50CK0 */ , /* RMMI0_TXDEN */ @@ -98,6 +113,12 @@ ; /* IRQ5 */ }; + /* Serial Console */ + scif4_pins: serial4 { + pinmux = , /* TxD4 */ + ; /* RxD4 */ + }; + sdhi0_pins: sdhi0 { pinmux = , /* SD0_CD */ ; /* SD0_WP */ @@ -109,13 +130,9 @@ }; }; -/* High resolution System tick timers */ -&ostm0 { - status = "okay"; -}; - -&ostm1 { - status = "okay"; +/* RTC_X1 */ +&rtc_x1_clk { + clock-frequency = <32768>; }; /* Serial Console */ @@ -126,28 +143,6 @@ status = "okay"; }; -ðer0 { - pinctrl-names = "default"; - pinctrl-0 = <ð0_pins>; - status = "okay"; - renesas,no-ether-link; - phy-handle = <&phy0>; - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ðer1 { - pinctrl-names = "default"; - pinctrl-0 = <ð1_pins>; - status = "okay"; - renesas,no-ether-link; - phy-handle = <&phy1>; - phy1: ethernet-phy@1 { - reg = <0>; - }; -}; - &sdhi0 { pinctrl-names = "default"; pinctrl-0 = <&sdhi0_pins>; @@ -161,3 +156,8 @@ bus-width = <4>; status = "okay"; }; + +/* USB_X1 */ +&usb_x1_clk { + clock-frequency = <48000000>; +};