From patchwork Tue May 21 01:10:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10952755 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4C4D3912 for ; Tue, 21 May 2019 01:11:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3B53528901 for ; Tue, 21 May 2019 01:11:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2E34928925; Tue, 21 May 2019 01:11:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DE0EB28901 for ; Tue, 21 May 2019 01:11:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=J6WVth2gNsMQLWrT6AYbd1Fwahp+vDwNXVq7JU9MglI=; b=IWxT/3viCFb7mQ OwTPOpbJHonx4yIPiAEW/HvM/J/Dx5+mhlsNZPwSCPHXeJSDtnl6SXX5h2MEzOTGhzgtwYPIPn1fj G1KxNMPotC/4LWjHfGc8g+Mhmu1pgfbOTGLdy6bBWFY8P1hZwYGJ6prlJb2aE9JRpEobZG4qjeFrP gUVz4iH7jxHLZFYz/qtQO+k1cLqLHEjM1dyJU0CmVQ0zvi+sgIdWXu7asNlpXAHGMY61MFUmbSXIC KeBOmCnmy68wwbknAVTrUGEIMh+dcPZ33D9SEwWOyL94CddMqvpwVWs8EAUSNfIdnyyoPQBUAjpI6 o8duupi1uANhwYFtkTTQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hStJh-0003uP-Hw; Tue, 21 May 2019 01:11:45 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hStJL-0003Oz-8c; Tue, 21 May 2019 01:11:24 +0000 X-UUID: 5db34aa6ef224f75921a96c5e4cd6a9f-20190520 X-UUID: 5db34aa6ef224f75921a96c5e4cd6a9f-20190520 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1343979464; Mon, 20 May 2019 17:11:13 -0800 Received: from MTKMBS01N1.mediatek.inc (172.21.101.68) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 20 May 2019 18:11:11 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 21 May 2019 09:11:10 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 21 May 2019 09:11:09 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v7 01/12] dt-binding: gce: remove thread-num property Date: Tue, 21 May 2019 09:10:57 +0800 Message-ID: <20190521011108.40428-2-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190521011108.40428-1-bibby.hsieh@mediatek.com> References: <20190521011108.40428-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190520_181123_302401_DDEF9F8B X-CRM114-Status: UNSURE ( 9.31 ) X-CRM114-Notice: Please train this message. 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Signed-off-by: Bibby Hsieh Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/mailbox/mtk-gce.txt | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt index 7d72b21c9e94..cfe40b01d164 100644 --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt @@ -39,7 +39,6 @@ Example: interrupts = ; clocks = <&infracfg CLK_INFRA_GCE>; clock-names = "gce"; - thread-num = CMDQ_THR_MAX_COUNT; #mbox-cells = <3>; }; From patchwork Tue May 21 01:10:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10952769 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 858BB912 for ; Tue, 21 May 2019 01:12:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 74EAD28901 for ; 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Mon, 20 May 2019 17:11:13 -0800 Received: from mtkmbs03n1.mediatek.inc (172.21.101.181) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 20 May 2019 18:11:12 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs03n1.mediatek.inc (172.21.101.181) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 21 May 2019 09:11:10 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 21 May 2019 09:11:10 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v7 02/12] dt-binding: gce: add gce header file for mt8183 Date: Tue, 21 May 2019 09:10:58 +0800 Message-ID: <20190521011108.40428-3-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190521011108.40428-1-bibby.hsieh@mediatek.com> References: <20190521011108.40428-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190520_181125_700718_D64F847F X-CRM114-Status: GOOD ( 12.96 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add documentation for the mt8183 gce. Add gce header file defined the gce hardware event, subsys number and constant for mt8183. Signed-off-by: Bibby Hsieh Reviewed-by: Rob Herring --- .../devicetree/bindings/mailbox/mtk-gce.txt | 6 +- include/dt-bindings/gce/mt8183-gce.h | 177 ++++++++++++++++++ 2 files changed, 180 insertions(+), 3 deletions(-) create mode 100644 include/dt-bindings/gce/mt8183-gce.h diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt index cfe40b01d164..1f7f8f2a3f49 100644 --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt @@ -9,7 +9,7 @@ CMDQ driver uses mailbox framework for communication. Please refer to mailbox.txt for generic information about mailbox device-tree bindings. Required properties: -- compatible: Must be "mediatek,mt8173-gce" +- compatible: can be "mediatek,mt8173-gce" or "mediatek,mt8183-gce" - reg: Address range of the GCE unit - interrupts: The interrupt signal from the GCE block - clock: Clocks according to the common clock binding @@ -28,8 +28,8 @@ Required properties for a client device: - mediatek,gce-subsys: u32, specify the sub-system id which is corresponding to the register address. -Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'. Such as -sub-system ids, thread priority, event ids. +Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h' +or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids. Example: diff --git a/include/dt-bindings/gce/mt8183-gce.h b/include/dt-bindings/gce/mt8183-gce.h new file mode 100644 index 000000000000..aeb95154fac2 --- /dev/null +++ b/include/dt-bindings/gce/mt8183-gce.h @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Bibby Hsieh + * + */ + +#ifndef _DT_BINDINGS_GCE_MT8183_H +#define _DT_BINDINGS_GCE_MT8183_H + +#define CMDQ_NO_TIMEOUT 0xffffffff + +#define CMDQ_THR_MAX_COUNT 24 + +/* GCE HW thread priority */ +#define CMDQ_THR_PRIO_LOWEST 0 +#define CMDQ_THR_PRIO_HIGHEST 1 + +/* GCE SUBSYS */ +#define SUBSYS_1300XXXX 0 +#define SUBSYS_1400XXXX 1 +#define SUBSYS_1401XXXX 2 +#define SUBSYS_1402XXXX 3 +#define SUBSYS_1502XXXX 4 +#define SUBSYS_1880XXXX 5 +#define SUBSYS_1881XXXX 6 +#define SUBSYS_1882XXXX 7 +#define SUBSYS_1883XXXX 8 +#define SUBSYS_1884XXXX 9 +#define SUBSYS_1000XXXX 10 +#define SUBSYS_1001XXXX 11 +#define SUBSYS_1002XXXX 12 +#define SUBSYS_1003XXXX 13 +#define SUBSYS_1004XXXX 14 +#define SUBSYS_1005XXXX 15 +#define SUBSYS_1020XXXX 16 +#define SUBSYS_1028XXXX 17 +#define SUBSYS_1700XXXX 18 +#define SUBSYS_1701XXXX 19 +#define SUBSYS_1702XXXX 20 +#define SUBSYS_1703XXXX 21 +#define SUBSYS_1800XXXX 22 +#define SUBSYS_1801XXXX 23 +#define SUBSYS_1802XXXX 24 +#define SUBSYS_1804XXXX 25 +#define SUBSYS_1805XXXX 26 +#define SUBSYS_1808XXXX 27 +#define SUBSYS_180aXXXX 28 +#define SUBSYS_180bXXXX 29 + +#define CMDQ_EVENT_DISP_RDMA0_SOF 0 +#define CMDQ_EVENT_DISP_RDMA1_SOF 1 +#define CMDQ_EVENT_MDP_RDMA0_SOF 2 +#define CMDQ_EVENT_MDP_RSZ0_SOF 4 +#define CMDQ_EVENT_MDP_RSZ1_SOF 5 +#define CMDQ_EVENT_MDP_TDSHP_SOF 6 +#define CMDQ_EVENT_MDP_WROT0_SOF 7 +#define CMDQ_EVENT_MDP_WDMA0_SOF 8 +#define CMDQ_EVENT_DISP_OVL0_SOF 9 +#define CMDQ_EVENT_DISP_OVL0_2L_SOF 10 +#define CMDQ_EVENT_DISP_OVL1_2L_SOF 11 +#define CMDQ_EVENT_DISP_WDMA0_SOF 12 +#define CMDQ_EVENT_DISP_COLOR0_SOF 13 +#define CMDQ_EVENT_DISP_CCORR0_SOF 14 +#define CMDQ_EVENT_DISP_AAL0_SOF 15 +#define CMDQ_EVENT_DISP_GAMMA0_SOF 16 +#define CMDQ_EVENT_DISP_DITHER0_SOF 17 +#define CMDQ_EVENT_DISP_PWM0_SOF 18 +#define CMDQ_EVENT_DISP_DSI0_SOF 19 +#define CMDQ_EVENT_DISP_DPI0_SOF 20 +#define CMDQ_EVENT_DISP_RSZ_SOF 22 +#define CMDQ_EVENT_MDP_AAL_SOF 23 +#define CMDQ_EVENT_MDP_CCORR_SOF 24 +#define CMDQ_EVENT_DISP_DBI_SOF 25 +#define CMDQ_EVENT_DISP_RDMA0_EOF 26 +#define CMDQ_EVENT_DISP_RDMA1_EOF 27 +#define CMDQ_EVENT_MDP_RDMA0_EOF 28 +#define CMDQ_EVENT_MDP_RSZ0_EOF 30 +#define CMDQ_EVENT_MDP_RSZ1_EOF 31 +#define CMDQ_EVENT_MDP_TDSHP_EOF 32 +#define CMDQ_EVENT_MDP_WROT0_EOF 33 +#define CMDQ_EVENT_MDP_WDMA0_EOF 34 +#define CMDQ_EVENT_DISP_OVL0_EOF 35 +#define CMDQ_EVENT_DISP_OVL0_2L_EOF 36 +#define CMDQ_EVENT_DISP_OVL1_2L_EOF 37 +#define CMDQ_EVENT_DISP_WDMA0_EOF 38 +#define CMDQ_EVENT_DISP_COLOR0_EOF 39 +#define CMDQ_EVENT_DISP_CCORR0_EOF 40 +#define CMDQ_EVENT_DISP_AAL0_EOF 41 +#define CMDQ_EVENT_DISP_GAMMA0_EOF 42 +#define CMDQ_EVENT_DISP_DITHER0_EOF 43 +#define CMDQ_EVENT_DSI0_EOF 44 +#define CMDQ_EVENT_DPI0_EOF 45 +#define CMDQ_EVENT_DISP_RSZ_EOF 47 +#define CMDQ_EVENT_MDP_AAL_EOF 48 +#define CMDQ_EVENT_MDP_CCORR_EOF 49 +#define CMDQ_EVENT_DBI_EOF 50 +#define CMDQ_EVENT_MUTEX_STREAM_DONE0 130 +#define CMDQ_EVENT_MUTEX_STREAM_DONE1 131 +#define CMDQ_EVENT_MUTEX_STREAM_DONE2 132 +#define CMDQ_EVENT_MUTEX_STREAM_DONE3 133 +#define CMDQ_EVENT_MUTEX_STREAM_DONE4 134 +#define CMDQ_EVENT_MUTEX_STREAM_DONE5 135 +#define CMDQ_EVENT_MUTEX_STREAM_DONE6 136 +#define CMDQ_EVENT_MUTEX_STREAM_DONE7 137 +#define CMDQ_EVENT_MUTEX_STREAM_DONE8 138 +#define CMDQ_EVENT_MUTEX_STREAM_DONE9 139 +#define CMDQ_EVENT_MUTEX_STREAM_DONE10 140 +#define CMDQ_EVENT_MUTEX_STREAM_DONE11 141 +#define CMDQ_EVENT_DISP_RDMA0_BUF_UNDERRUN_EVEN 142 +#define CMDQ_EVENT_DISP_RDMA1_BUF_UNDERRUN_EVEN 143 +#define CMDQ_EVENT_DSI0_TE_EVENT 144 +#define CMDQ_EVENT_DSI0_IRQ_EVENT 145 +#define CMDQ_EVENT_DSI0_DONE_EVENT 146 +#define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE 150 +#define CMDQ_EVENT_MDP_WDMA_SW_RST_DONE 151 +#define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE 152 +#define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE 154 +#define CMDQ_EVENT_DISP_OVL0_FRAME_RST_DONE_PULE 155 +#define CMDQ_EVENT_DISP_OVL0_2L_FRAME_RST_DONE_ULSE 156 +#define CMDQ_EVENT_DISP_OVL1_2L_FRAME_RST_DONE_ULSE 157 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_0 257 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_1 258 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_2 259 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_3 260 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_4 261 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_5 262 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_6 263 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_7 264 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_8 265 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_9 266 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_10 267 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_11 268 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_12 269 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_13 270 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_14 271 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_15 272 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_16 273 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_17 274 +#define CMDQ_EVENT_ISP_FRAME_DONE_P2_18 275 +#define CMDQ_EVENT_AMD_FRAME_DONE 276 +#define CMDQ_EVENT_DVE_DONE 277 +#define CMDQ_EVENT_WMFE_DONE 278 +#define CMDQ_EVENT_RSC_DONE 279 +#define CMDQ_EVENT_MFB_DONE 280 +#define CMDQ_EVENT_WPE_A_DONE 281 +#define CMDQ_EVENT_SPE_B_DONE 282 +#define CMDQ_EVENT_OCC_DONE 283 +#define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 289 +#define CMDQ_EVENT_JPG_ENC_CMDQ_DONE 290 +#define CMDQ_EVENT_JPG_DEC_CMDQ_DONE 291 +#define CMDQ_EVENT_VENC_CMDQ_MB_DONE 292 +#define CMDQ_EVENT_VENC_CMDQ_128BYTE_DONE 293 +#define CMDQ_EVENT_ISP_FRAME_DONE_A 321 +#define CMDQ_EVENT_ISP_FRAME_DONE_B 322 +#define CMDQ_EVENT_CAMSV0_PASS1_DONE 323 +#define CMDQ_EVENT_CAMSV1_PASS1_DONE 324 +#define CMDQ_EVENT_CAMSV2_PASS1_DONE 325 +#define CMDQ_EVENT_TSF_DONE 326 +#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 327 +#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 328 +#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 329 +#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 330 +#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 331 +#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 332 +#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 333 +#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 334 +#define CMDQ_EVENT_IPU_CORE0_DONE0 353 +#define CMDQ_EVENT_IPU_CORE0_DONE1 354 +#define CMDQ_EVENT_IPU_CORE0_DONE2 355 +#define CMDQ_EVENT_IPU_CORE0_DONE3 356 +#define CMDQ_EVENT_IPU_CORE1_DONE0 385 +#define CMDQ_EVENT_IPU_CORE1_DONE1 386 +#define CMDQ_EVENT_IPU_CORE1_DONE2 387 +#define CMDQ_EVENT_IPU_CORE1_DONE3 388 + +#endif From patchwork Tue May 21 01:10:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10952753 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6EAEF912 for ; Tue, 21 May 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with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hStJK-0003Ov-Oa; Tue, 21 May 2019 01:11:24 +0000 X-UUID: 02417148565b4cdc8ffc739be6164da3-20190520 X-UUID: 02417148565b4cdc8ffc739be6164da3-20190520 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 279025248; Mon, 20 May 2019 17:11:14 -0800 Received: from mtkmbs08n2.mediatek.inc (172.21.101.56) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 20 May 2019 18:11:12 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 21 May 2019 09:11:10 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 21 May 2019 09:11:10 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v7 03/12] dt-binding: gce: add binding for gce client reg property Date: Tue, 21 May 2019 09:10:59 +0800 Message-ID: <20190521011108.40428-4-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190521011108.40428-1-bibby.hsieh@mediatek.com> References: <20190521011108.40428-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 14454D09EB464D8918567F7301DFC7AC3235FDD557072CB26D4DCC58C1940B3A2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190520_181122_797687_4FBAB81A X-CRM114-Status: GOOD ( 11.32 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP cmdq driver provide a function that get the relationship of sub system number from device node for client. add specification for #subsys-cells, mediatek,gce-client-reg. Signed-off-by: Bibby Hsieh --- .../devicetree/bindings/mailbox/mtk-gce.txt | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt index 1f7f8f2a3f49..d48282d6b02d 100644 --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt @@ -21,12 +21,21 @@ Required properties: priority: Priority of GCE thread. atomic_exec: GCE processing continuous packets of commands in atomic way. +- #subsys-cells: Should be 3. + <&phandle subsys_number start_offset size> + phandle: Label name of a gce node. + subsys_number: specify the sub-system id which is corresponding + to the register address. + start_offset: the start offset of register address that GCE can access. + size: the total size of register address that GCE can access. Required properties for a client device: - mboxes: Client use mailbox to communicate with GCE, it should have this property and list of phandle, mailbox specifiers. -- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding - to the register address. +Optional properties for a client device: +- mediatek,gce-client-reg: Specify the sub-system id which is corresponding + to the register address, it should have this property and list of phandle, + sub-system specifiers. Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h' or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids. @@ -40,6 +49,7 @@ Example: clocks = <&infracfg CLK_INFRA_GCE>; clock-names = "gce"; #mbox-cells = <3>; + #subsys-cells = <3>; }; Example for a client device: @@ -48,9 +58,9 @@ Example for a client device: compatible = "mediatek,mt8173-mmsys"; mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>, <&gce 1 CMDQ_THR_PRIO_LOWEST 1>; - mediatek,gce-subsys = ; mutex-event-eof = ; - + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>, + <&gce SUBSYS_1401XXXX 0x2000 0x100>; ... }; From patchwork Tue May 21 01:11:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10952767 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 63E3C1390 for ; Tue, 21 May 2019 01:12:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 530B428901 for ; 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Mon, 20 May 2019 17:11:13 -0800 Received: from MTKMBS01N1.mediatek.inc (172.21.101.68) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 20 May 2019 18:11:12 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 21 May 2019 09:11:10 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 21 May 2019 09:11:11 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v7 04/12] mailbox: mediatek: cmdq: move the CMDQ_IRQ_MASK into cmdq driver data Date: Tue, 21 May 2019 09:11:00 +0800 Message-ID: <20190521011108.40428-5-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190521011108.40428-1-bibby.hsieh@mediatek.com> References: <20190521011108.40428-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190520_181125_031821_96EF6329 X-CRM114-Status: GOOD ( 11.87 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The interrupt mask and thread number has positive correlation, so we move the CMDQ_IRQ_MASK into cmdq driver data and calculate it by thread number. Signed-off-by: Bibby Hsieh Reviewed-by: CK Hu --- drivers/mailbox/mtk-cmdq-mailbox.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index 22811784dc7d..87617dc7504d 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -17,7 +17,6 @@ #include #define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT) -#define CMDQ_IRQ_MASK 0xffff #define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE) #define CMDQ_CURR_IRQ_STATUS 0x10 @@ -71,6 +70,7 @@ struct cmdq { void __iomem *base; u32 irq; u32 thread_nr; + u32 irq_mask; struct cmdq_thread *thread; struct clk *clock; bool suspended; @@ -284,11 +284,11 @@ static irqreturn_t cmdq_irq_handler(int irq, void *dev) unsigned long irq_status, flags = 0L; int bit; - irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & CMDQ_IRQ_MASK; - if (!(irq_status ^ CMDQ_IRQ_MASK)) + irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask; + if (!(irq_status ^ cmdq->irq_mask)) return IRQ_NONE; - for_each_clear_bit(bit, &irq_status, fls(CMDQ_IRQ_MASK)) { + for_each_clear_bit(bit, &irq_status, cmdq->thread_nr) { struct cmdq_thread *thread = &cmdq->thread[bit]; spin_lock_irqsave(&thread->chan->lock, flags); @@ -472,6 +472,9 @@ static int cmdq_probe(struct platform_device *pdev) dev_err(dev, "failed to get irq\n"); return -EINVAL; } + + cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev); + cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0); err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, "mtk_cmdq", cmdq); if (err < 0) { @@ -488,7 +491,6 @@ static int cmdq_probe(struct platform_device *pdev) return PTR_ERR(cmdq->clock); } - cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev); cmdq->mbox.dev = dev; cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr, sizeof(*cmdq->mbox.chans), GFP_KERNEL); From patchwork Tue May 21 01:11:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10952781 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B813017D2 for ; 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Tue, 21 May 2019 01:11:34 +0000 X-UUID: 0ceab7a42cc44675b920caec75e28a1b-20190520 X-UUID: 0ceab7a42cc44675b920caec75e28a1b-20190520 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 525616465; Mon, 20 May 2019 17:11:26 -0800 Received: from MTKMBS02N2.mediatek.inc (172.21.101.101) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 20 May 2019 18:11:24 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 21 May 2019 09:11:11 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 21 May 2019 09:11:11 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v7 05/12] mailbox: mediatek: cmdq: support mt8183 gce function Date: Tue, 21 May 2019 09:11:01 +0800 Message-ID: <20190521011108.40428-6-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190521011108.40428-1-bibby.hsieh@mediatek.com> References: <20190521011108.40428-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 0A96079B16573D3A3DE3A5A1AE43AABB43A513E7292C1ADA393A4CA12F5DBB2A2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190520_181132_049744_D9C363A1 X-CRM114-Status: UNSURE ( 9.87 ) X-CRM114-Notice: Please train this message. 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Tue, 21 May 2019 09:11:11 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v7 06/12] soc: mediatek: cmdq: clear the event in cmdq initial flow Date: Tue, 21 May 2019 09:11:02 +0800 Message-ID: <20190521011108.40428-7-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190521011108.40428-1-bibby.hsieh@mediatek.com> References: <20190521011108.40428-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 60CBC20F725209AE9EA4B5144984AD0A0EB4AF8738136C24C94D12886DCC6DC82000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190520_181128_086307_18AA478A X-CRM114-Status: GOOD ( 11.06 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP GCE hardware stored event information in own internal sysram, if the initial value in those sysram is not zero value it will cause a situation that gce can wait the event immediately after client ask gce to wait event but not really trigger the corresponding hardware. In order to make sure that the wait event function is exactly correct, we need to clear the sysram value in cmdq initial flow. Fixes: 623a6143a845 ("mailbox: mediatek: Add Mediatek CMDQ driver") Signed-off-by: Bibby Hsieh Reviewed-by: CK Hu --- drivers/mailbox/mtk-cmdq-mailbox.c | 5 +++++ include/linux/mailbox/mtk-cmdq-mailbox.h | 2 ++ include/linux/soc/mediatek/mtk-cmdq.h | 3 --- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index 6db1e2dd2dea..2c1b80d82c3a 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -20,6 +20,7 @@ #define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE) #define CMDQ_CURR_IRQ_STATUS 0x10 +#define CMDQ_SYNC_TOKEN_UPDATE 0x68 #define CMDQ_THR_SLOT_CYCLES 0x30 #define CMDQ_THR_BASE 0x100 #define CMDQ_THR_SIZE 0x80 @@ -103,8 +104,12 @@ static void cmdq_thread_resume(struct cmdq_thread *thread) static void cmdq_init(struct cmdq *cmdq) { + int i; + WARN_ON(clk_enable(cmdq->clock) < 0); writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); + for (i = 0; i <= CMDQ_MAX_EVENT; i++) + writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); clk_disable(cmdq->clock); } diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h index ccb73422c2fa..911475da7a53 100644 --- a/include/linux/mailbox/mtk-cmdq-mailbox.h +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h @@ -19,6 +19,8 @@ #define CMDQ_WFE_UPDATE BIT(31) #define CMDQ_WFE_WAIT BIT(15) #define CMDQ_WFE_WAIT_VALUE 0x1 +/** cmdq event maximum */ +#define CMDQ_MAX_EVENT 0x3ff /* * CMDQ_CODE_MASK: diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 54ade13a9b15..4e8899972db4 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -13,9 +13,6 @@ #define CMDQ_NO_TIMEOUT 0xffffffffu -/** cmdq event maximum */ -#define CMDQ_MAX_EVENT 0x3ff - struct cmdq_pkt; struct cmdq_client { From patchwork Tue May 21 01:11:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10952775 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 259161390 for ; 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Tue, 21 May 2019 01:11:32 +0000 X-UUID: 040089b2cea8445d96ee6739b762a67d-20190520 X-UUID: 040089b2cea8445d96ee6739b762a67d-20190520 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 785039292; Mon, 20 May 2019 17:11:21 -0800 Received: from MTKMBS01N2.mediatek.inc (172.21.101.79) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 20 May 2019 18:11:20 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 21 May 2019 09:11:11 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 21 May 2019 09:11:11 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v7 07/12] soc: mediatek: cmdq: reorder the parameter Date: Tue, 21 May 2019 09:11:03 +0800 Message-ID: <20190521011108.40428-8-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190521011108.40428-1-bibby.hsieh@mediatek.com> References: <20190521011108.40428-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: DD74AFE02F75887F3773AFACE73ED7968A3CEFE728A61FE67664BA999E66F10E2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190520_181129_905244_FB1DDA64 X-CRM114-Status: GOOD ( 11.14 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The order of instructions gce knowed is [subsys offset value] so reorder the parameter of cmdq_pkt_write_mask and cmdq_pkt_write function. Signed-off-by: Bibby Hsieh Reviewed-by: CK Hu --- drivers/soc/mediatek/mtk-cmdq-helper.c | 6 +++--- include/linux/soc/mediatek/mtk-cmdq.h | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index ff9fef5a032b..082b8978651e 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -136,7 +136,7 @@ static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code, return 0; } -int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value, u32 subsys, u32 offset) +int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 subsys, u32 offset, u32 value) { u32 arg_a = (offset & CMDQ_ARG_A_WRITE_MASK) | (subsys << CMDQ_SUBSYS_SHIFT); @@ -145,8 +145,8 @@ int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value, u32 subsys, u32 offset) } EXPORT_SYMBOL(cmdq_pkt_write); -int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value, - u32 subsys, u32 offset, u32 mask) +int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 subsys, + u32 offset, u32 value, u32 mask) { u32 offset_mask = offset; int err = 0; diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 4e8899972db4..39d813dde4b4 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -60,26 +60,26 @@ void cmdq_pkt_destroy(struct cmdq_pkt *pkt); /** * cmdq_pkt_write() - append write command to the CMDQ packet * @pkt: the CMDQ packet - * @value: the specified target register value * @subsys: the CMDQ sub system code * @offset: register offset from CMDQ sub system + * @value: the specified target register value * * Return: 0 for success; else the error code is returned */ -int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value, u32 subsys, u32 offset); +int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 subsys, u32 offset, u32 value); /** * cmdq_pkt_write_mask() - append write command with mask to the CMDQ packet * @pkt: the CMDQ packet - * @value: the specified target register value * @subsys: the CMDQ sub system code * @offset: register offset from CMDQ sub system + * @value: the specified target register value * @mask: the specified target register mask * * Return: 0 for success; else the error code is returned */ -int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value, - u32 subsys, u32 offset, u32 mask); +int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 subsys, + u32 offset, u32 value, u32 mask); /** * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet From patchwork Tue May 21 01:11:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10952761 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DF226912 for ; Tue, 21 May 2019 01:12:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CF08728906 for ; Tue, 21 May 2019 01:12:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C31D82892C; Tue, 21 May 2019 01:12:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 650B928906 for ; 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Tue, 21 May 2019 09:11:11 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v7 08/12] soc: mediatek: cmdq: change the type of input parameter Date: Tue, 21 May 2019 09:11:04 +0800 Message-ID: <20190521011108.40428-9-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190521011108.40428-1-bibby.hsieh@mediatek.com> References: <20190521011108.40428-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190520_181124_309308_F30B9518 X-CRM114-Status: GOOD ( 11.60 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP According to the cmdq hardware design, the subsys is u8, the offset is u16 and the event id is u16. This patch changes the type of subsys, offset and event id to the correct type. Signed-off-by: Bibby Hsieh Reviewed-by: CK Hu --- drivers/soc/mediatek/mtk-cmdq-helper.c | 10 +++++----- include/linux/soc/mediatek/mtk-cmdq.h | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index 082b8978651e..7aa0517ff2f3 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -136,7 +136,7 @@ static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code, return 0; } -int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 subsys, u32 offset, u32 value) +int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value) { u32 arg_a = (offset & CMDQ_ARG_A_WRITE_MASK) | (subsys << CMDQ_SUBSYS_SHIFT); @@ -145,8 +145,8 @@ int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 subsys, u32 offset, u32 value) } EXPORT_SYMBOL(cmdq_pkt_write); -int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 subsys, - u32 offset, u32 value, u32 mask) +int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys, + u16 offset, u32 value, u32 mask) { u32 offset_mask = offset; int err = 0; @@ -161,7 +161,7 @@ int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 subsys, } EXPORT_SYMBOL(cmdq_pkt_write_mask); -int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event) +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event) { u32 arg_b; @@ -181,7 +181,7 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event) } EXPORT_SYMBOL(cmdq_pkt_wfe); -int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u32 event) +int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event) { if (event >= CMDQ_MAX_EVENT) return -EINVAL; diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 39d813dde4b4..9618debb9ceb 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -66,7 +66,7 @@ void cmdq_pkt_destroy(struct cmdq_pkt *pkt); * * Return: 0 for success; else the error code is returned */ -int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 subsys, u32 offset, u32 value); +int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value); /** * cmdq_pkt_write_mask() - append write command with mask to the CMDQ packet @@ -78,8 +78,8 @@ int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 subsys, u32 offset, u32 value); * * Return: 0 for success; else the error code is returned */ -int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 subsys, - u32 offset, u32 value, u32 mask); +int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys, + u16 offset, u32 value, u32 mask); /** * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet @@ -88,7 +88,7 @@ int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 subsys, * * Return: 0 for success; else the error code is returned */ -int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event); +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event); /** * cmdq_pkt_clear_event() - append clear event command to the CMDQ packet @@ -97,7 +97,7 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event); * * Return: 0 for success; else the error code is returned */ -int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u32 event); +int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event); /** * cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ From patchwork Tue May 21 01:11:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10952797 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D474417D2 for ; Tue, 21 May 2019 01:18:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C09982892C for ; Tue, 21 May 2019 01:18:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9C27E28901; Tue, 21 May 2019 01:18:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0943028901 for ; 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Tue, 21 May 2019 09:11:11 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v7 09/12] soc: mediatek: cmdq: define the instruction struct Date: Tue, 21 May 2019 09:11:05 +0800 Message-ID: <20190521011108.40428-10-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190521011108.40428-1-bibby.hsieh@mediatek.com> References: <20190521011108.40428-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 5C53F5E50074F883B0DE11C0824CBF03FAEB26B63D4C0D0A20E1C03281D72F0F2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190520_181151_514575_814804BB X-CRM114-Status: GOOD ( 14.99 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Define an instruction structure for gce driver to append command. This structure can make the client's code more readability. Signed-off-by: Bibby Hsieh Reviewed-by: CK Hu --- drivers/soc/mediatek/mtk-cmdq-helper.c | 103 +++++++++++++++-------- include/linux/mailbox/mtk-cmdq-mailbox.h | 2 + 2 files changed, 72 insertions(+), 33 deletions(-) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index 7aa0517ff2f3..0886c4967ca4 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -9,12 +9,24 @@ #include #include -#define CMDQ_ARG_A_WRITE_MASK 0xffff #define CMDQ_WRITE_ENABLE_MASK BIT(0) #define CMDQ_EOC_IRQ_EN BIT(0) #define CMDQ_EOC_CMD ((u64)((CMDQ_CODE_EOC << CMDQ_OP_CODE_SHIFT)) \ << 32 | CMDQ_EOC_IRQ_EN) +struct cmdq_instruction { + union { + u32 value; + u32 mask; + }; + union { + u16 offset; + u16 event; + }; + u8 subsys; + u8 op; +}; + static void cmdq_client_timeout(struct timer_list *t) { struct cmdq_client *client = from_timer(client, t, timer); @@ -110,10 +122,8 @@ void cmdq_pkt_destroy(struct cmdq_pkt *pkt) } EXPORT_SYMBOL(cmdq_pkt_destroy); -static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code, - u32 arg_a, u32 arg_b) +static struct cmdq_instruction *cmdq_pkt_append_command(struct cmdq_pkt *pkt) { - u64 *cmd_ptr; if (unlikely(pkt->cmd_buf_size + CMDQ_INST_SIZE > pkt->buf_size)) { /* @@ -127,81 +137,108 @@ static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code, pkt->cmd_buf_size += CMDQ_INST_SIZE; WARN_ONCE(1, "%s: buffer size %u is too small !\n", __func__, (u32)pkt->buf_size); - return -ENOMEM; + return NULL; } - cmd_ptr = pkt->va_base + pkt->cmd_buf_size; - (*cmd_ptr) = (u64)((code << CMDQ_OP_CODE_SHIFT) | arg_a) << 32 | arg_b; + pkt->cmd_buf_size += CMDQ_INST_SIZE; - return 0; + return pkt->va_base + pkt->cmd_buf_size - CMDQ_INST_SIZE; } int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value) { - u32 arg_a = (offset & CMDQ_ARG_A_WRITE_MASK) | - (subsys << CMDQ_SUBSYS_SHIFT); + struct cmdq_instruction *inst; + + inst = cmdq_pkt_append_command(pkt); + if (!inst) + return -ENOMEM; + + inst->op = CMDQ_CODE_WRITE; + inst->value = value; + inst->offset = offset; + inst->subsys = subsys; - return cmdq_pkt_append_command(pkt, CMDQ_CODE_WRITE, arg_a, value); + return 0; } EXPORT_SYMBOL(cmdq_pkt_write); int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value, u32 mask) { + struct cmdq_instruction *inst; u32 offset_mask = offset; - int err = 0; if (mask != 0xffffffff) { - err = cmdq_pkt_append_command(pkt, CMDQ_CODE_MASK, 0, ~mask); + inst = cmdq_pkt_append_command(pkt); + if (!inst) + return -ENOMEM; + + inst->op = CMDQ_CODE_MASK; + inst->mask = ~mask; offset_mask |= CMDQ_WRITE_ENABLE_MASK; } - err |= cmdq_pkt_write(pkt, value, subsys, offset_mask); - return err; + return cmdq_pkt_write(pkt, subsys, offset_mask, value); } EXPORT_SYMBOL(cmdq_pkt_write_mask); int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event) { - u32 arg_b; + struct cmdq_instruction *inst; if (event >= CMDQ_MAX_EVENT) return -EINVAL; - /* - * WFE arg_b - * bit 0-11: wait value - * bit 15: 1 - wait, 0 - no wait - * bit 16-27: update value - * bit 31: 1 - update, 0 - no update - */ - arg_b = CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE; + inst = cmdq_pkt_append_command(pkt); + if (!inst) + return -ENOMEM; + + inst->op = CMDQ_CODE_WFE; + inst->value = CMDQ_WFE_OPTION; + inst->event = event; - return cmdq_pkt_append_command(pkt, CMDQ_CODE_WFE, event, arg_b); + return 0; } EXPORT_SYMBOL(cmdq_pkt_wfe); int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event) { + struct cmdq_instruction *inst; + if (event >= CMDQ_MAX_EVENT) return -EINVAL; - return cmdq_pkt_append_command(pkt, CMDQ_CODE_WFE, event, - CMDQ_WFE_UPDATE); + inst = cmdq_pkt_append_command(pkt); + if (!inst) + return -ENOMEM; + + inst->op = CMDQ_CODE_WFE; + inst->value = CMDQ_WFE_UPDATE; + inst->event = event; + + return 0; } EXPORT_SYMBOL(cmdq_pkt_clear_event); static int cmdq_pkt_finalize(struct cmdq_pkt *pkt) { - int err; + struct cmdq_instruction *inst; + + inst = cmdq_pkt_append_command(pkt); + if (!inst) + return -ENOMEM; - /* insert EOC and generate IRQ for each command iteration */ - err = cmdq_pkt_append_command(pkt, CMDQ_CODE_EOC, 0, CMDQ_EOC_IRQ_EN); + inst->op = CMDQ_CODE_EOC; + inst->value = CMDQ_EOC_IRQ_EN; - /* JUMP to end */ - err |= cmdq_pkt_append_command(pkt, CMDQ_CODE_JUMP, 0, CMDQ_JUMP_PASS); + inst = cmdq_pkt_append_command(pkt); + if (!inst) + return -ENOMEM; + + inst->op = CMDQ_CODE_JUMP; + inst->value = CMDQ_JUMP_PASS; - return err; + return 0; } static void cmdq_pkt_flush_async_cb(struct cmdq_cb_data data) diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h index 911475da7a53..c8adedefaf42 100644 --- a/include/linux/mailbox/mtk-cmdq-mailbox.h +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h @@ -19,6 +19,8 @@ #define CMDQ_WFE_UPDATE BIT(31) #define CMDQ_WFE_WAIT BIT(15) #define CMDQ_WFE_WAIT_VALUE 0x1 +#define CMDQ_WFE_OPTION (CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | \ + CMDQ_WFE_WAIT_VALUE) /** cmdq event maximum */ #define CMDQ_MAX_EVENT 0x3ff From patchwork Tue May 21 01:11:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10952747 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 74E44912 for ; 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Tue, 21 May 2019 01:11:23 +0000 X-UUID: 9f8cece812064424865b53d941a0ae6a-20190520 X-UUID: 9f8cece812064424865b53d941a0ae6a-20190520 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1052134183; Mon, 20 May 2019 17:11:14 -0800 Received: from mtkmbs03n1.mediatek.inc (172.21.101.181) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 20 May 2019 18:11:13 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs03n1.mediatek.inc (172.21.101.181) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 21 May 2019 09:11:12 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 21 May 2019 09:11:12 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v7 10/12] soc: mediatek: cmdq: add polling function Date: Tue, 21 May 2019 09:11:06 +0800 Message-ID: <20190521011108.40428-11-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190521011108.40428-1-bibby.hsieh@mediatek.com> References: <20190521011108.40428-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190520_181122_490571_BBEB3534 X-CRM114-Status: GOOD ( 12.36 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP add polling function in cmdq helper functions Signed-off-by: Bibby Hsieh Reviewed-by: CK Hu --- drivers/soc/mediatek/mtk-cmdq-helper.c | 28 ++++++++++++++++++++++++ include/linux/mailbox/mtk-cmdq-mailbox.h | 1 + include/linux/soc/mediatek/mtk-cmdq.h | 15 +++++++++++++ 3 files changed, 44 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index 0886c4967ca4..70ad4d806fac 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -220,6 +220,34 @@ int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event) } EXPORT_SYMBOL(cmdq_pkt_clear_event); +int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys, + u16 offset, u32 value, u32 mask) +{ + struct cmdq_instruction *inst; + + if (mask != 0xffffffff) { + inst = cmdq_pkt_append_command(pkt); + if (!inst) + return -ENOMEM; + + inst->op = CMDQ_CODE_MASK; + inst->value = ~mask; + offset = offset | 0x1; + } + + inst = cmdq_pkt_append_command(pkt); + if (!inst) + return -ENOMEM; + + inst->op = CMDQ_CODE_POLL; + inst->value = value; + inst->offset = offset; + inst->subsys = subsys; + + return 0; +} +EXPORT_SYMBOL(cmdq_pkt_poll); + static int cmdq_pkt_finalize(struct cmdq_pkt *pkt) { struct cmdq_instruction *inst; diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h index c8adedefaf42..9e3502945bc1 100644 --- a/include/linux/mailbox/mtk-cmdq-mailbox.h +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h @@ -46,6 +46,7 @@ enum cmdq_code { CMDQ_CODE_MASK = 0x02, CMDQ_CODE_WRITE = 0x04, + CMDQ_CODE_POLL = 0x08, CMDQ_CODE_JUMP = 0x10, CMDQ_CODE_WFE = 0x20, CMDQ_CODE_EOC = 0x40, diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 9618debb9ceb..a345870a6d10 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -99,6 +99,21 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event); */ int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event); +/** + * cmdq_pkt_poll() - Append polling command to the CMDQ packet, ask GCE to + * execute an instruction that wait for a specified hardware + * register to check for the value. All GCE hardware + * threads will be blocked by this instruction. + * @pkt: the CMDQ packet + * @subsys: the CMDQ sub system code + * @offset: register offset from CMDQ sub system + * @value: the specified target register value + * @mask: the specified target register mask + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys, + u16 offset, u32 value, u32 mask); /** * cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ * packet and call back at the end of done packet From patchwork Tue May 21 01:11:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10952791 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3B46E912 for ; Tue, 21 May 2019 01:13:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2A42A28901 for ; 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Mon, 20 May 2019 17:11:20 -0800 Received: from mtkmbs03n2.mediatek.inc (172.21.101.182) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 20 May 2019 18:11:19 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs03n2.mediatek.inc (172.21.101.182) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 21 May 2019 09:11:12 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 21 May 2019 09:11:12 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v7 11/12] soc: mediatek: cmdq: add cmdq_dev_get_client_reg function Date: Tue, 21 May 2019 09:11:07 +0800 Message-ID: <20190521011108.40428-12-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190521011108.40428-1-bibby.hsieh@mediatek.com> References: <20190521011108.40428-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: EB31BCC285E1AB052BEA5788C4AF42BA4F51DFC824E3E5B86A20834AD3655F012000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190520_181150_454275_8B14D3C0 X-CRM114-Status: GOOD ( 10.71 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP GCE cannot know the register base address, this function can help cmdq client to get the cmdq_client_reg structure. Signed-off-by: Bibby Hsieh --- drivers/soc/mediatek/mtk-cmdq-helper.c | 25 +++++++++++++++++++++++++ include/linux/soc/mediatek/mtk-cmdq.h | 18 ++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index 70ad4d806fac..815845bb5982 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -27,6 +27,31 @@ struct cmdq_instruction { u8 op; }; +struct cmdq_client_reg *cmdq_dev_get_client_reg(struct device *dev, int idx) +{ + struct cmdq_client_reg *client_reg; + struct of_phandle_args spec; + + client_reg = devm_kzalloc(dev, sizeof(*client_reg), GFP_KERNEL); + if (!client_reg) + return NULL; + + if (of_parse_phandle_with_args(dev->of_node, "mediatek,gce-client-reg", + "#subsys-cells", idx, &spec)) { + dev_err(dev, "can't parse gce-client-reg property (%d)", idx); + + return NULL; + } + + client_reg->subsys = spec.args[0]; + client_reg->offset = spec.args[1]; + client_reg->size = spec.args[2]; + of_node_put(spec.np); + + return client_reg; +} +EXPORT_SYMBOL(cmdq_dev_get_client_reg); + static void cmdq_client_timeout(struct timer_list *t) { struct cmdq_client *client = from_timer(client, t, timer); diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index a345870a6d10..d0dea3780f7a 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -15,6 +15,12 @@ struct cmdq_pkt; +struct cmdq_client_reg { + u8 subsys; + u16 offset; + u16 size; +}; + struct cmdq_client { spinlock_t lock; u32 pkt_cnt; @@ -142,4 +148,16 @@ int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb, */ int cmdq_pkt_flush(struct cmdq_pkt *pkt); +/** + * cmdq_dev_get_client_reg() - parse cmdq client reg from the device node of CMDQ client + * @dev: device of CMDQ mailbox client + * @idx: the index of desired reg + * + * Return: CMDQ client reg pointer + * + * Help CMDQ client pasing the cmdq client reg + * from the device node of CMDQ client. + */ +struct cmdq_client_reg *cmdq_dev_get_client_reg(struct device *dev, int idx); + #endif /* __MTK_CMDQ_H__ */ From patchwork Tue May 21 01:11:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibby Hsieh X-Patchwork-Id: 10952757 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C8E661390 for ; Tue, 21 May 2019 01:11:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B90EF28901 for ; Tue, 21 May 2019 01:11:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ACA4D2892C; Tue, 21 May 2019 01:11:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5A9A828901 for ; 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Tue, 21 May 2019 09:11:12 +0800 From: Bibby Hsieh To: Jassi Brar , Matthias Brugger , Rob Herring , CK HU Subject: [PATCH v7 12/12] arm64: dts: add gce node for mt8183 Date: Tue, 21 May 2019 09:11:08 +0800 Message-ID: <20190521011108.40428-13-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190521011108.40428-1-bibby.hsieh@mediatek.com> References: <20190521011108.40428-1-bibby.hsieh@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: EF65290D893DD45F4AA9FBFA4B91EAECA83E79C13938BA7B184A34CD0ED59DCE2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190520_181123_865502_3C8EB619 X-CRM114-Status: UNSURE ( 9.99 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Philipp Zabel , srv_heupstream@mediatek.com, Daoyuan Huang , Sascha Hauer , linux-kernel@vger.kernel.org, Dennis-YC Hsieh , linux-mediatek@lists.infradead.org, Houlong Wei , Sascha Hauer , Jiaguang Zhang , Bibby Hsieh , linux-arm-kernel@lists.infradead.org, ginny.chen@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP add gce device node for mt8183 Signed-off-by: Bibby Hsieh --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index b36e37fcdfe3..d6d26fa32dd7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include "mt8183-pinfunc.h" / { compatible = "mediatek,mt8183"; @@ -293,6 +294,16 @@ clock-names = "spi", "wrap"; }; + gce: gce@10238000 { + compatible = "mediatek,mt8183-gce"; + reg = <0 0x10238000 0 0x4000>; + interrupts = ; + #mbox-cells = <3>; + #subsys-cells = <3>; + clocks = <&infracfg CLK_INFRA_GCE>; + clock-names = "gce"; + }; + uart0: serial@11002000 { compatible = "mediatek,mt8183-uart", "mediatek,mt6577-uart";