From patchwork Tue May 21 09:35:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 10953241 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 11F40924 for ; Tue, 21 May 2019 09:35:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 028E72881A for ; Tue, 21 May 2019 09:35:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EAA0428841; Tue, 21 May 2019 09:35:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 944B8289BC for ; Tue, 21 May 2019 09:35:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727541AbfEUJf3 (ORCPT ); Tue, 21 May 2019 05:35:29 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:46653 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726389AbfEUJf3 (ORCPT ); Tue, 21 May 2019 05:35:29 -0400 Received: by mail-pl1-f195.google.com with SMTP id r18so8151636pls.13 for ; Tue, 21 May 2019 02:35:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=snr6I7xOlJyQUxx9e5KJWRPzOk5/RPGil0u5RknK1co=; b=rVPESzloEoFaSm5eQVX+SSjgn2ZsbWsXtAubks8NdodjIma1kybM3H7lhAqtQdgdAV clp9h5CkSJa2HT4/kfjRDBUErdWd8NUlKVMz7EI4G9oSHjOLfVg+xwmahACy9O4lIsrG xBnNq11FyV62nviOis7Kt9LMBoQiyhmjQiS3iVHHQxyR5OBTzlfDtui1q1cO3fnF6Np9 LQLAKENmgf621qZS3qr0dQW4fB4AYgzSZlLhR6N4C/LDBMvnAMRFkfYXGZR9Utn3Sien NLpOLL+DorAVv1FL32ViodUCMOimKafPcHVxEX1uLz2twuTW/BU/k7pBn7wrfVw/9daO 3F0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=snr6I7xOlJyQUxx9e5KJWRPzOk5/RPGil0u5RknK1co=; b=Xmu9QBnRt2hhdjbjyhSWE+B3QlOKwkwpDbiaIxfeHb8VzEIVr4ErSq2j+AYCNfn4wB c0gcHzUe+z84KKEowhBuoNSwE2KhdHVtNtiDII/F/+Y4NCs53MnS6rtQ/+P1SzNGx14W OdCYbTRePssXU9jl7SVEfZGrpZhINBDfoPizqTGHnvZ5Zhp2ZeQZSzD6Qt+q1cDEzyiC zg2XPlR2R+NRysNCKUtnK5vWpAl0SAIc6xuDoSChATe/KC6Js5tT8tO7iZTShWFo438v mlKgTT46duu8sZzVv+bI+fNx7qJQgN7fRDEsDLhnNHF0b/9RFQ/sIbvnH11l+3D2oygr LpNg== X-Gm-Message-State: APjAAAWJNiBJfmdTmXCebZftNLm7peQCKUyJm9NBiGJxuSPOT48qS7Ip BA1IKGI28fkEAatHnjk/bnW5Rw== X-Google-Smtp-Source: APXvYqxblgRSQgNYff41+kJRYh4Og5BQ8zoVZkjZcLjl8sKf00ZpyEGZOIT/R9ZECXRvs2o0hW9Abw== X-Received: by 2002:a17:902:aa45:: with SMTP id c5mr80617108plr.144.1558431328331; Tue, 21 May 2019 02:35:28 -0700 (PDT) Received: from localhost ([49.248.189.249]) by smtp.gmail.com with ESMTPSA id t18sm30938459pgm.69.2019.05.21.02.35.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 21 May 2019 02:35:27 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, agross@kernel.org, niklas.cassel@linaro.org, marc.w.gonzalez@free.fr, sibis@codeaurora.org, daniel.lezcano@linaro.org, Andy Gross , David Brown , Li Yang , Shawn Guo Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/9] arm64: dts: fsl: ls1028a: Fix entry-method property to reflect documentation Date: Tue, 21 May 2019 15:05:11 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The idle-states binding documentation[1] mentions that the 'entry-method' property is required on 64-bit platforms and must be set to "psci". We fixed up all uses of the entry-method property in commit e9880240e4f4 ("arm64: dts: Fix various entry-method properties to reflect documentation"). But a new one has appeared. Fix it up. [1] Documentation/devicetree/bindings/arm/idle-states.txt (see idle-states node) Signed-off-by: Amit Kucheria Acked-by: Sudeep Holla Reviewed-by: Bjorn Andersson Reviewed-by: Niklas Cassel --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 2896bbcfa3bb..42e7822a0227 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -51,7 +51,7 @@ * PSCI node is not added default, U-boot will add missing * parts if it determines to use PSCI. */ - entry-method = "arm,psci"; + entry-method = "psci"; CPU_PH20: cpu-ph20 { compatible = "arm,idle-state"; From patchwork Tue May 21 09:35:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 10953243 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C0067924 for ; Tue, 21 May 2019 09:35:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B141628562 for ; Tue, 21 May 2019 09:35:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A4EA828848; Tue, 21 May 2019 09:35:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 48FF928562 for ; Tue, 21 May 2019 09:35:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727572AbfEUJfd (ORCPT ); Tue, 21 May 2019 05:35:33 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:43754 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727564AbfEUJfc (ORCPT ); Tue, 21 May 2019 05:35:32 -0400 Received: by mail-pf1-f194.google.com with SMTP id c6so8760934pfa.10 for ; Tue, 21 May 2019 02:35:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=FnxOSFCClFXBL/MQEoj2x4esQGTm7evFd77Wm/m1NK4=; b=FFvJMEerPN6RTzJ+NEOY16l+7iMM0ppRraH6BWkcq2lCBKg0mIogK7V9VC0mYcnoFC lpcwM2Gk+YfdcAdRsD1nkSSdLsZUylUpeLVeBwh0oBruUCaG9/tx8N6CnMySTJwPQVOp 4Zcw1MxuGUvdcMaMWCGCeZXje44wam6ITlpgXVwK6Dc87G6IaG/nRabVCKTEJLTppkUO i3lgHNB01l3pm9EN1IpqlE91qR/FgJv4Ca/zhN6x8+WEkKKyLjd2ZBLFT4BAeggnr2C9 7U7qr/o1nxk0MfPBf5UVzNw3gO95qTis3Vw3EEfBCyjpdLtzvF/AH8mrQuUsFr4CIwaK Q+Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=FnxOSFCClFXBL/MQEoj2x4esQGTm7evFd77Wm/m1NK4=; b=lerQhofBGNINlFBwh08gkbv/R1D0GG2BeczqiW/G36I7Grioca+sL7n1u+Wu/1tlCZ mg+C7ctV5FRCG99+77yGrOVa7BVr9uH1d3sr+NePX/shIX/ro1r601ET/hjcwYN48ID2 jT6QpPCdX6CET4B3tIARgfPjXOsxjH8zNMJxD6ko4Atf/cOgdOSKbOfDfm8PPgvZvtbr g75ykwysKeOCpFBlpO41U8v9r/atlDA58MnV8lEVjlWXU39fJONx1xfXNP+uHz1wp3nP ogLptbHJbRJReqK4QGgzpEwUqhnE3YEuQJC7K6YJ3rSGRQVIVOlr66QIS1g0fL+H+YK9 C4Gg== X-Gm-Message-State: APjAAAUO62zSx2JktvN45zjt/y4hFwSVJP7mDjlwgdQDVfwKQyiBa0kc LcMTpUMl7CP39xl6d/kySlBx5Q== X-Google-Smtp-Source: APXvYqwADQFmBLmMydAb2ax1jzlS0xwcSIkCQrM5GCjaAteOFtjZewJqH81wNhkrczg63VjCnLukfA== X-Received: by 2002:a63:1354:: with SMTP id 20mr79407935pgt.356.1558431331764; Tue, 21 May 2019 02:35:31 -0700 (PDT) Received: from localhost ([49.248.189.249]) by smtp.gmail.com with ESMTPSA id l21sm28759496pff.40.2019.05.21.02.35.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 21 May 2019 02:35:31 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, agross@kernel.org, niklas.cassel@linaro.org, marc.w.gonzalez@free.fr, sibis@codeaurora.org, daniel.lezcano@linaro.org, Andy Gross , David Brown , Li Yang , Shawn Guo Cc: devicetree@vger.kernel.org Subject: [PATCH v2 2/9] Documentation: arm: Link idle-states binding to "enable-method" property Date: Tue, 21 May 2019 15:05:12 +0530 Message-Id: <9dc4ce06143de48039e841c337fafa7cb9c8d7d2.1558430617.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The "enable-method" property for cpu nodes needs to be "psci" for CPU idle management to be setup correctly. Add a note to the binding documentation to this effect to make it obvious. Signed-off-by: Amit Kucheria Acked-by: Sudeep Holla --- .../devicetree/bindings/arm/idle-states.txt | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt index 45730ba60af5..3bdbe675b9e6 100644 --- a/Documentation/devicetree/bindings/arm/idle-states.txt +++ b/Documentation/devicetree/bindings/arm/idle-states.txt @@ -241,9 +241,13 @@ processor idle states, defined as device tree nodes, are listed. - "psci" # On ARM 32-bit systems this property is optional -The nodes describing the idle states (state) can only be defined within the -idle-states node, any other configuration is considered invalid and therefore -must be ignored. +This assumes that the "enable-method" property is set to "psci" in the cpu +node[6] that is responsible for setting up CPU idle management in the OS +implementation. + +The nodes describing the idle states (state) can only be defined +within the idle-states node, any other configuration is considered invalid +and therefore must be ignored. =========================================== 4 - state node @@ -697,3 +701,6 @@ cpus { [5] Devicetree Specification https://www.devicetree.org/specifications/ + +[6] ARM Linux Kernel documentation - Booting AArch64 Linux + Documentation/arm64/booting.txt From patchwork Tue May 21 09:35:13 2019 Content-Type: text/plain; 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Tue, 21 May 2019 02:35:34 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, agross@kernel.org, niklas.cassel@linaro.org, marc.w.gonzalez@free.fr, sibis@codeaurora.org, daniel.lezcano@linaro.org, Andy Gross , David Brown , Li Yang , Shawn Guo Cc: devicetree@vger.kernel.org Subject: [PATCH v2 3/9] arm64: dts: qcom: msm8916: Add entry-method property for the idle-states node Date: Tue, 21 May 2019 15:05:13 +0530 Message-Id: <0374669560d13bba30dfa33cd10a0ad8a65b604b.1558430617.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The idle-states binding documentation[1] mentions that the 'entry-method' property is required on 64-bit platforms and must be set to "psci". [1] Documentation/devicetree/bindings/arm/idle-states.txt (see idle-states node) Signed-off-by: Amit Kucheria Reviewed-by: Niklas Cassel Acked-by: Daniel Lezcano --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 0803ca8c02da..82ea5b8b37a2 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -158,6 +158,8 @@ }; idle-states { + entry-method = "psci"; + CPU_SPC: spc { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000002>; From patchwork Tue May 21 09:35:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 10953251 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C67951390 for ; Tue, 21 May 2019 09:35:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B66641FFF9 for ; Tue, 21 May 2019 09:35:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AA4842881A; Tue, 21 May 2019 09:35:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 474121FFF9 for ; Tue, 21 May 2019 09:35:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727640AbfEUJfm (ORCPT ); Tue, 21 May 2019 05:35:42 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:34941 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727606AbfEUJfj (ORCPT ); Tue, 21 May 2019 05:35:39 -0400 Received: by mail-pl1-f196.google.com with SMTP id p1so2790729plo.2 for ; Tue, 21 May 2019 02:35:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=67/AKyXoPFVp4cqttbJIppWLYmQiwde4dFyqAbFMmds=; b=DtcDve6YywCjAO1Gsx8n2ByBki/1JYbbOX381slvKMV9kqYC9i/m6ea1ZqmczWSeKJ qqinec8tk6aq3RdfMXDADkRPldNJAIdHTf81Temc82fxlreA37oQX5+dxGSYoBTfK+C8 aNYiUHcx14/Vg2bePe7wUj8oXrCjHJycTTpDU7/m1nMae4WUhAGfJgeGUAMQAEZHOXnP ZpvFoRcx11tWKDofMV0grUAUO+2AHW2K692bkC+Qfckgqfel0BadkZkytFuc0l5oGoTX 9TtvuHADwTMhqgL6LI75jXktyrisaqvty1N9KqLoE5ZCWGdptB4SH7o82p/0uRv1PQFo SRBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=67/AKyXoPFVp4cqttbJIppWLYmQiwde4dFyqAbFMmds=; b=jBKVZard4m1fFlrN34Zs2JliTa5c/AWC+YTLN8ro7IPUnjj/s+vaAtxBgtQomskcED ERqOdoMPYVKu6ai5IbdyCKedKmBYvrBV8SHPe00zwnOt/3wATmP+CeuFSKR9wUomfhZu RQgMpXjF2iKgIf2EthIBnRxQII42MNQ1JjaIEnCvE2vk3zYiRz9nwi2NFoUrz229Uf8H mYsq00ZqSlzCjL5EkhsaFAo1DL4HayPp3gXmypxLgtX81917S3k1OVchQKKWARSckK4h HNf8SkLTsH8qHgeFApORUGLFX4heDoGtKYlssW/73Xno727IES3NsAB+SL53wjYvwDJZ 9xLQ== X-Gm-Message-State: APjAAAVtXa2RlgnbjvIn4VVqtWMklkTWCvyprzY4xeO6EgWum81Kdnl1 vKjrfvt6zXKv1csUmwge66aEtQ== X-Google-Smtp-Source: APXvYqxxPPHeM5A1TWlSQXxfOe059MDl8jQsVAYupC1E8gblrClJ2SJk4Nozm6RXlLG4FgvOu7E9vw== X-Received: by 2002:a17:902:9f8b:: with SMTP id g11mr74826615plq.199.1558431338839; Tue, 21 May 2019 02:35:38 -0700 (PDT) Received: from localhost ([49.248.189.249]) by smtp.gmail.com with ESMTPSA id n21sm23297281pgf.28.2019.05.21.02.35.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 21 May 2019 02:35:38 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, agross@kernel.org, niklas.cassel@linaro.org, marc.w.gonzalez@free.fr, sibis@codeaurora.org, daniel.lezcano@linaro.org, Andy Gross , David Brown , Li Yang , Shawn Guo Cc: devicetree@vger.kernel.org Subject: [PATCH v2 4/9] arm64: dts: qcom: msm8916: Use more generic idle state names Date: Tue, 21 May 2019 15:05:14 +0530 Message-Id: <606afcaab57021faacdb47220b9d9d0f5a27f7b8.1558430617.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Instead of using Qualcomm-specific terminology, use generic node names for the idle states that are easier to understand. Move the description into the "idle-state-name" property. Signed-off-by: Amit Kucheria Reviewed-by: Niklas Cassel Acked-by: Daniel Lezcano --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 82ea5b8b37a2..3a8c6c4fcf15 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -110,7 +110,7 @@ reg = <0x0>; next-level-cache = <&L2_0>; enable-method = "psci"; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; @@ -122,7 +122,7 @@ reg = <0x1>; next-level-cache = <&L2_0>; enable-method = "psci"; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; @@ -134,7 +134,7 @@ reg = <0x2>; next-level-cache = <&L2_0>; enable-method = "psci"; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; @@ -146,7 +146,7 @@ reg = <0x3>; next-level-cache = <&L2_0>; enable-method = "psci"; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; @@ -160,8 +160,9 @@ idle-states { entry-method = "psci"; - CPU_SPC: spc { + CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; + idle-state-name = "standalone-power-collapse"; arm,psci-suspend-param = <0x40000002>; entry-latency-us = <130>; exit-latency-us = <150>; From patchwork Tue May 21 09:35:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 10953261 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3C2291395 for ; Tue, 21 May 2019 09:36:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2C3941FFF9 for ; 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Tue, 21 May 2019 02:35:42 -0700 (PDT) Received: from localhost ([49.248.189.249]) by smtp.gmail.com with ESMTPSA id o6sm43731344pfa.88.2019.05.21.02.35.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 21 May 2019 02:35:41 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, agross@kernel.org, niklas.cassel@linaro.org, marc.w.gonzalez@free.fr, sibis@codeaurora.org, daniel.lezcano@linaro.org, Andy Gross , David Brown , Li Yang , Shawn Guo Cc: devicetree@vger.kernel.org Subject: [PATCH v2 5/9] arm64: dts: qcom: qcs404: Add PSCI cpuidle low power states Date: Tue, 21 May 2019 15:05:15 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Niklas Cassel Add device bindings for cpuidle states for cpu devices. Signed-off-by: Niklas Cassel Reviewed-by: Vinod Koul [rename the idle-states to more generic names and fixups] Signed-off-by: Amit Kucheria Acked-by: Daniel Lezcano --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index e8fd26633d57..0a9b29af64c2 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -30,6 +30,7 @@ compatible = "arm,cortex-a53"; reg = <0x100>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; }; @@ -38,6 +39,7 @@ compatible = "arm,cortex-a53"; reg = <0x101>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; }; @@ -46,6 +48,7 @@ compatible = "arm,cortex-a53"; reg = <0x102>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; }; @@ -54,6 +57,7 @@ compatible = "arm,cortex-a53"; reg = <0x103>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; }; @@ -61,6 +65,20 @@ compatible = "cache"; cache-level = <2>; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "standalone-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <125>; + exit-latency-us = <180>; + min-residency-us = <595>; + local-timer-stop; + }; + }; }; firmware { From patchwork Tue May 21 09:35:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 10953259 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CB525924 for ; Tue, 21 May 2019 09:36:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BC0221FFF9 for ; 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Tue, 21 May 2019 02:35:45 -0700 (PDT) Received: from localhost ([49.248.189.249]) by smtp.gmail.com with ESMTPSA id 63sm29430016pfu.95.2019.05.21.02.35.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 21 May 2019 02:35:45 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, agross@kernel.org, niklas.cassel@linaro.org, marc.w.gonzalez@free.fr, sibis@codeaurora.org, daniel.lezcano@linaro.org, Andy Gross , David Brown , Li Yang , Shawn Guo Cc: devicetree@vger.kernel.org Subject: [PATCH v2 6/9] arm64: dts: qcom: msm8996: Add PSCI cpuidle low power states Date: Tue, 21 May 2019 15:05:16 +0530 Message-Id: <2ffbb3f32484c03360ff7d6fa4668581ef298c9e.1558430617.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add device bindings for cpuidle states for cpu devices. msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement the same microarchitecture and the two clusters only differ in the maximum frequency attainable by the CPUs. Signed-off-by: Amit Kucheria Acked-by: Daniel Lezcano --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index c761269caf80..4f2fb7885f39 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -95,6 +95,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x0>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; @@ -107,6 +108,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x1>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; }; @@ -115,6 +117,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x100>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "cache"; @@ -127,6 +130,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x101>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_1>; }; @@ -151,6 +155,19 @@ }; }; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "standalone-power-collapse"; + arm,psci-suspend-param = <0x00000004>; + entry-latency-us = <40>; + exit-latency-us = <80>; + min-residency-us = <300>; + }; + }; }; thermal-zones { From patchwork Tue May 21 09:35:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 10953257 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9EAC71708 for ; Tue, 21 May 2019 09:36:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8FD481FFF9 for ; Tue, 21 May 2019 09:36:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 841A528841; 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Tue, 21 May 2019 02:35:49 -0700 (PDT) Received: from localhost ([49.248.189.249]) by smtp.gmail.com with ESMTPSA id i22sm23139715pfa.127.2019.05.21.02.35.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 21 May 2019 02:35:48 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, agross@kernel.org, niklas.cassel@linaro.org, marc.w.gonzalez@free.fr, sibis@codeaurora.org, daniel.lezcano@linaro.org, Andy Gross , David Brown , Li Yang , Shawn Guo Cc: devicetree@vger.kernel.org Subject: [PATCH v2 7/9] arm64: dts: qcom: msm8998: Add PSCI cpuidle low power states Date: Tue, 21 May 2019 15:05:17 +0530 Message-Id: <49cf5d94beb9af9ef4e78d4c52f3b0ad20b7c63f.1558430617.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add device bindings for cpuidle states for cpu devices. Cc: Marc Gonzalez Signed-off-by: Amit Kucheria Acked-by: Daniel Lezcano Tested-by: Marc Gonzalez --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 50 +++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 3fd0769fe648..54810980fcf9 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -78,6 +78,7 @@ compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; efficiency = <1024>; next-level-cache = <&L2_0>; L2_0: l2-cache { @@ -97,6 +98,7 @@ compatible = "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; efficiency = <1024>; next-level-cache = <&L2_0>; L1_I_1: l1-icache { @@ -112,6 +114,7 @@ compatible = "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; efficiency = <1024>; next-level-cache = <&L2_0>; L1_I_2: l1-icache { @@ -127,6 +130,7 @@ compatible = "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; efficiency = <1024>; next-level-cache = <&L2_0>; L1_I_3: l1-icache { @@ -142,6 +146,7 @@ compatible = "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; efficiency = <1536>; next-level-cache = <&L2_1>; L2_1: l2-cache { @@ -161,6 +166,7 @@ compatible = "arm,armv8"; reg = <0x0 0x101>; enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; efficiency = <1536>; next-level-cache = <&L2_1>; L1_I_101: l1-icache { @@ -176,6 +182,7 @@ compatible = "arm,armv8"; reg = <0x0 0x102>; enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; efficiency = <1536>; next-level-cache = <&L2_1>; L1_I_102: l1-icache { @@ -191,6 +198,7 @@ compatible = "arm,armv8"; reg = <0x0 0x103>; enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; efficiency = <1536>; next-level-cache = <&L2_1>; L1_I_103: l1-icache { @@ -238,6 +246,48 @@ }; }; }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-retention"; + arm,psci-suspend-param = <0x00000002>; + entry-latency-us = <43>; + exit-latency-us = <86>; + min-residency-us = <200>; + }; + + LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { + compatible = "arm,idle-state"; + idle-state-name = "little-power-collapse"; + arm,psci-suspend-param = <0x00000003>; + entry-latency-us = <100>; + exit-latency-us = <612>; + min-residency-us = <1000>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-retention"; + arm,psci-suspend-param = <0x00000002>; + entry-latency-us = <41>; + exit-latency-us = <82>; + min-residency-us = <200>; + }; + + BIG_CPU_SLEEP_1: cpu-sleep-1-1 { + compatible = "arm,idle-state"; + idle-state-name = "big-power-collapse"; + arm,psci-suspend-param = <0x00000003>; + entry-latency-us = <100>; + exit-latency-us = <525>; + min-residency-us = <1000>; + local-timer-stop; + }; + }; }; firmware { From patchwork Tue May 21 09:35:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 10953253 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 797791390 for ; Tue, 21 May 2019 09:35:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 688471FFF9 for ; Tue, 21 May 2019 09:35:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 58F9C2881A; Tue, 21 May 2019 09:35:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BDD0C1FFF9 for ; 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Tue, 21 May 2019 02:35:52 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, agross@kernel.org, niklas.cassel@linaro.org, marc.w.gonzalez@free.fr, sibis@codeaurora.org, daniel.lezcano@linaro.org, Andy Gross , David Brown , Li Yang , Shawn Guo Cc: "Raju P.L.S.S.S.N" , mkshah@codeaurora.org, devicetree@vger.kernel.org Subject: [PATCH v2 8/9] arm64: dts: qcom: sdm845: Add PSCI cpuidle low power states Date: Tue, 21 May 2019 15:05:18 +0530 Message-Id: <67d61032221b069082222347fb56effe17d4a7c3.1558430617.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Raju P.L.S.S.S.N" Add device bindings for cpuidle states for cpu devices. Cc: Signed-off-by: Raju P.L.S.S.S.N Reviewed-by: Evan Green [amit: rename the idle-states to more generic names and fixups] Signed-off-by: Amit Kucheria Acked-by: Daniel Lezcano --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 69 ++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 5308f1671824..a0ae6bf033ee 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -119,6 +119,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x0>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; next-level-cache = <&L2_0>; @@ -136,6 +137,8 @@ compatible = "qcom,kryo385"; reg = <0x0 0x100>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; next-level-cache = <&L2_100>; @@ -150,6 +153,8 @@ compatible = "qcom,kryo385"; reg = <0x0 0x200>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; next-level-cache = <&L2_200>; @@ -164,6 +169,8 @@ compatible = "qcom,kryo385"; reg = <0x0 0x300>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; next-level-cache = <&L2_300>; @@ -178,6 +185,8 @@ compatible = "qcom,kryo385"; reg = <0x0 0x400>; enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; next-level-cache = <&L2_400>; @@ -192,6 +201,8 @@ compatible = "qcom,kryo385"; reg = <0x0 0x500>; enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; next-level-cache = <&L2_500>; @@ -206,6 +217,8 @@ compatible = "qcom,kryo385"; reg = <0x0 0x600>; enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; next-level-cache = <&L2_600>; @@ -220,6 +233,8 @@ compatible = "qcom,kryo385"; reg = <0x0 0x700>; enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; next-level-cache = <&L2_700>; @@ -228,6 +243,60 @@ next-level-cache = <&L3_0>; }; }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-power-down"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <350>; + exit-latency-us = <461>; + min-residency-us = <1890>; + local-timer-stop; + }; + + LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { + compatible = "arm,idle-state"; + idle-state-name = "little-rail-power-down"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <360>; + exit-latency-us = <531>; + min-residency-us = <3934>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-power-down"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <264>; + exit-latency-us = <621>; + min-residency-us = <952>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_1: cpu-sleep-1-1 { + compatible = "arm,idle-state"; + idle-state-name = "big-rail-power-down"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <1061>; + min-residency-us = <4488>; + local-timer-stop; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "cluster-power-down"; + arm,psci-suspend-param = <0x400000F4>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9987>; + local-timer-stop; + }; + }; }; pmu { From patchwork Tue May 21 09:35:19 2019 Content-Type: text/plain; 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Tue, 21 May 2019 02:35:55 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, agross@kernel.org, niklas.cassel@linaro.org, marc.w.gonzalez@free.fr, sibis@codeaurora.org, daniel.lezcano@linaro.org, Andy Gross , David Brown , Li Yang , Shawn Guo Cc: devicetree@vger.kernel.org Subject: [PATCH v2 9/9] arm64: dts: msm8996: Add proper capacity scaling for the cpus Date: Tue, 21 May 2019 15:05:19 +0530 Message-Id: <5224535a7ef5b257e3baa698991bf6deeefccc36.1558430617.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement the same microarchitecture and the two clusters only differ in the maximum frequency attainable by the CPUs. Add capacity-dmips-mhz property to allow the topology code to determine the actual capacity by taking into account the highest frequency for each CPU. Signed-off-by: Amit Kucheria Suggested-by: Daniel Lezcano Acked-by: Daniel Lezcano --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 4f2fb7885f39..e0e8f30ce11a 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -96,6 +96,7 @@ reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + capacity-dmips-mhz = <1024>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; @@ -109,6 +110,7 @@ reg = <0x0 0x1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + capacity-dmips-mhz = <1024>; next-level-cache = <&L2_0>; }; @@ -118,6 +120,7 @@ reg = <0x0 0x100>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "cache"; @@ -131,6 +134,7 @@ reg = <0x0 0x101>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; };