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bh=GvIkFSS6zYb3I2dgFnSydPQ6jC4jn1KdG+v4VePYDQk=; b=jYole0hUprORkkheHvbEahpMQbHBAQ1Tc690+jqF3s0PH2v18bhl0HaJVLyMlz2LPq 7TkQKt632MEeyerKB2AVXQ5UusRJTEjuF89cH9fXuyRTkYy9e6/G3DUx5GTAAi3Isvf7 pzRZmrXJ3AdI0MWm7T2Gnb0jH+r93aSP5It/ycMtuY8vX1qrVY9NqW2VYpRVw8XapPHN X9B8Yj/h6GlW3cBKkjE0fyZ52llPtu63vYtyqm4CGDCCZTvGWc2AgHJfCIItp46oM3Xj vfhzZec2HfQK7DX3Uzu3dT9eamNEqeEwMHdCu52FGuZaFsq+zOuq+VaH+Y6Cu5+cj7XI X8kQ== X-Gm-Message-State: APjAAAVked7A/ZvB6EybxPWGt/yDjqMZ6HKgzLZN5r+XyftuScT/SCYr ivIP5c40qzCWoCWE0lAmhCM= X-Google-Smtp-Source: APXvYqzU0QjvBVCx0ssrUfq8kLh4g1PKTBBj2qaRjGJOAuYeog+j57yeoXYuz55utK4trv6oBJIKWw== X-Received: by 2002:a63:8ac3:: with SMTP id y186mr3590817pgd.22.1559221124817; Thu, 30 May 2019 05:58:44 -0700 (PDT) Received: from localhost.localdomain ([45.114.62.35]) by smtp.gmail.com with ESMTPSA id j13sm2928912pfh.13.2019.05.30.05.58.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 May 2019 05:58:44 -0700 (PDT) From: Anand Moon To: Rob Herring , Heiko Stuebner , Ezequiel Garcia , Manivannan Sadhasivam , Jagan Teki , Enric Balletbo i Serra Subject: [PATCH] arm64: dts: rockchip: Add missing PCIe pwr amd rst configuration Date: Thu, 30 May 2019 12:58:37 +0000 Message-Id: <20190530125837.730-1-linux.amoon@gmail.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190530_055846_367584_DE0D8B09 X-CRM114-Status: GOOD ( 12.96 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch add missing PCIe gpio and pinctrl for power (#PCIE_PWR) also add PCIe gpio and pinctrl for reset (#PCIE_PERST_L). Signed-off-by: Anand Moon --- Tested on Rock960 Model A --- arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi index c7d48d41e184..f5bef6b0fe89 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi @@ -55,9 +55,10 @@ vcc3v3_pcie: vcc3v3-pcie-regulator { compatible = "regulator-fixed"; + gpio = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; - pinctrl-0 = <&pcie_drv>; + pinctrl-0 = <&pcie_drv &pcie_pwr>; regulator-boot-on; regulator-name = "vcc3v3_pcie"; regulator-min-microvolt = <3300000>; @@ -381,9 +382,10 @@ }; &pcie0 { + ep-gpio = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; num-lanes = <4>; pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>; + pinctrl-0 = <&pcie_clkreqn_cpm &pcie_perst_l>; vpcie3v3-supply = <&vcc3v3_pcie>; status = "okay"; }; @@ -408,6 +410,16 @@ }; }; + pcie { + pcie_pwr: pcie-pwr { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_perst_l:pcie-perst-l { + rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sdmmc { sdmmc_bus1: sdmmc-bus1 { rockchip,pins =