From patchwork Tue Jun 4 20:09:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 10976109 X-Patchwork-Delegate: horms@verge.net.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 53A8214E5 for ; Tue, 4 Jun 2019 21:03:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 433F5288CF for ; Tue, 4 Jun 2019 21:03:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 378202855A; Tue, 4 Jun 2019 21:03:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BAA61288CF for ; Tue, 4 Jun 2019 21:03:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726354AbfFDVDB (ORCPT ); Tue, 4 Jun 2019 17:03:01 -0400 Received: from pbmsgap01.intersil.com ([192.157.179.201]:57642 "EHLO pbmsgap01.intersil.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726033AbfFDVDB (ORCPT ); Tue, 4 Jun 2019 17:03:01 -0400 X-Greylist: delayed 3197 seconds by postgrey-1.27 at vger.kernel.org; Tue, 04 Jun 2019 17:03:00 EDT Received: from pps.filterd (pbmsgap01.intersil.com [127.0.0.1]) by pbmsgap01.intersil.com (8.16.0.27/8.16.0.27) with SMTP id x54K2npv012444; Tue, 4 Jun 2019 16:09:35 -0400 Received: from pbmxdp03.intersil.corp (pbmxdp03.pb.intersil.com [132.158.200.224]) by pbmsgap01.intersil.com with ESMTP id 2sumvxtqpe-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 04 Jun 2019 16:09:35 -0400 Received: from pbmxdp02.intersil.corp (132.158.200.223) by pbmxdp03.intersil.corp (132.158.200.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.1531.3; Tue, 4 Jun 2019 16:09:34 -0400 Received: from localhost.localdomain (132.158.202.108) by pbmxdp02.intersil.corp (132.158.200.223) with Microsoft SMTP Server id 15.1.1531.3 via Frontend Transport; Tue, 4 Jun 2019 16:09:33 -0400 From: Chris Brandt To: Simon Horman , Rob Herring , "Mark Rutland" CC: Geert Uytterhoeven , , , Chris Brandt Subject: [PATCH 1/2] ARM: dts: r7s9210: Add IRQC device node Date: Tue, 4 Jun 2019 15:09:13 -0500 Message-ID: <20190604200914.64896-2-chris.brandt@renesas.com> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20190604200914.64896-1-chris.brandt@renesas.com> References: <20190604200914.64896-1-chris.brandt@renesas.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-06-04_12:,, signatures=0 X-Proofpoint-Spam-Details: rule=junk_notspam policy=junk score=0 suspectscore=2 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=786 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1906040127 X-Proofpoint-Spam-Reason: mlx Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Enable support for the IRQC on RZ/A2M, which is a small front-end to the GIC. This allows to use up to 8 external interrupts with configurable sense select. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r7s9210.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi index 3d0bbc1f4543..72b79770e336 100644 --- a/arch/arm/boot/dts/r7s9210.dtsi +++ b/arch/arm/boot/dts/r7s9210.dtsi @@ -473,6 +473,25 @@ reg = <0xfcfe8004 4>; }; + irqc: interrupt-controller@fcfef800 { + compatible = "renesas,r7s9210-irqc", + "renesas,rza1-irqc"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0xfcfef800 0x6>; + interrupt-map = + <0 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <7 0>; + }; + pinctrl: pin-controller@fcffe000 { compatible = "renesas,r7s9210-pinctrl"; reg = <0xfcffe000 0x1000>; From patchwork Tue Jun 4 20:09:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 10976017 X-Patchwork-Delegate: horms@verge.net.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 82BEA76 for ; Tue, 4 Jun 2019 20:34:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 730EC28641 for ; Tue, 4 Jun 2019 20:34:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 657E1288D9; Tue, 4 Jun 2019 20:34:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7296E286B9 for ; Tue, 4 Jun 2019 20:34:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726343AbfFDUeB (ORCPT ); Tue, 4 Jun 2019 16:34:01 -0400 Received: from pbmsgap02.intersil.com ([192.157.179.202]:60246 "EHLO pbmsgap02.intersil.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726301AbfFDUeA (ORCPT ); Tue, 4 Jun 2019 16:34:00 -0400 Received: from pps.filterd (pbmsgap02.intersil.com [127.0.0.1]) by pbmsgap02.intersil.com (8.16.0.27/8.16.0.27) with SMTP id x54K3xZq017262; Tue, 4 Jun 2019 16:09:44 -0400 Received: from pbmxdp01.intersil.corp (pbmxdp01.pb.intersil.com [132.158.200.222]) by pbmsgap02.intersil.com with ESMTP id 2sukhdjn3m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 04 Jun 2019 16:09:44 -0400 Received: from pbmxdp02.intersil.corp (132.158.200.223) by pbmxdp01.intersil.corp (132.158.200.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.1531.3; Tue, 4 Jun 2019 16:09:43 -0400 Received: from localhost.localdomain (132.158.202.108) by pbmxdp02.intersil.corp (132.158.200.223) with Microsoft SMTP Server id 15.1.1531.3 via Frontend Transport; Tue, 4 Jun 2019 16:09:42 -0400 From: Chris Brandt To: Simon Horman , Rob Herring , "Mark Rutland" CC: Geert Uytterhoeven , , , Chris Brandt Subject: [PATCH 2/2] ARM: dts: rza2mevb: Add input switch Date: Tue, 4 Jun 2019 15:09:14 -0500 Message-ID: <20190604200914.64896-3-chris.brandt@renesas.com> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20190604200914.64896-1-chris.brandt@renesas.com> References: <20190604200914.64896-1-chris.brandt@renesas.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-06-04_12:,, signatures=0 X-Proofpoint-Spam-Details: rule=junk_notspam policy=junk score=0 suspectscore=2 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=785 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1906040127 X-Proofpoint-Spam-Reason: mlx Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for input switch SW3 on the Renesas RZ/A2M EVB development board. Note that this uses the IRQ interrupt, as the RZ/A2 GPIO controller does not include interrupt support Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s9210-rza2mevb.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts index 4baf4a965090..6049145c120c 100644 --- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts +++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts @@ -9,6 +9,7 @@ /dts-v1/; #include "r7s9210.dtsi" #include +#include #include / { @@ -26,6 +27,21 @@ stdout-path = "serial0:115200n8"; }; + keyboard { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&keyboard_pins>; + + key-3 { + interrupt-parent = <&irqc>; + interrupts = <0 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + label = "SW3"; + wakeup-source; + }; + }; + lbsc { #address-cells = <1>; #size-cells = <1>; @@ -121,6 +137,10 @@ ; /* IRQ5 */ }; + keyboard_pins: keyboard { + pinmux = ; /* IRQ0 */ + }; + /* Serial Console */ scif4_pins: serial4 { pinmux = , /* TxD4 */