From patchwork Wed Jun 5 21:08:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 10977907 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D5BAC1398 for ; Wed, 5 Jun 2019 21:09:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C1FC5289AA for ; Wed, 5 Jun 2019 21:09:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B656D2854F; Wed, 5 Jun 2019 21:09:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 41DE5289AA for ; Wed, 5 Jun 2019 21:09:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=yCmazEGs3tUJwA/InC/SSgXLhFwz7+bvWN+HG404RBI=; b=Vpqc3K/xSaIWGV4sVVajXv7RO3 bwWkXAE0GE/UyoVGrNw3ctbZmmHCaYHXncLyE231vwmYDSt2bxjdDHMmCsLU8EV9HUvo8VPZimTA8 WGShgjNSuLmfSiUOMRVFnh/7JQinMF7+zePUfHPwMzi66KrHXmPlinII8vtolKbgqJCmz8VMeB9Et CaV5vkgKV51c765xs0FZngU0/Yav0xYo7BbqwZIcAqijWjZ7RX4YVTIM5D7tvuXGvZrXJWJc+Q4Ep 8RP4rsNVxM826bYW7sGSPQKWwjE9p/o+jmHtNX5nXPuhiS0Hj87WR/07URnHs3NfkxFCvRfzW4O4D m3Uh22aw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hYd9i-0002Yx-TM; Wed, 05 Jun 2019 21:09:10 +0000 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hYd9Z-0002QZ-8W for linux-arm-kernel@lists.infradead.org; Wed, 05 Jun 2019 21:09:02 +0000 Received: by mail-pl1-x642.google.com with SMTP id f97so5869plb.5 for ; Wed, 05 Jun 2019 14:09:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=doGqQfOnbpbz6KWyxr0y6OarZe4NFnZU43MXukaW24s=; b=zsLf+GJaoDAXKa5EdGWe2FOH0F+xp5lNHW7YtXxQp3F6tZIgoxWTg4ICtQmSyMUzFS b0EGjQtzqHXwjdTw3FRh9z+9C6OYT11qsbfHgjRZPZakvHnZPBN05Qfz7+TfLQvcmfZy k8JA698NZ2o0hx24JO+WjKTiegX0rZpAXCRvblhsB/qkNq0Pyo3Fld98laxJ++tnYiDP l5VuN6NUy0XCB/5KqMOTCc9277V09UY4OBy3OnP1pl5FX2/+XCRwYGMCFJZjI4mweOty 1iAo0dUwojRJmbTkcnex3nPunwVVOrWhwSE9evn6ehy9bWiqnakAnymht15U2Vk1qBfJ tx9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=doGqQfOnbpbz6KWyxr0y6OarZe4NFnZU43MXukaW24s=; b=IkJy8HXS0yqqMX1MBAarZKcvehm4ujWbWlGj/rJ5QpmWMp4evqIiyFaLhKjF12I7PB 0Dnk2A3XrRBl4oxQSCrjMDLqH0n5/9mZDbpNst4uGg12Alq9YD7uPSOdGit8KcWDFcoN aoBpTqB72vUrxzyFXIDq9MJLQJw6jc9TIycYrX+UcCG1bTffkZHCrCU5H07Z+r+DkQ1L XXBrVsD4Qns5rGIKocVC05RvrEQ8huth1K2CHiJ9R9gRDQkAEaI2rIfqfWYku8aVcksl ildbRiDDPP9p+aDWHEQL/i2Pvlc23ylSeNffNqTbD6EAmfJsjNpiGwZ68Uqkly9P29QF W7DA== X-Gm-Message-State: APjAAAV3u5NjTxTsay5x172uEQL9a1DEReXLBQZN31CieEbQyaN3PExe byGgY493MMWDT6+IrKIyGDCJvQ== X-Google-Smtp-Source: APXvYqwoS4/fIM8nKfSXqVALkUrziDsBx5YwkF6lBl7eSp+Ql0R6Eq9xI2taS6Dvk0vFthsrEHo8CA== X-Received: by 2002:a17:902:2aab:: with SMTP id j40mr7623927plb.76.1559768940538; Wed, 05 Jun 2019 14:09:00 -0700 (PDT) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id z68sm5093374pfb.37.2019.06.05.14.08.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jun 2019 14:09:00 -0700 (PDT) From: Bjorn Andersson To: Joerg Roedel , Will Deacon , Robin Murphy Subject: [RFC 1/2] iommu: arm-smmu: Handoff SMR registers and context banks Date: Wed, 5 Jun 2019 14:08:55 -0700 Message-Id: <20190605210856.20677-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190605210856.20677-1-bjorn.andersson@linaro.org> References: <20190605210856.20677-1-bjorn.andersson@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190605_140901_304251_2CF02F03 X-CRM114-Status: GOOD ( 19.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Patrick Daly , Jeffrey Hugo , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Vivek Gautam , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Boot splash screen or EFI framebuffer requires the display hardware to operate while the Linux iommu driver probes. Therefore, we cannot simply wipe out the SMR register settings programmed by the bootloader. Detect which SMR registers are in use during probe, and which context banks they are associated with. Reserve these context banks for the first Linux device whose stream-id matches the SMR register. Any existing page-tables will be discarded. Heavily based on downstream implementation by Patrick Daly . Signed-off-by: Bjorn Andersson Reviewed-by: Jeffrey Hugo --- drivers/iommu/arm-smmu-regs.h | 2 + drivers/iommu/arm-smmu.c | 80 ++++++++++++++++++++++++++++++++--- 2 files changed, 77 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm-smmu-regs.h b/drivers/iommu/arm-smmu-regs.h index e9132a926761..8c1fd84032a2 100644 --- a/drivers/iommu/arm-smmu-regs.h +++ b/drivers/iommu/arm-smmu-regs.h @@ -105,7 +105,9 @@ #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) #define SMR_VALID (1 << 31) #define SMR_MASK_SHIFT 16 +#define SMR_MASK_MASK 0x7fff #define SMR_ID_SHIFT 0 +#define SMR_ID_MASK 0xffff #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) #define S2CR_CBNDX_SHIFT 0 diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 5e54cc0a28b3..c8629a656b42 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -135,6 +135,7 @@ struct arm_smmu_s2cr { enum arm_smmu_s2cr_type type; enum arm_smmu_s2cr_privcfg privcfg; u8 cbndx; + bool handoff; }; #define s2cr_init_val (struct arm_smmu_s2cr){ \ @@ -399,9 +400,22 @@ static int arm_smmu_register_legacy_master(struct device *dev, return err; } -static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end) +static int __arm_smmu_alloc_cb(struct arm_smmu_device *smmu, int start, + struct device *dev) { + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + unsigned long *map = smmu->context_map; + int end = smmu->num_context_banks; + int cbndx; int idx; + int i; + + for_each_cfg_sme(fwspec, i, idx) { + if (smmu->s2crs[idx].handoff) { + cbndx = smmu->s2crs[idx].cbndx; + goto found_handoff; + } + } do { idx = find_next_zero_bit(map, end, start); @@ -410,6 +424,17 @@ static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end) } while (test_and_set_bit(idx, map)); return idx; + +found_handoff: + for (i = 0; i < smmu->num_mapping_groups; i++) { + if (smmu->s2crs[i].cbndx == cbndx) { + smmu->s2crs[i].cbndx = 0; + smmu->s2crs[i].handoff = false; + smmu->s2crs[i].count--; + } + } + + return cbndx; } static void __arm_smmu_free_bitmap(unsigned long *map, int idx) @@ -759,7 +784,8 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) } static int arm_smmu_init_domain_context(struct iommu_domain *domain, - struct arm_smmu_device *smmu) + struct arm_smmu_device *smmu, + struct device *dev) { int irq, start, ret = 0; unsigned long ias, oas; @@ -873,8 +899,7 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, ret = -EINVAL; goto out_unlock; } - ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, - smmu->num_context_banks); + ret = __arm_smmu_alloc_cb(smmu, start, dev); if (ret < 0) goto out_unlock; @@ -1264,7 +1289,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) return ret; /* Ensure that the domain is finalised */ - ret = arm_smmu_init_domain_context(domain, smmu); + ret = arm_smmu_init_domain_context(domain, smmu, dev); if (ret < 0) goto rpm_put; @@ -1798,6 +1823,49 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu) writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); } +static void arm_smmu_read_smr_state(struct arm_smmu_device *smmu) +{ + u32 privcfg; + u32 cbndx; + u32 mask; + u32 type; + u32 s2cr; + u32 smr; + u32 id; + int i; + + for (i = 0; i < smmu->num_mapping_groups; i++) { + smr = readl_relaxed(ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_SMR(i)); + mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK; + id = smr & SMR_ID_MASK; + if (!(smr & SMR_VALID)) + continue; + + s2cr = readl_relaxed(ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_S2CR(i)); + type = (s2cr >> S2CR_TYPE_SHIFT) & S2CR_TYPE_MASK; + cbndx = (s2cr >> S2CR_CBNDX_SHIFT) & S2CR_CBNDX_MASK; + privcfg = (s2cr >> S2CR_PRIVCFG_SHIFT) & S2CR_PRIVCFG_MASK; + if (type != S2CR_TYPE_TRANS) + continue; + + /* Populate the SMR */ + smmu->smrs[i].mask = mask; + smmu->smrs[i].id = id; + smmu->smrs[i].valid = true; + + /* Populate the S2CR */ + smmu->s2crs[i].group = NULL; + smmu->s2crs[i].count = 1; + smmu->s2crs[i].type = type; + smmu->s2crs[i].privcfg = privcfg; + smmu->s2crs[i].cbndx = cbndx; + smmu->s2crs[i].handoff = true; + + /* Mark the context bank as busy */ + bitmap_set(smmu->context_map, cbndx, 1); + } +} + static int arm_smmu_id_size_to_bits(int size) { switch (size) { @@ -2023,6 +2091,8 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n", smmu->ipa_size, smmu->pa_size); + arm_smmu_read_smr_state(smmu); + return 0; } From patchwork Wed Jun 5 21:08:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 10977909 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 769871398 for ; Wed, 5 Jun 2019 21:09:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 65E332854F for ; Wed, 5 Jun 2019 21:09:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 58C14288E8; Wed, 5 Jun 2019 21:09:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E44CA288E4 for ; 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id z68sm5093374pfb.37.2019.06.05.14.09.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jun 2019 14:09:01 -0700 (PDT) From: Bjorn Andersson To: Joerg Roedel , Will Deacon , Robin Murphy Subject: [RFC 2/2] iommu: arm-smmu: Don't blindly use first SMR to calculate mask Date: Wed, 5 Jun 2019 14:08:56 -0700 Message-Id: <20190605210856.20677-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190605210856.20677-1-bjorn.andersson@linaro.org> References: <20190605210856.20677-1-bjorn.andersson@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190605_140902_604226_0F64F594 X-CRM114-Status: GOOD ( 14.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Patrick Daly , Jeffrey Hugo , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Vivek Gautam , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP With the SMRs inherited from the bootloader the first SMR might actually be valid and in use. As such probing the SMR mask using the first SMR might break a stream in use. Search for an unused stream and use this to probe the SMR mask. Signed-off-by: Bjorn Andersson Reviewed-by: Jeffrey Hugo --- drivers/iommu/arm-smmu.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index c8629a656b42..0c6f5fe6f382 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1084,23 +1084,35 @@ static void arm_smmu_test_smr_masks(struct arm_smmu_device *smmu) { void __iomem *gr0_base = ARM_SMMU_GR0(smmu); u32 smr; + int idx; if (!smmu->smrs) return; + for (idx = 0; idx < smmu->num_mapping_groups; idx++) { + smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(idx)); + if (!(smr & SMR_VALID)) + break; + } + + if (idx == smmu->num_mapping_groups) { + dev_err(smmu->dev, "Unable to compute streamid_mask\n"); + return; + } + /* * SMR.ID bits may not be preserved if the corresponding MASK * bits are set, so check each one separately. We can reject * masters later if they try to claim IDs outside these masks. */ smr = smmu->streamid_mask << SMR_ID_SHIFT; - writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0)); - smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0)); + writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(idx)); + smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(idx)); smmu->streamid_mask = smr >> SMR_ID_SHIFT; smr = smmu->streamid_mask << SMR_MASK_SHIFT; - writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0)); - smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0)); + writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(idx)); + smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(idx)); smmu->smr_mask_mask = smr >> SMR_MASK_SHIFT; }