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Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR02MB2682 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190611_025719_549695_3DC217E8 X-CRM114-Status: GOOD ( 14.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add API for setting SDIO Tap Delays on ZynqMP platforms. Signed-off-by: Manish Narani --- drivers/firmware/xilinx/zynqmp.c | 32 ++++++++++++++++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 17 ++++++++++++++++- 2 files changed, 48 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index fd3d837..c6f9e72 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -664,6 +664,37 @@ static int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, qos, ack, NULL); } +/** + * zynqmp_pm_sdio_setphase() - PM call to set clock delays for SD clock + * @device_id: Device ID of the SD controller + * @degrees: Tap Delay value in degrees for Input/Output clocks + * + * This API function is to be used for setting the clock delays for SD + * clock. + * + * Return: Returns status, either success or error+reason + */ +static int zynqmp_pm_sdio_setphase(u32 device_id, int degrees) +{ + u32 node_id = (!device_id) ? NODE_SD_0 : NODE_SD_1; + enum tap_delay_type tap_type; + int ret; + + if (degrees < INPUT_TAP_BOUNDARY) { + tap_type = PM_TAPDELAY_INPUT; + } else { + tap_type = PM_TAPDELAY_OUTPUT; + degrees -= INPUT_TAP_BOUNDARY; + } + + ret = zynqmp_pm_ioctl(node_id, IOCTL_SET_SD_TAPDELAY, tap_type, + degrees, NULL); + if (ret) + pr_err("Error setting Tap Delay\n"); + + return ret; +} + static const struct zynqmp_eemi_ops eemi_ops = { .get_api_version = zynqmp_pm_get_api_version, .get_chipid = zynqmp_pm_get_chipid, @@ -687,6 +718,7 @@ static const struct zynqmp_eemi_ops eemi_ops = { .set_requirement = zynqmp_pm_set_requirement, .fpga_load = zynqmp_pm_fpga_load, .fpga_get_status = zynqmp_pm_fpga_get_status, + .sdio_setphase = zynqmp_pm_sdio_setphase, }; /** diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 1262ea6..0fc4bf7 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -56,6 +56,9 @@ #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0) +/* Input Tap Delay Boundary Value */ +#define INPUT_TAP_BOUNDARY 0x100 + enum pm_api_id { PM_GET_API_VERSION = 1, PM_REQUEST_NODE = 13, @@ -92,7 +95,8 @@ enum pm_ret_status { }; enum pm_ioctl_id { - IOCTL_SET_PLL_FRAC_MODE = 8, + IOCTL_SET_SD_TAPDELAY = 7, + IOCTL_SET_PLL_FRAC_MODE, IOCTL_GET_PLL_FRAC_MODE, IOCTL_SET_PLL_FRAC_DATA, IOCTL_GET_PLL_FRAC_DATA, @@ -251,6 +255,16 @@ enum zynqmp_pm_request_ack { ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING, }; +enum pm_node_id { + NODE_SD_0 = 39, + NODE_SD_1, +}; + +enum tap_delay_type { + PM_TAPDELAY_INPUT = 0, + PM_TAPDELAY_OUTPUT, +}; + /** * struct zynqmp_pm_query_data - PM query data * @qid: query ID @@ -295,6 +309,7 @@ struct zynqmp_eemi_ops { const u32 capabilities, const u32 qos, const enum zynqmp_pm_request_ack ack); + int (*sdio_setphase)(u32 device_id, int degrees); }; int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1, From patchwork Tue Jun 11 09:56:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manish Narani X-Patchwork-Id: 10986353 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 437951515 for ; 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Tue, 11 Jun 2019 02:57:01 -0700 Received: from [172.23.64.106] (helo=xhdvnc125.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1hadWX-0002S9-3R; Tue, 11 Jun 2019 02:57:01 -0700 Received: by xhdvnc125.xilinx.com (Postfix, from userid 16987) id 49D08121745; Tue, 11 Jun 2019 15:27:00 +0530 (IST) From: Manish Narani To: ulf.hansson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, michal.simek@xilinx.com, adrian.hunter@intel.com, rajan.vaja@xilinx.com, jolly.shah@xilinx.com, nava.manne@xilinx.com, manish.narani@xilinx.com, olof@lixom.net Subject: [PATCH 2/3] dt-bindings: mmc: arasan: Document 'xlnx, zynqmp-8.9a' controller Date: Tue, 11 Jun 2019 15:26:50 +0530 Message-Id: <1560247011-26369-3-git-send-email-manish.narani@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1560247011-26369-1-git-send-email-manish.narani@xilinx.com> References: <1560247011-26369-1-git-send-email-manish.narani@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.100; 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Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB4939 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190611_025719_580606_9638425F X-CRM114-Status: GOOD ( 11.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add documentation for 'xlnx,zynqmp-8.9a' SDHCI controller and optional properties followed by example. Signed-off-by: Manish Narani --- .../devicetree/bindings/mmc/arasan,sdhci.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt index 1edbb04..6945b3b 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt @@ -15,6 +15,9 @@ Required Properties: - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY For this device it is strongly suggested to include arasan,soc-ctl-syscon. + - "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY + For this device it is strongly suggested to include clock-output-names and + #clock-cells. - "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY Note: This binding has been deprecated and moved to [5]. @@ -45,6 +48,24 @@ Optional Properties: - xlnx,int-clock-stable-broken: when present, the controller always reports that the internal clock is stable even when it is not. +Optional Properties for "xlnx,zynqmp-8.9a": + - xlnx,tap-delay-mmc-hsd: Input/Output Tap Delays in degrees for MMC HS. + - xlnx,tap-delay-sd-hsd: Input/Output Tap Delays in degrees for SD HS. + - xlnx,tap-delay-sdr25: Input/Output Tap Delays in degrees for SDR25. + - xlnx,tap-delay-sdr50: Input/Output Tap Delays in degrees for SDR50. + - xlnx,tap-delay-sdr104: Input/Output Tap Delays in degrees for SDR104. + - xlnx,tap-delay-sd-ddr50: Input/Output Tap Delays in degrees for SD DDR50. + - xlnx,tap-delay-mmc-ddr52: Input/Output Tap Delays in degrees for MMC DDR52. + - xlnx,tap-delay-mmc-hs200: Input/Output Tap Delays in degrees for MMC HS200. + + Above mentioned are the clock (phase) delays which are to be configured in the + controller while switching to particular speed mode. If not specified, driver + will configure the default value defined for particular mode in it. + + - xlnx,mio-bank: When specified, this will indicate the MIO bank number in + which the command and data lines are configured. If not specified, driver + will assume this as 0. + Example: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; @@ -80,3 +101,14 @@ Example: phy-names = "phy_arasan"; #clock-cells = <0>; }; + + sdhci: mmc@ff160000 { + compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; + interrupt-parent = <&gic>; + interrupts = <0 48 4>; + reg = <0x0 0xff160000 0x0 0x1000>; + clock-names = "clk_xin", "clk_ahb"; + clock-output-names = "clk_sd0"; + #clock-cells = <0>; + xlnx,tap-delay-sd-hsd = <21>, <6>; + }; From patchwork Tue Jun 11 09:56:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manish Narani X-Patchwork-Id: 10986371 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 95DFC1515 for ; Tue, 11 Jun 2019 09:58:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8224528066 for ; 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Tue, 11 Jun 2019 02:57:02 -0700 Received: from [172.23.64.106] (helo=xhdvnc125.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1hadWY-0002TF-1c; Tue, 11 Jun 2019 02:57:02 -0700 Received: by xhdvnc125.xilinx.com (Postfix, from userid 16987) id 3FE5212174A; Tue, 11 Jun 2019 15:27:01 +0530 (IST) From: Manish Narani To: ulf.hansson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, michal.simek@xilinx.com, adrian.hunter@intel.com, rajan.vaja@xilinx.com, jolly.shah@xilinx.com, nava.manne@xilinx.com, manish.narani@xilinx.com, olof@lixom.net Subject: [PATCH 3/3] mmc: sdhci-of-arasan: Add support for ZynqMP Platform Tap Delays Setup Date: Tue, 11 Jun 2019 15:26:51 +0530 Message-Id: <1560247011-26369-4-git-send-email-manish.narani@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1560247011-26369-1-git-send-email-manish.narani@xilinx.com> References: <1560247011-26369-1-git-send-email-manish.narani@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; 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Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR02MB4931 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190611_025720_484270_4976D528 X-CRM114-Status: GOOD ( 22.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Apart from taps set by auto tuning, ZynqMP platform has feature to set the tap values manually. Add support to read tap delay values from DT and set the same in HW via ZynqMP SoC framework. Reading Tap Delays from DT is optional, if the property is not available in DT the driver will use the pre-defined Tap Delay Values. Signed-off-by: Manish Narani Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-of-arasan.c | 173 ++++++++++++++++++++++++++++++++++++- 1 file changed, 172 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index b12abf9..7af6cec 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "cqhci.h" #include "sdhci-pltfm.h" @@ -32,6 +33,10 @@ #define PHY_CLK_TOO_SLOW_HZ 400000 +/* Default settings for ZynqMP Tap Delays */ +#define ZYNQMP_ITAP_DELAYS {0, 0x15, 0x15, 0, 0x15, 0, 0, 0x3D, 0x12, 0, 0} +#define ZYNQMP_OTAP_DELAYS {0, 0x5, 0x6, 0, 0x5, 0x3, 0x3, 0x4, 0x6, 0x3, 0} + /* * On some SoCs the syscon area has a feature where the upper 16-bits of * each 32-bit register act as a write mask for the lower 16-bits. This allows @@ -81,6 +86,7 @@ struct sdhci_arasan_soc_ctl_map { * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw. * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers. * @soc_ctl_map: Map to get offsets into soc_ctl registers. + * @of_data: Platform specific runtime data storage pointer */ struct sdhci_arasan_data { struct sdhci_host *host; @@ -101,6 +107,15 @@ struct sdhci_arasan_data { /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the * internal clock even when the clock isn't stable */ #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1) + + void *of_data; +}; + +struct sdhci_arasan_zynqmp_data { + void (*set_tap_delay)(struct sdhci_host *host); + const struct zynqmp_eemi_ops *eemi_ops; + u8 tapdly[MMC_TIMING_MMC_HS400 + 1][2]; /* [0] for input delay, */ + /* [1] for output delay */ }; struct sdhci_arasan_of_data { @@ -209,6 +224,16 @@ static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) sdhci_arasan->is_phy_on = false; } + /* Set the Input and Output Tap Delays */ + if (host->version >= SDHCI_SPEC_300 && + host->timing != MMC_TIMING_LEGACY && + host->timing != MMC_TIMING_UHS_SDR12) { + struct sdhci_arasan_zynqmp_data *zynqmp_data = + sdhci_arasan->of_data; + if (zynqmp_data && zynqmp_data->set_tap_delay) + zynqmp_data->set_tap_delay(host); + } + sdhci_set_clock(host, clock); if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE) @@ -487,6 +512,10 @@ static const struct of_device_id sdhci_arasan_of_match[] = { .compatible = "arasan,sdhci-4.9a", .data = &sdhci_arasan_data, }, + { + .compatible = "xlnx,zynqmp-8.9a", + .data = &sdhci_arasan_data, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match); @@ -517,6 +546,37 @@ static const struct clk_ops arasan_sdcardclk_ops = { }; /** + * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Clock Tap Delays + * + * Set the SD Clock Tap Delays for Input and Output paths + * + * @hw: Pointer to the hardware clock structure. + * @degrees The clock phase shift between 0 - 359. + * Return: 0 on success and error value on error + */ +static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees) + +{ + struct sdhci_arasan_data *sdhci_arasan = + container_of(hw, struct sdhci_arasan_data, sdcardclk_hw); + struct sdhci_arasan_zynqmp_data *zynqmp_data = sdhci_arasan->of_data; + const struct zynqmp_eemi_ops *eemi_ops = zynqmp_data->eemi_ops; + const char *clk_name = clk_hw_get_name(hw); + u32 device_id = !strcmp(clk_name, "clk_sd0") ? 0 : 1; + + if (!eemi_ops->sdio_setphase) + return -ENODEV; + + /* Set the Clock Phase */ + return eemi_ops->sdio_setphase(device_id, degrees); +} + +static const struct clk_ops zynqmp_sdcardclk_ops = { + .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, + .set_phase = sdhci_zynqmp_sdcardclk_set_phase, +}; + +/** * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier * * The corecfg_clockmultiplier is supposed to contain clock multiplier @@ -638,7 +698,10 @@ static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, sdcardclk_init.parent_names = &parent_clk_name; sdcardclk_init.num_parents = 1; sdcardclk_init.flags = CLK_GET_RATE_NOCACHE; - sdcardclk_init.ops = &arasan_sdcardclk_ops; + if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) + sdcardclk_init.ops = &zynqmp_sdcardclk_ops; + else + sdcardclk_init.ops = &arasan_sdcardclk_ops; sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init; sdhci_arasan->sdcardclk = @@ -714,6 +777,108 @@ static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan) return ret; } +static void sdhci_arasan_zynqmp_set_tap_delay(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); + struct sdhci_arasan_zynqmp_data *zynqmp_data = sdhci_arasan->of_data; + + clk_set_phase(sdhci_arasan->sdcardclk, + (int)zynqmp_data->tapdly[host->timing][0]); + clk_set_phase(sdhci_arasan->sdcardclk, + (int)zynqmp_data->tapdly[host->timing][1] + + INPUT_TAP_BOUNDARY); +} + +static void arasan_dt_read_tap_delay(struct device *dev, u8 *tapdly, + const char *prop, u8 itap_def, u8 otap_def) +{ + struct device_node *np = dev->of_node; + + tapdly[0] = itap_def; + tapdly[1] = otap_def; + + /* + * Read Tap Delay values from DT, if the DT does not contain the + * Tap Values then use the pre-defined values. + */ + if (of_property_read_variable_u8_array(np, prop, &tapdly[0], 2, 0)) { + dev_dbg(dev, "Using predefined tapdly for %s = %d %d\n", + prop, tapdly[0], tapdly[1]); + } +} + +/** + * arasan_dt_parse_tap_delays - Read Tap Delay values from DT + * + * Called at initialization to parse the values of Tap Delays. + * + * @dev: Pointer to our struct device. + */ +static int arasan_dt_parse_tap_delays(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct sdhci_host *host = platform_get_drvdata(pdev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); + struct sdhci_arasan_zynqmp_data zynqmp_data; + const struct zynqmp_eemi_ops *eemi_ops; + u8 *itapdly, *otapdly; + u32 mio_bank = 0; + + eemi_ops = zynqmp_pm_get_eemi_ops(); + if (IS_ERR(eemi_ops)) + return PTR_ERR(eemi_ops); + + itapdly = (u8 [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_ITAP_DELAYS; + otapdly = (u8 [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_OTAP_DELAYS; + + of_property_read_u32(pdev->dev.of_node, "xlnx,mio-bank", &mio_bank); + if (mio_bank == 2) { + otapdly[MMC_TIMING_UHS_SDR104] = 0x2; + otapdly[MMC_TIMING_MMC_HS200] = 0x2; + } + + arasan_dt_read_tap_delay(dev, zynqmp_data.tapdly[MMC_TIMING_MMC_HS], + "xlnx,tap-delay-mmc-hsd", + itapdly[MMC_TIMING_MMC_HS], + otapdly[MMC_TIMING_MMC_HS]); + arasan_dt_read_tap_delay(dev, zynqmp_data.tapdly[MMC_TIMING_SD_HS], + "xlnx,tap-delay-sd-hsd", + itapdly[MMC_TIMING_SD_HS], + otapdly[MMC_TIMING_SD_HS]); + arasan_dt_read_tap_delay(dev, zynqmp_data.tapdly[MMC_TIMING_UHS_SDR25], + "xlnx,tap-delay-sdr25", + itapdly[MMC_TIMING_UHS_SDR25], + otapdly[MMC_TIMING_UHS_SDR25]); + arasan_dt_read_tap_delay(dev, zynqmp_data.tapdly[MMC_TIMING_UHS_SDR50], + "xlnx,tap-delay-sdr50", + itapdly[MMC_TIMING_UHS_SDR50], + otapdly[MMC_TIMING_UHS_SDR50]); + arasan_dt_read_tap_delay(dev, zynqmp_data.tapdly[MMC_TIMING_UHS_SDR104], + "xlnx,tap-delay-sdr104", + itapdly[MMC_TIMING_UHS_SDR104], + otapdly[MMC_TIMING_UHS_SDR104]); + arasan_dt_read_tap_delay(dev, zynqmp_data.tapdly[MMC_TIMING_UHS_DDR50], + "xlnx,tap-delay-sd-ddr50", + itapdly[MMC_TIMING_UHS_DDR50], + otapdly[MMC_TIMING_UHS_DDR50]); + arasan_dt_read_tap_delay(dev, zynqmp_data.tapdly[MMC_TIMING_MMC_DDR52], + "xlnx,tap-delay-mmc-ddr52", + itapdly[MMC_TIMING_MMC_DDR52], + otapdly[MMC_TIMING_MMC_DDR52]); + arasan_dt_read_tap_delay(dev, zynqmp_data.tapdly[MMC_TIMING_MMC_HS200], + "xlnx,tap-delay-mmc-hs200", + itapdly[MMC_TIMING_MMC_HS200], + otapdly[MMC_TIMING_MMC_HS200]); + + zynqmp_data.set_tap_delay = sdhci_arasan_zynqmp_set_tap_delay; + zynqmp_data.eemi_ops = eemi_ops; + sdhci_arasan->of_data = &zynqmp_data; + + return 0; +} + static int sdhci_arasan_probe(struct platform_device *pdev) { int ret; @@ -806,6 +971,12 @@ static int sdhci_arasan_probe(struct platform_device *pdev) goto unreg_clk; } + if (of_device_is_compatible(pdev->dev.of_node, "xlnx,zynqmp-8.9a")) { + ret = arasan_dt_parse_tap_delays(&pdev->dev); + if (ret) + goto unreg_clk; + } + sdhci_arasan->phy = ERR_PTR(-ENODEV); if (of_device_is_compatible(pdev->dev.of_node, "arasan,sdhci-5.1")) {