From patchwork Mon Jun 17 18:37:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeffrey Hugo X-Patchwork-Id: 11000083 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 049A8112C for ; Mon, 17 Jun 2019 18:37:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EDD01286F6 for ; Mon, 17 Jun 2019 18:37:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E06CB289B9; Mon, 17 Jun 2019 18:37:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7951B286F6 for ; Mon, 17 Jun 2019 18:37:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726048AbfFQShV (ORCPT ); Mon, 17 Jun 2019 14:37:21 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:35257 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725844AbfFQShU (ORCPT ); Mon, 17 Jun 2019 14:37:20 -0400 Received: by mail-pl1-f196.google.com with SMTP id p1so4458099plo.2; Mon, 17 Jun 2019 11:37:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pNCtTqN2On7Akbg5ZQ6dO9GyNd+lckTzvjUJWbNQ7ao=; b=cppmxtv9KfPrFVS95mmdcAGwbghcR3q6HELiPCXGP8Llbz0uz+dI47v2tmK9Qx4gdU zqCN4+FGJGDFikhXAypa+pATh/nhdG4MPNcgFrsRrPP7V+1sbT3ir6xcZPQayCXs/hKY g8fAkV2RoXJ3xGTd+e9ZUGHF3b6ExdaYW9YBBpiYSBxnzxztxoMJqRoWIIyszlzLTWuv eRQMHGBP0slbR44LyHnGbslcvvcYdmlH9p5NyIbFRfB3opNKI5MuOYTWTLMkpxwfRYbV LXAuJPxE6yk8Gj+UibeeQqCKxNDQyDif7taRrXJM0PxldzCk+vtdOuzaRI+fU1XE3ciY 9eew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pNCtTqN2On7Akbg5ZQ6dO9GyNd+lckTzvjUJWbNQ7ao=; b=n7RI/ufTnlnkNxNmNteS7I/lvXvPL1KUeiewjwGTaJRHEpV5c9t0bg298v1GHYb9su Ce8JoUqLxASMXhgiZWTmdOLhm0EkSMyB4t1D76AKRoPDdgicjSLLUzYFDrCW3o3sFO3E p0qGH9hB5mrX1xUxoDIX8ar64/EJRsEVSmcGFl2pCdKotMcC2UWpuHJxB2zXLYZbHjFB T6SDB//UNuOpdvk95LIlvhm/PDWYgOzA3SUKSDv7TuAcJnDAhfmvL++Y1LIUOgIbpnt/ HFI6EyBBK0ebBs17UAmKjRwbY6GQoYx25Lq2D7CB92d05JvX2tzA8SvviCeEY1jP8rVG 45dw== X-Gm-Message-State: APjAAAVD5M/1ENnIAjEJEsaWqQ+b5Xx6++iZk3fCoqHmxAT2wRW9YvvZ Vbg+Q+5Ya+GSbJAeYXo5qbk= X-Google-Smtp-Source: APXvYqyRIRHg6gMGrA70ZHt12EDv2nOd2Sc+DfCdHhHcq35f5zXe8FA2xvVho+l5pWCImt4YiDrGCA== X-Received: by 2002:a17:902:7b84:: with SMTP id w4mr813896pll.22.1560796640235; Mon, 17 Jun 2019 11:37:20 -0700 (PDT) Received: from aw-bldr-10.qualcomm.com (i-global254.qualcomm.com. [199.106.103.254]) by smtp.gmail.com with ESMTPSA id j14sm12832230pfn.120.2019.06.17.11.37.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 11:37:19 -0700 (PDT) From: Jeffrey Hugo To: lgirdwood@gmail.com, broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jeffrey Hugo Subject: [PATCH v5 1/5] dt-bindings: qcom_spmi: Document PM8005 regulators Date: Mon, 17 Jun 2019 11:37:16 -0700 Message-Id: <20190617183716.13501-1-jeffrey.l.hugo@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190617183643.13449-1-jeffrey.l.hugo@gmail.com> References: <20190617183643.13449-1-jeffrey.l.hugo@gmail.com> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Document the dt bindings for the PM8005 regulators which are usually used for VDD of standalone blocks on a SoC like the GPU. Signed-off-by: Jeffrey Hugo Reviewed-by: Bjorn Andersson --- .../devicetree/bindings/regulator/qcom,spmi-regulator.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt index 406f2e570c50..ba94bc2d407a 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt @@ -4,6 +4,7 @@ Qualcomm SPMI Regulators Usage: required Value type: Definition: must be one of: + "qcom,pm8005-regulators" "qcom,pm8841-regulators" "qcom,pm8916-regulators" "qcom,pm8941-regulators" @@ -120,6 +121,9 @@ The regulator node houses sub-nodes for each regulator within the device. Each sub-node is identified using the node's name, with valid values listed for each of the PMICs below. +pm8005: + s1, s2, s3, s4 + pm8841: s1, s2, s3, s4, s5, s6, s7, s8 From patchwork Mon Jun 17 18:37:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeffrey Hugo X-Patchwork-Id: 11000085 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D49B014DB for ; Mon, 17 Jun 2019 18:37:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C8C8F286F6 for ; Mon, 17 Jun 2019 18:37:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BC7EF289B9; Mon, 17 Jun 2019 18:37:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E66CD286F6 for ; Mon, 17 Jun 2019 18:37:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726996AbfFQShe (ORCPT ); Mon, 17 Jun 2019 14:37:34 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:46854 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725844AbfFQShd (ORCPT ); Mon, 17 Jun 2019 14:37:33 -0400 Received: by mail-pl1-f193.google.com with SMTP id e5so4434885pls.13; Mon, 17 Jun 2019 11:37:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CQof8F1xhz+F1ATPwPiy1QiO7IM8neuAEGxxMl2Ks3I=; b=N7SCY0+ii8ywOexLGjFWPsUZEEOH07JrYLRyl8BlrHMhazFuB3fBYseJLWgO10BdIb R5rJ1g/NUsmcY+BU8s7d6pp9eeyu6nxjhg5pG3safyTQSMzkzI4WPxjHchYwlehKxP1/ Ym1adYlbQCFXvnpVTUm/gCgzZo/ekucMyn/3avpVv2EsQaRjdqHc53U0+vSTs02Yp+rN XIt9uSH8nS9UNgVZCetJlLl2kjIrER0oSMgFfZhvi/YKdQoIjtWgYyV4mwaC8IE9S+Hg DmEMlGf5zA6Xv9+QYep4UXR4fsbBmrxDCdhtvl41aCMZaLoHwMXBOZ1zJ3JAtMw2vZ1A K1nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CQof8F1xhz+F1ATPwPiy1QiO7IM8neuAEGxxMl2Ks3I=; b=irqBta9TXuT9RTUNOF+1j9pz1cnw5md0kunV3hkR+QAhm++h6Fcwsp/X66a6i9CwZj DZmk/ygoVg/WMgs3QPT++5P2qNl0/tZ5IwzxTYmt64mIJmvjEaj4yQ3L9Q9WhPQUGFnV CZlFEBkSRwuGDx+UjRxrHXHkEozJ7SQIz7G1VngysPhvGSgWZ/ZcYzV6tkHzLfhJDsIh U5pWzD0WoQIkrhCxEk2OTBcTNI3CQjzUsRHEF0ST+9Qn+i9fE/jDQQ9UaX5KXVH2KhKW J7KsiZLihiwPmbeWjEsdlFkThCj5uBZecDEvnGyH53PjZ2Lf+/v/QsYR+HkRJzj9ko0U Ip8A== X-Gm-Message-State: APjAAAXyA0ph28LLvC0hXUBI9WN5DJHc3ypAkZ0KavBn4uPLwTYUNI2W tfSTFn/Zc6wY1iHZV2O1jQM= X-Google-Smtp-Source: APXvYqzMuqM00Zl2BNEGoD43HtrkPlEl1i1cpW+s4a3j4ZAkM12xIUhFYLXQ0yELF7J172COS8NgSQ== X-Received: by 2002:a17:902:403:: with SMTP id 3mr107568509ple.66.1560796652839; Mon, 17 Jun 2019 11:37:32 -0700 (PDT) Received: from aw-bldr-10.qualcomm.com (i-global254.qualcomm.com. [199.106.103.254]) by smtp.gmail.com with ESMTPSA id v4sm15417273pff.45.2019.06.17.11.37.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 11:37:32 -0700 (PDT) From: Jeffrey Hugo To: lgirdwood@gmail.com, broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jeffrey Hugo Subject: [PATCH v5 2/5] regulator: qcom_spmi: Add support for PM8005 Date: Mon, 17 Jun 2019 11:37:29 -0700 Message-Id: <20190617183729.13553-1-jeffrey.l.hugo@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190617183643.13449-1-jeffrey.l.hugo@gmail.com> References: <20190617183643.13449-1-jeffrey.l.hugo@gmail.com> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The PM8005 is used on the msm8998 MTP. The S1 regulator is VDD_GFX, ie it needs to be on and controlled inorder to use the GPU. Add support to drive the PM8005 regulators so that we can bring up the GPU on msm8998. Signed-off-by: Jeffrey Hugo Reviewed-by: Bjorn Andersson --- drivers/regulator/qcom_spmi-regulator.c | 176 ++++++++++++++++++++++++ 1 file changed, 176 insertions(+) diff --git a/drivers/regulator/qcom_spmi-regulator.c b/drivers/regulator/qcom_spmi-regulator.c index 1b3383a24c9d..8d1ee72ddbe2 100644 --- a/drivers/regulator/qcom_spmi-regulator.c +++ b/drivers/regulator/qcom_spmi-regulator.c @@ -104,6 +104,7 @@ enum spmi_regulator_logical_type { SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS, SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS, SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO, + SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426, }; enum spmi_regulator_type { @@ -150,6 +151,7 @@ enum spmi_regulator_subtype { SPMI_REGULATOR_SUBTYPE_5V_BOOST = 0x01, SPMI_REGULATOR_SUBTYPE_FTS_CTL = 0x08, SPMI_REGULATOR_SUBTYPE_FTS2p5_CTL = 0x09, + SPMI_REGULATOR_SUBTYPE_FTS426_CTL = 0x0a, SPMI_REGULATOR_SUBTYPE_BB_2A = 0x01, SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL1 = 0x0d, SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL2 = 0x0e, @@ -170,6 +172,18 @@ enum spmi_common_regulator_registers { SPMI_COMMON_REG_STEP_CTRL = 0x61, }; +/* + * Second common register layout used by newer devices starting with ftsmps426 + * Note that some of the registers from the first common layout remain + * unchanged and their definition is not duplicated. + */ +enum spmi_ftsmps426_regulator_registers { + SPMI_FTSMPS426_REG_VOLTAGE_LSB = 0x40, + SPMI_FTSMPS426_REG_VOLTAGE_MSB = 0x41, + SPMI_FTSMPS426_REG_VOLTAGE_ULS_LSB = 0x68, + SPMI_FTSMPS426_REG_VOLTAGE_ULS_MSB = 0x69, +}; + enum spmi_vs_registers { SPMI_VS_REG_OCP = 0x4a, SPMI_VS_REG_SOFT_START = 0x4c, @@ -229,6 +243,14 @@ enum spmi_common_control_register_index { #define SPMI_COMMON_MODE_FOLLOW_HW_EN0_MASK 0x01 #define SPMI_COMMON_MODE_FOLLOW_ALL_MASK 0x1f +#define SPMI_FTSMPS426_MODE_BYPASS_MASK 3 +#define SPMI_FTSMPS426_MODE_RETENTION_MASK 4 +#define SPMI_FTSMPS426_MODE_LPM_MASK 5 +#define SPMI_FTSMPS426_MODE_AUTO_MASK 6 +#define SPMI_FTSMPS426_MODE_HPM_MASK 7 + +#define SPMI_FTSMPS426_MODE_MASK 0x07 + /* Common regulator pull down control register layout */ #define SPMI_COMMON_PULL_DOWN_ENABLE_MASK 0x80 @@ -274,6 +296,23 @@ enum spmi_common_control_register_index { #define SPMI_FTSMPS_STEP_MARGIN_NUM 4 #define SPMI_FTSMPS_STEP_MARGIN_DEN 5 +#define SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK 0x03 +#define SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT 0 + +/* Clock rate in kHz of the FTSMPS426 regulator reference clock. */ +#define SPMI_FTSMPS426_CLOCK_RATE 4800 + +/* Minimum voltage stepper delay for each step. */ +#define SPMI_FTSMPS426_STEP_DELAY 2 + +/* + * The ratio SPMI_FTSMPS426_STEP_MARGIN_NUM/SPMI_FTSMPS426_STEP_MARGIN_DEN is + * used to adjust the step rate in order to account for oscillator variance. + */ +#define SPMI_FTSMPS426_STEP_MARGIN_NUM 10 +#define SPMI_FTSMPS426_STEP_MARGIN_DEN 11 + + /* VSET value to decide the range of ULT SMPS */ #define ULT_SMPS_RANGE_SPLIT 0x60 @@ -447,6 +486,10 @@ static struct spmi_voltage_range ftsmps2p5_ranges[] = { SPMI_VOLTAGE_RANGE(1, 160000, 1360000, 2200000, 2200000, 10000), }; +static struct spmi_voltage_range ftsmps426_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 0, 320000, 1352000, 1352000, 4000), +}; + static struct spmi_voltage_range boost_ranges[] = { SPMI_VOLTAGE_RANGE(0, 4000000, 4000000, 5550000, 5550000, 50000), }; @@ -480,6 +523,7 @@ static DEFINE_SPMI_SET_POINTS(ln_ldo); static DEFINE_SPMI_SET_POINTS(smps); static DEFINE_SPMI_SET_POINTS(ftsmps); static DEFINE_SPMI_SET_POINTS(ftsmps2p5); +static DEFINE_SPMI_SET_POINTS(ftsmps426); static DEFINE_SPMI_SET_POINTS(boost); static DEFINE_SPMI_SET_POINTS(boost_byp); static DEFINE_SPMI_SET_POINTS(ult_lo_smps); @@ -747,6 +791,23 @@ spmi_regulator_common_set_voltage(struct regulator_dev *rdev, unsigned selector) return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, buf, 2); } +static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev, + unsigned selector); + +static int spmi_regulator_ftsmps426_set_voltage(struct regulator_dev *rdev, + unsigned selector) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + u8 buf[2]; + int mV; + + mV = spmi_regulator_common_list_voltage(rdev, selector) / 1000; + + buf[0] = mV & 0xff; + buf[1] = mV >> 8; + return spmi_vreg_write(vreg, SPMI_FTSMPS426_REG_VOLTAGE_LSB, buf, 2); +} + static int spmi_regulator_set_voltage_time_sel(struct regulator_dev *rdev, unsigned int old_selector, unsigned int new_selector) { @@ -778,6 +839,21 @@ static int spmi_regulator_common_get_voltage(struct regulator_dev *rdev) return spmi_hw_selector_to_sw(vreg, voltage_sel, range); } +static int spmi_regulator_ftsmps426_get_voltage(struct regulator_dev *rdev) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + const struct spmi_voltage_range *range; + u8 buf[2]; + int uV; + + spmi_vreg_read(vreg, SPMI_FTSMPS426_REG_VOLTAGE_LSB, buf, 2); + + uV = (((unsigned int)buf[1] << 8) | (unsigned int)buf[0]) * 1000; + range = vreg->set_points->range; + + return (uV - range->set_point_min_uV) / range->step_uV; +} + static int spmi_regulator_single_map_voltage(struct regulator_dev *rdev, int min_uV, int max_uV) { @@ -923,6 +999,23 @@ static unsigned int spmi_regulator_common_get_mode(struct regulator_dev *rdev) } } +static unsigned int spmi_regulator_ftsmps426_get_mode(struct regulator_dev *rdev) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + u8 reg; + + spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, ®, 1); + + switch (reg) { + case SPMI_FTSMPS426_MODE_HPM_MASK: + return REGULATOR_MODE_NORMAL; + case SPMI_FTSMPS426_MODE_AUTO_MASK: + return REGULATOR_MODE_FAST; + default: + return REGULATOR_MODE_IDLE; + } +} + static int spmi_regulator_common_set_mode(struct regulator_dev *rdev, unsigned int mode) { @@ -945,6 +1038,30 @@ spmi_regulator_common_set_mode(struct regulator_dev *rdev, unsigned int mode) return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); } +static int +spmi_regulator_ftsmps426_set_mode(struct regulator_dev *rdev, unsigned int mode) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + u8 mask = SPMI_FTSMPS426_MODE_MASK; + u8 val; + + switch (mode) { + case REGULATOR_MODE_NORMAL: + val = SPMI_FTSMPS426_MODE_HPM_MASK; + break; + case REGULATOR_MODE_FAST: + val = SPMI_FTSMPS426_MODE_AUTO_MASK; + break; + case REGULATOR_MODE_IDLE: + val = SPMI_FTSMPS426_MODE_LPM_MASK; + break; + default: + return -EINVAL; + } + + return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); +} + static int spmi_regulator_common_set_load(struct regulator_dev *rdev, int load_uA) { @@ -1274,6 +1391,21 @@ static struct regulator_ops spmi_ult_ldo_ops = { .set_soft_start = spmi_regulator_common_set_soft_start, }; +static struct regulator_ops spmi_ftsmps426_ops = { + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage, + .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, + .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage, + .map_voltage = spmi_regulator_single_map_voltage, + .list_voltage = spmi_regulator_common_list_voltage, + .set_mode = spmi_regulator_ftsmps426_set_mode, + .get_mode = spmi_regulator_ftsmps426_get_mode, + .set_load = spmi_regulator_common_set_load, + .set_pull_down = spmi_regulator_common_set_pull_down, +}; + /* Maximum possible digital major revision value */ #define INF 0xFF @@ -1309,6 +1441,7 @@ static const struct spmi_regulator_mapping supported_regulators[] = { SPMI_VREG(BOOST, 5V_BOOST, 0, INF, BOOST, boost, boost, 0), SPMI_VREG(FTS, FTS_CTL, 0, INF, FTSMPS, ftsmps, ftsmps, 100000), SPMI_VREG(FTS, FTS2p5_CTL, 0, INF, FTSMPS, ftsmps, ftsmps2p5, 100000), + SPMI_VREG(FTS, FTS426_CTL, 0, INF, FTSMPS426, ftsmps426, ftsmps426, 100000), SPMI_VREG(BOOST_BYP, BB_2A, 0, INF, BOOST_BYP, boost, boost_byp, 0), SPMI_VREG(ULT_BUCK, ULT_HF_CTL1, 0, INF, ULT_LO_SMPS, ult_lo_smps, ult_lo_smps, 100000), @@ -1446,6 +1579,34 @@ static int spmi_regulator_init_slew_rate(struct spmi_regulator *vreg) return ret; } +static int spmi_regulator_init_slew_rate_ftsmps426(struct spmi_regulator *vreg) +{ + int ret; + u8 reg = 0; + int delay, slew_rate; + const struct spmi_voltage_range *range = &vreg->set_points->range[0]; + + ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, ®, 1); + if (ret) { + dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret); + return ret; + } + + delay = reg & SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK; + delay >>= SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT; + + /* slew_rate has units of uV/us */ + slew_rate = SPMI_FTSMPS426_CLOCK_RATE * range->step_uV; + slew_rate /= 1000 * (SPMI_FTSMPS426_STEP_DELAY << delay); + slew_rate *= SPMI_FTSMPS426_STEP_MARGIN_NUM; + slew_rate /= SPMI_FTSMPS426_STEP_MARGIN_DEN; + + /* Ensure that the slew rate is greater than 0 */ + vreg->slew_rate = max(slew_rate, 1); + + return ret; +} + static int spmi_regulator_init_registers(struct spmi_regulator *vreg, const struct spmi_regulator_init_data *data) { @@ -1585,6 +1746,12 @@ static int spmi_regulator_of_parse(struct device_node *node, ret = spmi_regulator_init_slew_rate(vreg); if (ret) return ret; + break; + case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426: + ret = spmi_regulator_init_slew_rate_ftsmps426(vreg); + if (ret) + return ret; + break; default: break; } @@ -1741,7 +1908,16 @@ static const struct spmi_regulator_data pmi8994_regulators[] = { { } }; +static const struct spmi_regulator_data pm8005_regulators[] = { + { "s1", 0x1400, "vdd_s1", }, + { "s2", 0x1700, "vdd_s2", }, + { "s3", 0x1a00, "vdd_s3", }, + { "s4", 0x1d00, "vdd_s4", }, + { } +}; + static const struct of_device_id qcom_spmi_regulator_match[] = { + { .compatible = "qcom,pm8005-regulators", .data = &pm8005_regulators }, { .compatible = "qcom,pm8841-regulators", .data = &pm8841_regulators }, { .compatible = "qcom,pm8916-regulators", .data = &pm8916_regulators }, { .compatible = "qcom,pm8941-regulators", .data = &pm8941_regulators }, From patchwork Mon Jun 17 18:37:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeffrey Hugo X-Patchwork-Id: 11000093 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6FDD014DB for ; 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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id i133sm8541348pfe.75.2019.06.17.11.38.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 11:38:01 -0700 (PDT) From: Jeffrey Hugo To: agross@kernel.org, bjorn.andersson@linaro.org Cc: lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jeffrey Hugo Subject: [PATCH v5 3/5] arm64: dts: msm8998-mtp: Add pm8005_s1 regulator Date: Mon, 17 Jun 2019 11:37:58 -0700 Message-Id: <20190617183759.13605-1-jeffrey.l.hugo@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190617183643.13449-1-jeffrey.l.hugo@gmail.com> References: <20190617183643.13449-1-jeffrey.l.hugo@gmail.com> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The pm8005_s1 is VDD_GFX, and needs to be on to enable the GPU. This should be hooked up to the GPU CPR, but we don't have support for that yet, so until then, just turn on the regulator and keep it on so that we can focus on basic GPU bringup. Signed-off-by: Jeffrey Hugo Reviewed-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi index f09f3e03f708..108667ce4f31 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi @@ -27,6 +27,23 @@ status = "okay"; }; +&pm8005_lsid1 { + pm8005-regulators { + compatible = "qcom,pm8005-regulators"; + + vdd_s1-supply = <&vph_pwr>; + + pm8005_s1: s1 { /* VDD_GFX supply */ + regulator-min-microvolt = <524000>; + regulator-max-microvolt = <1100000>; + regulator-enable-ramp-delay = <500>; + + /* hack until we rig up the gpu consumer */ + regulator-always-on; + }; + }; +}; + &qusb2phy { status = "okay"; From patchwork Mon Jun 17 18:38:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeffrey Hugo X-Patchwork-Id: 11000107 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5EE8A14DB for ; Mon, 17 Jun 2019 18:38:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 547E5286F6 for ; Mon, 17 Jun 2019 18:38:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 48C54289B9; Mon, 17 Jun 2019 18:38:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EBC05286F6 for ; Mon, 17 Jun 2019 18:38:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726026AbfFQSiU (ORCPT ); Mon, 17 Jun 2019 14:38:20 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:37767 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725844AbfFQSiU (ORCPT ); Mon, 17 Jun 2019 14:38:20 -0400 Received: by mail-pf1-f195.google.com with SMTP id 19so6152831pfa.4; Mon, 17 Jun 2019 11:38:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ypy1jYMMxHq//sxPDAaM1q7oa3FUUDRh/MaSzsTk114=; b=qC2QDWKhELhh0AsGIxnHawjI73Ycq5E6RSIesESuhIL0ozLxErKto9rlbqwV6K7yC2 9ou+jgPL6YJjCjCCw8C9K6rgRPHHrX/4rykDHM5uxT4Mgbk7CVjrXQX3hIIoWWQIx3Wr EKTdfzPBQMl90lMoWo/4NsBfHkgzh44iqgNNGSAEMg4ybRIqszoUAPfpQlpTGNimcx5i AIg89PYZ2kCkXTosmYZnx8PC3N4BDdo4aAI/9qHLD0BZQFI+b5mcsdCOZ5KomZFTrYBY i3EI9yAAy6rjjyJZC//KuuJmFzUjQrfkO9IimnT4ihqSDoO4pkh2IQEDPDyy3EIWFckG 2mkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ypy1jYMMxHq//sxPDAaM1q7oa3FUUDRh/MaSzsTk114=; b=CL34fySvkq73ujPgbrT1/SnImz8J1U8VFTojptq6ACkYQ7vCPp8BUd01RNsGCmuHYg qi4N0BKABiLLNqIW2tDfX2ZOD1WQ6Nc1BggOGIs1PNwXwyInUA+CxHje1bIaUBXQhAnr JGj+5Tbqc6B3tgwvMqfKIWdH9pqT5qq0+BEX1phCZ+odph9ZbjBM/kxY3NGtq5sayl/e xVEbk1MX5zcBFllGigvw9+q8/1RSir5KMo4IEO7+PIVCYdX0mLQrlffXeE6YHMat7/tu J6G+inYr2ciml7JP4RLEBBrjNzAj6wkvL0cdZoFtxQaKfVcJlUR5+GaSvOmXo9BUUeT4 d74w== X-Gm-Message-State: APjAAAW9ykWv3ByB1ObA5A87jg8Dm6QPS/1PgO+dh3SJ1f4CiK2DnEDj m3Zs97MZa72M1K/KDKcPZ6M= X-Google-Smtp-Source: APXvYqwmjm9XTI8o8K+v8RQpMdVWRNBeF0RTGANIJAhdHeXtpf8iR4ZoczjRKhs1tKxJitDimAfYZA== X-Received: by 2002:a62:e710:: with SMTP id s16mr82057504pfh.183.1560796699385; Mon, 17 Jun 2019 11:38:19 -0700 (PDT) Received: from aw-bldr-10.qualcomm.com (i-global254.qualcomm.com. [199.106.103.254]) by smtp.gmail.com with ESMTPSA id x7sm11759028pfa.125.2019.06.17.11.38.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 11:38:18 -0700 (PDT) From: Jeffrey Hugo To: lgirdwood@gmail.com, broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jorge Ramirez , Jeffrey Hugo Subject: [PATCH v5 4/5] dt-bindings: qcom_spmi: Document pms405 support Date: Mon, 17 Jun 2019 11:38:15 -0700 Message-Id: <20190617183815.13659-1-jeffrey.l.hugo@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190617183643.13449-1-jeffrey.l.hugo@gmail.com> References: <20190617183643.13449-1-jeffrey.l.hugo@gmail.com> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jorge Ramirez The PMS405 supports 5 SMPS and 13 LDO regulators. Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Rob Herring Signed-off-by: Jeffrey Hugo --- .../bindings/regulator/qcom,spmi-regulator.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt index ba94bc2d407a..430b8622bda1 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt @@ -10,6 +10,7 @@ Qualcomm SPMI Regulators "qcom,pm8941-regulators" "qcom,pm8994-regulators" "qcom,pmi8994-regulators" + "qcom,pms405-regulators" - interrupts: Usage: optional @@ -111,6 +112,23 @@ Qualcomm SPMI Regulators Definition: Reference to regulator supplying the input pin, as described in the data sheet. +- vdd_l1_l2-supply: +- vdd_l3_l8-supply: +- vdd_l4-supply: +- vdd_l5_l6-supply: +- vdd_l10_l11_l12_l13-supply: +- vdd_l7-supply: +- vdd_l9-supply: +- vdd_s1-supply: +- vdd_s2-supply: +- vdd_s3-supply: +- vdd_s4-supply: +- vdd_s5-supply + Usage: optional (pms405 only) + Value type: + Definition: Reference to regulator supplying the input pin, as + described in the data sheet. + - qcom,saw-reg: Usage: optional Value type: From patchwork Mon Jun 17 18:38:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeffrey Hugo X-Patchwork-Id: 11000109 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5687014DB for ; Mon, 17 Jun 2019 18:38:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4BB90286F6 for ; Mon, 17 Jun 2019 18:38:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3FDD0289B9; Mon, 17 Jun 2019 18:38:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A63DB286F6 for ; Mon, 17 Jun 2019 18:38:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727580AbfFQSic (ORCPT ); Mon, 17 Jun 2019 14:38:32 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:32836 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725844AbfFQSic (ORCPT ); Mon, 17 Jun 2019 14:38:32 -0400 Received: by mail-pg1-f193.google.com with SMTP id k187so6293866pga.0; Mon, 17 Jun 2019 11:38:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TaoZgnSZD/1NROkvSZ2KjTj9++aIk793JR4OVFGivf0=; b=AqteFdoo3VO8lJuxlqZsyjUs5wNuAg3gUpWEQ4zjwZOs0/UhkQEdQgYSN6PygB4vJ3 /tM0Lhqxap42YEQmSbhH12l93dB6GKccCuo/lBIkRzj8a0jN1urtn44jl3U29o1f5Cj0 Kh9T14x+cqgBH0WHYV1rI6G4iA3iKlMausMJYtzl/VXlz6ryclBcyZOblKCM3c2CAe5W C7F7Lp6F/FATjxmwYgAsq8JVbb6qwmA3T8p6is+qL9lflTYLxVjZIe3uS5Ls1CJMU/nY nUEsC05prTEpN/E6vFRlSLW68T2EqaUTvw+lukjDmxHRAby7L5t88tUEWREptFQPRmjJ 3htg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TaoZgnSZD/1NROkvSZ2KjTj9++aIk793JR4OVFGivf0=; b=UiXqDAK9mdtIer4pF7xNlNJok323sJgQpqsHdIqkX7fpsfx8DQh2zxMUHxBeUVdWIQ bBnWflKov9QE4pvyk/2yRTSWX7eKPD8I1q2dXK9w2+JdZc8otvMggSD4ztllxZYwLd/M rlCWL3gocTXQPpS1sW4nC35wtW9Lnc3YgXHz3RSTsNKs4EUpAbFMjWqfIve03mg1hmc7 wLASVi43SoxaxbmpSUbcprjvdbQZsvfzypEQ+Ud4sGYsMCNoP4sry69+die1W5XKl3EB DPoGSW4BmX1FexFTGGx/oqQtBvNknIEWYltzRxCweVJNWNN6Zfq971z3YFU53vDf7E+k z+iw== X-Gm-Message-State: APjAAAXk4NN9aR02YKbW6iWk2HPsdcHSGOdj0C97x9g0DtQ5apRgUckk 5V1noapBGETWxiyYtThVFuw= X-Google-Smtp-Source: APXvYqzNyDLYUjgVGU6gqF2jNqtRI9lR/CI2s7xCHc9LvzvlG43DYEXkxae/kiJYkxx5L/Zh36XjPQ== X-Received: by 2002:a62:754d:: with SMTP id q74mr90413986pfc.211.1560796711353; Mon, 17 Jun 2019 11:38:31 -0700 (PDT) Received: from aw-bldr-10.qualcomm.com (i-global254.qualcomm.com. [199.106.103.254]) by smtp.gmail.com with ESMTPSA id 3sm12145653pfp.114.2019.06.17.11.38.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 11:38:30 -0700 (PDT) From: Jeffrey Hugo To: lgirdwood@gmail.com, broonie@kernel.org Cc: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jorge Ramirez , Jeffrey Hugo Subject: [PATCH v5 5/5] regulator: qcom_spmi: add PMS405 SPMI regulator Date: Mon, 17 Jun 2019 11:38:27 -0700 Message-Id: <20190617183827.13710-1-jeffrey.l.hugo@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190617183643.13449-1-jeffrey.l.hugo@gmail.com> References: <20190617183643.13449-1-jeffrey.l.hugo@gmail.com> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jorge Ramirez The PMS405 has 5 HFSMPS and 13 LDO regulators, This commit adds support for one of the 5 HFSMPS regulators (s3) to the spmi regulator driver. The PMIC HFSMPS 430 regulators have 8 mV step size and a voltage control scheme consisting of two 8-bit registers defining a 16-bit voltage set point in units of millivolts S3 controls the cpu voltages (s3 is a buck regulator of type HFS430); it is therefore required so we can enable voltage scaling for safely running cpufreq. Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Jeffrey Hugo --- drivers/regulator/qcom_spmi-regulator.c | 43 +++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 3 deletions(-) diff --git a/drivers/regulator/qcom_spmi-regulator.c b/drivers/regulator/qcom_spmi-regulator.c index 8d1ee72ddbe2..a9e8b7045545 100644 --- a/drivers/regulator/qcom_spmi-regulator.c +++ b/drivers/regulator/qcom_spmi-regulator.c @@ -105,6 +105,7 @@ enum spmi_regulator_logical_type { SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS, SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO, SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426, + SPMI_REGULATOR_LOGICAL_TYPE_HFS430, }; enum spmi_regulator_type { @@ -157,6 +158,7 @@ enum spmi_regulator_subtype { SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL2 = 0x0e, SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f, SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10, + SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a, }; enum spmi_common_regulator_registers { @@ -302,6 +304,8 @@ enum spmi_common_control_register_index { /* Clock rate in kHz of the FTSMPS426 regulator reference clock. */ #define SPMI_FTSMPS426_CLOCK_RATE 4800 +#define SPMI_HFS430_CLOCK_RATE 1600 + /* Minimum voltage stepper delay for each step. */ #define SPMI_FTSMPS426_STEP_DELAY 2 @@ -515,6 +519,10 @@ static struct spmi_voltage_range ult_pldo_ranges[] = { SPMI_VOLTAGE_RANGE(0, 1750000, 1750000, 3337500, 3337500, 12500), }; +static struct spmi_voltage_range hfs430_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 320000, 320000, 2040000, 2040000, 8000), +}; + static DEFINE_SPMI_SET_POINTS(pldo); static DEFINE_SPMI_SET_POINTS(nldo1); static DEFINE_SPMI_SET_POINTS(nldo2); @@ -530,6 +538,7 @@ static DEFINE_SPMI_SET_POINTS(ult_lo_smps); static DEFINE_SPMI_SET_POINTS(ult_ho_smps); static DEFINE_SPMI_SET_POINTS(ult_nldo); static DEFINE_SPMI_SET_POINTS(ult_pldo); +static DEFINE_SPMI_SET_POINTS(hfs430); static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf, int len) @@ -1406,12 +1415,26 @@ static struct regulator_ops spmi_ftsmps426_ops = { .set_pull_down = spmi_regulator_common_set_pull_down, }; +static struct regulator_ops spmi_hfs430_ops = { + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage, + .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, + .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage, + .map_voltage = spmi_regulator_single_map_voltage, + .list_voltage = spmi_regulator_common_list_voltage, + .set_mode = spmi_regulator_ftsmps426_set_mode, + .get_mode = spmi_regulator_ftsmps426_get_mode, +}; + /* Maximum possible digital major revision value */ #define INF 0xFF static const struct spmi_regulator_mapping supported_regulators[] = { /* type subtype dig_min dig_max ltype ops setpoints hpm_min */ SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000), + SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000), SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000), SPMI_VREG(LDO, N600, 0, 0, LDO, ldo, nldo2, 10000), SPMI_VREG(LDO, N1200, 0, 0, LDO, ldo, nldo2, 10000), @@ -1579,7 +1602,8 @@ static int spmi_regulator_init_slew_rate(struct spmi_regulator *vreg) return ret; } -static int spmi_regulator_init_slew_rate_ftsmps426(struct spmi_regulator *vreg) +static int spmi_regulator_init_slew_rate_ftsmps426(struct spmi_regulator *vreg, + int clock_rate) { int ret; u8 reg = 0; @@ -1596,7 +1620,7 @@ static int spmi_regulator_init_slew_rate_ftsmps426(struct spmi_regulator *vreg) delay >>= SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT; /* slew_rate has units of uV/us */ - slew_rate = SPMI_FTSMPS426_CLOCK_RATE * range->step_uV; + slew_rate = clock_rate * range->step_uV; slew_rate /= 1000 * (SPMI_FTSMPS426_STEP_DELAY << delay); slew_rate *= SPMI_FTSMPS426_STEP_MARGIN_NUM; slew_rate /= SPMI_FTSMPS426_STEP_MARGIN_DEN; @@ -1748,7 +1772,14 @@ static int spmi_regulator_of_parse(struct device_node *node, return ret; break; case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426: - ret = spmi_regulator_init_slew_rate_ftsmps426(vreg); + ret = spmi_regulator_init_slew_rate_ftsmps426(vreg, + SPMI_FTSMPS426_CLOCK_RATE); + if (ret) + return ret; + break; + case SPMI_REGULATOR_LOGICAL_TYPE_HFS430: + ret = spmi_regulator_init_slew_rate_ftsmps426(vreg, + SPMI_HFS430_CLOCK_RATE); if (ret) return ret; break; @@ -1916,6 +1947,11 @@ static const struct spmi_regulator_data pm8005_regulators[] = { { } }; +static const struct spmi_regulator_data pms405_regulators[] = { + { "s3", 0x1a00, "vdd_s3"}, + { } +}; + static const struct of_device_id qcom_spmi_regulator_match[] = { { .compatible = "qcom,pm8005-regulators", .data = &pm8005_regulators }, { .compatible = "qcom,pm8841-regulators", .data = &pm8841_regulators }, @@ -1923,6 +1959,7 @@ static const struct of_device_id qcom_spmi_regulator_match[] = { { .compatible = "qcom,pm8941-regulators", .data = &pm8941_regulators }, { .compatible = "qcom,pm8994-regulators", .data = &pm8994_regulators }, { .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators }, + { .compatible = "qcom,pms405-regulators", .data = &pms405_regulators }, { } }; MODULE_DEVICE_TABLE(of, qcom_spmi_regulator_match);