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[73.95.159.87]) by smtp.gmail.com with ESMTPSA id i3sm3148925ion.9.2019.06.28.15.43.09 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 28 Jun 2019 15:43:10 -0700 (PDT) Date: Fri, 28 Jun 2019 15:43:09 -0700 (PDT) From: Paul Walmsley X-X-Sender: paulw@viisi.sifive.com To: Linus Torvalds Subject: [GIT PULL] RISC-V patches for v5.2-rc7 Message-ID: User-Agent: Alpine 2.21.9999 (DEB 301 2018-08-15) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190628_154313_192437_E5DA50B9 X-CRM114-Status: GOOD ( 12.62 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Linus, The following changes since commit 4b972a01a7da614b4796475f933094751a295a2f: Linux 5.2-rc6 (2019-06-22 16:01:36 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-v5.2/fixes-rc7 for you to fetch changes up to 0db7f5cd4aeba4cc63d0068598b3350eba8bb4cd: riscv: mm: Fix code comment (2019-06-26 15:10:30 -0700) ---------------------------------------------------------------- Minor RISC-V fixes and one defconfig update for the v5.2-rc series. The fixes have no functional impact: - Fix some comment text in the memory management vmalloc_fault path. - Fix some warnings from the DT compiler in our newly-added DT files. - Change the newly-added DT bindings such that SoC IP blocks with external I/O are marked as "disabled" by default, then enable them explicitly in board DT files when the devices are used on the board. This aligns the bindings with existing upstream practice. - Add the MIT license as an option for a minor header file, at the request of one of the U-Boot maintainers. The RISC-V defconfig update builds the SiFive SPI driver and the MMC-SPI driver by default. The intention here is to make v5.2 more usable for testers and users with RISC-V hardware. ---------------------------------------------------------------- Atish Patra (1): RISC-V: defconfig: enable MMC & SPI for RISC-V Paul Walmsley (2): dt-bindings: riscv: resolve 'make dt_binding_check' warnings dt-bindings: clock: sifive: add MIT license as an option for the header file ShihPo Hung (1): riscv: mm: Fix code comment Yash Shah (1): riscv: dts: Re-organize the DT nodes Documentation/devicetree/bindings/riscv/cpus.yaml | 26 ++++++++++++---------- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 6 +++++ .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 13 +++++++++++ arch/riscv/configs/defconfig | 5 +++++ arch/riscv/mm/fault.c | 3 --- include/dt-bindings/clock/sifive-fu540-prci.h | 2 +- 6 files changed, 39 insertions(+), 16 deletions(-)