From patchwork Fri Aug 31 22:09:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 10584501 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1258E5A4 for ; Fri, 31 Aug 2018 22:11:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 060852C8E9 for ; Fri, 31 Aug 2018 22:11:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 040EF2C8F6; Fri, 31 Aug 2018 22:11:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9EB082C8E9 for ; Fri, 31 Aug 2018 22:11:11 +0000 (UTC) Received: from localhost ([::1]:58646 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvrdG-0005qh-SM for patchwork-qemu-devel@patchwork.kernel.org; Fri, 31 Aug 2018 18:11:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51872) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvrbh-0004ZA-PS for qemu-devel@nongnu.org; Fri, 31 Aug 2018 18:09:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fvrbf-0004id-FN for qemu-devel@nongnu.org; Fri, 31 Aug 2018 18:09:33 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:35564) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fvrbe-0004gx-TL; Fri, 31 Aug 2018 18:09:31 -0400 Received: by mail-pf1-x432.google.com with SMTP id p12-v6so6109189pfh.2; Fri, 31 Aug 2018 15:09:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=Rg3wVxt7rFRes9qU+lBCVF26M2ACVOvZSLkqEDwOn4M=; b=EpxTRKq4Pcrd/6Dz+75A/bWPbiNkELo12QUKJqf26jtx2c4afdcObTS5XJGPTx/Lav CczWzFdx6V028Gs5bbrxP72EkaSgmkA3pbn4f0sNAfBB9LToR5nbZmNCSJNAIci/h1Nv fQX4U/qQWndIUDnxkBi+SW+bGsovq30rBr0jKQum178DiOmfLla98G1fjOM5ELpABunk FVll9gQKVW2CBC0UcBIpZZq09ks+UK0fj+QC+BPtwkdq6oi9C8Am0XdWwl46Tl9vMNVC qkIXP7vhyRK6SJiCA7MtW/Jfmu08xhPk8B0Bv/+8JtiniUctRY/1R+qq6crPm12I7hPX OmHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=Rg3wVxt7rFRes9qU+lBCVF26M2ACVOvZSLkqEDwOn4M=; b=VyxHCMBcJsiLOBw0ZEF9l7OCt6OSr4fVumVgQIJpSC64S23gLI5Y9bK8U+0LPzA4tm 8gEO9KWSlE0z1FlmB5h73P9XvB3cTxvQAVPdi9uEmV6siXtnXYCiaBe0pY9yP1b3ZAcT +/NmHcAcdPt9DsRQlBx4/Ffqi/RYua4p5IaThRu8G6RJPQpmDozLAIYKn1M/vVKRJv4n YpJJyu1dMLaI11zI/Mwpkis479Nui0CB89+7SHxxGkFD9ypoYa8pVIIlr4R94k9XrVQH OHEYxGstoFjguC45HSIlBKR5mqXKC7w/tqfwWe4IN4ioOArZbmPOSnAcGMcfaOiUNphU DOyg== X-Gm-Message-State: APzg51BcOsyztS3QkfN7IFgPzzFabAa6ACzKs2EPaAUVBrnU90nTd9qr sBeKqwWYHT4p1vu9QWt4ODs= X-Google-Smtp-Source: ANB0VdZ8btddQf35MIE2UFcRzm+4kKH+LtQqibBRx7isTNujmgUpzifhE8O84PQRzOgVlkMCL2zmEw== X-Received: by 2002:a63:4e5f:: with SMTP id o31-v6mr16248702pgl.256.1535753369832; Fri, 31 Aug 2018 15:09:29 -0700 (PDT) Received: from aurora.jms.id.au ([72.28.92.217]) by smtp.gmail.com with ESMTPSA id w69-v6sm22400873pgd.37.2018.08.31.15.09.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 31 Aug 2018 15:09:29 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Fri, 31 Aug 2018 15:09:27 -0700 From: Joel Stanley To: Peter Maydell Date: Fri, 31 Aug 2018 15:09:18 -0700 Message-Id: <20180831220920.27113-2-joel@jms.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180831220920.27113-1-joel@jms.id.au> References: <20180831220920.27113-1-joel@jms.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::432 Subject: [Qemu-devel] [PATCH v6 1/3] MAINTAINERS: Add NRF51 entry X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , =?utf-8?q?Steffen_G=C3=B6rtz?= , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Jim Mussared , Julia Suvorova Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This contains the NRF51, and the machine that uses it, the BBC micro:bit. Reviewed-by: Stefan Hajnoczi Reviewed-by: Peter Maydell Signed-off-by: Joel Stanley --- v3: fix spelling of mailing list add stefan's reviewed-by v6: Add Peter's reviewed-by --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d12518c08f10..d30f23f127ba 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -670,6 +670,14 @@ F: include/hw/*/*aspeed* F: hw/net/ftgmac100.c F: include/hw/net/ftgmac100.h +NRF51 +M: Joel Stanley +L: qemu-arm@nongnu.org +S: Maintained +F: hw/arm/nrf51_soc.c +F: hw/arm/microbit.c +F: include/hw/arm/nrf51_soc.h + CRIS Machines ------------- Axis Dev88 From patchwork Fri Aug 31 22:09:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 10584499 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BC65B5A4 for ; Fri, 31 Aug 2018 22:11:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AEE6D2C893 for ; Fri, 31 Aug 2018 22:11:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AD43D2C8E9; Fri, 31 Aug 2018 22:11:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BD6B72C907 for ; Fri, 31 Aug 2018 22:11:02 +0000 (UTC) Received: from localhost ([::1]:58645 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvrd8-0005ip-1E for patchwork-qemu-devel@patchwork.kernel.org; Fri, 31 Aug 2018 18:11:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52009) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvrbn-0004bs-PX for qemu-devel@nongnu.org; Fri, 31 Aug 2018 18:09:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fvrbh-0004kb-Bi for qemu-devel@nongnu.org; Fri, 31 Aug 2018 18:09:38 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:45153) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fvrbh-0004jx-26; Fri, 31 Aug 2018 18:09:33 -0400 Received: by mail-pl1-x641.google.com with SMTP id j8-v6so6020235pll.12; Fri, 31 Aug 2018 15:09:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=vqBx8fhtdob4tL4BQMb9LSVcapgn+tNBIHmgUnd5aBA=; b=rpPgTc1/Hza0fLWPQTXpEVsqjRfWTDCsYGNnp8jaJ761XgZckwJedJzlr8Gbs4SHlF Fdk1l3yPvzaaAqD96Ka4QO8hChl5QKp+23fUtc+ZODFLgoMMfUhgdtLKaSUoh172sM8W NNgvUdHKMiEf8v4xxeAWJDYXbWEkWopjZPN41hCYBrRkK/ZGNp+kACih1WZSjzN3OK+o Hf+JPU+53gOrhALrRcpUl1gftgoMB8J2ct+ObYI9H1argcePGHrsbUR68WfGZRs5ZwA7 cmjf1AYIQxeER3PgulhRr1xBXVlGDrusEGZecSmkW/f6x1ETSx4dWKgnCjMIBy/5wjqj ohXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=vqBx8fhtdob4tL4BQMb9LSVcapgn+tNBIHmgUnd5aBA=; b=S38P3/Ww47XZ0IVZk1C2YW+2/VkClBlf6plmFP/0Lwu6sgu2Xmw4rQ4UsfNERbV2u0 yh81+Yg6xsAmUgxORIAkQPl/8DQP3KIcAuQq1nzWSSh2g/r1UALESC3nKCkkFlfI/yTR IWRKulOBWwHCu17QErIxGz2tI0KTiDFinFGdJ73rP32H6wpQ0w7QN0kjzCnsbkOUQ5kx f0LJ3Bf8q3UvHUCk9wDRBNF5ohu3QVpNcrcH91TPdcPUwwb9rwSVKsZ3Qb38KtrfJPuN lSBcMcj7CH+4XggPMSGogIws7b4cjNuWYryVbCDLJqdVCi2IyZqboDr4e2fsgeTgxG0p EXjg== X-Gm-Message-State: APzg51BwSOLUvvIXl1Ktk8pyGL3ktY40YqpTLP9d0QyqneMcG+BxhHz6 5R5tD90P9AdQRjtAJ9RNENs= X-Google-Smtp-Source: ANB0Vdb2/4AvE6jf4GC/VT1cOU45QU/tIiChkeyMakmr8M9gXdbRnGBe/8ecqUl4lWM9sZ/sr7ivlg== X-Received: by 2002:a17:902:3a5:: with SMTP id d34-v6mr17403676pld.98.1535753372032; Fri, 31 Aug 2018 15:09:32 -0700 (PDT) Received: from aurora.jms.id.au ([72.28.92.217]) by smtp.gmail.com with ESMTPSA id a2-v6sm12794119pgc.68.2018.08.31.15.09.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 31 Aug 2018 15:09:31 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Fri, 31 Aug 2018 15:09:29 -0700 From: Joel Stanley To: Peter Maydell Date: Fri, 31 Aug 2018 15:09:19 -0700 Message-Id: <20180831220920.27113-3-joel@jms.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180831220920.27113-1-joel@jms.id.au> References: <20180831220920.27113-1-joel@jms.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v6 2/3] arm: Add Nordic Semiconductor nRF51 SoC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , =?utf-8?q?Steffen_G=C3=B6rtz?= , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Jim Mussared , Julia Suvorova Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The nRF51 is a Cortex-M0 microcontroller with an on-board radio module, plus other common ARM SoC peripherals. http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf This defines a basic model of the CPU and memory, with no peripherals implemented at this stage. Signed-off-by: Joel Stanley --- v2: - put memory as struct fileds in state structure - pass OBJECT(s) as owner, not NULL - Add missing addresses for ficr - Fix flash and sram sizes for microbit - Embed cpu object in state object an initalise it without use of armv7m_init - Link to datasheet v3: - rebase nrf51 on m0 changes - remove unused kernel_filename - clarify flash and sram size - make flash and sram size properties of the soc state v4: - set the number of interrupts to 32 v5: - move back to armv7m calls, as v4 of Stefan's patch removed the m_profile changes v6: - Split comment open and closing to it's own line - Check err after every call - Change flash _init_ram + _set_readonly to _init_rom - Add defines for 'private' region - Use sysbus_init_child_obj instead of _initalise, _property_add_child, _set_parent_bus - remove osdep.h include from header --- default-configs/arm-softmmu.mak | 1 + hw/arm/Makefile.objs | 1 + hw/arm/nrf51_soc.c | 130 ++++++++++++++++++++++++++++++++ include/hw/arm/nrf51_soc.h | 41 ++++++++++ 4 files changed, 173 insertions(+) create mode 100644 hw/arm/nrf51_soc.c create mode 100644 include/hw/arm/nrf51_soc.h diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 0483d548d96a..2420491aacd4 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -101,6 +101,7 @@ CONFIG_STM32F2XX_SYSCFG=y CONFIG_STM32F2XX_ADC=y CONFIG_STM32F2XX_SPI=y CONFIG_STM32F205_SOC=y +CONFIG_NRF51_SOC=y CONFIG_CMSDK_APB_TIMER=y CONFIG_CMSDK_APB_DUALTIMER=y diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 2902f47b4c4c..ae4e20373b9e 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -37,3 +37,4 @@ obj-$(CONFIG_IOTKIT) += iotkit.o obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o obj-$(CONFIG_FSL_IMX6UL) += fsl-imx6ul.o mcimx6ul-evk.o +obj-$(CONFIG_NRF51_SOC) += nrf51_soc.o diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c new file mode 100644 index 000000000000..874051b26853 --- /dev/null +++ b/hw/arm/nrf51_soc.c @@ -0,0 +1,130 @@ +/* + * Nordic Semiconductor nRF51 SoC + * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf + * + * Copyright 2018 Joel Stanley + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "hw/arm/arm.h" +#include "hw/sysbus.h" +#include "hw/boards.h" +#include "hw/devices.h" +#include "hw/misc/unimp.h" +#include "exec/address-spaces.h" +#include "sysemu/sysemu.h" +#include "qemu/log.h" +#include "cpu.h" + +#include "hw/arm/nrf51_soc.h" + +#define IOMEM_BASE 0x40000000 +#define IOMEM_SIZE 0x20000000 + +#define FICR_BASE 0x10000000 +#define FICR_SIZE 0x000000fc + +#define FLASH_BASE 0x00000000 +#define SRAM_BASE 0x20000000 + +#define PRIVATE_BASE 0xF0000000 +#define PRIVATE_SIZE 0x10000000 + +/* + * The size and base is for the NRF51822 part. If other parts + * are supported in the future, add a sub-class of NRF51SoC for + * the specific variants + */ +#define NRF51822_FLASH_SIZE (256 * 1024) +#define NRF51822_SRAM_SIZE (16 * 1024) + +static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) +{ + NRF51State *s = NRF51_SOC(dev_soc); + Error *err = NULL; + + if (!s->board_memory) { + error_setg(errp, "memory property was not set"); + return; + } + + object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory", + &err); + if (err) { + error_propagate(errp, err); + return; + } + object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); + + memory_region_init_rom(&s->flash, OBJECT(s), "nrf51.flash", s->flash_size, + &err); + if (err) { + error_propagate(errp, err); + return; + } + memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash); + + memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &err); + if (err) { + error_propagate(errp, err); + return; + } + memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram); + + create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE); + create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE); + create_unimplemented_device("nrf51_soc.private", PRIVATE_BASE, PRIVATE_SIZE); +} + +static void nrf51_soc_init(Object *obj) +{ + NRF51State *s = NRF51_SOC(obj); + + memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); + + sysbus_init_child_obj(OBJECT(s), "armv6m", OBJECT(&s->cpu), sizeof(s->cpu), + TYPE_ARMV7M); + qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", ARM_CPU_TYPE_NAME("cortex-m0")); + qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32); +} + +static Property nrf51_soc_properties[] = { + DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE), + DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, NRF51822_FLASH_SIZE), + DEFINE_PROP_END_OF_LIST(), +}; + +static void nrf51_soc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = nrf51_soc_realize; + dc->props = nrf51_soc_properties; +} + +static const TypeInfo nrf51_soc_info = { + .name = TYPE_NRF51_SOC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(NRF51State), + .instance_init = nrf51_soc_init, + .class_init = nrf51_soc_class_init, +}; + +static void nrf51_soc_types(void) +{ + type_register_static(&nrf51_soc_info); +} +type_init(nrf51_soc_types) diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h new file mode 100644 index 000000000000..f4e092b554e0 --- /dev/null +++ b/include/hw/arm/nrf51_soc.h @@ -0,0 +1,41 @@ +/* + * Nordic Semiconductor nRF51 SoC + * + * Copyright 2018 Joel Stanley + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#ifndef NRF51_SOC_H +#define NRF51_SOC_H + +#include "hw/sysbus.h" +#include "hw/arm/armv7m.h" + +#define TYPE_NRF51_SOC "nrf51-soc" +#define NRF51_SOC(obj) \ + OBJECT_CHECK(NRF51State, (obj), TYPE_NRF51_SOC) + +typedef struct NRF51State { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + ARMv7MState cpu; + + MemoryRegion iomem; + MemoryRegion sram; + MemoryRegion flash; + + uint32_t sram_size; + uint32_t flash_size; + + MemoryRegion *board_memory; + + MemoryRegion container; + +} NRF51State; + +#endif + From patchwork Fri Aug 31 22:09:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 10584503 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E551A1709 for ; Fri, 31 Aug 2018 22:13:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D2F932BFF9 for ; Fri, 31 Aug 2018 22:13:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C65192C029; Fri, 31 Aug 2018 22:13:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 38B632BFF9 for ; Fri, 31 Aug 2018 22:13:04 +0000 (UTC) Received: from localhost ([::1]:58658 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvrf5-0007fa-Gy for patchwork-qemu-devel@patchwork.kernel.org; Fri, 31 Aug 2018 18:13:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52146) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvrbr-0004ex-PP for qemu-devel@nongnu.org; Fri, 31 Aug 2018 18:09:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fvrbp-0004sm-7m for qemu-devel@nongnu.org; Fri, 31 Aug 2018 18:09:43 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:44590) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fvrbm-0004mb-QK; Fri, 31 Aug 2018 18:09:39 -0400 Received: by mail-pg1-x541.google.com with SMTP id r1-v6so6013674pgp.11; Fri, 31 Aug 2018 15:09:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=HECvTG3GejFa6sz+CKKWy/jQ+RL2N8C5303UsdeGdog=; b=sA68YOl8VGfUR9TaJJ97poZ/p6f4/6xoFgdPPa+z1btWMz6PoJgbY3nubQkzUmqv5Z YI89b7PDtwTNk1mhXFpi/azMGIJ5A7+78KPXCSqxUuiUpzkELDxoft4+V8xUtiovhcjK GyDG5VBdVetQSbsFbwZJghcXm7MZ0eqgC57qY3nMwVSsJ7dnN/cQUrCforvluGIA5XNc JAFaWHQ2uyFefcsjRRog4aYV8I9WFPiG5qIpSdjpKhqyKu44qKSZCJUPdmY9lL1uH8C5 sA6PkKVPSTxHtVxWICy7mcM9bovhWJAFXaOo9ywnZUc/xxiNWsO3a8pL7bxU5A4XXOwx lf9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=HECvTG3GejFa6sz+CKKWy/jQ+RL2N8C5303UsdeGdog=; b=bfedXGFS/vwDEMiUpxTWqMkXOZqL41xlmjo6uJDRSET48BqBkPEFdYce72TdYck1l8 1fC9h9DwvXtJ/B8v9M7LV82ff6ZM2Uo+RVoJwIB1qRxs1htFeczNSpqJFPdZqFGARvXT 8QfHVddMcpdlBPQQKOYtFV59Vp7cydO7KkxdnExKqa/m432sQEbvPzBKZqnk/iX9EwAS El5hJsVv0XdDGwTtlBlG3Ko9VC7NjQtmj6rCXCkGESrkfUTY4cfm6BATkQejzXkfnRpU OZMDPLti3+DMW+MQwkUEz4p7ENOGPuPJNr/gOUOoxEOTsHdnSoK0pLKvij9z3s20BoYr b5sw== X-Gm-Message-State: APzg51BIi0lubTlN7PXS/bh8JuIG3uSuKFTaW0EVHkjsrAXM+xvQPEX7 Syd4HXFIIR0oz0c0kqUga7c= X-Google-Smtp-Source: ANB0VdYHqB37AdRv4mAx9PJ1RgGNnKs+1cD9kZz5U9Z9MHHYlC2DTyqlaityQCRCeiNrYzuDxl+t5Q== X-Received: by 2002:a63:2354:: with SMTP id u20-v6mr1602019pgm.122.1535753374402; Fri, 31 Aug 2018 15:09:34 -0700 (PDT) Received: from aurora.jms.id.au ([72.28.92.217]) by smtp.gmail.com with ESMTPSA id d12-v6sm16634207pfk.69.2018.08.31.15.09.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 31 Aug 2018 15:09:33 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Fri, 31 Aug 2018 15:09:32 -0700 From: Joel Stanley To: Peter Maydell Date: Fri, 31 Aug 2018 15:09:20 -0700 Message-Id: <20180831220920.27113-4-joel@jms.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180831220920.27113-1-joel@jms.id.au> References: <20180831220920.27113-1-joel@jms.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v6 3/3] arm: Add BBC micro:bit machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , =?utf-8?q?Steffen_G=C3=B6rtz?= , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Jim Mussared , Julia Suvorova Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This adds the base for a machine model of the BBC micro:bit: https://en.wikipedia.org/wiki/Micro_Bit This is a system with a nRF51 SoC containing the main processor, with various peripherals on board. Reviewed-by: Stefan Hajnoczi Signed-off-by: Joel Stanley --- v2: - Instead of setting kernel filename property, load the image directly - Add link to hardware overview website v3: - Rebase microbit on m0 changes - Remove hard-coded flash size and retrieve from the soc - Add Stefan's reviewed-by v5: - move back to armv7m calls, as v4 of Stefan's patch removed the m_profile changes v6: - MICROBITMachineState -> MicrobitMachineState - Rework machine type init with PMM's suggestions --- hw/arm/Makefile.objs | 2 +- hw/arm/microbit.c | 67 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+), 1 deletion(-) create mode 100644 hw/arm/microbit.c diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index ae4e20373b9e..5f88062c666d 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -37,4 +37,4 @@ obj-$(CONFIG_IOTKIT) += iotkit.o obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o obj-$(CONFIG_FSL_IMX6UL) += fsl-imx6ul.o mcimx6ul-evk.o -obj-$(CONFIG_NRF51_SOC) += nrf51_soc.o +obj-$(CONFIG_NRF51_SOC) += nrf51_soc.o microbit.o diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c new file mode 100644 index 000000000000..e7d74116a504 --- /dev/null +++ b/hw/arm/microbit.c @@ -0,0 +1,67 @@ +/* + * BBC micro:bit machine + * http://tech.microbit.org/hardware/ + * + * Copyright 2018 Joel Stanley + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/arm/arm.h" +#include "exec/address-spaces.h" + +#include "hw/arm/nrf51_soc.h" + +typedef struct { + MachineState parent; + + NRF51State nrf51; +} MicrobitMachineState; + +#define TYPE_MICROBIT_MACHINE MACHINE_TYPE_NAME("microbit") + +#define MICROBIT_MACHINE(obj) \ + OBJECT_CHECK(MicrobitMachineState, obj, TYPE_MICROBIT_MACHINE) + +static void microbit_init(MachineState *machine) +{ + MicrobitMachineState *s = MICROBIT_MACHINE(machine); + MemoryRegion *system_memory = get_system_memory(); + Object *soc = OBJECT(&s->nrf51); + + sysbus_init_child_obj(OBJECT(machine), "nrf51", soc, sizeof(s->nrf51), + TYPE_NRF51_SOC); + object_property_set_link(soc, OBJECT(system_memory), "memory", + &error_fatal); + object_property_set_bool(soc, true, "realized", &error_fatal); + + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, + NRF51_SOC(soc)->flash_size); +} + +static void microbit_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->desc = "BBC micro:bit"; + mc->init = microbit_init; + mc->max_cpus = 1; +} + +static const TypeInfo microbit_info = { + .name = TYPE_MICROBIT_MACHINE, + .parent = TYPE_MACHINE, + .instance_size = sizeof(MicrobitMachineState), + .class_init = microbit_machine_class_init, +}; + +static void microbit_machine_init(void) +{ + type_register_static(µbit_info); +} + +type_init(microbit_machine_init);