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Tue, 09 Jul 2019 11:22:05 -0700 (PDT) From: Chuanhong Guo To: linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list), linux-mips@vger.kernel.org (open list:MIPS), devel@driverdev.osuosl.org (open list:STAGING SUBSYSTEM) Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , James Hogan , John Crispin , Greg Kroah-Hartman , Weijie Gao , NeilBrown , Chuanhong Guo , Rob Herring Subject: [PATCH 1/5] MIPS: ralink: add dt binding header for mt7621-pll Date: Wed, 10 Jul 2019 02:20:14 +0800 Message-Id: <20190709182018.23193-2-gch981213@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190709182018.23193-1-gch981213@gmail.com> References: <20190709182018.23193-1-gch981213@gmail.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds dt binding header for mediatek,mt7621-pll Signed-off-by: Weijie Gao Signed-off-by: Chuanhong Guo Reviewed-by: Rob Herring --- include/dt-bindings/clock/mt7621-clk.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h diff --git a/include/dt-bindings/clock/mt7621-clk.h b/include/dt-bindings/clock/mt7621-clk.h new file mode 100644 index 000000000000..a29e14ee2efe --- /dev/null +++ b/include/dt-bindings/clock/mt7621-clk.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Weijie Gao + */ + +#ifndef __DT_BINDINGS_MT7621_CLK_H +#define __DT_BINDINGS_MT7621_CLK_H + +#define MT7621_CLK_CPU 0 +#define MT7621_CLK_BUS 1 + +#define MT7621_CLK_MAX 2 + +#endif /* __DT_BINDINGS_MT7621_CLK_H */ From patchwork Tue Jul 9 18:20:15 2019 Content-Type: text/plain; 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Tue, 09 Jul 2019 11:22:12 -0700 (PDT) From: Chuanhong Guo To: linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list), linux-mips@vger.kernel.org (open list:MIPS), devel@driverdev.osuosl.org (open list:STAGING SUBSYSTEM) Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , James Hogan , John Crispin , Greg Kroah-Hartman , Weijie Gao , NeilBrown , Chuanhong Guo Subject: [PATCH 2/5] MIPS: ralink: fix cpu clock of mt7621 and add dt clk devices Date: Wed, 10 Jul 2019 02:20:15 +0800 Message-Id: <20190709182018.23193-3-gch981213@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190709182018.23193-1-gch981213@gmail.com> References: <20190709182018.23193-1-gch981213@gmail.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For a long time the mt7621 uses a fixed cpu clock which causes a problem if the cpu frequency is not 880MHz. This patch fixes the cpu clock calculation and adds the cpu/bus clkdev which will be used in dts. Ported from OpenWrt: c7ca224299 ramips: fix cpu clock of mt7621 and add dt clk devices Signed-off-by: Weijie Gao Signed-off-by: Chuanhong Guo --- arch/mips/include/asm/mach-ralink/mt7621.h | 20 ++++ arch/mips/ralink/mt7621.c | 102 ++++++++++++++------- arch/mips/ralink/timer-gic.c | 4 +- 3 files changed, 93 insertions(+), 33 deletions(-) diff --git a/arch/mips/include/asm/mach-ralink/mt7621.h b/arch/mips/include/asm/mach-ralink/mt7621.h index 65483a4681ab..51a6e51aef3f 100644 --- a/arch/mips/include/asm/mach-ralink/mt7621.h +++ b/arch/mips/include/asm/mach-ralink/mt7621.h @@ -17,6 +17,10 @@ #define SYSC_REG_CHIP_REV 0x0c #define SYSC_REG_SYSTEM_CONFIG0 0x10 #define SYSC_REG_SYSTEM_CONFIG1 0x14 +#define SYSC_REG_CLKCFG0 0x2c +#define SYSC_REG_CUR_CLK_STS 0x44 + +#define MEMC_REG_CPU_PLL 0x648 #define CHIP_REV_PKG_MASK 0x1 #define CHIP_REV_PKG_SHIFT 16 @@ -24,6 +28,22 @@ #define CHIP_REV_VER_SHIFT 8 #define CHIP_REV_ECO_MASK 0xf +#define XTAL_MODE_SEL_MASK 0x7 +#define XTAL_MODE_SEL_SHIFT 6 + +#define CPU_CLK_SEL_MASK 0x3 +#define CPU_CLK_SEL_SHIFT 30 + +#define CUR_CPU_FDIV_MASK 0x1f +#define CUR_CPU_FDIV_SHIFT 8 +#define CUR_CPU_FFRAC_MASK 0x1f +#define CUR_CPU_FFRAC_SHIFT 0 + +#define CPU_PLL_PREDIV_MASK 0x3 +#define CPU_PLL_PREDIV_SHIFT 12 +#define CPU_PLL_FBDIV_MASK 0x7f +#define CPU_PLL_FBDIV_SHIFT 4 + #define MT7621_DRAM_BASE 0x0 #define MT7621_DDR2_SIZE_MIN 32 #define MT7621_DDR2_SIZE_MAX 256 diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c index 9415be0d57b8..31158b88bcb6 100644 --- a/arch/mips/ralink/mt7621.c +++ b/arch/mips/ralink/mt7621.c @@ -7,22 +7,22 @@ #include #include +#include +#include +#include +#include #include #include #include #include #include +#include #include #include "common.h" -#define SYSC_REG_SYSCFG 0x10 -#define SYSC_REG_CPLL_CLKCFG0 0x2c -#define SYSC_REG_CUR_CLK_STS 0x44 -#define CPU_CLK_SEL (BIT(30) | BIT(31)) - #define MT7621_GPIO_MODE_UART1 1 #define MT7621_GPIO_MODE_I2C 2 #define MT7621_GPIO_MODE_UART3_MASK 0x3 @@ -108,49 +108,89 @@ static struct rt2880_pmx_group mt7621_pinmux_data[] = { { 0 } }; +static struct clk *clks[MT7621_CLK_MAX]; +static struct clk_onecell_data clk_data = { + .clks = clks, + .clk_num = ARRAY_SIZE(clks), +}; + phys_addr_t mips_cpc_default_phys_base(void) { panic("Cannot detect cpc address"); } +static struct clk *__init mt7621_add_sys_clkdev( + const char *id, unsigned long rate) +{ + struct clk *clk; + int err; + + clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate); + if (IS_ERR(clk)) + panic("failed to allocate %s clock structure", id); + + err = clk_register_clkdev(clk, id, NULL); + if (err) + panic("unable to register %s clock device", id); + + return clk; +} + void __init ralink_clk_init(void) { - int cpu_fdiv = 0; - int cpu_ffrac = 0; - int fbdiv = 0; - u32 clk_sts, syscfg; - u8 clk_sel = 0, xtal_mode; - u32 cpu_clk; + const static u32 prediv_tbl[] = {0, 1, 2, 2}; + u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac; + u32 pll, prediv, fbdiv; + u32 xtal_clk, cpu_clk, bus_clk; + + syscfg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); + xtal_sel = (syscfg >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK; - if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0) - clk_sel = 1; + clkcfg = rt_sysc_r32(SYSC_REG_CLKCFG0); + clk_sel = (clkcfg >> CPU_CLK_SEL_SHIFT) & CPU_CLK_SEL_MASK; + + curclk = rt_sysc_r32(SYSC_REG_CUR_CLK_STS); + ffiv = (curclk >> CUR_CPU_FDIV_SHIFT) & CUR_CPU_FDIV_MASK; + ffrac = (curclk >> CUR_CPU_FFRAC_SHIFT) & CUR_CPU_FFRAC_MASK; + + if (xtal_sel <= 2) + xtal_clk = 20 * 1000 * 1000; + else if (xtal_sel <= 5) + xtal_clk = 40 * 1000 * 1000; + else + xtal_clk = 25 * 1000 * 1000; switch (clk_sel) { case 0: - clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS); - cpu_fdiv = ((clk_sts >> 8) & 0x1F); - cpu_ffrac = (clk_sts & 0x1F); - cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000; + cpu_clk = 500 * 1000 * 1000; break; - case 1: - fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1; - syscfg = rt_sysc_r32(SYSC_REG_SYSCFG); - xtal_mode = (syscfg >> 6) & 0x7; - if (xtal_mode >= 6) { - /* 25Mhz Xtal */ - cpu_clk = 25 * fbdiv * 1000 * 1000; - } else if (xtal_mode >= 3) { - /* 40Mhz Xtal */ - cpu_clk = 40 * fbdiv * 1000 * 1000; - } else { - /* 20Mhz Xtal */ - cpu_clk = 20 * fbdiv * 1000 * 1000; - } + pll = rt_memc_r32(MEMC_REG_CPU_PLL); + fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK; + prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK; + cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv]; break; + default: + cpu_clk = xtal_clk; } + + cpu_clk = cpu_clk / ffiv * ffrac; + bus_clk = cpu_clk / 4; + + clks[MT7621_CLK_CPU] = mt7621_add_sys_clkdev("cpu", cpu_clk); + clks[MT7621_CLK_BUS] = mt7621_add_sys_clkdev("bus", bus_clk); + + pr_info("CPU Clock: %dMHz\n", cpu_clk / 1000000); + mips_hpt_frequency = cpu_clk / 2; } +static void __init mt7621_clocks_init_dt(struct device_node *np) +{ + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); +} + +CLK_OF_DECLARE(mt7621_clk, "mediatek,mt7621-pll", mt7621_clocks_init_dt); + void __init ralink_of_remap(void) { rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc"); diff --git a/arch/mips/ralink/timer-gic.c b/arch/mips/ralink/timer-gic.c index 944fbe0fc741..9bbaa37a0da1 100644 --- a/arch/mips/ralink/timer-gic.c +++ b/arch/mips/ralink/timer-gic.c @@ -9,14 +9,14 @@ #include #include -#include +#include #include "common.h" void __init plat_time_init(void) { ralink_of_remap(); - + ralink_clk_init(); of_clk_init(NULL); timer_probe(); } From patchwork Tue Jul 9 18:20:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chuanhong Guo X-Patchwork-Id: 11037299 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3D1AC912 for ; Tue, 9 Jul 2019 18:22:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2F2E428815 for ; Tue, 9 Jul 2019 18:22:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 22C3528826; Tue, 9 Jul 2019 18:22:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B89F428815 for ; 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Tue, 09 Jul 2019 11:22:35 -0700 (PDT) From: Chuanhong Guo To: linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list), linux-mips@vger.kernel.org (open list:MIPS), devel@driverdev.osuosl.org (open list:STAGING SUBSYSTEM) Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , James Hogan , John Crispin , Greg Kroah-Hartman , Weijie Gao , NeilBrown , Chuanhong Guo Subject: [PATCH 3/5] dt: bindings: add mt7621-pll dt binding documentation Date: Wed, 10 Jul 2019 02:20:16 +0800 Message-Id: <20190709182018.23193-4-gch981213@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190709182018.23193-1-gch981213@gmail.com> References: <20190709182018.23193-1-gch981213@gmail.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This commit adds device tree binding documentation for MT7621 PLL controller. Signed-off-by: Chuanhong Guo --- .../bindings/clock/mediatek,mt7621-pll.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt new file mode 100644 index 000000000000..05c15062cd20 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt @@ -0,0 +1,19 @@ +Binding for Mediatek MT7621 PLL controller + +The PLL controller provides the 2 main clocks of the SoC: CPU and BUS. + +Required Properties: +- compatible: has to be "mediatek,mt7621-pll" +- #clock-cells: has to be one + +Optional properties: +- clock-output-names: should be "cpu", "bus" + +Example: + pll { + compatible = "mediatek,mt7621-pll", "syscon"; + + #clock-cells = <1>; + clock-output-names = "cpu", "bus"; + }; + From patchwork Tue Jul 9 18:20:17 2019 Content-Type: text/plain; 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Tue, 09 Jul 2019 11:22:43 -0700 (PDT) From: Chuanhong Guo To: linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list), linux-mips@vger.kernel.org (open list:MIPS), devel@driverdev.osuosl.org (open list:STAGING SUBSYSTEM) Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , James Hogan , John Crispin , Greg Kroah-Hartman , Weijie Gao , NeilBrown , Chuanhong Guo Subject: [PATCH 4/5] staging: mt7621-dts: add dt nodes for mt7621-pll Date: Wed, 10 Jul 2019 02:20:17 +0800 Message-Id: <20190709182018.23193-5-gch981213@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190709182018.23193-1-gch981213@gmail.com> References: <20190709182018.23193-1-gch981213@gmail.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This commit adds device-tree node for mt7621-pll and use its clock accordingly. Signed-off-by: Chuanhong Guo --- drivers/staging/mt7621-dts/mt7621.dtsi | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index a4c08110094b..12717f570ceb 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -1,4 +1,5 @@ #include +#include #include / { @@ -27,12 +28,11 @@ serial0 = &uartlite; }; - cpuclock: cpuclock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; + pll: pll { + compatible = "mediatek,mt7621-pll", "syscon"; - /* FIXME: there should be way to detect this */ - clock-frequency = <880000000>; + #clock-cells = <1>; + clock-output-names = "cpu", "bus"; }; sysclock: sysclock@0 { @@ -155,7 +155,6 @@ compatible = "ns16550a"; reg = <0xc00 0x100>; - clocks = <&sysclock>; clock-frequency = <50000000>; interrupt-parent = <&gic>; @@ -172,7 +171,7 @@ compatible = "ralink,mt7621-spi"; reg = <0xb00 0x100>; - clocks = <&sysclock>; + clocks = <&pll MT7621_CLK_BUS>; resets = <&rstctrl 18>; reset-names = "spi"; @@ -372,7 +371,7 @@ timer { compatible = "mti,gic-timer"; interrupts = ; - clocks = <&cpuclock>; + clocks = <&pll MT7621_CLK_CPU>; }; }; From patchwork Tue Jul 9 18:20:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chuanhong Guo X-Patchwork-Id: 11037307 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E361B912 for ; Tue, 9 Jul 2019 18:22:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D27A62882D for ; Tue, 9 Jul 2019 18:22:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C638A28826; Tue, 9 Jul 2019 18:22:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9D19A28826 for ; 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Tue, 09 Jul 2019 11:22:49 -0700 (PDT) From: Chuanhong Guo To: linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list), linux-mips@vger.kernel.org (open list:MIPS), devel@driverdev.osuosl.org (open list:STAGING SUBSYSTEM) Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , James Hogan , John Crispin , Greg Kroah-Hartman , Weijie Gao , NeilBrown , Chuanhong Guo Subject: [PATCH 5/5] staging: mt7621-dts: fix register range of memc node in mt7621.dtsi Date: Wed, 10 Jul 2019 02:20:18 +0800 Message-Id: <20190709182018.23193-6-gch981213@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190709182018.23193-1-gch981213@gmail.com> References: <20190709182018.23193-1-gch981213@gmail.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The memc node from mt7621.dtsi has incorrect register resource. Fix it according to the programming guide. Signed-off-by: Weijie Gao Signed-off-by: Chuanhong Guo --- drivers/staging/mt7621-dts/mt7621.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 12717f570ceb..ac9189276590 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -138,7 +138,7 @@ memc: memc@5000 { compatible = "mtk,mt7621-memc"; - reg = <0x300 0x100>; + reg = <0x5000 0x1000>; }; cpc: cpc@1fbf0000 {