From patchwork Mon Sep 3 21:50:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 10586397 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2383316B1 for ; Mon, 3 Sep 2018 21:50:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1393529183 for ; Mon, 3 Sep 2018 21:50:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 05FE8291B6; Mon, 3 Sep 2018 21:50:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6187029183 for ; Mon, 3 Sep 2018 21:50:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726183AbeIDCMy (ORCPT ); Mon, 3 Sep 2018 22:12:54 -0400 Received: from mail-lj1-f196.google.com ([209.85.208.196]:35124 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727100AbeIDCMy (ORCPT ); Mon, 3 Sep 2018 22:12:54 -0400 Received: by mail-lj1-f196.google.com with SMTP id p10-v6so1454692ljg.2 for ; Mon, 03 Sep 2018 14:50:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SJuFv+lF2yIIAer5KVTofLqD35pnm/sU6RwnGCbRx2M=; b=CvGlONwHxxbyI6lTsJ4VCTtDyUVP7Q6VQIb00iqfuc64cCo5N893tUTcSRit7GlDoo cwDb7mrs0BeF/wBiZzKnyOZgqb86VY9MKCDAMy8wM9oXiU6XPIDYDfiME4dHHlHIyLdl WRQFCyXFc1WQ9GX3cFieGO6ADjnW3vlXCtk+8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SJuFv+lF2yIIAer5KVTofLqD35pnm/sU6RwnGCbRx2M=; b=hI0oxfGLVldSq51NT983bcqz0QbJlax+VJ2rTqh4+mm7woOyNg3cjPO0wHx27nfqxC hfLZ8ymCFM/6cMuHUD6AwL0QnIaPNekhpjBhS7kuU+ZjoHp4M6q24hYwuLqkj0CTwOsH Qf/5BkCnwSArQpQq67N61vXlepx7281Zu12WdNuuWMuStQAFEVqgt7YUBkvnSFyzzocK 0som3uCtZhG7vqEmBzmPS0vIIirOXFG4Rc55gjOGuzagZPc3STOoaN/i0lY1nn88Lek3 2en2k3Czd8gRv+QOWIxIyfkQb1bvxSQj5xqpXnK3K0baDZtw+XcVwejZ2Mb15P2lZSDa Xu6A== X-Gm-Message-State: APzg51BGDF31kZUw2dIMG4YI4FPqIrOkAefGyvc7DNZgWfMelUtrbIt7 MeReqzZmPBJXjovwSV/5/iiiVg== X-Google-Smtp-Source: ANB0VdaFXH38GLKoUZIybTSPe9nU67q6opuqHpfjRpwhgA2iyxxoiDGlsXtI20zFG/+Z3jh4wUJ0iQ== X-Received: by 2002:a2e:291c:: with SMTP id u28-v6mr18207089lje.70.1536011446939; Mon, 03 Sep 2018 14:50:46 -0700 (PDT) Received: from localhost.bredbandsbolaget (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm3665503ljq.72.2018.09.03.14.50.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Sep 2018 14:50:45 -0700 (PDT) From: Linus Walleij To: Mark Brown , linux-spi@vger.kernel.org, Andrzej Hajda , Lorenzo Bianconi Cc: linux-gpio@vger.kernel.org, Rob Herring , Linus Walleij Subject: [PATCH 1/4] spi: core: Allow both TX and RX transfers in 3WIRE Date: Mon, 3 Sep 2018 23:50:32 +0200 Message-Id: <20180903215035.17265-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180903215035.17265-1-linus.walleij@linaro.org> References: <20180903215035.17265-1-linus.walleij@linaro.org> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The SPI message validation code in __spi_validate() is too restrictive on 3WIRE transfers: the core bitbanging code, for example, will gladly switch direction of the line inbetween transfers. Allow 3WIRE messages even if there is both TX and RX transfers in the message. Transfers with TX and RX at the same time will not work however (just one wire after all), so be sure to disallow those. Cc: Andrzej Hajda Cc: Lorenzo Bianconi Signed-off-by: Linus Walleij Acked-by: Lorenzo Bianconi --- drivers/spi/spi.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index ec395a6baf9c..f6f9314e9a18 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -2841,10 +2841,17 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message) list_for_each_entry(xfer, &message->transfers, transfer_list) { if (xfer->rx_buf && xfer->tx_buf) return -EINVAL; - if ((flags & SPI_CONTROLLER_NO_TX) && xfer->tx_buf) - return -EINVAL; - if ((flags & SPI_CONTROLLER_NO_RX) && xfer->rx_buf) - return -EINVAL; + /* + * 3WIRE can indeed do a write message followed by a + * read message, the direction of the line will be + * switched between the two messages. + */ + if (spi->mode & SPI_CONTROLLER_HALF_DUPLEX) { + if ((flags & SPI_CONTROLLER_NO_TX) && xfer->tx_buf) + return -EINVAL; + if ((flags & SPI_CONTROLLER_NO_RX) && xfer->rx_buf) + return -EINVAL; + } } } From patchwork Mon Sep 3 21:50:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 10586399 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ADE3816B1 for ; Mon, 3 Sep 2018 21:50:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9DB5F29183 for ; Mon, 3 Sep 2018 21:50:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 92123291B6; Mon, 3 Sep 2018 21:50:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3321729183 for ; Mon, 3 Sep 2018 21:50:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727212AbeIDCM5 (ORCPT ); Mon, 3 Sep 2018 22:12:57 -0400 Received: from mail-lf1-f68.google.com ([209.85.167.68]:45629 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727100AbeIDCM5 (ORCPT ); Mon, 3 Sep 2018 22:12:57 -0400 Received: by mail-lf1-f68.google.com with SMTP id r4-v6so1319556lff.12 for ; Mon, 03 Sep 2018 14:50:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=z0JAMZTPBOk70wPnOcW/n1U02PRHWoOYXYXqO3F0FD0=; b=aHquJOgXggxxFbce46YP+0HD7iSUp/9NaeGHmZ2MsYFJhU5gYZj1Fy3fKTAoinG4fu 3rY9J/NvopLU15xRvx2y1dcFTjWZQDdDgQkXmYNEKKl0aqv8EZfi47dREiJVA88BWRH/ otGajQAsE+Rt6s+sVHqQnlMj0wnlAB/AfM1wA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=z0JAMZTPBOk70wPnOcW/n1U02PRHWoOYXYXqO3F0FD0=; b=ibOasMNyz62+MoFO+XnNhUNjH2VYPqpHjzyqw6u1LXI5V7QciZMEj/sl7rcX7PbwAS 9IWnwC2tYnVRFbT3LY25ke/Puvn2XBWL1qXdKuaVUhcCIA7EdQ+GD5f7RSG85hZn0/0X m/e6fGEXguT5/9WqTirfWO/8fen5WvlTg/b0LXr39ZIHOo4VGzMoYponMiCtMpv9vZSw Osm/+JofWpV0cxpPLPmtZZiMX9gePAHUhSzaTc8P2Hw2qSGyP10nLpxHqO7eKXq4OuGr Jl3Pa5dVqgT+76t0PmaZg0/6/hIhRhgj1uemyKhx5Oc59vgzZolq1e3wUCOEGDOYjgXc BomA== X-Gm-Message-State: APzg51DdPo4TeL3bPiztLtDOoxEpyAIN0Wbyx6ZxH7uyPQ6tPIaFwbTK fwcLh1jTyqisibpFrWShzBklDw== X-Google-Smtp-Source: ANB0VdaNCeF7K0TCWXcJANbHg6umPmAytkL24kL374q8KEfvtze4i3prte18z+flRzM20xc2+AUbnA== X-Received: by 2002:a19:8c8:: with SMTP id 191-v6mr984383lfi.152.1536011449766; Mon, 03 Sep 2018 14:50:49 -0700 (PDT) Received: from localhost.bredbandsbolaget (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm3665503ljq.72.2018.09.03.14.50.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Sep 2018 14:50:48 -0700 (PDT) From: Linus Walleij To: Mark Brown , linux-spi@vger.kernel.org, Andrzej Hajda , Lorenzo Bianconi Cc: linux-gpio@vger.kernel.org, Rob Herring , Linus Walleij Subject: [PATCH 2/4] spi: gpio: Fix reading for 3WIRE Date: Mon, 3 Sep 2018 23:50:33 +0200 Message-Id: <20180903215035.17265-3-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180903215035.17265-1-linus.walleij@linaro.org> References: <20180903215035.17265-1-linus.walleij@linaro.org> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If he GPIO bitbanged host is registered using just one line, MISO, naturally the DT parser will flag the host as SPI_MASTER_NO_RX. This makes the GPIO SPI driver assign word transfer functions that enforce the SPI master flags SPI_MASTER_NO_RX (or SPI_MASTER_NO_TX) to the flags on each call down to the inlined bitbang functions such as bitbang_txrx_be_cpha0(). In the 3WIRE case, enforcing this flag is wrong, because the master can then do both TX and RX (albeit not at the same time) using the same line, by just switching the direction of the line and keep clocking in bits. Augment spi_gpio_spec_txrx_word_mode[0123] to account for this. Cc: Andrzej Hajda Cc: Lorenzo Bianconi Signed-off-by: Linus Walleij Acked-by: Lorenzo Bianconi --- drivers/spi/spi-gpio.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-gpio.c b/drivers/spi/spi-gpio.c index 9f4882f82c3c..6bd692304b92 100644 --- a/drivers/spi/spi-gpio.c +++ b/drivers/spi/spi-gpio.c @@ -183,33 +183,42 @@ static u32 spi_gpio_txrx_word_mode3(struct spi_device *spi, * speed in the generic case (when both MISO and MOSI lines are * available), as optimiser will remove the checks when argument is * constant. + * + * A special kludge is needed for 3WIRE SPI, as this mode can use + * the same line for RX and TX and should not enforce the host + * flag - we will just switch MISO from output to input mode when + * needed. */ static u32 spi_gpio_spec_txrx_word_mode0(struct spi_device *spi, unsigned nsecs, u32 word, u8 bits, unsigned flags) { - flags = spi->master->flags; + if (!(spi->mode & SPI_3WIRE)) + flags = spi->master->flags; return bitbang_txrx_be_cpha0(spi, nsecs, 0, flags, word, bits); } static u32 spi_gpio_spec_txrx_word_mode1(struct spi_device *spi, unsigned nsecs, u32 word, u8 bits, unsigned flags) { - flags = spi->master->flags; + if (!(spi->mode & SPI_3WIRE)) + flags = spi->master->flags; return bitbang_txrx_be_cpha1(spi, nsecs, 0, flags, word, bits); } static u32 spi_gpio_spec_txrx_word_mode2(struct spi_device *spi, unsigned nsecs, u32 word, u8 bits, unsigned flags) { - flags = spi->master->flags; + if (!(spi->mode & SPI_3WIRE)) + flags = spi->master->flags; return bitbang_txrx_be_cpha0(spi, nsecs, 1, flags, word, bits); } static u32 spi_gpio_spec_txrx_word_mode3(struct spi_device *spi, unsigned nsecs, u32 word, u8 bits, unsigned flags) { - flags = spi->master->flags; + if (!(spi->mode & SPI_3WIRE)) + flags = spi->master->flags; return bitbang_txrx_be_cpha1(spi, nsecs, 1, flags, word, bits); } From patchwork Mon Sep 3 21:50:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 10586401 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8BDA116B1 for ; Mon, 3 Sep 2018 21:50:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7CA9229183 for ; Mon, 3 Sep 2018 21:50:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 711A0291B6; Mon, 3 Sep 2018 21:50:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1F15129183 for ; Mon, 3 Sep 2018 21:50:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727272AbeIDCNA (ORCPT ); Mon, 3 Sep 2018 22:13:00 -0400 Received: from mail-lf1-f66.google.com ([209.85.167.66]:44732 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727273AbeIDCNA (ORCPT ); Mon, 3 Sep 2018 22:13:00 -0400 Received: by mail-lf1-f66.google.com with SMTP id g6-v6so1328558lfb.11 for ; Mon, 03 Sep 2018 14:50:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NodyPtFTeyWEqtACo59e0OsLQRfFpgaLAwpAkqdVh9c=; b=dKtzxHPsEj783dvFuI26g6H1d3l0IHeNIU65d0oADpClRY1sZj5bdfAekrJPb2cSqJ +4xfDUDVA3rJiPbfj6R1Rj9bUR/yxekLs2ysFvO6EctxGDazBFxQu27N0GdBLnPoQjCR 647Vl/R3iET6+9iASe5UUKl7dftarvGzSkmI4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NodyPtFTeyWEqtACo59e0OsLQRfFpgaLAwpAkqdVh9c=; b=qyCVH+p2ciANNAI9ogKsA2eBsJS09zmji2vQgosvVLyECUMUly54Z3bojfkMXS9M4/ zdsbsg17aEnmn5dk1dwlxtxN2BZJ0Uahu+/ij3fgJMpWqFaRdLG4bNtmSZFojZ+rM6BC 9x7RQXW94Iq6b0CRuT59ll2SSfVLjbic3yhnlUuOSLrUvUlTx3PysUefRcBNPs4YpT5k 7lD+iJgJgAenSAAQJa5snUgT+4meD1sVj0KeAbg98yU5aRKbUlpbuRXlqlGnAkUr7twj UxFKP2CtdYIRKFdTsYpkfQcki+CFRus7rME/2T35tUyw6GaWq2ORSM1lIckuKRriIHP/ puag== X-Gm-Message-State: APzg51DBcS9p5yoCV2+6NnPd7ECI3Kp90Y3dhMdRG9W0COtEZorHyWuZ 9HvT1fzyYjJviOK8h0GvKcQdQA== X-Google-Smtp-Source: ANB0VdavQV9FMtV7rA/3SAdYf++XYfxmq750of/fsnBJbwCemaekUPAEJsIqdub96bz5d5zCjzZSkQ== X-Received: by 2002:a19:d98f:: with SMTP id s15-v6mr19675822lfi.103.1536011452622; Mon, 03 Sep 2018 14:50:52 -0700 (PDT) Received: from localhost.bredbandsbolaget (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm3665503ljq.72.2018.09.03.14.50.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Sep 2018 14:50:51 -0700 (PDT) From: Linus Walleij To: Mark Brown , linux-spi@vger.kernel.org, Andrzej Hajda , Lorenzo Bianconi Cc: linux-gpio@vger.kernel.org, Rob Herring , Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH 3/4] spi: Add a DT binding for high impedance turnaround Date: Mon, 3 Sep 2018 23:50:34 +0200 Message-Id: <20180903215035.17265-4-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180903215035.17265-1-linus.walleij@linaro.org> References: <20180903215035.17265-1-linus.walleij@linaro.org> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some 3WIRE SPI devices require the host to insert a "high impedance turnaround" essentially a clock pulse after switching the one line from output to input. This is needed to support the TPO TPG110 panel to use the 3WIRE SPI bindings. Cc: devicetree@vger.kernel.org Cc: Andrzej Hajda Cc: Lorenzo Bianconi Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/spi/spi-bus.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt index 1f6e86f787ef..ee08be2894eb 100644 --- a/Documentation/devicetree/bindings/spi/spi-bus.txt +++ b/Documentation/devicetree/bindings/spi/spi-bus.txt @@ -70,6 +70,10 @@ All slave nodes can contain the following optional properties: - spi-cs-high - Empty property indicating device requires chip select active high. - spi-3wire - Empty property indicating device requires 3-wire mode. +- spi-3wire-high-impedance-turnaround - Empty property indicating that a + 3wire host need to insert a high impedance turn-around + clock cycle after turning the one output line into an + input line. - spi-lsb-first - Empty property indicating device requires LSB first mode. - spi-tx-bus-width - The bus width (number of data wires) that is used for MOSI. Defaults to 1 if not present. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm3665503ljq.72.2018.09.03.14.50.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Sep 2018 14:50:54 -0700 (PDT) From: Linus Walleij To: Mark Brown , linux-spi@vger.kernel.org, Andrzej Hajda , Lorenzo Bianconi Cc: linux-gpio@vger.kernel.org, Rob Herring , Linus Walleij Subject: [PATCH 4/4] spi: gpio: Support 3WIRE high impedance turn-around Date: Mon, 3 Sep 2018 23:50:35 +0200 Message-Id: <20180903215035.17265-5-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180903215035.17265-1-linus.walleij@linaro.org> References: <20180903215035.17265-1-linus.walleij@linaro.org> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some devices such as the TPO TPG110 display panel require a "high impedance turnaround", in effect a clock cycle after switching the line from output to input mode. Support this in the GPIO driver to begin with. Other driver may implement it if they can, it is unclear if this can be achieved with anything else than GPIO bit-banging. Cc: Andrzej Hajda Cc: Lorenzo Bianconi Signed-off-by: Linus Walleij Acked-by: Lorenzo Bianconi --- drivers/spi/spi-gpio.c | 24 +++++++++++++++++++++--- drivers/spi/spi.c | 2 ++ include/linux/spi/spi.h | 1 + 3 files changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-gpio.c b/drivers/spi/spi-gpio.c index 6bd692304b92..36e481ad38f7 100644 --- a/drivers/spi/spi-gpio.c +++ b/drivers/spi/spi-gpio.c @@ -265,11 +265,29 @@ static int spi_gpio_setup(struct spi_device *spi) static int spi_gpio_set_direction(struct spi_device *spi, bool output) { struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi); + int ret; if (output) return gpiod_direction_output(spi_gpio->mosi, 1); - else - return gpiod_direction_input(spi_gpio->mosi); + + ret = gpiod_direction_input(spi_gpio->mosi); + if (ret) + return ret; + /* + * Send a turnaround high impedance cycle when switching + * from output to input. Theoretically there should be + * a clock delay here, but as has been noted above, the + * nsec delay function for bit-banged GPIO is simply + * {} because bit-banging just doesn't get fast enough + * anyway. + */ + if (spi->mode & SPI_3WIRE_HIZ) { + gpiod_set_value_cansleep(spi_gpio->sck, + !(spi->mode & SPI_CPOL)); + gpiod_set_value_cansleep(spi_gpio->sck, + !!(spi->mode & SPI_CPOL)); + } + return 0; } static void spi_gpio_cleanup(struct spi_device *spi) @@ -417,7 +435,7 @@ static int spi_gpio_probe(struct platform_device *pdev) return status; master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); - master->mode_bits = SPI_3WIRE | SPI_CPHA | SPI_CPOL; + master->mode_bits = SPI_3WIRE | SPI_3WIRE_HIZ | SPI_CPHA | SPI_CPOL; master->flags = master_flags; master->bus_num = pdev->id; /* The master needs to think there is a chipselect even if not connected */ diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index f6f9314e9a18..97159cedd6dd 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -1559,6 +1559,8 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, spi->mode |= SPI_CS_HIGH; if (of_property_read_bool(nc, "spi-3wire")) spi->mode |= SPI_3WIRE; + if (of_property_read_bool(nc, "spi-3wire-high-impedance-turnaround")) + spi->mode |= SPI_3WIRE_HIZ; if (of_property_read_bool(nc, "spi-lsb-first")) spi->mode |= SPI_LSB_FIRST; diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index a64235e05321..b58aaf4a4e4b 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -163,6 +163,7 @@ struct spi_device { #define SPI_TX_QUAD 0x200 /* transmit with 4 wires */ #define SPI_RX_DUAL 0x400 /* receive with 2 wires */ #define SPI_RX_QUAD 0x800 /* receive with 4 wires */ +#define SPI_3WIRE_HIZ 0x1000 /* high impedance turnaround */ int irq; void *controller_state; void *controller_data;