From patchwork Tue Jul 30 18:42:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helen Mae Koike Fornazier X-Patchwork-Id: 11066509 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 45FA11823 for ; Tue, 30 Jul 2019 18:45:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3B5E828847 for ; Tue, 30 Jul 2019 18:45:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2F3F828875; Tue, 30 Jul 2019 18:45:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CC8DD2886B for ; Tue, 30 Jul 2019 18:45:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=lDeQvmWA0X4C0mzgXctsSUjifqumwL34Xa2Gqr6h3tg=; b=N1OGGB8o6AJIR/ cZDr88katU+VPb+zBb/APfkMUKi4HftC6cUJLz2YIw1Y6u0yzjQvhohe29IYXJf/x1V2vEu7Yy13e z80l8CtMuWVTkZwawArEaedXkJXkipaZeS14hq8HytiKZjsxyq3Ljo9DTfs9Q7JcUrvkYG8YEyba/ 72/XupkZKKD/58PhmrvgkeThrNX0WMRcDfhnHlFGj9PIdSUzhI06j9vGYGxjeLrumFVnYLlo57C0D +g7/mmWCRo3MTkPXSwuHlo6+Iv/y4bZeyMIQPrnCICBSdG9ApQONa5uHu1sK+Jn+s6/bTzVYOl8az SZUaWHkbaQYWqG67d7RA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hsX7M-0003By-AY; Tue, 30 Jul 2019 18:45:00 +0000 Received: from bhuna.collabora.co.uk ([2a00:1098:0:82:1000:25:2eeb:e3e3]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hsX77-0002xa-IL; Tue, 30 Jul 2019 18:44:46 +0000 Received: from floko.floko.floko (unknown [IPv6:2804:431:c7f1:ce2f:ec1:e6e6:2e9f:e76e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: koike) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id 58AC528B914; Tue, 30 Jul 2019 19:44:38 +0100 (BST) From: Helen Koike To: linux-rockchip@lists.infradead.org Subject: [PATCH v8 01/14] media: videodev2.h, v4l2-ioctl: add rkisp1 meta buffer format Date: Tue, 30 Jul 2019 15:42:43 -0300 Message-Id: <20190730184256.30338-2-helen.koike@collabora.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190730184256.30338-1-helen.koike@collabora.com> References: <20190730184256.30338-1-helen.koike@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190730_114445_741554_2CB65E25 X-CRM114-Status: UNSURE ( 9.00 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, eddie.cai.linux@gmail.com, kernel@collabora.com, heiko@sntech.de, jacob2.chen@rock-chips.com, jeffy.chen@rock-chips.com, zyc@rock-chips.com, linux-kernel@vger.kernel.org, tfiga@chromium.org, Helen Koike , hans.verkuil@cisco.com, laurent.pinchart@ideasonboard.com, sakari.ailus@linux.intel.com, zhengsq@rock-chips.com, mchehab@kernel.org, ezequiel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shunqian Zheng Add the Rockchip ISP1 specific processing parameter format V4L2_META_FMT_RK_ISP1_PARAMS and metadata format V4L2_META_FMT_RK_ISP1_STAT_3A for 3A. Signed-off-by: Shunqian Zheng Signed-off-by: Jacob Chen Acked-by: Hans Verkuil [update for upstream] Signed-off-by: Helen Koike Reviewed-by: Laurent Pinchart --- Changes in v8: None Changes in v7: - s/IPU3/RK_ISP1 drivers/media/v4l2-core/v4l2-ioctl.c | 2 ++ include/uapi/linux/videodev2.h | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c index bb5b4926538a..2df20801a299 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c @@ -1330,6 +1330,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_META_FMT_VSP1_HGT: descr = "R-Car VSP1 2-D Histogram"; break; case V4L2_META_FMT_UVC: descr = "UVC Payload Header Metadata"; break; case V4L2_META_FMT_D4XX: descr = "Intel D4xx UVC Metadata"; break; + case V4L2_META_FMT_RK_ISP1_PARAMS: descr = "Rockchip ISP1 3A params"; break; + case V4L2_META_FMT_RK_ISP1_STAT_3A: descr = "Rockchip ISP1 3A statistics"; break; default: /* Compressed formats */ diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 2427bc4d8eba..ae1e375a10d7 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -756,6 +756,10 @@ struct v4l2_pix_format { #define V4L2_META_FMT_UVC v4l2_fourcc('U', 'V', 'C', 'H') /* UVC Payload Header metadata */ #define V4L2_META_FMT_D4XX v4l2_fourcc('D', '4', 'X', 'X') /* D4XX Payload Header metadata */ +/* Vendor specific - used for RK_ISP1 camera sub-system */ +#define V4L2_META_FMT_RK_ISP1_PARAMS v4l2_fourcc('R', 'K', '1', 'P') /* Rockchip ISP1 params */ +#define V4L2_META_FMT_RK_ISP1_STAT_3A v4l2_fourcc('R', 'K', '1', 'S') /* Rockchip ISP1 3A statistics */ + /* priv field value to indicates that subsequent fields are valid. */ #define V4L2_PIX_FMT_PRIV_MAGIC 0xfeedcafe From patchwork Tue Jul 30 18:42:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helen Mae Koike Fornazier X-Patchwork-Id: 11066523 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5731613AC for ; Tue, 30 Jul 2019 18:45:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4B75328592 for ; Tue, 30 Jul 2019 18:45:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3CB73285FB; Tue, 30 Jul 2019 18:45:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DCDB3285C9 for ; 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Tue, 30 Jul 2019 18:45:42 +0000 Received: from bhuna.collabora.co.uk ([46.235.227.227]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hsX7B-0002zS-F2; Tue, 30 Jul 2019 18:44:51 +0000 Received: from floko.floko.floko (unknown [IPv6:2804:431:c7f1:ce2f:ec1:e6e6:2e9f:e76e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: koike) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id 8A69A28B920; Tue, 30 Jul 2019 19:44:43 +0100 (BST) From: Helen Koike To: linux-rockchip@lists.infradead.org Subject: [PATCH v8 02/14] media: doc: add document for rkisp1 meta buffer format Date: Tue, 30 Jul 2019 15:42:44 -0300 Message-Id: <20190730184256.30338-3-helen.koike@collabora.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190730184256.30338-1-helen.koike@collabora.com> References: <20190730184256.30338-1-helen.koike@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190730_114449_780987_15C50585 X-CRM114-Status: GOOD ( 11.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, eddie.cai.linux@gmail.com, kernel@collabora.com, heiko@sntech.de, Jacob Chen , jacob2.chen@rock-chips.com, jeffy.chen@rock-chips.com, zyc@rock-chips.com, linux-kernel@vger.kernel.org, tfiga@chromium.org, Helen Koike , hans.verkuil@cisco.com, laurent.pinchart@ideasonboard.com, sakari.ailus@linux.intel.com, zhengsq@rock-chips.com, mchehab@kernel.org, ezequiel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jacob Chen This commit add document for rkisp1 meta buffer format Signed-off-by: Jacob Chen Acked-by: Hans Verkuil [update for upstream] Signed-off-by: Helen Koike --- Changes in v8: - Add SPDX in the header - Remove emacs configs - Fix doc style Changes in v7: - s/correspond/corresponding - s/use/uses - s/docuemnt/document Documentation/media/uapi/v4l/meta-formats.rst | 2 ++ .../uapi/v4l/pixfmt-meta-rkisp1-params.rst | 23 +++++++++++++++++++ .../uapi/v4l/pixfmt-meta-rkisp1-stat.rst | 22 ++++++++++++++++++ 3 files changed, 47 insertions(+) create mode 100644 Documentation/media/uapi/v4l/pixfmt-meta-rkisp1-params.rst create mode 100644 Documentation/media/uapi/v4l/pixfmt-meta-rkisp1-stat.rst diff --git a/Documentation/media/uapi/v4l/meta-formats.rst b/Documentation/media/uapi/v4l/meta-formats.rst index b10ca9ee3968..5de621fea3cc 100644 --- a/Documentation/media/uapi/v4l/meta-formats.rst +++ b/Documentation/media/uapi/v4l/meta-formats.rst @@ -24,3 +24,5 @@ These formats are used for the :ref:`metadata` interface only. pixfmt-meta-uvc pixfmt-meta-vsp1-hgo pixfmt-meta-vsp1-hgt + pixfmt-meta-rkisp1-params + pixfmt-meta-rkisp1-stat diff --git a/Documentation/media/uapi/v4l/pixfmt-meta-rkisp1-params.rst b/Documentation/media/uapi/v4l/pixfmt-meta-rkisp1-params.rst new file mode 100644 index 000000000000..103b5cb79b7c --- /dev/null +++ b/Documentation/media/uapi/v4l/pixfmt-meta-rkisp1-params.rst @@ -0,0 +1,23 @@ +.. SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +.. _v4l2-meta-fmt-rkisp1-params: + +============================ +V4L2_META_FMT_RK_ISP1_PARAMS +============================ + +Rockchip ISP1 Parameters Data + +Description +=========== + +This format describes input parameters for the Rockchip ISP1. + +It uses c-struct :c:type:`rkisp1_isp_params_cfg`, which is defined in +the ``linux/rkisp1-config.h`` header file. + +The parameters consist of multiple modules. +The module won't be updated if the corresponding bit was not set in module_*_update. + +.. kernel-doc:: include/uapi/linux/rkisp1-config.h + :functions: rkisp1_isp_params_cfg diff --git a/Documentation/media/uapi/v4l/pixfmt-meta-rkisp1-stat.rst b/Documentation/media/uapi/v4l/pixfmt-meta-rkisp1-stat.rst new file mode 100644 index 000000000000..4ad303f96421 --- /dev/null +++ b/Documentation/media/uapi/v4l/pixfmt-meta-rkisp1-stat.rst @@ -0,0 +1,22 @@ +.. SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +.. _v4l2-meta-fmt-rkisp1-stat: + +============================= +V4L2_META_FMT_RK_ISP1_STAT_3A +============================= + + +Rockchip ISP1 Statistics Data + +Description +=========== + +This format describes image color statistics information generated by the Rockchip +ISP1. + +It uses c-struct :c:type:`rkisp1_stat_buffer`, which is defined in +the ``linux/rkisp1-config.h`` header file. + +.. kernel-doc:: include/uapi/linux/rkisp1-config.h + :functions: rkisp1_stat_buffer From patchwork Tue Jul 30 18:42:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helen Mae Koike Fornazier X-Patchwork-Id: 11066541 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6865F13AC for ; Tue, 30 Jul 2019 18:46:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5B7A128892 for ; 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Tue, 30 Jul 2019 19:44:48 +0100 (BST) From: Helen Koike To: linux-rockchip@lists.infradead.org Subject: [PATCH v8 03/14] media: rkisp1: Add user space ABI definitions Date: Tue, 30 Jul 2019 15:42:45 -0300 Message-Id: <20190730184256.30338-4-helen.koike@collabora.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190730184256.30338-1-helen.koike@collabora.com> References: <20190730184256.30338-1-helen.koike@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190730_114455_185823_34A4B7FA X-CRM114-Status: GOOD ( 15.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, eddie.cai.linux@gmail.com, kernel@collabora.com, heiko@sntech.de, jacob2.chen@rock-chips.com, jeffy.chen@rock-chips.com, zyc@rock-chips.com, linux-kernel@vger.kernel.org, tfiga@chromium.org, Helen Koike , hans.verkuil@cisco.com, laurent.pinchart@ideasonboard.com, sakari.ailus@linux.intel.com, zhengsq@rock-chips.com, mchehab@kernel.org, ezequiel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jeffy Chen Add the header for userspace Signed-off-by: Jeffy Chen Signed-off-by: Jacob Chen [update for upstream] Signed-off-by: Helen Koike --- Hi, I don't have the "REF_01 - ISP_user_manual, Rev 2.57" document that was mentioned in previous version, so I'm adding a TODO for now to improve the docs once we collect the information. If Rockchip people could help here it would be great. Thanks Helen Changes in v8: None Changes in v7: - Fix checkpatch errors (lines over 80 and SPDX) - Add TODO to improve docs include/uapi/linux/rkisp1-config.h | 816 +++++++++++++++++++++++++++++ 1 file changed, 816 insertions(+) create mode 100644 include/uapi/linux/rkisp1-config.h diff --git a/include/uapi/linux/rkisp1-config.h b/include/uapi/linux/rkisp1-config.h new file mode 100644 index 000000000000..9ab979bb4adb --- /dev/null +++ b/include/uapi/linux/rkisp1-config.h @@ -0,0 +1,816 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Rockchip isp1 driver + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. + */ + +/* + * TODO: Improve documentation, mostly regarding abbreviation and hardware + * specificities. + */ + +#ifndef _UAPI_RKISP1_CONFIG_H +#define _UAPI_RKISP1_CONFIG_H + +#include +#include + +#define CIFISP_MODULE_DPCC (1 << 0) +#define CIFISP_MODULE_BLS (1 << 1) +#define CIFISP_MODULE_SDG (1 << 2) +#define CIFISP_MODULE_HST (1 << 3) +#define CIFISP_MODULE_LSC (1 << 4) +#define CIFISP_MODULE_AWB_GAIN (1 << 5) +#define CIFISP_MODULE_FLT (1 << 6) +#define CIFISP_MODULE_BDM (1 << 7) +#define CIFISP_MODULE_CTK (1 << 8) +#define CIFISP_MODULE_GOC (1 << 9) +#define CIFISP_MODULE_CPROC (1 << 10) +#define CIFISP_MODULE_AFC (1 << 11) +#define CIFISP_MODULE_AWB (1 << 12) +#define CIFISP_MODULE_IE (1 << 13) +#define CIFISP_MODULE_AEC (1 << 14) +#define CIFISP_MODULE_WDR (1 << 15) +#define CIFISP_MODULE_DPF (1 << 16) +#define CIFISP_MODULE_DPF_STRENGTH (1 << 17) + +#define CIFISP_CTK_COEFF_MAX 0x100 +#define CIFISP_CTK_OFFSET_MAX 0x800 + +#define CIFISP_AE_MEAN_MAX 25 +#define CIFISP_HIST_BIN_N_MAX 16 +#define CIFISP_AFM_MAX_WINDOWS 3 +#define CIFISP_DEGAMMA_CURVE_SIZE 17 + +#define CIFISP_BDM_MAX_TH 0xFF + +/* + * Black level compensation + */ +/* maximum value for horizontal start address */ +#define CIFISP_BLS_START_H_MAX 0x00000FFF +/* maximum value for horizontal stop address */ +#define CIFISP_BLS_STOP_H_MAX 0x00000FFF +/* maximum value for vertical start address */ +#define CIFISP_BLS_START_V_MAX 0x00000FFF +/* maximum value for vertical stop address */ +#define CIFISP_BLS_STOP_V_MAX 0x00000FFF +/* maximum is 2^18 = 262144*/ +#define CIFISP_BLS_SAMPLES_MAX 0x00000012 +/* maximum value for fixed black level */ +#define CIFISP_BLS_FIX_SUB_MAX 0x00000FFF +/* minimum value for fixed black level */ +#define CIFISP_BLS_FIX_SUB_MIN 0xFFFFF000 +/* 13 bit range (signed)*/ +#define CIFISP_BLS_FIX_MASK 0x00001FFF + +/* + * Automatic white balance measurments + */ +#define CIFISP_AWB_MAX_GRID 1 +#define CIFISP_AWB_MAX_FRAMES 7 + +/* + * Gamma out + */ +/* Maximum number of color samples supported */ +#define CIFISP_GAMMA_OUT_MAX_SAMPLES 17 + +/* + * Lens shade correction + */ +#define CIFISP_LSC_GRAD_TBL_SIZE 8 +#define CIFISP_LSC_SIZE_TBL_SIZE 8 +/* + * The following matches the tuning process, + * not the max capabilities of the chip. + * Last value unused. + */ +#define CIFISP_LSC_DATA_TBL_SIZE 290 + +/* + * Histogram calculation + */ +/* Last 3 values unused. */ +#define CIFISP_HISTOGRAM_WEIGHT_GRIDS_SIZE 28 + +/* + * Defect Pixel Cluster Correction + */ +#define CIFISP_DPCC_METHODS_MAX 3 + +/* + * Denoising pre filter + */ +#define CIFISP_DPF_MAX_NLF_COEFFS 17 +#define CIFISP_DPF_MAX_SPATIAL_COEFFS 6 + +/* + * Measurement types + */ +#define CIFISP_STAT_AWB (1 << 0) +#define CIFISP_STAT_AUTOEXP (1 << 1) +#define CIFISP_STAT_AFM_FIN (1 << 2) +#define CIFISP_STAT_HIST (1 << 3) + +enum cifisp_histogram_mode { + CIFISP_HISTOGRAM_MODE_DISABLE, + CIFISP_HISTOGRAM_MODE_RGB_COMBINED, + CIFISP_HISTOGRAM_MODE_R_HISTOGRAM, + CIFISP_HISTOGRAM_MODE_G_HISTOGRAM, + CIFISP_HISTOGRAM_MODE_B_HISTOGRAM, + CIFISP_HISTOGRAM_MODE_Y_HISTOGRAM +}; + +enum cifisp_awb_mode_type { + CIFISP_AWB_MODE_MANUAL, + CIFISP_AWB_MODE_RGB, + CIFISP_AWB_MODE_YCBCR +}; + +enum cifisp_flt_mode { + CIFISP_FLT_STATIC_MODE, + CIFISP_FLT_DYNAMIC_MODE +}; + +/** + * enum cifisp_exp_ctrl_autostop - stop modes + * @CIFISP_EXP_CTRL_AUTOSTOP_0: continuous measurement + * @CIFISP_EXP_CTRL_AUTOSTOP_1: stop measuring after a complete frame + */ +enum cifisp_exp_ctrl_autostop { + CIFISP_EXP_CTRL_AUTOSTOP_0 = 0, + CIFISP_EXP_CTRL_AUTOSTOP_1 = 1, +}; + +/** + * enum cifisp_exp_meas_mode - Exposure measure mode + * @CIFISP_EXP_MEASURING_MODE_0: Y = 16 + 0.25R + 0.5G + 0.1094B + * @CIFISP_EXP_MEASURING_MODE_1: Y = (R + G + B) x (85/256) + */ +enum cifisp_exp_meas_mode { + CIFISP_EXP_MEASURING_MODE_0, + CIFISP_EXP_MEASURING_MODE_1, +}; + +/*---------- PART1: Input Parameters ------------*/ + +struct cifisp_window { + __u16 h_offs; + __u16 v_offs; + __u16 h_size; + __u16 v_size; +} __attribute__ ((packed)); + +/** + * struct cifisp_bls_fixed_val - BLS fixed subtraction values + * + * The values will be subtracted from the sensor + * values. Therefore a negative value means addition instead of subtraction! + * + * @r: Fixed (signed!) subtraction value for Bayer pattern R + * @gr: Fixed (signed!) subtraction value for Bayer pattern Gr + * @gb: Fixed (signed!) subtraction value for Bayer pattern Gb + * @b: Fixed (signed!) subtraction value for Bayer pattern B + */ +struct cifisp_bls_fixed_val { + __s16 r; + __s16 gr; + __s16 gb; + __s16 b; +} __attribute__ ((packed)); + +/** + * struct cifisp_bls_config - Configuration used by black level subtraction + * + * @enable_auto: Automatic mode activated means that the measured values + * are subtracted. Otherwise the fixed subtraction + * values will be subtracted. + * @en_windows: enabled window + * @bls_window1: Measurement window 1 size + * @bls_window2: Measurement window 2 size + * @bls_samples: Set amount of measured pixels for each Bayer position + * (A, B,C and D) to 2^bls_samples. + * @cifisp_bls_fixed_val: Fixed subtraction values + */ +struct cifisp_bls_config { + __u8 enable_auto; + __u8 en_windows; + struct cifisp_window bls_window1; + struct cifisp_window bls_window2; + __u8 bls_samples; + struct cifisp_bls_fixed_val fixed_val; +} __attribute__ ((packed)); + +/** + * struct cifisp_dpcc_methods_config - Methods Configuration used by DPCC + * + * Methods Configuration used by Defect Pixel Cluster Correction + * + * @method: Method enable bits + * @line_thresh: Line threshold + * @line_mad_fac: Line MAD factor + * @pg_fac: Peak gradient factor + * @rnd_thresh: Rank Neighbor Difference threshold + * @rg_fac: Rank gradient factor + */ +struct cifisp_dpcc_methods_config { + __u32 method; + __u32 line_thresh; + __u32 line_mad_fac; + __u32 pg_fac; + __u32 rnd_thresh; + __u32 rg_fac; +} __attribute__ ((packed)); + +/** + * struct cifisp_dpcc_methods_config - Configuration used by DPCC + * + * Configuration used by Defect Pixel Cluster Correction + * + * @mode: dpcc output mode + * @output_mode: whether use hard coded methods + * @set_use: stage1 methods set + * @methods: methods config + * @ro_limits: rank order limits + * @rnd_offs: differential rank offsets for rank neighbor difference + */ +struct cifisp_dpcc_config { + __u32 mode; + __u32 output_mode; + __u32 set_use; + struct cifisp_dpcc_methods_config methods[CIFISP_DPCC_METHODS_MAX]; + __u32 ro_limits; + __u32 rnd_offs; +} __attribute__ ((packed)); + +struct cifisp_gamma_corr_curve { + __u16 gamma_y[CIFISP_DEGAMMA_CURVE_SIZE]; +} __attribute__ ((packed)); + +struct cifisp_gamma_curve_x_axis_pnts { + __u32 gamma_dx0; + __u32 gamma_dx1; +} __attribute__ ((packed)); + +/** + * struct cifisp_gamma_corr_curve - Configuration used by sensor degamma + * + * @curve_x: gamma curve point definition axis for x + * @xa_pnts: x increments + */ +struct cifisp_sdg_config { + struct cifisp_gamma_corr_curve curve_r; + struct cifisp_gamma_corr_curve curve_g; + struct cifisp_gamma_corr_curve curve_b; + struct cifisp_gamma_curve_x_axis_pnts xa_pnts; +} __attribute__ ((packed)); + +/** + * struct cifisp_lsc_config - Configuration used by Lens shading correction + * + * refer to REF_01 for details + */ +struct cifisp_lsc_config { + __u32 r_data_tbl[CIFISP_LSC_DATA_TBL_SIZE]; + __u32 gr_data_tbl[CIFISP_LSC_DATA_TBL_SIZE]; + __u32 gb_data_tbl[CIFISP_LSC_DATA_TBL_SIZE]; + __u32 b_data_tbl[CIFISP_LSC_DATA_TBL_SIZE]; + + __u32 x_grad_tbl[CIFISP_LSC_GRAD_TBL_SIZE]; + __u32 y_grad_tbl[CIFISP_LSC_GRAD_TBL_SIZE]; + + __u32 x_size_tbl[CIFISP_LSC_SIZE_TBL_SIZE]; + __u32 y_size_tbl[CIFISP_LSC_SIZE_TBL_SIZE]; + __u16 config_width; + __u16 config_height; +} __attribute__ ((packed)); + +/** + * struct cifisp_ie_config - Configuration used by image effects + * + * @eff_mat_1: 3x3 Matrix Coefficients for Emboss Effect 1 + * @eff_mat_2: 3x3 Matrix Coefficients for Emboss Effect 2 + * @eff_mat_3: 3x3 Matrix Coefficients for Emboss 3/Sketch 1 + * @eff_mat_4: 3x3 Matrix Coefficients for Sketch Effect 2 + * @eff_mat_5: 3x3 Matrix Coefficients for Sketch Effect 3 + * @eff_tint: Chrominance increment values of tint (used for sepia effect) + */ +struct cifisp_ie_config { + __u16 effect; + __u16 color_sel; + __u16 eff_mat_1; + __u16 eff_mat_2; + __u16 eff_mat_3; + __u16 eff_mat_4; + __u16 eff_mat_5; + __u16 eff_tint; +} __attribute__ ((packed)); + +/** + * struct cifisp_cproc_config - Configuration used by Color Processing + * + * @c_out_range: Chrominance pixel clipping range at output. + * (0 for limit, 1 for full) + * @y_in_range: Luminance pixel clipping range at output. + * @y_out_range: Luminance pixel clipping range at output. + * @contrast: 00~ff, 0.0~1.992 + * @brightness: 80~7F, -128~+127 + * @sat: saturation, 00~FF, 0.0~1.992 + * @hue: 80~7F, -90~+87.188 + */ +struct cifisp_cproc_config { + __u8 c_out_range; + __u8 y_in_range; + __u8 y_out_range; + __u8 contrast; + __u8 brightness; + __u8 sat; + __u8 hue; +} __attribute__ ((packed)); + +/** + * struct cifisp_awb_meas_config - Configuration used by auto white balance + * + * @awb_wnd: white balance measurement window (in pixels) + * (from enum cifisp_awb_mode_type) + * @max_y: only pixels values < max_y contribute to awb measurement, set to 0 + * to disable this feature + * @min_y: only pixels values > min_y contribute to awb measurement + * @max_csum: Chrominance sum maximum value, only consider pixels with Cb+Cr, + * smaller than threshold for awb measurements + * @min_c: Chrominance minimum value, only consider pixels with Cb/Cr + * each greater than threshold value for awb measurements + * @frames: number of frames - 1 used for mean value calculation + * (ucFrames=0 means 1 Frame) + * @awb_ref_cr: reference Cr value for AWB regulation, target for AWB + * @awb_ref_cb: reference Cb value for AWB regulation, target for AWB + */ +struct cifisp_awb_meas_config { + /* + * Note: currently the h and v offsets are mapped to grid offsets + */ + struct cifisp_window awb_wnd; + __u32 awb_mode; + __u8 max_y; + __u8 min_y; + __u8 max_csum; + __u8 min_c; + __u8 frames; + __u8 awb_ref_cr; + __u8 awb_ref_cb; + __u8 enable_ymax_cmp; +} __attribute__ ((packed)); + +/** + * struct cifisp_awb_gain_config - Configuration used by auto white balance gain + * + * out_data_x = ( AWB_GEAIN_X * in_data + 128) >> 8 + */ +struct cifisp_awb_gain_config { + __u16 gain_red; + __u16 gain_green_r; + __u16 gain_blue; + __u16 gain_green_b; +} __attribute__ ((packed)); + +/** + * struct cifisp_flt_config - Configuration used by ISP filtering + * + * @mode: ISP_FILT_MODE register fields (from enum cifisp_flt_mode) + * @grn_stage1: ISP_FILT_MODE register fields + * @chr_h_mode: ISP_FILT_MODE register fields + * @chr_v_mode: ISP_FILT_MODE register fields + * + * refer to REF_01 for details. + */ + +struct cifisp_flt_config { + __u32 mode; + __u8 grn_stage1; + __u8 chr_h_mode; + __u8 chr_v_mode; + __u32 thresh_bl0; + __u32 thresh_bl1; + __u32 thresh_sh0; + __u32 thresh_sh1; + __u32 lum_weight; + __u32 fac_sh1; + __u32 fac_sh0; + __u32 fac_mid; + __u32 fac_bl0; + __u32 fac_bl1; +} __attribute__ ((packed)); + +/** + * struct cifisp_bdm_config - Configuration used by Bayer DeMosaic + * + * @demosaic_th: threshod for bayer demosaicing texture detection + */ +struct cifisp_bdm_config { + __u8 demosaic_th; +} __attribute__ ((packed)); + +/** + * struct cifisp_ctk_config - Configuration used by Cross Talk correction + * + * @coeff: color correction matrix + * @ct_offset_b: offset for the crosstalk correction matrix + */ +struct cifisp_ctk_config { + __u16 coeff0; + __u16 coeff1; + __u16 coeff2; + __u16 coeff3; + __u16 coeff4; + __u16 coeff5; + __u16 coeff6; + __u16 coeff7; + __u16 coeff8; + __u16 ct_offset_r; + __u16 ct_offset_g; + __u16 ct_offset_b; +} __attribute__ ((packed)); + +enum cifisp_goc_mode { + CIFISP_GOC_MODE_LOGARITHMIC, + CIFISP_GOC_MODE_EQUIDISTANT +}; + +/** + * struct cifisp_goc_config - Configuration used by Gamma Out correction + * + * @mode: goc mode (from enum cifisp_goc_mode) + * @gamma_y: gamma out curve y-axis for all color components + */ +struct cifisp_goc_config { + __u32 mode; + __u16 gamma_y[CIFISP_GAMMA_OUT_MAX_SAMPLES]; +} __attribute__ ((packed)); + +/** + * struct cifisp_hst_config - Configuration used by Histogram + * + * @mode: histogram mode (from enum cifisp_histogram_mode) + * @histogram_predivider: process every stepsize pixel, all other pixels are + * skipped + * @meas_window: coordinates of the measure window + * @hist_weight: weighting factor for sub-windows + */ +struct cifisp_hst_config { + __u32 mode; + __u8 histogram_predivider; + struct cifisp_window meas_window; + __u8 hist_weight[CIFISP_HISTOGRAM_WEIGHT_GRIDS_SIZE]; +} __attribute__ ((packed)); + +/** + * struct cifisp_aec_config - Configuration used by Auto Exposure Control + * + * @mode: Exposure measure mode (from enum cifisp_exp_meas_mode) + * @autostop: stop mode (from enum cifisp_exp_ctrl_autostop) + * @meas_window: coordinates of the measure window + */ +struct cifisp_aec_config { + __u32 mode; + __u32 autostop; + struct cifisp_window meas_window; +} __attribute__ ((packed)); + +/** + * struct cifisp_afc_config - Configuration used by Auto Focus Control + * + * @num_afm_win: max CIFISP_AFM_MAX_WINDOWS + * @afm_win: coordinates of the meas window + * @thres: threshold used for minimizing the influence of noise + * @var_shift: the number of bits for the shift operation at the end of the + * calculation chain. + */ +struct cifisp_afc_config { + __u8 num_afm_win; + struct cifisp_window afm_win[CIFISP_AFM_MAX_WINDOWS]; + __u32 thres; + __u32 var_shift; +} __attribute__ ((packed)); + +/** + * enum cifisp_dpf_gain_usage - dpf gain usage + * @CIFISP_DPF_GAIN_USAGE_DISABLED: don't use any gains in preprocessing stage + * @CIFISP_DPF_GAIN_USAGE_NF_GAINS: use only the noise function gains from + * registers DPF_NF_GAIN_R, ... + * @CIFISP_DPF_GAIN_USAGE_LSC_GAINS: use only the gains from LSC module + * @CIFISP_DPF_GAIN_USAGE_NF_LSC_GAINS: use the noise function gains and the + * gains from LSC module + * @CIFISP_DPF_GAIN_USAGE_AWB_GAINS: use only the gains from AWB module + * @CIFISP_DPF_GAIN_USAGE_AWB_LSC_GAINS: use the gains from AWB and LSC module + * @CIFISP_DPF_GAIN_USAGE_MAX: upper border (only for an internal evaluation) + */ +enum cifisp_dpf_gain_usage { + CIFISP_DPF_GAIN_USAGE_DISABLED, + CIFISP_DPF_GAIN_USAGE_NF_GAINS, + CIFISP_DPF_GAIN_USAGE_LSC_GAINS, + CIFISP_DPF_GAIN_USAGE_NF_LSC_GAINS, + CIFISP_DPF_GAIN_USAGE_AWB_GAINS, + CIFISP_DPF_GAIN_USAGE_AWB_LSC_GAINS, + CIFISP_DPF_GAIN_USAGE_MAX +}; + +/** + * enum cifisp_dpf_gain_usage - dpf gain usage + * @CIFISP_DPF_RB_FILTERSIZE_13x9: red and blue filter kernel size 13x9 + * (means 7x5 active pixel) + * @CIFISP_DPF_RB_FILTERSIZE_9x9: red and blue filter kernel size 9x9 + * (means 5x5 active pixel) + */ +enum cifisp_dpf_rb_filtersize { + CIFISP_DPF_RB_FILTERSIZE_13x9, + CIFISP_DPF_RB_FILTERSIZE_9x9, +}; + +/** + * enum cifisp_dpf_nll_scale_mode - dpf noise level scale mode + * @CIFISP_NLL_SCALE_LINEAR: use a linear scaling + * @CIFISP_NLL_SCALE_LOGARITHMIC: use a logarithmic scaling + */ +enum cifisp_dpf_nll_scale_mode { + CIFISP_NLL_SCALE_LINEAR, + CIFISP_NLL_SCALE_LOGARITHMIC, +}; + +/** + * struct cifisp_dpf_nll - Noise level lookup + * + * @coeff: Noise level Lookup coefficient + * @scale_mode: dpf noise level scale mode (from enum cifisp_dpf_nll_scale_mode) + */ +struct cifisp_dpf_nll { + __u16 coeff[CIFISP_DPF_MAX_NLF_COEFFS]; + __u32 scale_mode; +} __attribute__ ((packed)); + +/** + * struct cifisp_dpf_rb_flt - Red blue filter config + * + * @fltsize: The filter size for the red and blue pixels + * (from enum cifisp_dpf_rb_filtersize) + * @spatial_coeff: Spatial weights + * @r_enable: enable filter processing for red pixels + * @b_enable: enable filter processing for blue pixels + */ +struct cifisp_dpf_rb_flt { + __u32 fltsize; + __u8 spatial_coeff[CIFISP_DPF_MAX_SPATIAL_COEFFS]; + __u8 r_enable; + __u8 b_enable; +} __attribute__ ((packed)); + +/** + * struct cifisp_dpf_g_flt - Green filter Configuration + * + * @spatial_coeff: Spatial weights + * @gr_enable: enable filter processing for green pixels in green/red lines + * @gb_enable: enable filter processing for green pixels in green/blue lines + */ +struct cifisp_dpf_g_flt { + __u8 spatial_coeff[CIFISP_DPF_MAX_SPATIAL_COEFFS]; + __u8 gr_enable; + __u8 gb_enable; +} __attribute__ ((packed)); + +/** + * struct cifisp_dpf_gain - Noise function Configuration + * + * @mode: dpf gain usage (from enum cifisp_dpf_gain_usage) + * @nf_r_gain: Noise function Gain that replaces the AWB gain for red pixels + * @nf_b_gain: Noise function Gain that replaces the AWB gain for blue pixels + * @nf_gr_gain: Noise function Gain that replaces the AWB gain + * for green pixels in a red line + * @nf_gb_gain: Noise function Gain that replaces the AWB gain + * for green pixels in a blue line + */ +struct cifisp_dpf_gain { + __u32 mode; + __u16 nf_r_gain; + __u16 nf_b_gain; + __u16 nf_gr_gain; + __u16 nf_gb_gain; +} __attribute__ ((packed)); + +/** + * struct cifisp_dpf_config - Configuration used by De-noising pre-filter + * + * @gain: noise function gain + * @g_flt: green filter config + * @rb_flt: red blue filter config + * @nll: noise level lookup + */ +struct cifisp_dpf_config { + struct cifisp_dpf_gain gain; + struct cifisp_dpf_g_flt g_flt; + struct cifisp_dpf_rb_flt rb_flt; + struct cifisp_dpf_nll nll; +} __attribute__ ((packed)); + +/** + * struct cifisp_dpf_strength_config - strength of the filter + * + * @r: filter strength of the RED filter + * @g: filter strength of the GREEN filter + * @b: filter strength of the BLUE filter + */ +struct cifisp_dpf_strength_config { + __u8 r; + __u8 g; + __u8 b; +} __attribute__ ((packed)); + +/** + * struct cifisp_isp_other_cfg - Parameters for some blocks in rockchip isp1 + * + * @dpcc_config: Defect Pixel Cluster Correction config + * @bls_config: Black Level Subtraction config + * @sdg_config: sensor degamma config + * @lsc_config: Lens Shade config + * @awb_gain_config: Auto White balance gain config + * @flt_config: filter config + * @bdm_config: demosaic config + * @ctk_config: cross talk config + * @goc_config: gamma out config + * @bls_config: black level subtraction config + * @dpf_config: De-noising pre-filter config + * @dpf_strength_config: dpf strength config + * @cproc_config: color process config + * @ie_config: image effects config + */ +struct cifisp_isp_other_cfg { + struct cifisp_dpcc_config dpcc_config; + struct cifisp_bls_config bls_config; + struct cifisp_sdg_config sdg_config; + struct cifisp_lsc_config lsc_config; + struct cifisp_awb_gain_config awb_gain_config; + struct cifisp_flt_config flt_config; + struct cifisp_bdm_config bdm_config; + struct cifisp_ctk_config ctk_config; + struct cifisp_goc_config goc_config; + struct cifisp_dpf_config dpf_config; + struct cifisp_dpf_strength_config dpf_strength_config; + struct cifisp_cproc_config cproc_config; + struct cifisp_ie_config ie_config; +} __attribute__ ((packed)); + +/** + * struct cifisp_isp_meas_cfg - Rockchip ISP1 Measure Parameters + * + * @awb_meas_config: auto white balance config + * @hst_config: histogram config + * @aec_config: auto exposure config + * @afc_config: auto focus config + */ +struct cifisp_isp_meas_cfg { + struct cifisp_awb_meas_config awb_meas_config; + struct cifisp_hst_config hst_config; + struct cifisp_aec_config aec_config; + struct cifisp_afc_config afc_config; +} __attribute__ ((packed)); + +/** + * struct rkisp1_isp_params_cfg - Rockchip ISP1 Input Parameters Meta Data + * + * @module_en_update: mask the enable bits of which module should be updated + * @module_ens: mask the enable value of each module, only update the module + * which correspond bit was set in module_en_update + * @module_cfg_update: mask the config bits of which module should be updated + * @meas: measurement config + * @others: other config + */ +struct rkisp1_isp_params_cfg { + __u32 module_en_update; + __u32 module_ens; + __u32 module_cfg_update; + + struct cifisp_isp_meas_cfg meas; + struct cifisp_isp_other_cfg others; +} __attribute__ ((packed)); + +/*---------- PART2: Measurement Statistics ------------*/ + +/** + * struct cifisp_bls_meas_val - AWB measured values + * + * @cnt: White pixel count, number of "white pixels" found during laster + * measurement + * @mean_y_or_g: Mean value of Y within window and frames, + * Green if RGB is selected. + * @mean_cb_or_b: Mean value of Cb within window and frames, + * Blue if RGB is selected. + * @mean_cr_or_r: Mean value of Cr within window and frames, + * Red if RGB is selected. + */ +struct cifisp_awb_meas { + __u32 cnt; + __u8 mean_y_or_g; + __u8 mean_cb_or_b; + __u8 mean_cr_or_r; +} __attribute__ ((packed)); + +/** + * struct cifisp_awb_stat - statistics automatic white balance data + * + * @awb_mean: Mean measured data + */ +struct cifisp_awb_stat { + struct cifisp_awb_meas awb_mean[CIFISP_AWB_MAX_GRID]; +} __attribute__ ((packed)); + +/** + * struct cifisp_bls_meas_val - BLS measured values + * + * @meas_r: Mean measured value for Bayer pattern R + * @meas_gr: Mean measured value for Bayer pattern Gr + * @meas_gb: Mean measured value for Bayer pattern Gb + * @meas_b: Mean measured value for Bayer pattern B + */ +struct cifisp_bls_meas_val { + __u16 meas_r; + __u16 meas_gr; + __u16 meas_gb; + __u16 meas_b; +} __attribute__ ((packed)); + +/** + * struct cifisp_ae_stat - statistics auto exposure data + * + * @exp_mean: Mean luminance value of block xx + * @bls_val: BLS measured values + * + * Image is divided into 5x5 blocks. + */ +struct cifisp_ae_stat { + __u8 exp_mean[CIFISP_AE_MEAN_MAX]; + struct cifisp_bls_meas_val bls_val; +} __attribute__ ((packed)); + +/** + * struct cifisp_af_meas_val - AF measured values + * + * @sum: sharpness, refer to REF_01 for definition + * @lum: luminance, refer to REF_01 for definition + */ +struct cifisp_af_meas_val { + __u32 sum; + __u32 lum; +} __attribute__ ((packed)); + +/** + * struct cifisp_af_stat - statistics auto focus data + * + * @window: AF measured value of window x + * + * The module measures the sharpness in 3 windows of selectable size via + * register settings(ISP_AFM_*_A/B/C) + */ +struct cifisp_af_stat { + struct cifisp_af_meas_val window[CIFISP_AFM_MAX_WINDOWS]; +} __attribute__ ((packed)); + +/** + * struct cifisp_hist_stat - statistics histogram data + * + * @hist_bins: measured bin counters + * + * Measurement window divided into 25 sub-windows, set + * with ISP_HIST_XXX + */ +struct cifisp_hist_stat { + __u16 hist_bins[CIFISP_HIST_BIN_N_MAX]; +} __attribute__ ((packed)); + +/** + * struct rkisp1_stat_buffer - Rockchip ISP1 Statistics Data + * + * @cifisp_awb_stat: statistics data for automatic white balance + * @cifisp_ae_stat: statistics data for auto exposure + * @cifisp_af_stat: statistics data for auto focus + * @cifisp_hist_stat: statistics histogram data + */ +struct cifisp_stat { + struct cifisp_awb_stat awb; + struct cifisp_ae_stat ae; + struct cifisp_af_stat af; + struct cifisp_hist_stat hist; +} __attribute__ ((packed)); + +/** + * struct rkisp1_stat_buffer - Rockchip ISP1 Statistics Meta Data + * + * @meas_type: measurement types (CIFISP_STAT_ definitions) + * @frame_id: frame ID for sync + * @params: statistics data + */ +struct rkisp1_stat_buffer { + __u32 meas_type; + __u32 frame_id; + struct cifisp_stat params; +} __attribute__ ((packed)); + +#endif /* _UAPI_RKISP1_CONFIG_H */ From patchwork Tue Jul 30 18:42:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helen Mae Koike Fornazier X-Patchwork-Id: 11066545 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ABC7C174A for ; Tue, 30 Jul 2019 18:46:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9F49A28498 for ; Tue, 30 Jul 2019 18:46:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 92A8228872; Tue, 30 Jul 2019 18:46:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by 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helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hsX8w-0005TG-4w; Tue, 30 Jul 2019 18:46:38 +0000 Received: from bhuna.collabora.co.uk ([46.235.227.227]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hsX7M-0003Cw-BN; Tue, 30 Jul 2019 18:45:03 +0000 Received: from floko.floko.floko (unknown [IPv6:2804:431:c7f1:ce2f:ec1:e6e6:2e9f:e76e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: koike) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id 5215228B914; Tue, 30 Jul 2019 19:44:54 +0100 (BST) From: Helen Koike To: linux-rockchip@lists.infradead.org Subject: [PATCH v8 04/14] media: rkisp1: add Rockchip MIPI Synopsys DPHY driver Date: Tue, 30 Jul 2019 15:42:46 -0300 Message-Id: <20190730184256.30338-5-helen.koike@collabora.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190730184256.30338-1-helen.koike@collabora.com> References: <20190730184256.30338-1-helen.koike@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190730_114500_766727_EF889A3B X-CRM114-Status: GOOD ( 19.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, eddie.cai.linux@gmail.com, kernel@collabora.com, heiko@sntech.de, jacob2.chen@rock-chips.com, jeffy.chen@rock-chips.com, zyc@rock-chips.com, linux-kernel@vger.kernel.org, tfiga@chromium.org, Helen Koike , hans.verkuil@cisco.com, laurent.pinchart@ideasonboard.com, sakari.ailus@linux.intel.com, zhengsq@rock-chips.com, mchehab@kernel.org, ezequiel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jacob Chen This commit adds a subdev driver for Rockchip MIPI Synopsys DPHY driver Signed-off-by: Jacob Chen Signed-off-by: Shunqian Zheng Signed-off-by: Tomasz Figa [migrate to phy framework] Signed-off-by: Ezequiel Garcia [update for upstream] Signed-off-by: Helen Koike --- Changes in v8: - Remove boiler plate license text Changes in v7: - Migrate dphy specific code from drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c to drivers/phy/rockchip/phy-rockchip-dphy.c - Drop support for rk3288 - Drop support for dphy txrx - code styling and checkpatch fixes drivers/phy/rockchip/Kconfig | 8 + drivers/phy/rockchip/Makefile | 1 + drivers/phy/rockchip/phy-rockchip-dphy.c | 408 +++++++++++++++++++++++ 3 files changed, 417 insertions(+) create mode 100644 drivers/phy/rockchip/phy-rockchip-dphy.c diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index c454c90cd99e..afd072f135e6 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -9,6 +9,14 @@ config PHY_ROCKCHIP_DP help Enable this to support the Rockchip Display Port PHY. +config PHY_ROCKCHIP_DPHY + tristate "Rockchip MIPI Synopsys DPHY driver" + depends on ARCH_ROCKCHIP && OF + select GENERIC_PHY_MIPI_DPHY + select GENERIC_PHY + help + Enable this to support the Rockchip MIPI Synopsys DPHY. + config PHY_ROCKCHIP_EMMC tristate "Rockchip EMMC PHY Driver" depends on ARCH_ROCKCHIP && OF diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index fd21cbaf40dd..f62e9010bcaf 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o +obj-$(CONFIG_PHY_ROCKCHIP_DPHY) += phy-rockchip-dphy.o obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o diff --git a/drivers/phy/rockchip/phy-rockchip-dphy.c b/drivers/phy/rockchip/phy-rockchip-dphy.c new file mode 100644 index 000000000000..3a29976c2dff --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-dphy.c @@ -0,0 +1,408 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Rockchip MIPI Synopsys DPHY driver + * + * Based on: + * + * Copyright (C) 2016 FuZhou Rockchip Co., Ltd. + * Author: Yakir Yang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RK3399_GRF_SOC_CON9 0x6224 +#define RK3399_GRF_SOC_CON21 0x6254 +#define RK3399_GRF_SOC_CON22 0x6258 +#define RK3399_GRF_SOC_CON23 0x625c +#define RK3399_GRF_SOC_CON24 0x6260 +#define RK3399_GRF_SOC_CON25 0x6264 +#define RK3399_GRF_SOC_STATUS1 0xe2a4 + +#define CLOCK_LANE_HS_RX_CONTROL 0x34 +#define LANE0_HS_RX_CONTROL 0x44 +#define LANE1_HS_RX_CONTROL 0x54 +#define LANE2_HS_RX_CONTROL 0x84 +#define LANE3_HS_RX_CONTROL 0x94 +#define HS_RX_DATA_LANES_THS_SETTLE_CONTROL 0x75 + +#define MAX_DPHY_CLK 8 + +#define PHY_TESTEN_ADDR (0x1 << 16) +#define PHY_TESTEN_DATA (0x0 << 16) +#define PHY_TESTCLK (0x1 << 1) +#define PHY_TESTCLR (0x1 << 0) +#define THS_SETTLE_COUNTER_THRESHOLD 0x04 + +#define HIWORD_UPDATE(val, mask, shift) \ + ((val) << (shift) | (mask) << ((shift) + 16)) + +#define GRF_SOC_CON12 0x0274 + +#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(20) +#define GRF_EDP_REF_CLK_SEL_INTER BIT(4) + +#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21) +#define GRF_EDP_PHY_SIDDQ_ON 0 +#define GRF_EDP_PHY_SIDDQ_OFF BIT(5) + +struct hsfreq_range { + u32 range_h; + u8 cfg_bit; +}; + +static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = { + { 89, 0x00}, { 99, 0x10}, { 109, 0x20}, { 129, 0x01}, + { 139, 0x11}, { 149, 0x21}, { 169, 0x02}, { 179, 0x12}, + { 199, 0x22}, { 219, 0x03}, { 239, 0x13}, { 249, 0x23}, + { 269, 0x04}, { 299, 0x14}, { 329, 0x05}, { 359, 0x15}, + { 399, 0x25}, { 449, 0x06}, { 499, 0x16}, { 549, 0x07}, + { 599, 0x17}, { 649, 0x08}, { 699, 0x18}, { 749, 0x09}, + { 799, 0x19}, { 849, 0x29}, { 899, 0x39}, { 949, 0x0a}, + { 999, 0x1a}, {1049, 0x2a}, {1099, 0x3a}, {1149, 0x0b}, + {1199, 0x1b}, {1249, 0x2b}, {1299, 0x3b}, {1349, 0x0c}, + {1399, 0x1c}, {1449, 0x2c}, {1500, 0x3c} +}; + +static const char * const rk3399_mipidphy_clks[] = { + "dphy-ref", + "dphy-cfg", + "grf", +}; + +enum dphy_reg_id { + GRF_DPHY_RX0_TURNDISABLE = 0, + GRF_DPHY_RX0_FORCERXMODE, + GRF_DPHY_RX0_FORCETXSTOPMODE, + GRF_DPHY_RX0_ENABLE, + GRF_DPHY_RX0_TESTCLR, + GRF_DPHY_RX0_TESTCLK, + GRF_DPHY_RX0_TESTEN, + GRF_DPHY_RX0_TESTDIN, + GRF_DPHY_RX0_TURNREQUEST, + GRF_DPHY_RX0_TESTDOUT, + GRF_DPHY_TX0_TURNDISABLE, + GRF_DPHY_TX0_FORCERXMODE, + GRF_DPHY_TX0_FORCETXSTOPMODE, + GRF_DPHY_TX0_TURNREQUEST, + GRF_DPHY_TX1RX1_TURNDISABLE, + GRF_DPHY_TX1RX1_FORCERXMODE, + GRF_DPHY_TX1RX1_FORCETXSTOPMODE, + GRF_DPHY_TX1RX1_ENABLE, + GRF_DPHY_TX1RX1_MASTERSLAVEZ, + GRF_DPHY_TX1RX1_BASEDIR, + GRF_DPHY_TX1RX1_ENABLECLK, + GRF_DPHY_TX1RX1_TURNREQUEST, + GRF_DPHY_RX1_SRC_SEL, + /* rk3288 only */ + GRF_CON_DISABLE_ISP, + GRF_CON_ISP_DPHY_SEL, + GRF_DSI_CSI_TESTBUS_SEL, + GRF_DVP_V18SEL, + /* below is for rk3399 only */ + GRF_DPHY_RX0_CLK_INV_SEL, + GRF_DPHY_RX1_CLK_INV_SEL, +}; + +struct dphy_reg { + u32 offset; + u32 mask; + u32 shift; +}; + +#define PHY_REG(_offset, _width, _shift) \ + { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, } + +static const struct dphy_reg rk3399_grf_dphy_regs[] = { + [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0), + [GRF_DPHY_RX0_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 10), + [GRF_DPHY_RX1_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 11), + [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 0), + [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 4), + [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 8), + [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 12), + [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 0), + [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 4), + [GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 8), + [GRF_DPHY_TX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 12), + [GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 0), + [GRF_DPHY_TX1RX1_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 4), + [GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 8), + [GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 12), + [GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON24, 4, 0), + [GRF_DPHY_RX1_SRC_SEL] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 4), + [GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 5), + [GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 6), + [GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 7), + [GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3399_GRF_SOC_CON25, 8, 0), + [GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 8), + [GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 9), + [GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 10), + [GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3399_GRF_SOC_STATUS1, 8, 0), +}; + +struct dphy_drv_data { + const char * const *clks; + int num_clks; + const struct hsfreq_range *hsfreq_ranges; + int num_hsfreq_ranges; + const struct dphy_reg *regs; +}; + +struct rockchip_dphy { + struct device *dev; + struct regmap *grf; + const struct dphy_reg *grf_regs; + struct clk_bulk_data clks[MAX_DPHY_CLK]; + + const struct dphy_drv_data *drv_data; + struct phy_configure_opts_mipi_dphy config; +}; + +static inline void write_grf_reg(struct rockchip_dphy *priv, + int index, u8 value) +{ + const struct dphy_reg *reg = &priv->grf_regs[index]; + unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift); + + WARN_ON(!reg->offset); + regmap_write(priv->grf, reg->offset, val); +} + +static void mipidphy0_wr_reg(struct rockchip_dphy *priv, + u8 test_code, u8 test_data) +{ + /* + * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content + * is latched internally as the current test code. Test data is + * programmed internally by rising edge on TESTCLK. + */ + write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1); + write_grf_reg(priv, GRF_DPHY_RX0_TESTDIN, test_code); + write_grf_reg(priv, GRF_DPHY_RX0_TESTEN, 1); + write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 0); + write_grf_reg(priv, GRF_DPHY_RX0_TESTEN, 0); + write_grf_reg(priv, GRF_DPHY_RX0_TESTDIN, test_data); + write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1); +} + +/* should be move to power_on */ +static int mipidphy_rx_stream_on(struct rockchip_dphy *priv) +{ + const struct dphy_drv_data *drv_data = priv->drv_data; + const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges; + struct phy_configure_opts_mipi_dphy *config = &priv->config; + unsigned int i, hsfreq = 0, data_rate_mbps = config->hs_clk_rate; + int num_hsfreq_ranges = drv_data->num_hsfreq_ranges; + + do_div(data_rate_mbps, 1000 * 1000); + + dev_dbg(priv->dev, "%s: lanes %d - data_rate_mbps %u\n", + __func__, config->lanes, data_rate_mbps); + + for (i = 0; i < num_hsfreq_ranges; i++) { + if (hsfreq_ranges[i].range_h >= data_rate_mbps) { + hsfreq = hsfreq_ranges[i].cfg_bit; + break; + } + } + + write_grf_reg(priv, GRF_DPHY_RX0_FORCERXMODE, 0); + write_grf_reg(priv, GRF_DPHY_RX0_FORCETXSTOPMODE, 0); + + /* Disable lan turn around, which is ignored in receive mode */ + write_grf_reg(priv, GRF_DPHY_RX0_TURNREQUEST, 0); + write_grf_reg(priv, GRF_DPHY_RX0_TURNDISABLE, 0xf); + + write_grf_reg(priv, GRF_DPHY_RX0_ENABLE, GENMASK(config->lanes - 1, 0)); + + /* dphy start */ + write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1); + write_grf_reg(priv, GRF_DPHY_RX0_TESTCLR, 1); + usleep_range(100, 150); + write_grf_reg(priv, GRF_DPHY_RX0_TESTCLR, 0); + usleep_range(100, 150); + + /* set clock lane */ + /* HS hsfreq_range & lane 0 settle bypass */ + mipidphy0_wr_reg(priv, CLOCK_LANE_HS_RX_CONTROL, 0); + /* HS RX Control of lane0 */ + mipidphy0_wr_reg(priv, LANE0_HS_RX_CONTROL, hsfreq << 1); + /* HS RX Control of lane1 */ + mipidphy0_wr_reg(priv, LANE1_HS_RX_CONTROL, 0); + /* HS RX Control of lane2 */ + mipidphy0_wr_reg(priv, LANE2_HS_RX_CONTROL, 0); + /* HS RX Control of lane3 */ + mipidphy0_wr_reg(priv, LANE3_HS_RX_CONTROL, 0); + /* HS RX Data Lanes Settle State Time Control */ + mipidphy0_wr_reg(priv, HS_RX_DATA_LANES_THS_SETTLE_CONTROL, + THS_SETTLE_COUNTER_THRESHOLD); + + /* Normal operation */ + mipidphy0_wr_reg(priv, 0x0, 0); + + return 0; +} + +static int rockchip_dphy_configure(struct phy *phy, union phy_configure_opts *opts) +{ + struct rockchip_dphy *priv = phy_get_drvdata(phy); + int ret; + + /* pass with phy_mipi_dphy_get_default_config (with pixel rate?) */ + ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); + if (ret) + return ret; + + memcpy(&priv->config, opts, sizeof(priv->config)); + + return 0; +} + +static int rockchip_dphy_power_on(struct phy *phy) +{ + struct rockchip_dphy *priv = phy_get_drvdata(phy); + int ret; + + ret = clk_bulk_enable(priv->drv_data->num_clks, priv->clks); + if (ret) + return ret; + + return mipidphy_rx_stream_on(priv); +} + +static int rockchip_dphy_power_off(struct phy *phy) +{ + struct rockchip_dphy *priv = phy_get_drvdata(phy); + + clk_bulk_disable(priv->drv_data->num_clks, priv->clks); + return 0; +} + +static int rockchip_dphy_init(struct phy *phy) +{ + struct rockchip_dphy *priv = phy_get_drvdata(phy); + int ret; + + ret = clk_bulk_prepare(priv->drv_data->num_clks, priv->clks); + if (ret) + return ret; + return 0; +} + +static int rockchip_dphy_exit(struct phy *phy) +{ + struct rockchip_dphy *priv = phy_get_drvdata(phy); + + clk_bulk_unprepare(priv->drv_data->num_clks, priv->clks); + return 0; +} + +static const struct phy_ops rockchip_dphy_ops = { + .power_on = rockchip_dphy_power_on, + .power_off = rockchip_dphy_power_off, + .init = rockchip_dphy_init, + .exit = rockchip_dphy_exit, + .configure = rockchip_dphy_configure, + .owner = THIS_MODULE, +}; + +static const struct dphy_drv_data rk3399_mipidphy_drv_data = { + .clks = rk3399_mipidphy_clks, + .num_clks = ARRAY_SIZE(rk3399_mipidphy_clks), + .hsfreq_ranges = rk3399_mipidphy_hsfreq_ranges, + .num_hsfreq_ranges = ARRAY_SIZE(rk3399_mipidphy_hsfreq_ranges), + .regs = rk3399_grf_dphy_regs, +}; + +static const struct of_device_id rockchip_dphy_dt_ids[] = { + { + .compatible = "rockchip,rk3399-mipi-dphy", + .data = &rk3399_mipidphy_drv_data, + }, + {} +}; +MODULE_DEVICE_TABLE(of, rockchip_dphy_dt_ids); + +static int rockchip_dphy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + const struct dphy_drv_data *drv_data; + struct phy_provider *phy_provider; + const struct of_device_id *of_id; + struct rockchip_dphy *priv; + struct regmap *grf; + struct phy *phy; + unsigned int i; + int ret; + + if (!dev->parent || !dev->parent->of_node) + return -ENODEV; + + if (platform_get_resource(pdev, IORESOURCE_MEM, 0)) { + dev_err(&pdev->dev, "Rockchip DPHY driver only suports rx\n"); + return -EINVAL; + } + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + priv->dev = dev; + + grf = syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(grf)) { + grf = syscon_regmap_lookup_by_phandle(dev->of_node, + "rockchip,grf"); + if (IS_ERR(grf)) { + dev_err(dev, "Can't find GRF syscon\n"); + return -ENODEV; + } + } + priv->grf = grf; + + of_id = of_match_device(rockchip_dphy_dt_ids, dev); + if (!of_id) + return -EINVAL; + + drv_data = of_id->data; + priv->grf_regs = drv_data->regs; + priv->drv_data = drv_data; + for (i = 0; i < drv_data->num_clks; i++) + priv->clks[i].id = drv_data->clks[i]; + ret = devm_clk_bulk_get(&pdev->dev, drv_data->num_clks, priv->clks); + if (ret) + return ret; + + phy = devm_phy_create(dev, np, &rockchip_dphy_ops); + if (IS_ERR(phy)) { + dev_err(dev, "failed to create phy\n"); + return PTR_ERR(phy); + } + phy_set_drvdata(phy, priv); + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static struct platform_driver rockchip_dphy_driver = { + .probe = rockchip_dphy_probe, + .driver = { + .name = "rockchip-mipi-dphy", + .of_match_table = rockchip_dphy_dt_ids, + }, +}; +module_platform_driver(rockchip_dphy_driver); + +MODULE_AUTHOR("Ezequiel Garcia "); +MODULE_DESCRIPTION("Rockchip MIPI Synopsys DPHY driver"); +MODULE_LICENSE("Dual MIT/GPL"); From patchwork Tue Jul 30 18:42:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helen Mae Koike Fornazier X-Patchwork-Id: 11066549 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EE0AC912 for ; Tue, 30 Jul 2019 18:47:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DC41628498 for ; Tue, 30 Jul 2019 18:47:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CFE34284D4; Tue, 30 Jul 2019 18:47:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C9EF628856 for ; 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Tue, 30 Jul 2019 18:46:59 +0000 Received: from bhuna.collabora.co.uk ([46.235.227.227]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hsX7S-0003dX-BF; Tue, 30 Jul 2019 18:45:11 +0000 Received: from floko.floko.floko (unknown [IPv6:2804:431:c7f1:ce2f:ec1:e6e6:2e9f:e76e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: koike) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id 8731F28B922; Tue, 30 Jul 2019 19:44:59 +0100 (BST) From: Helen Koike To: linux-rockchip@lists.infradead.org Subject: [PATCH v8 05/14] media: rkisp1: add Rockchip ISP1 subdev driver Date: Tue, 30 Jul 2019 15:42:47 -0300 Message-Id: <20190730184256.30338-6-helen.koike@collabora.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190730184256.30338-1-helen.koike@collabora.com> References: <20190730184256.30338-1-helen.koike@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190730_114507_327461_59BAC104 X-CRM114-Status: GOOD ( 20.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, eddie.cai.linux@gmail.com, kernel@collabora.com, heiko@sntech.de, jacob2.chen@rock-chips.com, jeffy.chen@rock-chips.com, zyc@rock-chips.com, linux-kernel@vger.kernel.org, tfiga@chromium.org, Allon Huang , Jacob Chen , hans.verkuil@cisco.com, laurent.pinchart@ideasonboard.com, sakari.ailus@linux.intel.com, zhengsq@rock-chips.com, mchehab@kernel.org, ezequiel@collabora.com, Helen Koike , linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jacob Chen Add the subdev driver for rockchip isp1. Signed-off-by: Jacob Chen Signed-off-by: Shunqian Zheng Signed-off-by: Yichong Zhong Signed-off-by: Jacob Chen Signed-off-by: Eddie Cai Signed-off-by: Jeffy Chen Signed-off-by: Allon Huang Signed-off-by: Tomasz Figa [fixed unknown entity type / switched to PIXEL_RATE] Signed-off-by: Ezequiel Garcia [update for upstream] Signed-off-by: Helen Koike --- Changes in v8: None Changes in v7: - fixed warning because of unknown entity type - fixed v4l2-compliance errors regarding rkisp1 formats, try formats and default values - fix typo riksp1/rkisp1 - redesign: remove mipi/csi subdevice, sensors connect directly to the isp subdevice in the media topology now. As a consequence, remove the hack in mipidphy_g_mbus_config() where information from the sensor was being propagated through the topology. - From the old dphy: * cache get_remote_sensor() in s_stream * use V4L2_CID_PIXEL_RATE instead of V4L2_CID_LINK_FREQ - Replace stream state with a boolean - code styling and checkpatch fixes - fix stop_stream (return after calling stop, do not reenable the stream) - fix rkisp1_isp_sd_get_selection when V4L2_SUBDEV_FORMAT_TRY is set - fix get format in output (isp_sd->out_fmt.mbus_code was being ignored) - s/intput/input - remove #define sd_to_isp_sd(_sd), add a static inline as it will be reused by the capture drivers/media/platform/rockchip/isp1/rkisp1.c | 1286 +++++++++++++++++ drivers/media/platform/rockchip/isp1/rkisp1.h | 111 ++ 2 files changed, 1397 insertions(+) create mode 100644 drivers/media/platform/rockchip/isp1/rkisp1.c create mode 100644 drivers/media/platform/rockchip/isp1/rkisp1.h diff --git a/drivers/media/platform/rockchip/isp1/rkisp1.c b/drivers/media/platform/rockchip/isp1/rkisp1.c new file mode 100644 index 000000000000..6d0c0ffb5e03 --- /dev/null +++ b/drivers/media/platform/rockchip/isp1/rkisp1.c @@ -0,0 +1,1286 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Rockchip isp1 driver + * + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" +#include "regs.h" + +#define CIF_ISP_INPUT_W_MAX 4032 +#define CIF_ISP_INPUT_H_MAX 3024 +#define CIF_ISP_INPUT_W_MIN 32 +#define CIF_ISP_INPUT_H_MIN 32 +#define CIF_ISP_OUTPUT_W_MAX CIF_ISP_INPUT_W_MAX +#define CIF_ISP_OUTPUT_H_MAX CIF_ISP_INPUT_H_MAX +#define CIF_ISP_OUTPUT_W_MIN CIF_ISP_INPUT_W_MIN +#define CIF_ISP_OUTPUT_H_MIN CIF_ISP_INPUT_H_MIN + +/* + * NOTE: MIPI controller and input MUX are also configured in this file, + * because ISP Subdev is not only describe ISP submodule(input size,format, + * output size, format), but also a virtual route device. + */ + +/* + * There are many variables named with format/frame in below code, + * please see here for their meaning. + * + * Cropping regions of ISP + * + * +---------------------------------------------------------+ + * | Sensor image | + * | +---------------------------------------------------+ | + * | | ISP_ACQ (for black level) | | + * | | in_frm | | + * | | +--------------------------------------------+ | | + * | | | ISP_OUT | | | + * | | | in_crop | | | + * | | | +---------------------------------+ | | | + * | | | | ISP_IS | | | | + * | | | | rkisp1_isp_subdev: out_crop | | | | + * | | | +---------------------------------+ | | | + * | | +--------------------------------------------+ | | + * | +---------------------------------------------------+ | + * +---------------------------------------------------------+ + */ + +static inline struct rkisp1_device *sd_to_isp_dev(struct v4l2_subdev *sd) +{ + return container_of(sd->v4l2_dev, struct rkisp1_device, v4l2_dev); +} + +/* Get sensor by enabled media link */ +static struct v4l2_subdev *get_remote_sensor(struct v4l2_subdev *sd) +{ + struct media_pad *local, *remote; + struct media_entity *sensor_me; + + local = &sd->entity.pads[RKISP1_ISP_PAD_SINK]; + remote = media_entity_remote_pad(local); + if (!remote) { + v4l2_warn(sd, "No link between isp and sensor\n"); + return NULL; + } + + sensor_me = media_entity_remote_pad(local)->entity; + return media_entity_to_v4l2_subdev(sensor_me); +} + +static struct rkisp1_sensor *sd_to_sensor(struct rkisp1_device *dev, + struct v4l2_subdev *sd) +{ + struct rkisp1_sensor *sensor; + + list_for_each_entry(sensor, &dev->sensors, list) + if (sensor->sd == sd) + return sensor; + + return NULL; +} + +/**************** register operations ****************/ + +/* + * Image Stabilization. + * This should only be called when configuring CIF + * or at the frame end interrupt + */ +static void rkisp1_config_ism(struct rkisp1_device *dev) +{ + void __iomem *base = dev->base_addr; + struct v4l2_rect *out_crop = &dev->isp_sdev.out_crop; + u32 val; + + writel(0, base + CIF_ISP_IS_RECENTER); + writel(0, base + CIF_ISP_IS_MAX_DX); + writel(0, base + CIF_ISP_IS_MAX_DY); + writel(0, base + CIF_ISP_IS_DISPLACE); + writel(out_crop->left, base + CIF_ISP_IS_H_OFFS); + writel(out_crop->top, base + CIF_ISP_IS_V_OFFS); + writel(out_crop->width, base + CIF_ISP_IS_H_SIZE); + writel(out_crop->height, base + CIF_ISP_IS_V_SIZE); + + /* IS(Image Stabilization) is always on, working as output crop */ + writel(1, base + CIF_ISP_IS_CTRL); + val = readl(base + CIF_ISP_CTRL); + val |= CIF_ISP_CTRL_ISP_CFG_UPD; + writel(val, base + CIF_ISP_CTRL); +} + +/* + * configure isp blocks with input format, size...... + */ +static int rkisp1_config_isp(struct rkisp1_device *dev) +{ + u32 isp_ctrl = 0, irq_mask = 0, acq_mult = 0, signal = 0; + struct v4l2_rect *out_crop, *in_crop; + void __iomem *base = dev->base_addr; + struct v4l2_mbus_framefmt *in_frm; + struct ispsd_out_fmt *out_fmt; + struct rkisp1_sensor *sensor; + struct ispsd_in_fmt *in_fmt; + + sensor = dev->active_sensor; + in_frm = &dev->isp_sdev.in_frm; + in_fmt = &dev->isp_sdev.in_fmt; + out_fmt = &dev->isp_sdev.out_fmt; + out_crop = &dev->isp_sdev.out_crop; + in_crop = &dev->isp_sdev.in_crop; + + if (in_fmt->fmt_type == FMT_BAYER) { + acq_mult = 1; + if (out_fmt->fmt_type == FMT_BAYER) { + if (sensor->mbus.type == V4L2_MBUS_BT656) + isp_ctrl = + CIF_ISP_CTRL_ISP_MODE_RAW_PICT_ITU656; + else + isp_ctrl = + CIF_ISP_CTRL_ISP_MODE_RAW_PICT; + } else { + writel(CIF_ISP_DEMOSAIC_TH(0xc), + base + CIF_ISP_DEMOSAIC); + + if (sensor->mbus.type == V4L2_MBUS_BT656) + isp_ctrl = CIF_ISP_CTRL_ISP_MODE_BAYER_ITU656; + else + isp_ctrl = CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601; + } + } else if (in_fmt->fmt_type == FMT_YUV) { + acq_mult = 2; + if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) { + isp_ctrl = CIF_ISP_CTRL_ISP_MODE_ITU601; + } else { + if (sensor->mbus.type == V4L2_MBUS_BT656) + isp_ctrl = CIF_ISP_CTRL_ISP_MODE_ITU656; + else + isp_ctrl = CIF_ISP_CTRL_ISP_MODE_ITU601; + + } + + irq_mask |= CIF_ISP_DATA_LOSS; + } + + /* Set up input acquisition properties */ + if (sensor->mbus.type == V4L2_MBUS_BT656 || + sensor->mbus.type == V4L2_MBUS_PARALLEL) { + if (sensor->mbus.flags & V4L2_MBUS_PCLK_SAMPLE_RISING) + signal = CIF_ISP_ACQ_PROP_POS_EDGE; + } + + if (sensor->mbus.type == V4L2_MBUS_PARALLEL) { + if (sensor->mbus.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) + signal |= CIF_ISP_ACQ_PROP_VSYNC_LOW; + + if (sensor->mbus.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) + signal |= CIF_ISP_ACQ_PROP_HSYNC_LOW; + } + + writel(isp_ctrl, base + CIF_ISP_CTRL); + writel(signal | in_fmt->yuv_seq | + CIF_ISP_ACQ_PROP_BAYER_PAT(in_fmt->bayer_pat) | + CIF_ISP_ACQ_PROP_FIELD_SEL_ALL, base + CIF_ISP_ACQ_PROP); + writel(0, base + CIF_ISP_ACQ_NR_FRAMES); + + /* Acquisition Size */ + writel(0, base + CIF_ISP_ACQ_H_OFFS); + writel(0, base + CIF_ISP_ACQ_V_OFFS); + writel(acq_mult * in_frm->width, base + CIF_ISP_ACQ_H_SIZE); + writel(in_frm->height, base + CIF_ISP_ACQ_V_SIZE); + + /* ISP Out Area */ + writel(in_crop->left, base + CIF_ISP_OUT_H_OFFS); + writel(in_crop->top, base + CIF_ISP_OUT_V_OFFS); + writel(in_crop->width, base + CIF_ISP_OUT_H_SIZE); + writel(in_crop->height, base + CIF_ISP_OUT_V_SIZE); + + /* interrupt mask */ + irq_mask |= CIF_ISP_FRAME | CIF_ISP_V_START | CIF_ISP_PIC_SIZE_ERROR | + CIF_ISP_FRAME_IN; + writel(irq_mask, base + CIF_ISP_IMSC); + + if (out_fmt->fmt_type == FMT_BAYER) + rkisp1_params_disable_isp(&dev->params_vdev); + else + rkisp1_params_configure_isp(&dev->params_vdev, in_fmt, + dev->isp_sdev.quantization); + + return 0; +} + +static int rkisp1_config_dvp(struct rkisp1_device *dev) +{ + struct ispsd_in_fmt *in_fmt = &dev->isp_sdev.in_fmt; + void __iomem *base = dev->base_addr; + u32 val, input_sel; + + switch (in_fmt->bus_width) { + case 8: + input_sel = CIF_ISP_ACQ_PROP_IN_SEL_8B_ZERO; + break; + case 10: + input_sel = CIF_ISP_ACQ_PROP_IN_SEL_10B_ZERO; + break; + case 12: + input_sel = CIF_ISP_ACQ_PROP_IN_SEL_12B; + break; + default: + v4l2_err(&dev->v4l2_dev, "Invalid bus width\n"); + return -EINVAL; + } + + val = readl(base + CIF_ISP_ACQ_PROP); + writel(val | input_sel, base + CIF_ISP_ACQ_PROP); + + return 0; +} + +static int rkisp1_config_mipi(struct rkisp1_device *dev) +{ + struct ispsd_in_fmt *in_fmt = &dev->isp_sdev.in_fmt; + struct rkisp1_sensor *sensor = dev->active_sensor; + void __iomem *base = dev->base_addr; + unsigned int lanes; + u32 mipi_ctrl; + + /* + * sensor->mbus is set in isp or d-phy notifier_bound function + */ + switch (sensor->mbus.flags & V4L2_MBUS_CSI2_LANES) { + case V4L2_MBUS_CSI2_4_LANE: + lanes = 4; + break; + case V4L2_MBUS_CSI2_3_LANE: + lanes = 3; + break; + case V4L2_MBUS_CSI2_2_LANE: + lanes = 2; + break; + case V4L2_MBUS_CSI2_1_LANE: + lanes = 1; + break; + default: + return -EINVAL; + } + + mipi_ctrl = CIF_MIPI_CTRL_NUM_LANES(lanes - 1) | + CIF_MIPI_CTRL_SHUTDOWNLANES(0xf) | + CIF_MIPI_CTRL_ERR_SOT_SYNC_HS_SKIP | + CIF_MIPI_CTRL_CLOCKLANE_ENA; + + writel(mipi_ctrl, base + CIF_MIPI_CTRL); + + /* Configure Data Type and Virtual Channel */ + writel(CIF_MIPI_DATA_SEL_DT(in_fmt->mipi_dt) | CIF_MIPI_DATA_SEL_VC(0), + base + CIF_MIPI_IMG_DATA_SEL); + + /* Clear MIPI interrupts */ + writel(~0, base + CIF_MIPI_ICR); + /* + * Disable CIF_MIPI_ERR_DPHY interrupt here temporary for + * isp bus may be dead when switch isp. + */ + writel(CIF_MIPI_FRAME_END | CIF_MIPI_ERR_CSI | CIF_MIPI_ERR_DPHY | + CIF_MIPI_SYNC_FIFO_OVFLW(0x03) | CIF_MIPI_ADD_DATA_OVFLW, + base + CIF_MIPI_IMSC); + + v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev, "\n MIPI_CTRL 0x%08x\n" + " MIPI_IMG_DATA_SEL 0x%08x\n" + " MIPI_STATUS 0x%08x\n" + " MIPI_IMSC 0x%08x\n", + readl(base + CIF_MIPI_CTRL), + readl(base + CIF_MIPI_IMG_DATA_SEL), + readl(base + CIF_MIPI_STATUS), + readl(base + CIF_MIPI_IMSC)); + + return 0; +} + +/* Configure MUX */ +static int rkisp1_config_path(struct rkisp1_device *dev) +{ + struct rkisp1_sensor *sensor = dev->active_sensor; + u32 dpcl = readl(dev->base_addr + CIF_VI_DPCL); + int ret = 0; + + if (sensor->mbus.type == V4L2_MBUS_BT656 || + sensor->mbus.type == V4L2_MBUS_PARALLEL) { + ret = rkisp1_config_dvp(dev); + dpcl |= CIF_VI_DPCL_IF_SEL_PARALLEL; + } else if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) { + ret = rkisp1_config_mipi(dev); + dpcl |= CIF_VI_DPCL_IF_SEL_MIPI; + } + + writel(dpcl, dev->base_addr + CIF_VI_DPCL); + + return ret; +} + +/* Hareware configure Entry */ +static int rkisp1_config_cif(struct rkisp1_device *dev) +{ + u32 cif_id; + int ret; + + v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev, + "SP streaming = %d, MP streaming = %d\n", + dev->stream[RKISP1_STREAM_SP].streaming, + dev->stream[RKISP1_STREAM_MP].streaming); + + cif_id = readl(dev->base_addr + CIF_VI_ID); + v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev, "CIF_ID 0x%08x\n", cif_id); + + ret = rkisp1_config_isp(dev); + if (ret < 0) + return ret; + ret = rkisp1_config_path(dev); + if (ret < 0) + return ret; + rkisp1_config_ism(dev); + + return 0; +} + +/* Mess register operations to stop isp */ +static int rkisp1_isp_stop(struct rkisp1_device *dev) +{ + void __iomem *base = dev->base_addr; + u32 val; + + v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev, + "SP streaming = %d, MP streaming = %d\n", + dev->stream[RKISP1_STREAM_SP].streaming, + dev->stream[RKISP1_STREAM_MP].streaming); + + /* + * ISP(mi) stop in mi frame end -> Stop ISP(mipi) -> + * Stop ISP(isp) ->wait for ISP isp off + */ + /* stop and clear MI, MIPI, and ISP interrupts */ + writel(0, base + CIF_MIPI_IMSC); + writel(~0, base + CIF_MIPI_ICR); + + writel(0, base + CIF_ISP_IMSC); + writel(~0, base + CIF_ISP_ICR); + + writel(0, base + CIF_MI_IMSC); + writel(~0, base + CIF_MI_ICR); + val = readl(base + CIF_MIPI_CTRL); + writel(val & (~CIF_MIPI_CTRL_OUTPUT_ENA), base + CIF_MIPI_CTRL); + /* stop ISP */ + val = readl(base + CIF_ISP_CTRL); + val &= ~(CIF_ISP_CTRL_ISP_INFORM_ENABLE | CIF_ISP_CTRL_ISP_ENABLE); + writel(val, base + CIF_ISP_CTRL); + + val = readl(base + CIF_ISP_CTRL); + writel(val | CIF_ISP_CTRL_ISP_CFG_UPD, base + CIF_ISP_CTRL); + + readx_poll_timeout(readl, base + CIF_ISP_RIS, + val, val & CIF_ISP_OFF, 20, 100); + v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev, + "streaming(MP:%d, SP:%d), MI_CTRL:%x, ISP_CTRL:%x, MIPI_CTRL:%x\n", + dev->stream[RKISP1_STREAM_SP].streaming, + dev->stream[RKISP1_STREAM_MP].streaming, + readl(base + CIF_MI_CTRL), + readl(base + CIF_ISP_CTRL), + readl(base + CIF_MIPI_CTRL)); + + writel(CIF_IRCL_MIPI_SW_RST | CIF_IRCL_ISP_SW_RST, base + CIF_IRCL); + writel(0x0, base + CIF_IRCL); + + return 0; +} + +/* Mess register operations to start isp */ +static int rkisp1_isp_start(struct rkisp1_device *dev) +{ + struct rkisp1_sensor *sensor = dev->active_sensor; + void __iomem *base = dev->base_addr; + u32 val; + + v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev, + "SP streaming = %d, MP streaming = %d\n", + dev->stream[RKISP1_STREAM_SP].streaming, + dev->stream[RKISP1_STREAM_MP].streaming); + + /* Activate MIPI */ + if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) { + val = readl(base + CIF_MIPI_CTRL); + writel(val | CIF_MIPI_CTRL_OUTPUT_ENA, base + CIF_MIPI_CTRL); + } + /* Activate ISP */ + val = readl(base + CIF_ISP_CTRL); + val |= CIF_ISP_CTRL_ISP_CFG_UPD | CIF_ISP_CTRL_ISP_ENABLE | + CIF_ISP_CTRL_ISP_INFORM_ENABLE; + writel(val, base + CIF_ISP_CTRL); + + /* XXX: Is the 1000us too long? + * CIF spec says to wait for sufficient time after enabling + * the MIPI interface and before starting the sensor output. + */ + usleep_range(1000, 1200); + + v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev, + "SP streaming = %d, MP streaming = %d MI_CTRL 0x%08x\n" + " ISP_CTRL 0x%08x MIPI_CTRL 0x%08x\n", + dev->stream[RKISP1_STREAM_SP].streaming, + dev->stream[RKISP1_STREAM_MP].streaming, + readl(base + CIF_MI_CTRL), + readl(base + CIF_ISP_CTRL), + readl(base + CIF_MIPI_CTRL)); + + return 0; +} + +static void rkisp1_config_clk(struct rkisp1_device *dev) +{ + u32 val = CIF_ICCL_ISP_CLK | CIF_ICCL_CP_CLK | CIF_ICCL_MRSZ_CLK | + CIF_ICCL_SRSZ_CLK | CIF_ICCL_JPEG_CLK | CIF_ICCL_MI_CLK | + CIF_ICCL_IE_CLK | CIF_ICCL_MIPI_CLK | CIF_ICCL_DCROP_CLK; + + writel(val, dev->base_addr + CIF_ICCL); +} + +/***************************** isp sub-devs *******************************/ + +static const struct ispsd_in_fmt rkisp1_isp_input_formats[] = { + { + .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, + .fmt_type = FMT_BAYER, + .mipi_dt = CIF_CSI2_DT_RAW10, + .bayer_pat = RAW_BGGR, + .bus_width = 10, + }, { + .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, + .fmt_type = FMT_BAYER, + .mipi_dt = CIF_CSI2_DT_RAW10, + .bayer_pat = RAW_RGGB, + .bus_width = 10, + }, { + .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, + .fmt_type = FMT_BAYER, + .mipi_dt = CIF_CSI2_DT_RAW10, + .bayer_pat = RAW_GBRG, + .bus_width = 10, + }, { + .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, + .fmt_type = FMT_BAYER, + .mipi_dt = CIF_CSI2_DT_RAW10, + .bayer_pat = RAW_GRBG, + .bus_width = 10, + }, { + .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, + .fmt_type = FMT_BAYER, + .mipi_dt = CIF_CSI2_DT_RAW12, + .bayer_pat = RAW_RGGB, + .bus_width = 12, + }, { + .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, + .fmt_type = FMT_BAYER, + .mipi_dt = CIF_CSI2_DT_RAW12, + .bayer_pat = RAW_BGGR, + .bus_width = 12, + }, { + .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, + .fmt_type = FMT_BAYER, + .mipi_dt = CIF_CSI2_DT_RAW12, + .bayer_pat = RAW_GBRG, + .bus_width = 12, + }, { + .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, + .fmt_type = FMT_BAYER, + .mipi_dt = CIF_CSI2_DT_RAW12, + .bayer_pat = RAW_GRBG, + .bus_width = 12, + }, { + .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, + .fmt_type = FMT_BAYER, + .mipi_dt = CIF_CSI2_DT_RAW8, + .bayer_pat = RAW_RGGB, + .bus_width = 8, + }, { + .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, + .fmt_type = FMT_BAYER, + .mipi_dt = CIF_CSI2_DT_RAW8, + .bayer_pat = RAW_BGGR, + .bus_width = 8, + }, { + .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, + .fmt_type = FMT_BAYER, + .mipi_dt = CIF_CSI2_DT_RAW8, + .bayer_pat = RAW_GBRG, + .bus_width = 8, + }, { + .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, + .fmt_type = FMT_BAYER, + .mipi_dt = CIF_CSI2_DT_RAW8, + .bayer_pat = RAW_GRBG, + .bus_width = 8, + }, { + .mbus_code = MEDIA_BUS_FMT_YUYV8_1X16, + .fmt_type = FMT_YUV, + .mipi_dt = CIF_CSI2_DT_YUV422_8b, + .yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR, + .bus_width = 16, + }, { + .mbus_code = MEDIA_BUS_FMT_YVYU8_1X16, + .fmt_type = FMT_YUV, + .mipi_dt = CIF_CSI2_DT_YUV422_8b, + .yuv_seq = CIF_ISP_ACQ_PROP_YCRYCB, + .bus_width = 16, + }, { + .mbus_code = MEDIA_BUS_FMT_UYVY8_1X16, + .fmt_type = FMT_YUV, + .mipi_dt = CIF_CSI2_DT_YUV422_8b, + .yuv_seq = CIF_ISP_ACQ_PROP_CBYCRY, + .bus_width = 16, + }, { + .mbus_code = MEDIA_BUS_FMT_VYUY8_1X16, + .fmt_type = FMT_YUV, + .mipi_dt = CIF_CSI2_DT_YUV422_8b, + .yuv_seq = CIF_ISP_ACQ_PROP_CRYCBY, + .bus_width = 16, + }, +}; + +static const struct ispsd_out_fmt rkisp1_isp_output_formats[] = { + { + .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, + .fmt_type = FMT_YUV, + }, { + .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, + .fmt_type = FMT_BAYER, + }, { + .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, + .fmt_type = FMT_BAYER, + }, { + .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, + .fmt_type = FMT_BAYER, + }, { + .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, + .fmt_type = FMT_BAYER, + }, { + .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, + .fmt_type = FMT_BAYER, + }, { + .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, + .fmt_type = FMT_BAYER, + }, { + .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, + .fmt_type = FMT_BAYER, + }, { + .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, + .fmt_type = FMT_BAYER, + }, { + .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, + .fmt_type = FMT_BAYER, + }, { + .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, + .fmt_type = FMT_BAYER, + }, { + .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, + .fmt_type = FMT_BAYER, + }, { + .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, + .fmt_type = FMT_BAYER, + }, +}; + +static const struct ispsd_in_fmt *find_in_fmt(u32 mbus_code) +{ + unsigned int i, array_size = ARRAY_SIZE(rkisp1_isp_input_formats); + const struct ispsd_in_fmt *fmt; + + for (i = 0; i < array_size; i++) { + fmt = &rkisp1_isp_input_formats[i]; + if (fmt->mbus_code == mbus_code) + return fmt; + } + + return NULL; +} + +static const struct ispsd_out_fmt *find_out_fmt(u32 mbus_code) +{ + unsigned int i, array_size = ARRAY_SIZE(rkisp1_isp_output_formats); + const struct ispsd_out_fmt *fmt; + + for (i = 0; i < array_size; i++) { + fmt = &rkisp1_isp_output_formats[i]; + if (fmt->mbus_code == mbus_code) + return fmt; + } + + return NULL; +} + +static int rkisp1_isp_sd_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + unsigned int i = code->index; + + if ((code->pad != RKISP1_ISP_PAD_SINK) && + (code->pad != RKISP1_ISP_PAD_SOURCE_PATH)) { + if (i > 0) + return -EINVAL; + code->code = MEDIA_BUS_FMT_FIXED; + return 0; + } + + if (code->pad == RKISP1_ISP_PAD_SINK) { + if (i >= ARRAY_SIZE(rkisp1_isp_input_formats)) + return -EINVAL; + code->code = rkisp1_isp_input_formats[i].mbus_code; + } else { + if (i >= ARRAY_SIZE(rkisp1_isp_output_formats)) + return -EINVAL; + code->code = rkisp1_isp_output_formats[i].mbus_code; + } + + return 0; +} + +static int rkisp1_isp_sd_init_config(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg) +{ + struct v4l2_rect *mf_in_crop, *mf_out_crop; + struct v4l2_mbus_framefmt *mf_in, *mf_out; + + mf_in = v4l2_subdev_get_try_format(sd, cfg, RKISP1_ISP_PAD_SINK); + mf_in->width = RKISP1_DEFAULT_WIDTH; + mf_in->height = RKISP1_DEFAULT_HEIGHT; + mf_in->field = V4L2_FIELD_NONE; + mf_in->code = rkisp1_isp_input_formats[0].mbus_code; + + mf_in_crop = v4l2_subdev_get_try_crop(sd, cfg, RKISP1_ISP_PAD_SINK); + mf_in_crop->width = RKISP1_DEFAULT_WIDTH; + mf_in_crop->height = RKISP1_DEFAULT_HEIGHT; + mf_in_crop->left = 0; + mf_in_crop->top = 0; + + mf_out = v4l2_subdev_get_try_format(sd, cfg, + RKISP1_ISP_PAD_SOURCE_PATH); + *mf_out = *mf_in; + mf_out->code = rkisp1_isp_output_formats[0].mbus_code; + mf_out->quantization = V4L2_QUANTIZATION_FULL_RANGE; + + mf_out_crop = v4l2_subdev_get_try_crop(sd, cfg, + RKISP1_ISP_PAD_SOURCE_PATH); + *mf_out_crop = *mf_in_crop; + + return 0; +} + +static int rkisp1_isp_sd_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct rkisp1_isp_subdev *isp_sd = sd_to_isp_sd(sd); + struct v4l2_mbus_framefmt *mf = &fmt->format; + + if ((fmt->pad != RKISP1_ISP_PAD_SINK) && + (fmt->pad != RKISP1_ISP_PAD_SOURCE_PATH)) { + fmt->format.code = MEDIA_BUS_FMT_FIXED; + /* + * NOTE: setting a format here doesn't make much sense + * but v4l2-compliance complains + */ + fmt->format.width = RKISP1_DEFAULT_WIDTH; + fmt->format.height = RKISP1_DEFAULT_HEIGHT; + fmt->format.field = V4L2_FIELD_NONE; + return 0; + } + + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { + mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad); + fmt->format = *mf; + return 0; + } + + if (fmt->pad == RKISP1_ISP_PAD_SINK) { + *mf = isp_sd->in_frm; + } else if (fmt->pad == RKISP1_ISP_PAD_SOURCE_PATH) { + /* format of source pad */ + *mf = isp_sd->in_frm; + mf->code = isp_sd->out_fmt.mbus_code; + /* window size of source pad */ + mf->width = isp_sd->out_crop.width; + mf->height = isp_sd->out_crop.height; + mf->quantization = isp_sd->quantization; + } + mf->field = V4L2_FIELD_NONE; + + return 0; +} + +static void rkisp1_isp_sd_try_fmt(struct v4l2_subdev *sd, + unsigned int pad, + struct v4l2_mbus_framefmt *fmt) +{ + struct rkisp1_device *isp_dev = sd_to_isp_dev(sd); + struct rkisp1_isp_subdev *isp_sd = &isp_dev->isp_sdev; + const struct ispsd_out_fmt *out_fmt; + const struct ispsd_in_fmt *in_fmt; + + switch (pad) { + case RKISP1_ISP_PAD_SINK: + in_fmt = find_in_fmt(fmt->code); + if (in_fmt) + fmt->code = in_fmt->mbus_code; + else + fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10; + fmt->width = clamp_t(u32, fmt->width, CIF_ISP_INPUT_W_MIN, + CIF_ISP_INPUT_W_MAX); + fmt->height = clamp_t(u32, fmt->height, CIF_ISP_INPUT_H_MIN, + CIF_ISP_INPUT_H_MAX); + break; + case RKISP1_ISP_PAD_SOURCE_PATH: + out_fmt = find_out_fmt(fmt->code); + if (out_fmt) + fmt->code = out_fmt->mbus_code; + else + fmt->code = rkisp1_isp_output_formats[0].mbus_code; + /* window size is set in s_selection */ + fmt->width = isp_sd->out_crop.width; + fmt->height = isp_sd->out_crop.height; + /* full range by default */ + if (!fmt->quantization) + fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; + break; + } + + fmt->field = V4L2_FIELD_NONE; +} + +static int rkisp1_isp_sd_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct rkisp1_device *isp_dev = sd_to_isp_dev(sd); + struct rkisp1_isp_subdev *isp_sd = &isp_dev->isp_sdev; + struct v4l2_mbus_framefmt *mf = &fmt->format; + + if ((fmt->pad != RKISP1_ISP_PAD_SINK) && + (fmt->pad != RKISP1_ISP_PAD_SOURCE_PATH)) + return rkisp1_isp_sd_get_fmt(sd, cfg, fmt); + + rkisp1_isp_sd_try_fmt(sd, fmt->pad, mf); + + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { + struct v4l2_mbus_framefmt *try_mf; + + try_mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad); + *try_mf = *mf; + return 0; + } + + if (fmt->pad == RKISP1_ISP_PAD_SINK) { + const struct ispsd_in_fmt *in_fmt; + + in_fmt = find_in_fmt(mf->code); + isp_sd->in_fmt = *in_fmt; + isp_sd->in_frm = *mf; + } else if (fmt->pad == RKISP1_ISP_PAD_SOURCE_PATH) { + const struct ispsd_out_fmt *out_fmt; + + /* Ignore width/height */ + out_fmt = find_out_fmt(mf->code); + isp_sd->out_fmt = *out_fmt; + /* + * It is quantization for output, + * isp use bt601 limit-range in internal + */ + isp_sd->quantization = mf->quantization; + } + + return 0; +} + +static void rkisp1_isp_sd_try_crop(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_selection *sel) +{ + struct rkisp1_isp_subdev *isp_sd = sd_to_isp_sd(sd); + struct v4l2_mbus_framefmt in_frm = isp_sd->in_frm; + struct v4l2_rect in_crop = isp_sd->in_crop; + struct v4l2_rect *input = &sel->r; + + if (sel->which == V4L2_SUBDEV_FORMAT_TRY) { + in_frm = *v4l2_subdev_get_try_format(sd, cfg, + RKISP1_ISP_PAD_SINK); + in_crop = *v4l2_subdev_get_try_crop(sd, cfg, + RKISP1_ISP_PAD_SINK); + } + + input->left = ALIGN(input->left, 2); + input->width = ALIGN(input->width, 2); + + if (sel->pad == RKISP1_ISP_PAD_SINK) { + input->left = clamp_t(u32, input->left, 0, in_frm.width); + input->top = clamp_t(u32, input->top, 0, in_frm.height); + input->width = clamp_t(u32, input->width, CIF_ISP_INPUT_W_MIN, + in_frm.width - input->left); + input->height = clamp_t(u32, input->height, + CIF_ISP_INPUT_H_MIN, + in_frm.height - input->top); + } else if (sel->pad == RKISP1_ISP_PAD_SOURCE_PATH) { + input->left = clamp_t(u32, input->left, 0, in_crop.width); + input->top = clamp_t(u32, input->top, 0, in_crop.height); + input->width = clamp_t(u32, input->width, CIF_ISP_OUTPUT_W_MIN, + in_crop.width - input->left); + input->height = clamp_t(u32, input->height, + CIF_ISP_OUTPUT_H_MIN, + in_crop.height - input->top); + } +} + +static int rkisp1_isp_sd_get_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_selection *sel) +{ + struct rkisp1_isp_subdev *isp_sd = sd_to_isp_sd(sd); + struct v4l2_mbus_framefmt *frm; + struct v4l2_rect *rect; + + if (sel->pad != RKISP1_ISP_PAD_SOURCE_PATH && + sel->pad != RKISP1_ISP_PAD_SINK) + return -EINVAL; + + switch (sel->target) { + case V4L2_SEL_TGT_CROP_BOUNDS: + if (sel->pad == RKISP1_ISP_PAD_SINK) { + if (sel->which == V4L2_SUBDEV_FORMAT_TRY) + frm = v4l2_subdev_get_try_format(sd, cfg, + sel->pad); + else + frm = &isp_sd->in_frm; + + sel->r.height = frm->height; + sel->r.width = frm->width; + sel->r.left = 0; + sel->r.top = 0; + } else { + if (sel->which == V4L2_SUBDEV_FORMAT_TRY) + rect = v4l2_subdev_get_try_crop(sd, cfg, + RKISP1_ISP_PAD_SINK); + else + rect = &isp_sd->in_crop; + sel->r = *rect; + } + break; + case V4L2_SEL_TGT_CROP: + if (sel->which == V4L2_SUBDEV_FORMAT_TRY) + rect = v4l2_subdev_get_try_crop(sd, cfg, sel->pad); + else if (sel->pad == RKISP1_ISP_PAD_SINK) + rect = &isp_sd->in_crop; + else + rect = &isp_sd->out_crop; + sel->r = *rect; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rkisp1_isp_sd_set_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_selection *sel) +{ + struct rkisp1_isp_subdev *isp_sd = sd_to_isp_sd(sd); + struct rkisp1_device *dev = sd_to_isp_dev(sd); + + if (sel->pad != RKISP1_ISP_PAD_SOURCE_PATH && + sel->pad != RKISP1_ISP_PAD_SINK) + return -EINVAL; + if (sel->target != V4L2_SEL_TGT_CROP) + return -EINVAL; + + v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev, + "%s: pad: %d sel(%d,%d)/%dx%d\n", __func__, sel->pad, + sel->r.left, sel->r.top, sel->r.width, sel->r.height); + rkisp1_isp_sd_try_crop(sd, cfg, sel); + + if (sel->which == V4L2_SUBDEV_FORMAT_TRY) { + struct v4l2_rect *try_sel = + v4l2_subdev_get_try_crop(sd, cfg, sel->pad); + + *try_sel = sel->r; + return 0; + } + + if (sel->pad == RKISP1_ISP_PAD_SINK) + isp_sd->in_crop = sel->r; + else + isp_sd->out_crop = sel->r; + + return 0; +} + +static int mipi_csi2_s_stream_start(struct rkisp1_isp_subdev *isp_sd, + struct rkisp1_sensor *sensor) +{ + union phy_configure_opts opts = { 0 }; + struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy; + struct v4l2_ctrl *pixel_rate; + s64 pixel_clock; + + pixel_rate = v4l2_ctrl_find(sensor->sd->ctrl_handler, + V4L2_CID_PIXEL_RATE); + if (!pixel_rate) { + v4l2_warn(sensor->sd, "No pixel rate control in subdev\n"); + return -EPIPE; + } + + pixel_clock = v4l2_ctrl_g_ctrl_int64(pixel_rate); + if (!pixel_clock) { + v4l2_err(sensor->sd, "Invalid pixel rate value\n"); + return -EINVAL; + } + + phy_mipi_dphy_get_default_config(pixel_clock, isp_sd->in_fmt.bus_width, + sensor->lanes, cfg); + phy_set_mode(sensor->dphy, PHY_MODE_MIPI_DPHY); + phy_configure(sensor->dphy, &opts); + phy_power_on(sensor->dphy); + + return 0; +} + +static void mipi_csi2_s_stream_stop(struct rkisp1_sensor *sensor) +{ + phy_power_off(sensor->dphy); +} + +static int rkisp1_isp_sd_s_stream(struct v4l2_subdev *sd, int on) +{ + struct rkisp1_device *isp_dev = sd_to_isp_dev(sd); + struct v4l2_subdev *sensor_sd; + int ret = 0; + + if (!on) { + ret = rkisp1_isp_stop(isp_dev); + if (ret < 0) + return ret; + mipi_csi2_s_stream_stop(isp_dev->active_sensor); + return 0; + } + + sensor_sd = get_remote_sensor(sd); + if (!sensor_sd) + return -ENODEV; + + isp_dev->active_sensor = sd_to_sensor(isp_dev, sensor_sd); + if (!isp_dev->active_sensor) + return -ENODEV; + + atomic_set(&isp_dev->isp_sdev.frm_sync_seq, 0); + ret = rkisp1_config_cif(isp_dev); + if (ret < 0) + return ret; + + /* TODO: support other interfaces */ + if (isp_dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY) + return -EINVAL; + + ret = mipi_csi2_s_stream_start(&isp_dev->isp_sdev, + isp_dev->active_sensor); + if (ret < 0) + return ret; + + ret = rkisp1_isp_start(isp_dev); + if (ret) + mipi_csi2_s_stream_stop(isp_dev->active_sensor); + + return ret; +} + +static int rkisp1_isp_sd_s_power(struct v4l2_subdev *sd, int on) +{ + struct rkisp1_device *isp_dev = sd_to_isp_dev(sd); + int ret; + + v4l2_dbg(1, rkisp1_debug, &isp_dev->v4l2_dev, "s_power: %d\n", on); + + if (on) { + ret = pm_runtime_get_sync(isp_dev->dev); + if (ret < 0) + return ret; + + rkisp1_config_clk(isp_dev); + } else { + ret = pm_runtime_put(isp_dev->dev); + if (ret < 0) + return ret; + } + + return 0; +} + +static int rkisp1_subdev_link_validate(struct media_link *link) +{ + if (link->source->index == RKISP1_ISP_PAD_SINK_PARAMS) + return 0; + + return v4l2_subdev_link_validate(link); +} + +static int rkisp1_subdev_fmt_link_validate(struct v4l2_subdev *sd, + struct media_link *link, + struct v4l2_subdev_format *source_fmt, + struct v4l2_subdev_format *sink_fmt) +{ + if (source_fmt->format.code != sink_fmt->format.code) + return -EINVAL; + + /* Crop is available */ + if (source_fmt->format.width < sink_fmt->format.width || + source_fmt->format.height < sink_fmt->format.height) + return -EINVAL; + + return 0; +} + +static void rkisp1_isp_queue_event_sof(struct rkisp1_isp_subdev *isp) +{ + struct v4l2_event event = { + .type = V4L2_EVENT_FRAME_SYNC, + .u.frame_sync.frame_sequence = + atomic_inc_return(&isp->frm_sync_seq) - 1, + }; + v4l2_event_queue(isp->sd.devnode, &event); +} + +static int rkisp1_isp_sd_subs_evt(struct v4l2_subdev *sd, struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + if (sub->type != V4L2_EVENT_FRAME_SYNC) + return -EINVAL; + + /* Line number. For now only zero accepted. */ + if (sub->id != 0) + return -EINVAL; + + return v4l2_event_subscribe(fh, sub, 0, NULL); +} + +static const struct v4l2_subdev_pad_ops rkisp1_isp_sd_pad_ops = { + .enum_mbus_code = rkisp1_isp_sd_enum_mbus_code, + .get_selection = rkisp1_isp_sd_get_selection, + .set_selection = rkisp1_isp_sd_set_selection, + .init_cfg = rkisp1_isp_sd_init_config, + .get_fmt = rkisp1_isp_sd_get_fmt, + .set_fmt = rkisp1_isp_sd_set_fmt, + .link_validate = rkisp1_subdev_fmt_link_validate, +}; + +static const struct media_entity_operations rkisp1_isp_sd_media_ops = { + .link_validate = rkisp1_subdev_link_validate, +}; + +static const struct v4l2_subdev_video_ops rkisp1_isp_sd_video_ops = { + .s_stream = rkisp1_isp_sd_s_stream, +}; + +static const struct v4l2_subdev_core_ops rkisp1_isp_core_ops = { + .subscribe_event = rkisp1_isp_sd_subs_evt, + .unsubscribe_event = v4l2_event_subdev_unsubscribe, + .s_power = rkisp1_isp_sd_s_power, +}; + +static struct v4l2_subdev_ops rkisp1_isp_sd_ops = { + .core = &rkisp1_isp_core_ops, + .video = &rkisp1_isp_sd_video_ops, + .pad = &rkisp1_isp_sd_pad_ops, +}; + +static void rkisp1_isp_sd_init_default_fmt(struct rkisp1_isp_subdev *isp_sd) +{ + struct v4l2_mbus_framefmt *in_frm = &isp_sd->in_frm; + struct v4l2_rect *in_crop = &isp_sd->in_crop; + struct v4l2_rect *out_crop = &isp_sd->out_crop; + struct ispsd_in_fmt *in_fmt = &isp_sd->in_fmt; + struct ispsd_out_fmt *out_fmt = &isp_sd->out_fmt; + + *in_fmt = rkisp1_isp_input_formats[0]; + in_frm->width = RKISP1_DEFAULT_WIDTH; + in_frm->height = RKISP1_DEFAULT_HEIGHT; + in_frm->code = in_fmt->mbus_code; + + in_crop->width = in_frm->width; + in_crop->height = in_frm->height; + in_crop->left = 0; + in_crop->top = 0; + + /* propagate to source */ + *out_crop = *in_crop; + *out_fmt = rkisp1_isp_output_formats[0]; + isp_sd->quantization = V4L2_QUANTIZATION_FULL_RANGE; +} + +int rkisp1_register_isp_subdev(struct rkisp1_device *isp_dev, + struct v4l2_device *v4l2_dev) +{ + struct rkisp1_isp_subdev *isp_sdev = &isp_dev->isp_sdev; + struct v4l2_subdev *sd = &isp_sdev->sd; + int ret; + + v4l2_subdev_init(sd, &rkisp1_isp_sd_ops); + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; + sd->entity.ops = &rkisp1_isp_sd_media_ops; + snprintf(sd->name, sizeof(sd->name), "rkisp1-isp-subdev"); + + isp_sdev->pads[RKISP1_ISP_PAD_SINK].flags = + MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT; + isp_sdev->pads[RKISP1_ISP_PAD_SINK_PARAMS].flags = MEDIA_PAD_FL_SINK; + isp_sdev->pads[RKISP1_ISP_PAD_SOURCE_PATH].flags = MEDIA_PAD_FL_SOURCE; + isp_sdev->pads[RKISP1_ISP_PAD_SOURCE_STATS].flags = MEDIA_PAD_FL_SOURCE; + sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; + ret = media_entity_pads_init(&sd->entity, RKISP1_ISP_PAD_MAX, + isp_sdev->pads); + if (ret < 0) + return ret; + + sd->owner = THIS_MODULE; + v4l2_set_subdevdata(sd, isp_dev); + + sd->grp_id = GRP_ID_ISP; + ret = v4l2_device_register_subdev(v4l2_dev, sd); + if (ret < 0) { + v4l2_err(sd, "Failed to register isp subdev\n"); + goto err_cleanup_media_entity; + } + + rkisp1_isp_sd_init_default_fmt(isp_sdev); + + return 0; +err_cleanup_media_entity: + media_entity_cleanup(&sd->entity); + return ret; +} + +void rkisp1_unregister_isp_subdev(struct rkisp1_device *isp_dev) +{ + struct v4l2_subdev *sd = &isp_dev->isp_sdev.sd; + + v4l2_device_unregister_subdev(sd); + media_entity_cleanup(&sd->entity); +} + +/**************** Interrupter Handler ****************/ + +void rkisp1_mipi_isr(unsigned int mis, struct rkisp1_device *dev) +{ + struct v4l2_device *v4l2_dev = &dev->v4l2_dev; + void __iomem *base = dev->base_addr; + u32 val; + + writel(~0, base + CIF_MIPI_ICR); + + /* + * Disable DPHY errctrl interrupt, because this dphy + * erctrl signal is asserted until the next changes + * of line state. This time is may be too long and cpu + * is hold in this interrupt. + */ + if (mis & CIF_MIPI_ERR_CTRL(0x0f)) { + val = readl(base + CIF_MIPI_IMSC); + writel(val & ~CIF_MIPI_ERR_CTRL(0x0f), base + CIF_MIPI_IMSC); + dev->isp_sdev.dphy_errctrl_disabled = true; + } + + /* + * Enable DPHY errctrl interrupt again, if mipi have receive + * the whole frame without any error. + */ + if (mis == CIF_MIPI_FRAME_END) { + /* + * Enable DPHY errctrl interrupt again, if mipi have receive + * the whole frame without any error. + */ + if (dev->isp_sdev.dphy_errctrl_disabled) { + val = readl(base + CIF_MIPI_IMSC); + val |= CIF_MIPI_ERR_CTRL(0x0f); + writel(val, base + CIF_MIPI_IMSC); + dev->isp_sdev.dphy_errctrl_disabled = false; + } + } else { + v4l2_warn(v4l2_dev, "MIPI mis error: 0x%08x\n", mis); + } +} + +void rkisp1_isp_isr(unsigned int isp_mis, struct rkisp1_device *dev) +{ + void __iomem *base = dev->base_addr; + unsigned int isp_mis_tmp = 0; + unsigned int isp_err = 0; + + /* start edge of v_sync */ + if (isp_mis & CIF_ISP_V_START) { + rkisp1_isp_queue_event_sof(&dev->isp_sdev); + + writel(CIF_ISP_V_START, base + CIF_ISP_ICR); + isp_mis_tmp = readl(base + CIF_ISP_MIS); + if (isp_mis_tmp & CIF_ISP_V_START) + v4l2_err(&dev->v4l2_dev, "isp icr v_statr err: 0x%x\n", + isp_mis_tmp); + } + + if ((isp_mis & CIF_ISP_PIC_SIZE_ERROR)) { + /* Clear pic_size_error */ + writel(CIF_ISP_PIC_SIZE_ERROR, base + CIF_ISP_ICR); + isp_err = readl(base + CIF_ISP_ERR); + v4l2_err(&dev->v4l2_dev, + "CIF_ISP_PIC_SIZE_ERROR (0x%08x)", isp_err); + writel(isp_err, base + CIF_ISP_ERR_CLR); + } else if ((isp_mis & CIF_ISP_DATA_LOSS)) { + /* Clear data_loss */ + writel(CIF_ISP_DATA_LOSS, base + CIF_ISP_ICR); + v4l2_err(&dev->v4l2_dev, "CIF_ISP_DATA_LOSS\n"); + writel(CIF_ISP_DATA_LOSS, base + CIF_ISP_ICR); + } + + /* sampled input frame is complete */ + if (isp_mis & CIF_ISP_FRAME_IN) { + writel(CIF_ISP_FRAME_IN, base + CIF_ISP_ICR); + isp_mis_tmp = readl(base + CIF_ISP_MIS); + if (isp_mis_tmp & CIF_ISP_FRAME_IN) + v4l2_err(&dev->v4l2_dev, "isp icr frame_in err: 0x%x\n", + isp_mis_tmp); + } + + /* frame was completely put out */ + if (isp_mis & CIF_ISP_FRAME) { + u32 isp_ris = 0; + /* Clear Frame In (ISP) */ + writel(CIF_ISP_FRAME, base + CIF_ISP_ICR); + isp_mis_tmp = readl(base + CIF_ISP_MIS); + if (isp_mis_tmp & CIF_ISP_FRAME) + v4l2_err(&dev->v4l2_dev, + "isp icr frame end err: 0x%x\n", isp_mis_tmp); + + isp_ris = readl(base + CIF_ISP_RIS); + if (isp_ris & (CIF_ISP_AWB_DONE | CIF_ISP_AFM_FIN | + CIF_ISP_EXP_END | CIF_ISP_HIST_MEASURE_RDY)) + rkisp1_stats_isr(&dev->stats_vdev, isp_ris); + } + + /* + * Then update changed configs. Some of them involve + * lot of register writes. Do those only one per frame. + * Do the updates in the order of the processing flow. + */ + rkisp1_params_isr(&dev->params_vdev, isp_mis); +} diff --git a/drivers/media/platform/rockchip/isp1/rkisp1.h b/drivers/media/platform/rockchip/isp1/rkisp1.h new file mode 100644 index 000000000000..b0366e354ec2 --- /dev/null +++ b/drivers/media/platform/rockchip/isp1/rkisp1.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Rockchip isp1 driver + * + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. + */ + +#ifndef _RKISP1_H +#define _RKISP1_H + +#include +#include + +#include "common.h" + +struct rkisp1_stream; + +/* + * struct ispsd_in_fmt - ISP intput-pad format + * + * Translate mbus_code to hardware format values + * + * @bus_width: used for parallel + */ +struct ispsd_in_fmt { + u32 mbus_code; + u8 fmt_type; + u32 mipi_dt; + u32 yuv_seq; + enum rkisp1_fmt_raw_pat_type bayer_pat; + u8 bus_width; +}; + +struct ispsd_out_fmt { + u32 mbus_code; + u8 fmt_type; +}; + +struct rkisp1_ie_config { + unsigned int effect; +}; + +enum rkisp1_isp_pad { + RKISP1_ISP_PAD_SINK, + RKISP1_ISP_PAD_SINK_PARAMS, + RKISP1_ISP_PAD_SOURCE_PATH, + RKISP1_ISP_PAD_SOURCE_STATS, + RKISP1_ISP_PAD_MAX +}; + +/* + * struct rkisp1_isp_subdev - ISP sub-device + * + * See Cropping regions of ISP in rkisp1.c for details + * @in_frm: input size, don't have to be equal to sensor size + * @in_fmt: input format + * @in_crop: crop for sink pad + * @out_fmt: output format + * @out_crop: output size + * + * @dphy_errctrl_disabled: if dphy errctrl is disabled(avoid endless interrupt) + * @frm_sync_seq: frame sequence, to sync frame_id between video devices. + * @quantization: output quantization + */ +struct rkisp1_isp_subdev { + struct v4l2_subdev sd; + struct media_pad pads[RKISP1_ISP_PAD_MAX]; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_mbus_framefmt in_frm; + struct ispsd_in_fmt in_fmt; + struct v4l2_rect in_crop; + struct ispsd_out_fmt out_fmt; + struct v4l2_rect out_crop; + bool dphy_errctrl_disabled; + atomic_t frm_sync_seq; + enum v4l2_quantization quantization; +}; + +int rkisp1_register_isp_subdev(struct rkisp1_device *isp_dev, + struct v4l2_device *v4l2_dev); + +void rkisp1_unregister_isp_subdev(struct rkisp1_device *isp_dev); + +void rkisp1_mipi_isr(unsigned int mipi_mis, struct rkisp1_device *dev); + +void rkisp1_isp_isr(unsigned int isp_mis, struct rkisp1_device *dev); + +static inline +struct ispsd_out_fmt *rkisp1_get_ispsd_out_fmt(struct rkisp1_isp_subdev *isp_sdev) +{ + return &isp_sdev->out_fmt; +} + +static inline +struct ispsd_in_fmt *rkisp1_get_ispsd_in_fmt(struct rkisp1_isp_subdev *isp_sdev) +{ + return &isp_sdev->in_fmt; +} + +static inline +struct v4l2_rect *rkisp1_get_isp_sd_win(struct rkisp1_isp_subdev *isp_sdev) +{ + return &isp_sdev->out_crop; +} + +static inline struct rkisp1_isp_subdev *sd_to_isp_sd(struct v4l2_subdev *sd) +{ + return container_of(sd, struct rkisp1_isp_subdev, sd); +} + +#endif /* _RKISP1_H */ From patchwork Tue Jul 30 18:42:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helen Mae Koike Fornazier X-Patchwork-Id: 11066551 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EA3D7912 for ; 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Tue, 30 Jul 2019 19:45:05 +0100 (BST) From: Helen Koike To: linux-rockchip@lists.infradead.org Subject: [PATCH v8 06/14] media: rkisp1: add ISP1 statistics driver Date: Tue, 30 Jul 2019 15:42:48 -0300 Message-Id: <20190730184256.30338-7-helen.koike@collabora.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190730184256.30338-1-helen.koike@collabora.com> References: <20190730184256.30338-1-helen.koike@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190730_114512_845063_7EE1CD68 X-CRM114-Status: GOOD ( 17.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, eddie.cai.linux@gmail.com, kernel@collabora.com, heiko@sntech.de, jacob2.chen@rock-chips.com, jeffy.chen@rock-chips.com, zyc@rock-chips.com, linux-kernel@vger.kernel.org, tfiga@chromium.org, Allon Huang , Jacob Chen , hans.verkuil@cisco.com, laurent.pinchart@ideasonboard.com, sakari.ailus@linux.intel.com, zhengsq@rock-chips.com, mchehab@kernel.org, ezequiel@collabora.com, Helen Koike , linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jacob Chen Add the capture video driver for rockchip isp1 statistics block. Signed-off-by: Jacob Chen Signed-off-by: Shunqian Zheng Signed-off-by: Yichong Zhong Signed-off-by: Jacob Chen Signed-off-by: Eddie Cai Signed-off-by: Jeffy Chen Signed-off-by: Allon Huang Signed-off-by: Tomasz Figa [update for upstream] Signed-off-by: Helen Koike Acked-by: Hans Verkuil --- Changes in v8: None Changes in v7: - s/strlcpy/strscpy - sort out the locks in isp stats - code styling and checkpatch fixes .../media/platform/rockchip/isp1/isp_stats.c | 508 ++++++++++++++++++ .../media/platform/rockchip/isp1/isp_stats.h | 60 +++ 2 files changed, 568 insertions(+) create mode 100644 drivers/media/platform/rockchip/isp1/isp_stats.c create mode 100644 drivers/media/platform/rockchip/isp1/isp_stats.h diff --git a/drivers/media/platform/rockchip/isp1/isp_stats.c b/drivers/media/platform/rockchip/isp1/isp_stats.c new file mode 100644 index 000000000000..01d947867c70 --- /dev/null +++ b/drivers/media/platform/rockchip/isp1/isp_stats.c @@ -0,0 +1,508 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Rockchip isp1 driver + * + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include /* for ISP statistics */ + +#include "dev.h" +#include "regs.h" + +#define RKISP1_ISP_STATS_REQ_BUFS_MIN 2 +#define RKISP1_ISP_STATS_REQ_BUFS_MAX 8 + +static int rkisp1_stats_enum_fmt_meta_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + struct video_device *video = video_devdata(file); + struct rkisp1_isp_stats_vdev *stats_vdev = video_get_drvdata(video); + + if (f->index > 0 || f->type != video->queue->type) + return -EINVAL; + + f->pixelformat = stats_vdev->vdev_fmt.fmt.meta.dataformat; + return 0; +} + +static int rkisp1_stats_g_fmt_meta_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct video_device *video = video_devdata(file); + struct rkisp1_isp_stats_vdev *stats_vdev = video_get_drvdata(video); + struct v4l2_meta_format *meta = &f->fmt.meta; + + if (f->type != video->queue->type) + return -EINVAL; + + memset(meta, 0, sizeof(*meta)); + meta->dataformat = stats_vdev->vdev_fmt.fmt.meta.dataformat; + meta->buffersize = stats_vdev->vdev_fmt.fmt.meta.buffersize; + + return 0; +} + +static int rkisp1_stats_querycap(struct file *file, + void *priv, struct v4l2_capability *cap) +{ + struct video_device *vdev = video_devdata(file); + + strscpy(cap->driver, DRIVER_NAME, sizeof(cap->driver)); + strscpy(cap->card, vdev->name, sizeof(cap->card)); + strscpy(cap->bus_info, "platform: " DRIVER_NAME, sizeof(cap->bus_info)); + + return 0; +} + +/* ISP video device IOCTLs */ +static const struct v4l2_ioctl_ops rkisp1_stats_ioctl = { + .vidioc_reqbufs = vb2_ioctl_reqbufs, + .vidioc_querybuf = vb2_ioctl_querybuf, + .vidioc_create_bufs = vb2_ioctl_create_bufs, + .vidioc_qbuf = vb2_ioctl_qbuf, + .vidioc_dqbuf = vb2_ioctl_dqbuf, + .vidioc_prepare_buf = vb2_ioctl_prepare_buf, + .vidioc_expbuf = vb2_ioctl_expbuf, + .vidioc_streamon = vb2_ioctl_streamon, + .vidioc_streamoff = vb2_ioctl_streamoff, + .vidioc_enum_fmt_meta_cap = rkisp1_stats_enum_fmt_meta_cap, + .vidioc_g_fmt_meta_cap = rkisp1_stats_g_fmt_meta_cap, + .vidioc_s_fmt_meta_cap = rkisp1_stats_g_fmt_meta_cap, + .vidioc_try_fmt_meta_cap = rkisp1_stats_g_fmt_meta_cap, + .vidioc_querycap = rkisp1_stats_querycap, + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +struct v4l2_file_operations rkisp1_stats_fops = { + .mmap = vb2_fop_mmap, + .unlocked_ioctl = video_ioctl2, + .poll = vb2_fop_poll, + .open = v4l2_fh_open, + .release = vb2_fop_release +}; + +static int rkisp1_stats_vb2_queue_setup(struct vb2_queue *vq, + unsigned int *num_buffers, + unsigned int *num_planes, + unsigned int sizes[], + struct device *alloc_devs[]) +{ + struct rkisp1_isp_stats_vdev *stats_vdev = vq->drv_priv; + + *num_planes = 1; + + *num_buffers = clamp_t(u32, *num_buffers, RKISP1_ISP_STATS_REQ_BUFS_MIN, + RKISP1_ISP_STATS_REQ_BUFS_MAX); + + sizes[0] = sizeof(struct rkisp1_stat_buffer); + + INIT_LIST_HEAD(&stats_vdev->stat); + + return 0; +} + +static void rkisp1_stats_vb2_buf_queue(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct rkisp1_buffer *stats_buf = to_rkisp1_buffer(vbuf); + struct vb2_queue *vq = vb->vb2_queue; + struct rkisp1_isp_stats_vdev *stats_dev = vq->drv_priv; + + stats_buf->vaddr[0] = vb2_plane_vaddr(vb, 0); + + mutex_lock(&stats_dev->wq_lock); + list_add_tail(&stats_buf->queue, &stats_dev->stat); + mutex_unlock(&stats_dev->wq_lock); +} + +static int rkisp1_stats_vb2_buf_prepare(struct vb2_buffer *vb) +{ + if (vb2_plane_size(vb, 0) < sizeof(struct rkisp1_stat_buffer)) + return -EINVAL; + + vb2_set_plane_payload(vb, 0, sizeof(struct rkisp1_stat_buffer)); + + return 0; +} + +static void rkisp1_stats_vb2_stop_streaming(struct vb2_queue *vq) +{ + struct rkisp1_isp_stats_vdev *stats_vdev = vq->drv_priv; + struct rkisp1_buffer *buf; + unsigned long flags; + unsigned int i; + + /* Make sure no new work queued in isr before draining wq */ + spin_lock_irqsave(&stats_vdev->irq_lock, flags); + stats_vdev->streamon = false; + spin_unlock_irqrestore(&stats_vdev->irq_lock, flags); + + drain_workqueue(stats_vdev->readout_wq); + + mutex_lock(&stats_vdev->wq_lock); + for (i = 0; i < RKISP1_ISP_STATS_REQ_BUFS_MAX; i++) { + if (list_empty(&stats_vdev->stat)) + break; + buf = list_first_entry(&stats_vdev->stat, + struct rkisp1_buffer, queue); + list_del(&buf->queue); + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + } + mutex_unlock(&stats_vdev->wq_lock); +} + +static int +rkisp1_stats_vb2_start_streaming(struct vb2_queue *queue, + unsigned int count) +{ + struct rkisp1_isp_stats_vdev *stats_vdev = queue->drv_priv; + + stats_vdev->streamon = true; + + return 0; +} + +static struct vb2_ops rkisp1_stats_vb2_ops = { + .queue_setup = rkisp1_stats_vb2_queue_setup, + .buf_queue = rkisp1_stats_vb2_buf_queue, + .buf_prepare = rkisp1_stats_vb2_buf_prepare, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, + .stop_streaming = rkisp1_stats_vb2_stop_streaming, + .start_streaming = rkisp1_stats_vb2_start_streaming, +}; + +static int rkisp1_stats_init_vb2_queue(struct vb2_queue *q, + struct rkisp1_isp_stats_vdev *stats_vdev) +{ + struct rkisp1_vdev_node *node; + + node = queue_to_node(q); + + q->type = V4L2_BUF_TYPE_META_CAPTURE; + q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; + q->drv_priv = stats_vdev; + q->ops = &rkisp1_stats_vb2_ops; + q->mem_ops = &vb2_vmalloc_memops; + q->buf_struct_size = sizeof(struct rkisp1_buffer); + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->lock = &node->vlock; + + return vb2_queue_init(q); +} + +static void rkisp1_stats_get_awb_meas(struct rkisp1_isp_stats_vdev *stats_vdev, + struct rkisp1_stat_buffer *pbuf) +{ + /* Protect against concurrent access from ISR? */ + u32 reg_val; + + pbuf->meas_type |= CIFISP_STAT_AWB; + reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_WHITE_CNT); + pbuf->params.awb.awb_mean[0].cnt = CIF_ISP_AWB_GET_PIXEL_CNT(reg_val); + reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_MEAN); + + pbuf->params.awb.awb_mean[0].mean_cr_or_r = + CIF_ISP_AWB_GET_MEAN_CR_R(reg_val); + pbuf->params.awb.awb_mean[0].mean_cb_or_b = + CIF_ISP_AWB_GET_MEAN_CB_B(reg_val); + pbuf->params.awb.awb_mean[0].mean_y_or_g = + CIF_ISP_AWB_GET_MEAN_Y_G(reg_val); +} + +static void rkisp1_stats_get_aec_meas(struct rkisp1_isp_stats_vdev *stats_vdev, + struct rkisp1_stat_buffer *pbuf) +{ + void __iomem *addr = stats_vdev->dev->base_addr + CIF_ISP_EXP_MEAN_00; + unsigned int i; + + pbuf->meas_type |= CIFISP_STAT_AUTOEXP; + for (i = 0; i < CIFISP_AE_MEAN_MAX; i++) + pbuf->params.ae.exp_mean[i] = (u8)readl(addr + i * 4); +} + +static void rkisp1_stats_get_afc_meas(struct rkisp1_isp_stats_vdev *stats_vdev, + struct rkisp1_stat_buffer *pbuf) +{ + void __iomem *base_addr; + struct cifisp_af_stat *af; + + pbuf->meas_type = CIFISP_STAT_AFM_FIN; + + af = &pbuf->params.af; + base_addr = stats_vdev->dev->base_addr; + af->window[0].sum = readl(base_addr + CIF_ISP_AFM_SUM_A); + af->window[0].lum = readl(base_addr + CIF_ISP_AFM_LUM_A); + af->window[1].sum = readl(base_addr + CIF_ISP_AFM_SUM_B); + af->window[1].lum = readl(base_addr + CIF_ISP_AFM_LUM_B); + af->window[2].sum = readl(base_addr + CIF_ISP_AFM_SUM_C); + af->window[2].lum = readl(base_addr + CIF_ISP_AFM_LUM_C); +} + +static void rkisp1_stats_get_hst_meas(struct rkisp1_isp_stats_vdev *stats_vdev, + struct rkisp1_stat_buffer *pbuf) +{ + void __iomem *addr = stats_vdev->dev->base_addr + CIF_ISP_HIST_BIN_0; + unsigned int i; + + pbuf->meas_type |= CIFISP_STAT_HIST; + for (i = 0; i < CIFISP_HIST_BIN_N_MAX; i++) + pbuf->params.hist.hist_bins[i] = readl(addr + (i * 4)); +} + +static void rkisp1_stats_get_bls_meas(struct rkisp1_isp_stats_vdev *stats_vdev, + struct rkisp1_stat_buffer *pbuf) +{ + struct rkisp1_device *dev = stats_vdev->dev; + const struct ispsd_in_fmt *in_fmt = + rkisp1_get_ispsd_in_fmt(&dev->isp_sdev); + void __iomem *base = stats_vdev->dev->base_addr; + struct cifisp_bls_meas_val *bls_val; + + bls_val = &pbuf->params.ae.bls_val; + if (in_fmt->bayer_pat == RAW_BGGR) { + bls_val->meas_b = readl(base + CIF_ISP_BLS_A_MEASURED); + bls_val->meas_gb = readl(base + CIF_ISP_BLS_B_MEASURED); + bls_val->meas_gr = readl(base + CIF_ISP_BLS_C_MEASURED); + bls_val->meas_r = readl(base + CIF_ISP_BLS_D_MEASURED); + } else if (in_fmt->bayer_pat == RAW_GBRG) { + bls_val->meas_gb = readl(base + CIF_ISP_BLS_A_MEASURED); + bls_val->meas_b = readl(base + CIF_ISP_BLS_B_MEASURED); + bls_val->meas_r = readl(base + CIF_ISP_BLS_C_MEASURED); + bls_val->meas_gr = readl(base + CIF_ISP_BLS_D_MEASURED); + } else if (in_fmt->bayer_pat == RAW_GRBG) { + bls_val->meas_gr = readl(base + CIF_ISP_BLS_A_MEASURED); + bls_val->meas_r = readl(base + CIF_ISP_BLS_B_MEASURED); + bls_val->meas_b = readl(base + CIF_ISP_BLS_C_MEASURED); + bls_val->meas_gb = readl(base + CIF_ISP_BLS_D_MEASURED); + } else if (in_fmt->bayer_pat == RAW_RGGB) { + bls_val->meas_r = readl(base + CIF_ISP_BLS_A_MEASURED); + bls_val->meas_gr = readl(base + CIF_ISP_BLS_B_MEASURED); + bls_val->meas_gb = readl(base + CIF_ISP_BLS_C_MEASURED); + bls_val->meas_b = readl(base + CIF_ISP_BLS_D_MEASURED); + } +} + +static void +rkisp1_stats_send_measurement(struct rkisp1_isp_stats_vdev *stats_vdev, + struct rkisp1_isp_readout_work *meas_work) +{ + struct rkisp1_stat_buffer *cur_stat_buf; + struct rkisp1_buffer *cur_buf = NULL; + unsigned int cur_frame_id = -1; + + cur_frame_id = atomic_read(&stats_vdev->dev->isp_sdev.frm_sync_seq) - 1; + if (cur_frame_id != meas_work->frame_id) { + v4l2_warn(stats_vdev->vnode.vdev.v4l2_dev, + "Measurement late(%d, %d)\n", + cur_frame_id, meas_work->frame_id); + cur_frame_id = meas_work->frame_id; + } + + mutex_lock(&stats_vdev->wq_lock); + /* get one empty buffer */ + if (!list_empty(&stats_vdev->stat)) { + cur_buf = list_first_entry(&stats_vdev->stat, + struct rkisp1_buffer, queue); + list_del(&cur_buf->queue); + } + mutex_unlock(&stats_vdev->wq_lock); + + if (!cur_buf) + return; + + cur_stat_buf = + (struct rkisp1_stat_buffer *)(cur_buf->vaddr[0]); + + if (meas_work->isp_ris & CIF_ISP_AWB_DONE) { + rkisp1_stats_get_awb_meas(stats_vdev, cur_stat_buf); + cur_stat_buf->meas_type |= CIFISP_STAT_AWB; + } + + if (meas_work->isp_ris & CIF_ISP_AFM_FIN) { + rkisp1_stats_get_afc_meas(stats_vdev, cur_stat_buf); + cur_stat_buf->meas_type |= CIFISP_STAT_AFM_FIN; + } + + if (meas_work->isp_ris & CIF_ISP_EXP_END) { + rkisp1_stats_get_aec_meas(stats_vdev, cur_stat_buf); + rkisp1_stats_get_bls_meas(stats_vdev, cur_stat_buf); + cur_stat_buf->meas_type |= CIFISP_STAT_AUTOEXP; + } + + if (meas_work->isp_ris & CIF_ISP_HIST_MEASURE_RDY) { + rkisp1_stats_get_hst_meas(stats_vdev, cur_stat_buf); + cur_stat_buf->meas_type |= CIFISP_STAT_HIST; + } + + vb2_set_plane_payload(&cur_buf->vb.vb2_buf, 0, + sizeof(struct rkisp1_stat_buffer)); + cur_buf->vb.sequence = cur_frame_id; + cur_buf->vb.vb2_buf.timestamp = ktime_get_ns(); + vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); +} + +static void rkisp1_stats_readout_work(struct work_struct *work) +{ + struct rkisp1_isp_readout_work *readout_work = container_of(work, + struct rkisp1_isp_readout_work, + work); + struct rkisp1_isp_stats_vdev *stats_vdev = readout_work->stats_vdev; + + if (readout_work->readout == RKISP1_ISP_READOUT_MEAS) + rkisp1_stats_send_measurement(stats_vdev, readout_work); + + kfree(readout_work); +} + +int rkisp1_stats_isr(struct rkisp1_isp_stats_vdev *stats_vdev, u32 isp_ris) +{ + unsigned int cur_frame_id = + atomic_read(&stats_vdev->dev->isp_sdev.frm_sync_seq) - 1; + struct rkisp1_isp_readout_work *work; + unsigned int isp_mis_tmp = 0; +#ifdef LOG_ISR_EXE_TIME + ktime_t in_t = ktime_get(); +#endif + + spin_lock(&stats_vdev->irq_lock); + + writel((CIF_ISP_AWB_DONE | CIF_ISP_AFM_FIN | CIF_ISP_EXP_END | + CIF_ISP_HIST_MEASURE_RDY), + stats_vdev->dev->base_addr + CIF_ISP_ICR); + + isp_mis_tmp = readl(stats_vdev->dev->base_addr + CIF_ISP_MIS); + if (isp_mis_tmp & + (CIF_ISP_AWB_DONE | CIF_ISP_AFM_FIN | + CIF_ISP_EXP_END | CIF_ISP_HIST_MEASURE_RDY)) + v4l2_err(stats_vdev->vnode.vdev.v4l2_dev, + "isp icr 3A info err: 0x%x\n", + isp_mis_tmp); + + if (!stats_vdev->streamon) + goto unlock; + if (isp_ris & (CIF_ISP_AWB_DONE | CIF_ISP_AFM_FIN | CIF_ISP_EXP_END | + CIF_ISP_HIST_MEASURE_RDY)) { + work = (struct rkisp1_isp_readout_work *) + kzalloc(sizeof(struct rkisp1_isp_readout_work), + GFP_ATOMIC); + if (work) { + INIT_WORK(&work->work, + rkisp1_stats_readout_work); + work->readout = RKISP1_ISP_READOUT_MEAS; + work->stats_vdev = stats_vdev; + work->frame_id = cur_frame_id; + work->isp_ris = isp_ris; + if (!queue_work(stats_vdev->readout_wq, + &work->work)) + kfree(work); + } else { + v4l2_err(stats_vdev->vnode.vdev.v4l2_dev, + "Could not allocate work\n"); + } + } + +#ifdef LOG_ISR_EXE_TIME + if (isp_ris & (CIF_ISP_EXP_END | CIF_ISP_AWB_DONE | + CIF_ISP_FRAME | CIF_ISP_HIST_MEASURE_RDY)) { + unsigned int diff_us = + ktime_to_us(ktime_sub(ktime_get(), in_t)); + + if (diff_us > g_longest_isr_time) + g_longest_isr_time = diff_us; + + v4l2_info(stats_vdev->vnode.vdev.v4l2_dev, + "isp_isr time %d %d\n", diff_us, g_longest_isr_time); + } +#endif + +unlock: + spin_unlock(&stats_vdev->irq_lock); + + return 0; +} + +static void rkisp1_init_stats_vdev(struct rkisp1_isp_stats_vdev *stats_vdev) +{ + stats_vdev->vdev_fmt.fmt.meta.dataformat = + V4L2_META_FMT_RK_ISP1_STAT_3A; + stats_vdev->vdev_fmt.fmt.meta.buffersize = + sizeof(struct rkisp1_stat_buffer); +} + +int rkisp1_register_stats_vdev(struct rkisp1_isp_stats_vdev *stats_vdev, + struct v4l2_device *v4l2_dev, + struct rkisp1_device *dev) +{ + struct rkisp1_vdev_node *node = &stats_vdev->vnode; + struct video_device *vdev = &node->vdev; + unsigned int ret; + + stats_vdev->dev = dev; + mutex_init(&stats_vdev->wq_lock); + mutex_init(&node->vlock); + INIT_LIST_HEAD(&stats_vdev->stat); + spin_lock_init(&stats_vdev->irq_lock); + + strlcpy(vdev->name, "rkisp1-statistics", sizeof(vdev->name)); + + video_set_drvdata(vdev, stats_vdev); + vdev->ioctl_ops = &rkisp1_stats_ioctl; + vdev->fops = &rkisp1_stats_fops; + vdev->release = video_device_release_empty; + vdev->lock = &node->vlock; + vdev->v4l2_dev = v4l2_dev; + vdev->queue = &node->buf_queue; + vdev->device_caps = V4L2_CAP_META_CAPTURE | V4L2_CAP_STREAMING; + vdev->vfl_dir = VFL_DIR_RX; + rkisp1_stats_init_vb2_queue(vdev->queue, stats_vdev); + rkisp1_init_stats_vdev(stats_vdev); + video_set_drvdata(vdev, stats_vdev); + + node->pad.flags = MEDIA_PAD_FL_SINK; + ret = media_entity_pads_init(&vdev->entity, 1, &node->pad); + if (ret < 0) + goto err_release_queue; + + ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1); + if (ret < 0) { + dev_err(&vdev->dev, + "could not register Video for Linux device\n"); + goto err_cleanup_media_entity; + } + + stats_vdev->readout_wq = + alloc_workqueue("measurement_queue", + WQ_UNBOUND | WQ_MEM_RECLAIM, 1); + + if (!stats_vdev->readout_wq) { + ret = -ENOMEM; + goto err_unreg_vdev; + } + + return 0; +err_unreg_vdev: + video_unregister_device(vdev); +err_cleanup_media_entity: + media_entity_cleanup(&vdev->entity); +err_release_queue: + vb2_queue_release(vdev->queue); + return ret; +} + +void rkisp1_unregister_stats_vdev(struct rkisp1_isp_stats_vdev *stats_vdev) +{ + struct rkisp1_vdev_node *node = &stats_vdev->vnode; + struct video_device *vdev = &node->vdev; + + destroy_workqueue(stats_vdev->readout_wq); + video_unregister_device(vdev); + media_entity_cleanup(&vdev->entity); + vb2_queue_release(vdev->queue); +} diff --git a/drivers/media/platform/rockchip/isp1/isp_stats.h b/drivers/media/platform/rockchip/isp1/isp_stats.h new file mode 100644 index 000000000000..b46c8537e1c7 --- /dev/null +++ b/drivers/media/platform/rockchip/isp1/isp_stats.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Rockchip isp1 driver + * + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. + */ + +#ifndef _RKISP1_ISP_STATS_H +#define _RKISP1_ISP_STATS_H + +#include + +#include "common.h" + +struct rkisp1_isp_stats_vdev; + +enum rkisp1_isp_readout_cmd { + RKISP1_ISP_READOUT_MEAS, + RKISP1_ISP_READOUT_META, +}; + +struct rkisp1_isp_readout_work { + struct work_struct work; + struct rkisp1_isp_stats_vdev *stats_vdev; + + unsigned int frame_id; + unsigned int isp_ris; + enum rkisp1_isp_readout_cmd readout; + struct vb2_buffer *vb; +}; + +/* + * struct rkisp1_isp_stats_vdev - ISP Statistics device + * + * @irq_lock: buffer queue lock + * @stat: stats buffer list + * @readout_wq: workqueue for statistics information read + */ +struct rkisp1_isp_stats_vdev { + struct rkisp1_vdev_node vnode; + struct rkisp1_device *dev; + + spinlock_t irq_lock; + struct list_head stat; + struct v4l2_format vdev_fmt; + bool streamon; + + struct workqueue_struct *readout_wq; + struct mutex wq_lock; +}; + +int rkisp1_stats_isr(struct rkisp1_isp_stats_vdev *stats_vdev, u32 isp_ris); + +int rkisp1_register_stats_vdev(struct rkisp1_isp_stats_vdev *stats_vdev, + struct v4l2_device *v4l2_dev, + struct rkisp1_device *dev); + +void rkisp1_unregister_stats_vdev(struct rkisp1_isp_stats_vdev *stats_vdev); + +#endif /* _RKISP1_ISP_STATS_H */ From patchwork Tue Jul 30 18:42:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helen Mae Koike Fornazier X-Patchwork-Id: 11066557 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BAB66912 for ; Tue, 30 Jul 2019 18:47:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A87F028498 for ; Tue, 30 Jul 2019 18:47:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9BD542858F; Tue, 30 Jul 2019 18:47:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2ADBB284D4 for ; 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Tue, 30 Jul 2019 18:47:28 +0000 Received: from bhuna.collabora.co.uk ([46.235.227.227]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hsX7d-0004fW-KM; Tue, 30 Jul 2019 18:45:23 +0000 Received: from floko.floko.floko (unknown [IPv6:2804:431:c7f1:ce2f:ec1:e6e6:2e9f:e76e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: koike) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id 1C86528B927; Tue, 30 Jul 2019 19:45:10 +0100 (BST) From: Helen Koike To: linux-rockchip@lists.infradead.org Subject: [PATCH v8 07/14] media: rkisp1: add ISP1 params driver Date: Tue, 30 Jul 2019 15:42:49 -0300 Message-Id: <20190730184256.30338-8-helen.koike@collabora.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190730184256.30338-1-helen.koike@collabora.com> References: <20190730184256.30338-1-helen.koike@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190730_114518_736450_47307A08 X-CRM114-Status: GOOD ( 17.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, eddie.cai.linux@gmail.com, kernel@collabora.com, heiko@sntech.de, jacob2.chen@rock-chips.com, jeffy.chen@rock-chips.com, zyc@rock-chips.com, linux-kernel@vger.kernel.org, tfiga@chromium.org, Allon Huang , Jacob Chen , hans.verkuil@cisco.com, laurent.pinchart@ideasonboard.com, sakari.ailus@linux.intel.com, zhengsq@rock-chips.com, mchehab@kernel.org, ezequiel@collabora.com, Helen Koike , linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jacob Chen Add the output video driver that accept params from userspace. Signed-off-by: Jacob Chen Signed-off-by: Shunqian Zheng Signed-off-by: Yichong Zhong Signed-off-by: Jacob Chen Signed-off-by: Eddie Cai Signed-off-by: Jeffy Chen Signed-off-by: Allon Huang Signed-off-by: Tomasz Figa [update for upstream] Signed-off-by: Helen Koike --- Changes in v8: None Changes in v7: - s/strlcpy/strscpy - s/strcpy/strscpy - fix config lsc error LSC data table size is 17x17, but when configuring data to ISP, should be aligned to 18x17. That means every last data of last line should be filled with 0, and not filled with the data of next line. - Update new ISP parameters immediately For those sub modules that have shadow registers in core isp, the new programing parameters would not be active if both CIF_ISP_CTRL_ISP_CFG_UPD_PERMANENT and CFG_UPD are not set. Now we configure CFG_UPD to force update the shadow registers when new ISP parameters are configured. - fix some ISP parameters config error Some ISP parameter config functions may override the old enable bit value, because the enable bits of these modules are in the same registers with parameters. So we should save the old enable bits firstly. - code styling and checkpatch fixes .../media/platform/rockchip/isp1/isp_params.c | 1604 +++++++++++++++++ .../media/platform/rockchip/isp1/isp_params.h | 50 + 2 files changed, 1654 insertions(+) create mode 100644 drivers/media/platform/rockchip/isp1/isp_params.c create mode 100644 drivers/media/platform/rockchip/isp1/isp_params.h diff --git a/drivers/media/platform/rockchip/isp1/isp_params.c b/drivers/media/platform/rockchip/isp1/isp_params.c new file mode 100644 index 000000000000..7b470b6bf90f --- /dev/null +++ b/drivers/media/platform/rockchip/isp1/isp_params.c @@ -0,0 +1,1604 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Rockchip isp1 driver + * + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include /* for ISP params */ + +#include "dev.h" +#include "regs.h" + +#define RKISP1_ISP_PARAMS_REQ_BUFS_MIN 2 +#define RKISP1_ISP_PARAMS_REQ_BUFS_MAX 8 + +#define BLS_START_H_MAX_IS_VALID(val) ((val) < CIFISP_BLS_START_H_MAX) +#define BLS_STOP_H_MAX_IS_VALID(val) ((val) < CIFISP_BLS_STOP_H_MAX) + +#define BLS_START_V_MAX_IS_VALID(val) ((val) < CIFISP_BLS_START_V_MAX) +#define BLS_STOP_V_MAX_IS_VALID(val) ((val) < CIFISP_BLS_STOP_V_MAX) + +#define BLS_SAMPLE_MAX_IS_VALID(val) ((val) < CIFISP_BLS_SAMPLES_MAX) + +#define BLS_FIX_SUB_IS_VALID(val) \ + ((val) > (s16) CIFISP_BLS_FIX_SUB_MIN && (val) < CIFISP_BLS_FIX_SUB_MAX) + +#define RKISP1_ISP_DPCC_LINE_THRESH(n) (CIF_ISP_DPCC_LINE_THRESH_1 + 0x14 * (n)) +#define RKISP1_ISP_DPCC_LINE_MAD_FAC(n) (CIF_ISP_DPCC_LINE_MAD_FAC_1 + 0x14 * (n)) +#define RKISP1_ISP_DPCC_PG_FAC(n) (CIF_ISP_DPCC_PG_FAC_1 + 0x14 * (n)) +#define RKISP1_ISP_DPCC_RND_THRESH(n) (CIF_ISP_DPCC_RND_THRESH_1 + 0x14 * (n)) +#define RKISP1_ISP_DPCC_RG_FAC(n) (CIF_ISP_DPCC_RG_FAC_1 + 0x14 * (n)) +#define RKISP1_ISP_CC_COEFF(n) (CIF_ISP_CC_COEFF_0 + (n) * 4) + +static inline void rkisp1_iowrite32(struct rkisp1_isp_params_vdev *params_vdev, + u32 value, u32 addr) +{ + iowrite32(value, params_vdev->dev->base_addr + addr); +} + +static inline u32 rkisp1_ioread32(struct rkisp1_isp_params_vdev *params_vdev, + u32 addr) +{ + return ioread32(params_vdev->dev->base_addr + addr); +} + +static inline void isp_param_set_bits(struct rkisp1_isp_params_vdev + *params_vdev, + u32 reg, u32 bit_mask) +{ + u32 val; + + val = rkisp1_ioread32(params_vdev, reg); + rkisp1_iowrite32(params_vdev, val | bit_mask, reg); +} + +static inline void isp_param_clear_bits(struct rkisp1_isp_params_vdev + *params_vdev, + u32 reg, u32 bit_mask) +{ + u32 val; + + val = rkisp1_ioread32(params_vdev, reg); + rkisp1_iowrite32(params_vdev, val & ~bit_mask, reg); +} + +/* ISP BP interface function */ +static void dpcc_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_dpcc_config *arg) +{ + unsigned int i; + u32 mode; + + /* avoid to override the old enable value */ + mode = rkisp1_ioread32(params_vdev, CIF_ISP_DPCC_MODE); + mode &= CIF_ISP_DPCC_ENA; + mode |= arg->mode & ~CIF_ISP_DPCC_ENA; + rkisp1_iowrite32(params_vdev, mode, CIF_ISP_DPCC_MODE); + rkisp1_iowrite32(params_vdev, arg->output_mode, + CIF_ISP_DPCC_OUTPUT_MODE); + rkisp1_iowrite32(params_vdev, arg->set_use, CIF_ISP_DPCC_SET_USE); + + rkisp1_iowrite32(params_vdev, arg->methods[0].method, + CIF_ISP_DPCC_METHODS_SET_1); + rkisp1_iowrite32(params_vdev, arg->methods[1].method, + CIF_ISP_DPCC_METHODS_SET_2); + rkisp1_iowrite32(params_vdev, arg->methods[2].method, + CIF_ISP_DPCC_METHODS_SET_3); + for (i = 0; i < CIFISP_DPCC_METHODS_MAX; i++) { + rkisp1_iowrite32(params_vdev, arg->methods[i].line_thresh, + RKISP1_ISP_DPCC_LINE_THRESH(i)); + rkisp1_iowrite32(params_vdev, arg->methods[i].line_mad_fac, + RKISP1_ISP_DPCC_LINE_MAD_FAC(i)); + rkisp1_iowrite32(params_vdev, arg->methods[i].pg_fac, + RKISP1_ISP_DPCC_PG_FAC(i)); + rkisp1_iowrite32(params_vdev, arg->methods[i].rnd_thresh, + RKISP1_ISP_DPCC_RND_THRESH(i)); + rkisp1_iowrite32(params_vdev, arg->methods[i].rg_fac, + RKISP1_ISP_DPCC_RG_FAC(i)); + } + + rkisp1_iowrite32(params_vdev, arg->rnd_offs, CIF_ISP_DPCC_RND_OFFS); + rkisp1_iowrite32(params_vdev, arg->ro_limits, CIF_ISP_DPCC_RO_LIMITS); +} + +/* ISP black level subtraction interface function */ +static void bls_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_bls_config *arg) +{ + /* avoid to override the old enable value */ + u32 new_control; + + new_control = rkisp1_ioread32(params_vdev, CIF_ISP_BLS_CTRL); + new_control &= CIF_ISP_BLS_ENA; + /* fixed subtraction values */ + if (!arg->enable_auto) { + const struct cifisp_bls_fixed_val *pval = &arg->fixed_val; + + switch (params_vdev->raw_type) { + case RAW_BGGR: + rkisp1_iowrite32(params_vdev, + pval->r, CIF_ISP_BLS_D_FIXED); + rkisp1_iowrite32(params_vdev, + pval->gr, CIF_ISP_BLS_C_FIXED); + rkisp1_iowrite32(params_vdev, + pval->gb, CIF_ISP_BLS_B_FIXED); + rkisp1_iowrite32(params_vdev, + pval->b, CIF_ISP_BLS_A_FIXED); + break; + case RAW_GBRG: + rkisp1_iowrite32(params_vdev, + pval->r, CIF_ISP_BLS_C_FIXED); + rkisp1_iowrite32(params_vdev, + pval->gr, CIF_ISP_BLS_D_FIXED); + rkisp1_iowrite32(params_vdev, + pval->gb, CIF_ISP_BLS_A_FIXED); + rkisp1_iowrite32(params_vdev, + pval->b, CIF_ISP_BLS_B_FIXED); + break; + case RAW_GRBG: + rkisp1_iowrite32(params_vdev, + pval->r, CIF_ISP_BLS_B_FIXED); + rkisp1_iowrite32(params_vdev, + pval->gr, CIF_ISP_BLS_A_FIXED); + rkisp1_iowrite32(params_vdev, + pval->gb, CIF_ISP_BLS_D_FIXED); + rkisp1_iowrite32(params_vdev, + pval->b, CIF_ISP_BLS_C_FIXED); + break; + case RAW_RGGB: + rkisp1_iowrite32(params_vdev, + pval->r, CIF_ISP_BLS_A_FIXED); + rkisp1_iowrite32(params_vdev, + pval->gr, CIF_ISP_BLS_B_FIXED); + rkisp1_iowrite32(params_vdev, + pval->gb, CIF_ISP_BLS_C_FIXED); + rkisp1_iowrite32(params_vdev, + pval->b, CIF_ISP_BLS_D_FIXED); + break; + default: + break; + } + + } else { + if (arg->en_windows & BIT(1)) { + rkisp1_iowrite32(params_vdev, arg->bls_window2.h_offs, + CIF_ISP_BLS_H2_START); + rkisp1_iowrite32(params_vdev, arg->bls_window2.h_size, + CIF_ISP_BLS_H2_STOP); + rkisp1_iowrite32(params_vdev, arg->bls_window2.v_offs, + CIF_ISP_BLS_V2_START); + rkisp1_iowrite32(params_vdev, arg->bls_window2.v_size, + CIF_ISP_BLS_V2_STOP); + new_control |= CIF_ISP_BLS_WINDOW_2; + } + + if (arg->en_windows & BIT(0)) { + rkisp1_iowrite32(params_vdev, arg->bls_window1.h_offs, + CIF_ISP_BLS_H1_START); + rkisp1_iowrite32(params_vdev, arg->bls_window1.h_size, + CIF_ISP_BLS_H1_STOP); + rkisp1_iowrite32(params_vdev, arg->bls_window1.v_offs, + CIF_ISP_BLS_V1_START); + rkisp1_iowrite32(params_vdev, arg->bls_window1.v_size, + CIF_ISP_BLS_V1_STOP); + new_control |= CIF_ISP_BLS_WINDOW_1; + } + + rkisp1_iowrite32(params_vdev, arg->bls_samples, + CIF_ISP_BLS_SAMPLES); + + new_control |= CIF_ISP_BLS_MODE_MEASURED; + } + rkisp1_iowrite32(params_vdev, new_control, CIF_ISP_BLS_CTRL); +} + +/* ISP LS correction interface function */ +static void +__lsc_correct_matrix_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_lsc_config *pconfig) +{ + unsigned int isp_lsc_status, sram_addr, isp_lsc_table_sel; + unsigned int i, j, data; + + isp_lsc_status = rkisp1_ioread32(params_vdev, CIF_ISP_LSC_STATUS); + + /* CIF_ISP_LSC_TABLE_ADDRESS_153 = ( 17 * 18 ) >> 1 */ + sram_addr = (isp_lsc_status & CIF_ISP_LSC_ACTIVE_TABLE) ? + CIF_ISP_LSC_TABLE_ADDRESS_0 : + CIF_ISP_LSC_TABLE_ADDRESS_153; + rkisp1_iowrite32(params_vdev, sram_addr, CIF_ISP_LSC_R_TABLE_ADDR); + rkisp1_iowrite32(params_vdev, sram_addr, CIF_ISP_LSC_GR_TABLE_ADDR); + rkisp1_iowrite32(params_vdev, sram_addr, CIF_ISP_LSC_GB_TABLE_ADDR); + rkisp1_iowrite32(params_vdev, sram_addr, CIF_ISP_LSC_B_TABLE_ADDR); + + /* program data tables (table size is 9 * 17 = 153) */ + for (i = 0; i < CIF_ISP_LSC_SECTORS_MAX * CIF_ISP_LSC_SECTORS_MAX; + i += CIF_ISP_LSC_SECTORS_MAX) { + /* + * 17 sectors with 2 values in one DWORD = 9 + * DWORDs (2nd value of last DWORD unused) + */ + for (j = 0; j < CIF_ISP_LSC_SECTORS_MAX - 1; j += 2) { + data = CIF_ISP_LSC_TABLE_DATA( + pconfig->r_data_tbl[i + j], + pconfig->r_data_tbl[i + j + 1]); + rkisp1_iowrite32(params_vdev, data, + CIF_ISP_LSC_R_TABLE_DATA); + + data = CIF_ISP_LSC_TABLE_DATA( + pconfig->gr_data_tbl[i + j], + pconfig->gr_data_tbl[i + j + 1]); + rkisp1_iowrite32(params_vdev, data, + CIF_ISP_LSC_GR_TABLE_DATA); + + data = CIF_ISP_LSC_TABLE_DATA( + pconfig->gb_data_tbl[i + j], + pconfig->gb_data_tbl[i + j + 1]); + rkisp1_iowrite32(params_vdev, data, + CIF_ISP_LSC_GB_TABLE_DATA); + + data = CIF_ISP_LSC_TABLE_DATA( + pconfig->b_data_tbl[i + j], + pconfig->b_data_tbl[i + j + 1]); + rkisp1_iowrite32(params_vdev, data, + CIF_ISP_LSC_B_TABLE_DATA); + } + data = CIF_ISP_LSC_TABLE_DATA( + pconfig->r_data_tbl[i + j], + 0); + rkisp1_iowrite32(params_vdev, data, + CIF_ISP_LSC_R_TABLE_DATA); + + data = CIF_ISP_LSC_TABLE_DATA( + pconfig->gr_data_tbl[i + j], + 0); + rkisp1_iowrite32(params_vdev, data, + CIF_ISP_LSC_GR_TABLE_DATA); + + data = CIF_ISP_LSC_TABLE_DATA( + pconfig->gb_data_tbl[i + j], + 0); + rkisp1_iowrite32(params_vdev, data, + CIF_ISP_LSC_GB_TABLE_DATA); + + data = CIF_ISP_LSC_TABLE_DATA( + pconfig->b_data_tbl[i + j], + 0); + rkisp1_iowrite32(params_vdev, data, + CIF_ISP_LSC_B_TABLE_DATA); + } + isp_lsc_table_sel = (isp_lsc_status & CIF_ISP_LSC_ACTIVE_TABLE) ? + CIF_ISP_LSC_TABLE_0 : CIF_ISP_LSC_TABLE_1; + rkisp1_iowrite32(params_vdev, isp_lsc_table_sel, CIF_ISP_LSC_TABLE_SEL); +} + +static void lsc_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_lsc_config *arg) +{ + unsigned int i, data; + u32 lsc_ctrl; + + /* To config must be off , store the current status firstly */ + lsc_ctrl = rkisp1_ioread32(params_vdev, CIF_ISP_LSC_CTRL); + isp_param_clear_bits(params_vdev, CIF_ISP_LSC_CTRL, + CIF_ISP_LSC_CTRL_ENA); + __lsc_correct_matrix_config(params_vdev, arg); + + for (i = 0; i < 4; i++) { + /* program x size tables */ + data = CIF_ISP_LSC_SECT_SIZE(arg->x_size_tbl[i * 2], + arg->x_size_tbl[i * 2 + 1]); + rkisp1_iowrite32(params_vdev, data, + CIF_ISP_LSC_XSIZE_01 + i * 4); + + /* program x grad tables */ + data = CIF_ISP_LSC_SECT_SIZE(arg->x_grad_tbl[i * 2], + arg->x_grad_tbl[i * 2 + 1]); + rkisp1_iowrite32(params_vdev, data, + CIF_ISP_LSC_XGRAD_01 + i * 4); + + /* program y size tables */ + data = CIF_ISP_LSC_SECT_SIZE(arg->y_size_tbl[i * 2], + arg->y_size_tbl[i * 2 + 1]); + rkisp1_iowrite32(params_vdev, data, + CIF_ISP_LSC_YSIZE_01 + i * 4); + + /* program y grad tables */ + data = CIF_ISP_LSC_SECT_SIZE(arg->y_grad_tbl[i * 2], + arg->y_grad_tbl[i * 2 + 1]); + rkisp1_iowrite32(params_vdev, data, + CIF_ISP_LSC_YGRAD_01 + i * 4); + } + + /* restore the lsc ctrl status */ + if (lsc_ctrl & CIF_ISP_LSC_CTRL_ENA) { + isp_param_set_bits(params_vdev, + CIF_ISP_LSC_CTRL, + CIF_ISP_LSC_CTRL_ENA); + } else { + isp_param_clear_bits(params_vdev, + CIF_ISP_LSC_CTRL, + CIF_ISP_LSC_CTRL_ENA); + } +} + +/* ISP Filtering function */ +static void flt_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_flt_config *arg) +{ + u32 filt_mode; + + rkisp1_iowrite32(params_vdev, arg->thresh_bl0, CIF_ISP_FILT_THRESH_BL0); + rkisp1_iowrite32(params_vdev, arg->thresh_bl1, CIF_ISP_FILT_THRESH_BL1); + rkisp1_iowrite32(params_vdev, arg->thresh_sh0, CIF_ISP_FILT_THRESH_SH0); + rkisp1_iowrite32(params_vdev, arg->thresh_sh1, CIF_ISP_FILT_THRESH_SH1); + rkisp1_iowrite32(params_vdev, arg->fac_bl0, CIF_ISP_FILT_FAC_BL0); + rkisp1_iowrite32(params_vdev, arg->fac_bl1, CIF_ISP_FILT_FAC_BL1); + rkisp1_iowrite32(params_vdev, arg->fac_mid, CIF_ISP_FILT_FAC_MID); + rkisp1_iowrite32(params_vdev, arg->fac_sh0, CIF_ISP_FILT_FAC_SH0); + rkisp1_iowrite32(params_vdev, arg->fac_sh1, CIF_ISP_FILT_FAC_SH1); + rkisp1_iowrite32(params_vdev, arg->lum_weight, CIF_ISP_FILT_LUM_WEIGHT); + + rkisp1_iowrite32(params_vdev, (arg->mode ? CIF_ISP_FLT_MODE_DNR : 0) | + CIF_ISP_FLT_CHROMA_V_MODE(arg->chr_v_mode) | + CIF_ISP_FLT_CHROMA_H_MODE(arg->chr_h_mode) | + CIF_ISP_FLT_GREEN_STAGE1(arg->grn_stage1), + CIF_ISP_FILT_MODE); + + /* avoid to override the old enable value */ + filt_mode = rkisp1_ioread32(params_vdev, CIF_ISP_FILT_MODE); + filt_mode &= CIF_ISP_FLT_ENA; + if (arg->mode) + filt_mode |= CIF_ISP_FLT_MODE_DNR; + filt_mode |= CIF_ISP_FLT_CHROMA_V_MODE(arg->chr_v_mode) | + CIF_ISP_FLT_CHROMA_H_MODE(arg->chr_h_mode) | + CIF_ISP_FLT_GREEN_STAGE1(arg->grn_stage1); + rkisp1_iowrite32(params_vdev, filt_mode, CIF_ISP_FILT_MODE); +} + +/* ISP demosaic interface function */ +static int bdm_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_bdm_config *arg) +{ + u32 bdm_th; + + /* avoid to override the old enable value */ + bdm_th = rkisp1_ioread32(params_vdev, CIF_ISP_DEMOSAIC); + bdm_th &= CIF_ISP_DEMOSAIC_BYPASS; + bdm_th |= arg->demosaic_th & ~CIF_ISP_DEMOSAIC_BYPASS; + /* set demosaic threshold */ + rkisp1_iowrite32(params_vdev, bdm_th, CIF_ISP_DEMOSAIC); + return 0; +} + +/* ISP GAMMA correction interface function */ +static void sdg_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_sdg_config *arg) +{ + unsigned int i; + + rkisp1_iowrite32(params_vdev, + arg->xa_pnts.gamma_dx0, CIF_ISP_GAMMA_DX_LO); + rkisp1_iowrite32(params_vdev, + arg->xa_pnts.gamma_dx1, CIF_ISP_GAMMA_DX_HI); + + for (i = 0; i < CIFISP_DEGAMMA_CURVE_SIZE; i++) { + rkisp1_iowrite32(params_vdev, arg->curve_r.gamma_y[i], + CIF_ISP_GAMMA_R_Y0 + i * 4); + rkisp1_iowrite32(params_vdev, arg->curve_g.gamma_y[i], + CIF_ISP_GAMMA_G_Y0 + i * 4); + rkisp1_iowrite32(params_vdev, arg->curve_b.gamma_y[i], + CIF_ISP_GAMMA_B_Y0 + i * 4); + } +} + +/* ISP GAMMA correction interface function */ +static void goc_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_goc_config *arg) +{ + unsigned int i; + + isp_param_clear_bits(params_vdev, CIF_ISP_CTRL, + CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA); + rkisp1_iowrite32(params_vdev, arg->mode, CIF_ISP_GAMMA_OUT_MODE); + + for (i = 0; i < CIFISP_GAMMA_OUT_MAX_SAMPLES; i++) + rkisp1_iowrite32(params_vdev, arg->gamma_y[i], + CIF_ISP_GAMMA_OUT_Y_0 + i * 4); +} + +/* ISP Cross Talk */ +static void ctk_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_ctk_config *arg) +{ + rkisp1_iowrite32(params_vdev, arg->coeff0, CIF_ISP_CT_COEFF_0); + rkisp1_iowrite32(params_vdev, arg->coeff1, CIF_ISP_CT_COEFF_1); + rkisp1_iowrite32(params_vdev, arg->coeff2, CIF_ISP_CT_COEFF_2); + rkisp1_iowrite32(params_vdev, arg->coeff3, CIF_ISP_CT_COEFF_3); + rkisp1_iowrite32(params_vdev, arg->coeff4, CIF_ISP_CT_COEFF_4); + rkisp1_iowrite32(params_vdev, arg->coeff5, CIF_ISP_CT_COEFF_5); + rkisp1_iowrite32(params_vdev, arg->coeff6, CIF_ISP_CT_COEFF_6); + rkisp1_iowrite32(params_vdev, arg->coeff7, CIF_ISP_CT_COEFF_7); + rkisp1_iowrite32(params_vdev, arg->coeff8, CIF_ISP_CT_COEFF_8); + rkisp1_iowrite32(params_vdev, arg->ct_offset_r, CIF_ISP_CT_OFFSET_R); + rkisp1_iowrite32(params_vdev, arg->ct_offset_g, CIF_ISP_CT_OFFSET_G); + rkisp1_iowrite32(params_vdev, arg->ct_offset_b, CIF_ISP_CT_OFFSET_B); +} + +static void ctk_enable(struct rkisp1_isp_params_vdev *params_vdev, bool en) +{ + if (en) + return; + + /* Write back the default values. */ + rkisp1_iowrite32(params_vdev, 0x80, CIF_ISP_CT_COEFF_0); + rkisp1_iowrite32(params_vdev, 0, CIF_ISP_CT_COEFF_1); + rkisp1_iowrite32(params_vdev, 0, CIF_ISP_CT_COEFF_2); + rkisp1_iowrite32(params_vdev, 0, CIF_ISP_CT_COEFF_3); + rkisp1_iowrite32(params_vdev, 0x80, CIF_ISP_CT_COEFF_4); + rkisp1_iowrite32(params_vdev, 0, CIF_ISP_CT_COEFF_5); + rkisp1_iowrite32(params_vdev, 0, CIF_ISP_CT_COEFF_6); + rkisp1_iowrite32(params_vdev, 0, CIF_ISP_CT_COEFF_7); + rkisp1_iowrite32(params_vdev, 0x80, CIF_ISP_CT_COEFF_8); + + rkisp1_iowrite32(params_vdev, 0, CIF_ISP_CT_OFFSET_R); + rkisp1_iowrite32(params_vdev, 0, CIF_ISP_CT_OFFSET_G); + rkisp1_iowrite32(params_vdev, 0, CIF_ISP_CT_OFFSET_B); +} + +/* ISP White Balance Mode */ +static void awb_meas_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_awb_meas_config *arg) +{ + u32 reg_val = 0; + /* based on the mode,configure the awb module */ + if (arg->awb_mode == CIFISP_AWB_MODE_YCBCR) { + /* Reference Cb and Cr */ + rkisp1_iowrite32(params_vdev, + CIF_ISP_AWB_REF_CR_SET(arg->awb_ref_cr) | + arg->awb_ref_cb, CIF_ISP_AWB_REF); + /* Yc Threshold */ + rkisp1_iowrite32(params_vdev, + CIF_ISP_AWB_MAX_Y_SET(arg->max_y) | + CIF_ISP_AWB_MIN_Y_SET(arg->min_y) | + CIF_ISP_AWB_MAX_CS_SET(arg->max_csum) | + arg->min_c, CIF_ISP_AWB_THRESH); + } + + reg_val = rkisp1_ioread32(params_vdev, CIF_ISP_AWB_PROP); + if (arg->enable_ymax_cmp) + reg_val |= CIF_ISP_AWB_YMAX_CMP_EN; + else + reg_val &= ~CIF_ISP_AWB_YMAX_CMP_EN; + rkisp1_iowrite32(params_vdev, reg_val, CIF_ISP_AWB_PROP); + + /* window offset */ + rkisp1_iowrite32(params_vdev, + arg->awb_wnd.v_offs, CIF_ISP_AWB_WND_V_OFFS); + rkisp1_iowrite32(params_vdev, + arg->awb_wnd.h_offs, CIF_ISP_AWB_WND_H_OFFS); + /* AWB window size */ + rkisp1_iowrite32(params_vdev, + arg->awb_wnd.v_size, CIF_ISP_AWB_WND_V_SIZE); + rkisp1_iowrite32(params_vdev, + arg->awb_wnd.h_size, CIF_ISP_AWB_WND_H_SIZE); + /* Number of frames */ + rkisp1_iowrite32(params_vdev, + arg->frames, CIF_ISP_AWB_FRAMES); +} + +static void awb_meas_enable(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_awb_meas_config *arg, bool en) +{ + u32 reg_val = rkisp1_ioread32(params_vdev, CIF_ISP_AWB_PROP); + + /* switch off */ + reg_val &= CIF_ISP_AWB_MODE_MASK_NONE; + + if (en) { + if (arg->awb_mode == CIFISP_AWB_MODE_RGB) + reg_val |= CIF_ISP_AWB_MODE_RGB_EN; + else + reg_val |= CIF_ISP_AWB_MODE_YCBCR_EN; + + rkisp1_iowrite32(params_vdev, reg_val, CIF_ISP_AWB_PROP); + + /* Measurements require AWB block be active. */ + /* TODO: need to enable here ? awb_gain_enable has done this */ + isp_param_set_bits(params_vdev, CIF_ISP_CTRL, + CIF_ISP_CTRL_ISP_AWB_ENA); + } else { + rkisp1_iowrite32(params_vdev, + reg_val, CIF_ISP_AWB_PROP); + isp_param_clear_bits(params_vdev, CIF_ISP_CTRL, + CIF_ISP_CTRL_ISP_AWB_ENA); + } +} + +static void awb_gain_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_awb_gain_config *arg) +{ + rkisp1_iowrite32(params_vdev, + CIF_ISP_AWB_GAIN_R_SET(arg->gain_green_r) | + arg->gain_green_b, CIF_ISP_AWB_GAIN_G); + + rkisp1_iowrite32(params_vdev, CIF_ISP_AWB_GAIN_R_SET(arg->gain_red) | + arg->gain_blue, CIF_ISP_AWB_GAIN_RB); +} + +static void aec_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_aec_config *arg) +{ + unsigned int block_hsize, block_vsize; + u32 exp_ctrl; + + /* avoid to override the old enable value */ + exp_ctrl = rkisp1_ioread32(params_vdev, CIF_ISP_EXP_CTRL); + exp_ctrl &= CIF_ISP_EXP_ENA; + if (arg->autostop) + exp_ctrl |= CIF_ISP_EXP_CTRL_AUTOSTOP; + if (arg->mode == CIFISP_EXP_MEASURING_MODE_1) + exp_ctrl |= CIF_ISP_EXP_CTRL_MEASMODE_1; + rkisp1_iowrite32(params_vdev, exp_ctrl, CIF_ISP_EXP_CTRL); + + rkisp1_iowrite32(params_vdev, + arg->meas_window.h_offs, CIF_ISP_EXP_H_OFFSET); + rkisp1_iowrite32(params_vdev, + arg->meas_window.v_offs, CIF_ISP_EXP_V_OFFSET); + + block_hsize = arg->meas_window.h_size / CIF_ISP_EXP_COLUMN_NUM - 1; + block_vsize = arg->meas_window.v_size / CIF_ISP_EXP_ROW_NUM - 1; + + rkisp1_iowrite32(params_vdev, CIF_ISP_EXP_H_SIZE_SET(block_hsize), + CIF_ISP_EXP_H_SIZE); + rkisp1_iowrite32(params_vdev, CIF_ISP_EXP_V_SIZE_SET(block_vsize), + CIF_ISP_EXP_V_SIZE); +} + +static void cproc_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_cproc_config *arg) +{ + struct cifisp_isp_other_cfg *cur_other_cfg = + ¶ms_vdev->cur_params.others; + struct cifisp_ie_config *cur_ie_config = &cur_other_cfg->ie_config; + u32 effect = cur_ie_config->effect; + u32 quantization = params_vdev->quantization; + + rkisp1_iowrite32(params_vdev, arg->contrast, CIF_C_PROC_CONTRAST); + rkisp1_iowrite32(params_vdev, arg->hue, CIF_C_PROC_HUE); + rkisp1_iowrite32(params_vdev, arg->sat, CIF_C_PROC_SATURATION); + rkisp1_iowrite32(params_vdev, arg->brightness, CIF_C_PROC_BRIGHTNESS); + + if (quantization != V4L2_QUANTIZATION_FULL_RANGE || + effect != V4L2_COLORFX_NONE) { + isp_param_clear_bits(params_vdev, CIF_C_PROC_CTRL, + CIF_C_PROC_YOUT_FULL | + CIF_C_PROC_YIN_FULL | + CIF_C_PROC_COUT_FULL); + } else { + isp_param_set_bits(params_vdev, CIF_C_PROC_CTRL, + CIF_C_PROC_YOUT_FULL | + CIF_C_PROC_YIN_FULL | + CIF_C_PROC_COUT_FULL); + } +} + +static void hst_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_hst_config *arg) +{ + unsigned int block_hsize, block_vsize; + static const u32 hist_weight_regs[] = { + CIF_ISP_HIST_WEIGHT_00TO30, CIF_ISP_HIST_WEIGHT_40TO21, + CIF_ISP_HIST_WEIGHT_31TO12, CIF_ISP_HIST_WEIGHT_22TO03, + CIF_ISP_HIST_WEIGHT_13TO43, CIF_ISP_HIST_WEIGHT_04TO34, + CIF_ISP_HIST_WEIGHT_44, + }; + const u8 *weight; + unsigned int i; + u32 hist_prop; + + /* avoid to override the old enable value */ + hist_prop = rkisp1_ioread32(params_vdev, CIF_ISP_HIST_PROP); + hist_prop &= CIF_ISP_HIST_PROP_MODE_MASK; + hist_prop |= CIF_ISP_HIST_PREDIV_SET(arg->histogram_predivider); + rkisp1_iowrite32(params_vdev, hist_prop, CIF_ISP_HIST_PROP); + rkisp1_iowrite32(params_vdev, + arg->meas_window.h_offs, + CIF_ISP_HIST_H_OFFS); + rkisp1_iowrite32(params_vdev, + arg->meas_window.v_offs, + CIF_ISP_HIST_V_OFFS); + + block_hsize = arg->meas_window.h_size / CIF_ISP_HIST_COLUMN_NUM - 1; + block_vsize = arg->meas_window.v_size / CIF_ISP_HIST_ROW_NUM - 1; + + rkisp1_iowrite32(params_vdev, block_hsize, CIF_ISP_HIST_H_SIZE); + rkisp1_iowrite32(params_vdev, block_vsize, CIF_ISP_HIST_V_SIZE); + + weight = arg->hist_weight; + for (i = 0; i < ARRAY_SIZE(hist_weight_regs); ++i, weight += 4) + rkisp1_iowrite32(params_vdev, CIF_ISP_HIST_WEIGHT_SET( + weight[0], weight[1], weight[2], weight[3]), + hist_weight_regs[i]); +} + +static void hst_enable(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_hst_config *arg, bool en) +{ + if (en) { + u32 hist_prop = rkisp1_ioread32(params_vdev, CIF_ISP_HIST_PROP); + + hist_prop &= ~CIF_ISP_HIST_PROP_MODE_MASK; + hist_prop |= arg->mode; + isp_param_set_bits(params_vdev, CIF_ISP_HIST_PROP, hist_prop); + } else { + isp_param_clear_bits(params_vdev, CIF_ISP_HIST_PROP, + CIF_ISP_HIST_PROP_MODE_MASK); + } +} + +static void afm_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_afc_config *arg) +{ + size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->afm_win), + arg->num_afm_win); + u32 afm_ctrl = rkisp1_ioread32(params_vdev, CIF_ISP_AFM_CTRL); + unsigned int i; + + /* Switch off to configure. */ + isp_param_clear_bits(params_vdev, CIF_ISP_AFM_CTRL, CIF_ISP_AFM_ENA); + + for (i = 0; i < num_of_win; i++) { + rkisp1_iowrite32(params_vdev, + CIF_ISP_AFM_WINDOW_X(arg->afm_win[i].h_offs) | + CIF_ISP_AFM_WINDOW_Y(arg->afm_win[i].v_offs), + CIF_ISP_AFM_LT_A + i * 8); + rkisp1_iowrite32(params_vdev, + CIF_ISP_AFM_WINDOW_X(arg->afm_win[i].h_size + + arg->afm_win[i].h_offs) | + CIF_ISP_AFM_WINDOW_Y(arg->afm_win[i].v_size + + arg->afm_win[i].v_offs), + CIF_ISP_AFM_RB_A + i * 8); + } + rkisp1_iowrite32(params_vdev, arg->thres, CIF_ISP_AFM_THRES); + rkisp1_iowrite32(params_vdev, arg->var_shift, CIF_ISP_AFM_VAR_SHIFT); + /* restore afm status */ + rkisp1_iowrite32(params_vdev, afm_ctrl, CIF_ISP_AFM_CTRL); +} + +static void ie_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_ie_config *arg) +{ + u32 eff_ctrl; + + eff_ctrl = rkisp1_ioread32(params_vdev, CIF_IMG_EFF_CTRL); + eff_ctrl &= ~CIF_IMG_EFF_CTRL_MODE_MASK; + + if (params_vdev->quantization == V4L2_QUANTIZATION_FULL_RANGE) + eff_ctrl |= CIF_IMG_EFF_CTRL_YCBCR_FULL; + + switch (arg->effect) { + case V4L2_COLORFX_SEPIA: + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SEPIA; + break; + case V4L2_COLORFX_SET_CBCR: + rkisp1_iowrite32(params_vdev, arg->eff_tint, CIF_IMG_EFF_TINT); + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SEPIA; + break; + /* + * Color selection is similar to water color(AQUA): + * grayscale + selected color w threshold + */ + case V4L2_COLORFX_AQUA: + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_COLOR_SEL; + rkisp1_iowrite32(params_vdev, arg->color_sel, + CIF_IMG_EFF_COLOR_SEL); + break; + case V4L2_COLORFX_EMBOSS: + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_EMBOSS; + rkisp1_iowrite32(params_vdev, arg->eff_mat_1, + CIF_IMG_EFF_MAT_1); + rkisp1_iowrite32(params_vdev, arg->eff_mat_2, + CIF_IMG_EFF_MAT_2); + rkisp1_iowrite32(params_vdev, arg->eff_mat_3, + CIF_IMG_EFF_MAT_3); + break; + case V4L2_COLORFX_SKETCH: + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SKETCH; + rkisp1_iowrite32(params_vdev, arg->eff_mat_3, + CIF_IMG_EFF_MAT_3); + rkisp1_iowrite32(params_vdev, arg->eff_mat_4, + CIF_IMG_EFF_MAT_4); + rkisp1_iowrite32(params_vdev, arg->eff_mat_5, + CIF_IMG_EFF_MAT_5); + break; + case V4L2_COLORFX_BW: + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_BLACKWHITE; + break; + case V4L2_COLORFX_NEGATIVE: + eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_NEGATIVE; + break; + default: + break; + } + + rkisp1_iowrite32(params_vdev, eff_ctrl, CIF_IMG_EFF_CTRL); +} + +static void ie_enable(struct rkisp1_isp_params_vdev *params_vdev, bool en) +{ + if (en) { + isp_param_set_bits(params_vdev, CIF_ICCL, CIF_ICCL_IE_CLK); + rkisp1_iowrite32(params_vdev, CIF_IMG_EFF_CTRL_ENABLE, + CIF_IMG_EFF_CTRL); + isp_param_set_bits(params_vdev, CIF_IMG_EFF_CTRL, + CIF_IMG_EFF_CTRL_CFG_UPD); + } else { + isp_param_clear_bits(params_vdev, CIF_IMG_EFF_CTRL, + CIF_IMG_EFF_CTRL_ENABLE); + isp_param_clear_bits(params_vdev, CIF_ICCL, CIF_ICCL_IE_CLK); + } +} + +static void csm_config(struct rkisp1_isp_params_vdev *params_vdev, + bool full_range) +{ + static const u16 full_range_coeff[] = { + 0x0026, 0x004b, 0x000f, + 0x01ea, 0x01d6, 0x0040, + 0x0040, 0x01ca, 0x01f6 + }; + static const u16 limited_range_coeff[] = { + 0x0021, 0x0040, 0x000d, + 0x01ed, 0x01db, 0x0038, + 0x0038, 0x01d1, 0x01f7, + }; + unsigned int i; + + if (full_range) { + for (i = 0; i < ARRAY_SIZE(full_range_coeff); i++) + rkisp1_iowrite32(params_vdev, full_range_coeff[i], + CIF_ISP_CC_COEFF_0 + i * 4); + + isp_param_set_bits(params_vdev, CIF_ISP_CTRL, + CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA | + CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA); + } else { + for (i = 0; i < ARRAY_SIZE(limited_range_coeff); i++) + rkisp1_iowrite32(params_vdev, limited_range_coeff[i], + CIF_ISP_CC_COEFF_0 + i * 4); + + isp_param_clear_bits(params_vdev, CIF_ISP_CTRL, + CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA | + CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA); + } +} + +/* ISP De-noise Pre-Filter(DPF) function */ +static void dpf_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_dpf_config *arg) +{ + unsigned int isp_dpf_mode, spatial_coeff, i; + + switch (arg->gain.mode) { + case CIFISP_DPF_GAIN_USAGE_NF_GAINS: + isp_dpf_mode = CIF_ISP_DPF_MODE_USE_NF_GAIN | + CIF_ISP_DPF_MODE_AWB_GAIN_COMP; + break; + case CIFISP_DPF_GAIN_USAGE_LSC_GAINS: + isp_dpf_mode = CIF_ISP_DPF_MODE_LSC_GAIN_COMP; + break; + case CIFISP_DPF_GAIN_USAGE_NF_LSC_GAINS: + isp_dpf_mode = CIF_ISP_DPF_MODE_USE_NF_GAIN | + CIF_ISP_DPF_MODE_AWB_GAIN_COMP | + CIF_ISP_DPF_MODE_LSC_GAIN_COMP; + break; + case CIFISP_DPF_GAIN_USAGE_AWB_GAINS: + isp_dpf_mode = CIF_ISP_DPF_MODE_AWB_GAIN_COMP; + break; + case CIFISP_DPF_GAIN_USAGE_AWB_LSC_GAINS: + isp_dpf_mode = CIF_ISP_DPF_MODE_LSC_GAIN_COMP | + CIF_ISP_DPF_MODE_AWB_GAIN_COMP; + break; + case CIFISP_DPF_GAIN_USAGE_DISABLED: + default: + isp_dpf_mode = 0; + break; + } + + if (arg->nll.scale_mode == CIFISP_NLL_SCALE_LOGARITHMIC) + isp_dpf_mode |= CIF_ISP_DPF_MODE_NLL_SEGMENTATION; + if (arg->rb_flt.fltsize == CIFISP_DPF_RB_FILTERSIZE_9x9) + isp_dpf_mode |= CIF_ISP_DPF_MODE_RB_FLTSIZE_9x9; + if (!arg->rb_flt.r_enable) + isp_dpf_mode |= CIF_ISP_DPF_MODE_R_FLT_DIS; + if (!arg->rb_flt.b_enable) + isp_dpf_mode |= CIF_ISP_DPF_MODE_B_FLT_DIS; + if (!arg->g_flt.gb_enable) + isp_dpf_mode |= CIF_ISP_DPF_MODE_GB_FLT_DIS; + if (!arg->g_flt.gr_enable) + isp_dpf_mode |= CIF_ISP_DPF_MODE_GR_FLT_DIS; + + isp_param_set_bits(params_vdev, CIF_ISP_DPF_MODE, isp_dpf_mode); + rkisp1_iowrite32(params_vdev, arg->gain.nf_b_gain, + CIF_ISP_DPF_NF_GAIN_B); + rkisp1_iowrite32(params_vdev, arg->gain.nf_r_gain, + CIF_ISP_DPF_NF_GAIN_R); + rkisp1_iowrite32(params_vdev, arg->gain.nf_gb_gain, + CIF_ISP_DPF_NF_GAIN_GB); + rkisp1_iowrite32(params_vdev, arg->gain.nf_gr_gain, + CIF_ISP_DPF_NF_GAIN_GR); + + for (i = 0; i < CIFISP_DPF_MAX_NLF_COEFFS; i++) { + rkisp1_iowrite32(params_vdev, arg->nll.coeff[i], + CIF_ISP_DPF_NULL_COEFF_0 + i * 4); + } + + spatial_coeff = arg->g_flt.spatial_coeff[0] | + (arg->g_flt.spatial_coeff[1] << 8) | + (arg->g_flt.spatial_coeff[2] << 16) | + (arg->g_flt.spatial_coeff[3] << 24); + rkisp1_iowrite32(params_vdev, spatial_coeff, + CIF_ISP_DPF_S_WEIGHT_G_1_4); + + spatial_coeff = arg->g_flt.spatial_coeff[4] | + (arg->g_flt.spatial_coeff[5] << 8); + rkisp1_iowrite32(params_vdev, spatial_coeff, + CIF_ISP_DPF_S_WEIGHT_G_5_6); + + spatial_coeff = arg->rb_flt.spatial_coeff[0] | + (arg->rb_flt.spatial_coeff[1] << 8) | + (arg->rb_flt.spatial_coeff[2] << 16) | + (arg->rb_flt.spatial_coeff[3] << 24); + rkisp1_iowrite32(params_vdev, spatial_coeff, + CIF_ISP_DPF_S_WEIGHT_RB_1_4); + + spatial_coeff = arg->rb_flt.spatial_coeff[4] | + (arg->rb_flt.spatial_coeff[5] << 8); + rkisp1_iowrite32(params_vdev, spatial_coeff, + CIF_ISP_DPF_S_WEIGHT_RB_5_6); +} + +static void dpf_strength_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_dpf_strength_config *arg) +{ + rkisp1_iowrite32(params_vdev, arg->b, CIF_ISP_DPF_STRENGTH_B); + rkisp1_iowrite32(params_vdev, arg->g, CIF_ISP_DPF_STRENGTH_G); + rkisp1_iowrite32(params_vdev, arg->r, CIF_ISP_DPF_STRENGTH_R); +} + +static __maybe_unused +void __isp_isr_other_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct rkisp1_isp_params_cfg *new_params) +{ + unsigned int module_en_update, module_cfg_update, module_ens; + + module_en_update = new_params->module_en_update; + module_cfg_update = new_params->module_cfg_update; + module_ens = new_params->module_ens; + + if ((module_en_update & CIFISP_MODULE_DPCC) || + (module_cfg_update & CIFISP_MODULE_DPCC)) { + /*update dpc config */ + if ((module_cfg_update & CIFISP_MODULE_DPCC)) + dpcc_config(params_vdev, + &new_params->others.dpcc_config); + + if (module_en_update & CIFISP_MODULE_DPCC) { + if (!!(module_ens & CIFISP_MODULE_DPCC)) + isp_param_set_bits(params_vdev, + CIF_ISP_DPCC_MODE, + CIF_ISP_DPCC_ENA); + else + isp_param_clear_bits(params_vdev, + CIF_ISP_DPCC_MODE, + CIF_ISP_DPCC_ENA); + } + } + + if ((module_en_update & CIFISP_MODULE_BLS) || + (module_cfg_update & CIFISP_MODULE_BLS)) { + /* update bls config */ + if ((module_cfg_update & CIFISP_MODULE_BLS)) + bls_config(params_vdev, &new_params->others.bls_config); + + if (module_en_update & CIFISP_MODULE_BLS) { + if (!!(module_ens & CIFISP_MODULE_BLS)) + isp_param_set_bits(params_vdev, + CIF_ISP_BLS_CTRL, + CIF_ISP_BLS_ENA); + else + isp_param_clear_bits(params_vdev, + CIF_ISP_BLS_CTRL, + CIF_ISP_BLS_ENA); + } + } + + if ((module_en_update & CIFISP_MODULE_SDG) || + (module_cfg_update & CIFISP_MODULE_SDG)) { + /* update sdg config */ + if ((module_cfg_update & CIFISP_MODULE_SDG)) + sdg_config(params_vdev, &new_params->others.sdg_config); + + if (module_en_update & CIFISP_MODULE_SDG) { + if (!!(module_ens & CIFISP_MODULE_SDG)) + isp_param_set_bits(params_vdev, + CIF_ISP_CTRL, + CIF_ISP_CTRL_ISP_GAMMA_IN_ENA); + else + isp_param_clear_bits(params_vdev, + CIF_ISP_CTRL, + CIF_ISP_CTRL_ISP_GAMMA_IN_ENA); + } + } + + if ((module_en_update & CIFISP_MODULE_LSC) || + (module_cfg_update & CIFISP_MODULE_LSC)) { + /* update lsc config */ + if ((module_cfg_update & CIFISP_MODULE_LSC)) + lsc_config(params_vdev, &new_params->others.lsc_config); + + if (module_en_update & CIFISP_MODULE_LSC) { + if (!!(module_ens & CIFISP_MODULE_LSC)) + isp_param_set_bits(params_vdev, + CIF_ISP_LSC_CTRL, + CIF_ISP_LSC_CTRL_ENA); + else + isp_param_clear_bits(params_vdev, + CIF_ISP_LSC_CTRL, + CIF_ISP_LSC_CTRL_ENA); + } + } + + if ((module_en_update & CIFISP_MODULE_AWB_GAIN) || + (module_cfg_update & CIFISP_MODULE_AWB_GAIN)) { + /* update awb gains */ + if ((module_cfg_update & CIFISP_MODULE_AWB_GAIN)) + awb_gain_config(params_vdev, + &new_params->others.awb_gain_config); + + if (module_en_update & CIFISP_MODULE_AWB_GAIN) { + if (!!(module_ens & CIFISP_MODULE_AWB_GAIN)) + isp_param_set_bits(params_vdev, + CIF_ISP_CTRL, + CIF_ISP_CTRL_ISP_AWB_ENA); + else + isp_param_clear_bits(params_vdev, + CIF_ISP_CTRL, + CIF_ISP_CTRL_ISP_AWB_ENA); + } + } + + if ((module_en_update & CIFISP_MODULE_BDM) || + (module_cfg_update & CIFISP_MODULE_BDM)) { + /* update bdm config */ + if ((module_cfg_update & CIFISP_MODULE_BDM)) + bdm_config(params_vdev, &new_params->others.bdm_config); + + if (module_en_update & CIFISP_MODULE_BDM) { + if (!!(module_ens & CIFISP_MODULE_BDM)) + isp_param_set_bits(params_vdev, + CIF_ISP_DEMOSAIC, + CIF_ISP_DEMOSAIC_BYPASS); + else + isp_param_clear_bits(params_vdev, + CIF_ISP_DEMOSAIC, + CIF_ISP_DEMOSAIC_BYPASS); + } + } + + if ((module_en_update & CIFISP_MODULE_FLT) || + (module_cfg_update & CIFISP_MODULE_FLT)) { + /* update filter config */ + if ((module_cfg_update & CIFISP_MODULE_FLT)) + flt_config(params_vdev, &new_params->others.flt_config); + + if (module_en_update & CIFISP_MODULE_FLT) { + if (!!(module_ens & CIFISP_MODULE_FLT)) + isp_param_set_bits(params_vdev, + CIF_ISP_FILT_MODE, + CIF_ISP_FLT_ENA); + else + isp_param_clear_bits(params_vdev, + CIF_ISP_FILT_MODE, + CIF_ISP_FLT_ENA); + } + } + + if ((module_en_update & CIFISP_MODULE_CTK) || + (module_cfg_update & CIFISP_MODULE_CTK)) { + /* update ctk config */ + if ((module_cfg_update & CIFISP_MODULE_CTK)) + ctk_config(params_vdev, &new_params->others.ctk_config); + + if (module_en_update & CIFISP_MODULE_CTK) + ctk_enable(params_vdev, + !!(module_ens & CIFISP_MODULE_CTK)); + } + + if ((module_en_update & CIFISP_MODULE_GOC) || + (module_cfg_update & CIFISP_MODULE_GOC)) { + /* update goc config */ + if ((module_cfg_update & CIFISP_MODULE_GOC)) + goc_config(params_vdev, &new_params->others.goc_config); + + if (module_en_update & CIFISP_MODULE_GOC) { + if (!!(module_ens & CIFISP_MODULE_GOC)) + isp_param_set_bits(params_vdev, + CIF_ISP_CTRL, + CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA); + else + isp_param_clear_bits(params_vdev, + CIF_ISP_CTRL, + CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA); + } + } + + if ((module_en_update & CIFISP_MODULE_CPROC) || + (module_cfg_update & CIFISP_MODULE_CPROC)) { + /* update cproc config */ + if ((module_cfg_update & CIFISP_MODULE_CPROC)) { + cproc_config(params_vdev, + &new_params->others.cproc_config); + + } + + if (module_en_update & CIFISP_MODULE_CPROC) { + if (!!(module_ens & CIFISP_MODULE_CPROC)) + isp_param_set_bits(params_vdev, + CIF_C_PROC_CTRL, + CIF_C_PROC_CTR_ENABLE); + else + isp_param_clear_bits(params_vdev, + CIF_C_PROC_CTRL, + CIF_C_PROC_CTR_ENABLE); + } + } + + if ((module_en_update & CIFISP_MODULE_IE) || + (module_cfg_update & CIFISP_MODULE_IE)) { + /* update ie config */ + if ((module_cfg_update & CIFISP_MODULE_IE)) + ie_config(params_vdev, &new_params->others.ie_config); + + if (module_en_update & CIFISP_MODULE_IE) + ie_enable(params_vdev, + !!(module_ens & CIFISP_MODULE_IE)); + } + + if ((module_en_update & CIFISP_MODULE_DPF) || + (module_cfg_update & CIFISP_MODULE_DPF)) { + /* update dpf config */ + if ((module_cfg_update & CIFISP_MODULE_DPF)) + dpf_config(params_vdev, &new_params->others.dpf_config); + + if (module_en_update & CIFISP_MODULE_DPF) { + if (!!(module_ens & CIFISP_MODULE_DPF)) + isp_param_set_bits(params_vdev, + CIF_ISP_DPF_MODE, + CIF_ISP_DPF_MODE_EN); + else + isp_param_clear_bits(params_vdev, + CIF_ISP_DPF_MODE, + CIF_ISP_DPF_MODE_EN); + } + } + + if ((module_en_update & CIFISP_MODULE_DPF_STRENGTH) || + (module_cfg_update & CIFISP_MODULE_DPF_STRENGTH)) { + /* update dpf strength config */ + dpf_strength_config(params_vdev, + &new_params->others.dpf_strength_config); + } +} + +static __maybe_unused +void __isp_isr_meas_config(struct rkisp1_isp_params_vdev *params_vdev, + struct rkisp1_isp_params_cfg *new_params) +{ + unsigned int module_en_update, module_cfg_update, module_ens; + + module_en_update = new_params->module_en_update; + module_cfg_update = new_params->module_cfg_update; + module_ens = new_params->module_ens; + + if ((module_en_update & CIFISP_MODULE_AWB) || + (module_cfg_update & CIFISP_MODULE_AWB)) { + /* update awb config */ + if ((module_cfg_update & CIFISP_MODULE_AWB)) + awb_meas_config(params_vdev, + &new_params->meas.awb_meas_config); + + if (module_en_update & CIFISP_MODULE_AWB) + awb_meas_enable(params_vdev, + &new_params->meas.awb_meas_config, + !!(module_ens & CIFISP_MODULE_AWB)); + } + + if ((module_en_update & CIFISP_MODULE_AFC) || + (module_cfg_update & CIFISP_MODULE_AFC)) { + /* update afc config */ + if ((module_cfg_update & CIFISP_MODULE_AFC)) + afm_config(params_vdev, &new_params->meas.afc_config); + + if (module_en_update & CIFISP_MODULE_AFC) { + if (!!(module_ens & CIFISP_MODULE_AFC)) + isp_param_set_bits(params_vdev, + CIF_ISP_AFM_CTRL, + CIF_ISP_AFM_ENA); + else + isp_param_clear_bits(params_vdev, + CIF_ISP_AFM_CTRL, + CIF_ISP_AFM_ENA); + } + } + + if ((module_en_update & CIFISP_MODULE_HST) || + (module_cfg_update & CIFISP_MODULE_HST)) { + /* update hst config */ + if ((module_cfg_update & CIFISP_MODULE_HST)) + hst_config(params_vdev, &new_params->meas.hst_config); + + if (module_en_update & CIFISP_MODULE_HST) + hst_enable(params_vdev, + &new_params->meas.hst_config, + !!(module_ens & CIFISP_MODULE_HST)); + } + + if ((module_en_update & CIFISP_MODULE_AEC) || + (module_cfg_update & CIFISP_MODULE_AEC)) { + /* update aec config */ + if ((module_cfg_update & CIFISP_MODULE_AEC)) + aec_config(params_vdev, &new_params->meas.aec_config); + + if (module_en_update & CIFISP_MODULE_AEC) { + if (!!(module_ens & CIFISP_MODULE_AEC)) + isp_param_set_bits(params_vdev, + CIF_ISP_EXP_CTRL, + CIF_ISP_EXP_ENA); + else + isp_param_clear_bits(params_vdev, + CIF_ISP_EXP_CTRL, + CIF_ISP_EXP_ENA); + } + } +} + +void rkisp1_params_isr(struct rkisp1_isp_params_vdev *params_vdev, u32 isp_mis) +{ + struct rkisp1_isp_params_cfg *new_params; + struct rkisp1_buffer *cur_buf = NULL; + unsigned int cur_frame_id = -1; + + cur_frame_id = + atomic_read(¶ms_vdev->dev->isp_sdev.frm_sync_seq) - 1; + + spin_lock(¶ms_vdev->config_lock); + if (!params_vdev->streamon) { + spin_unlock(¶ms_vdev->config_lock); + return; + } + + /* get one empty buffer */ + if (!list_empty(¶ms_vdev->params)) + cur_buf = list_first_entry(¶ms_vdev->params, + struct rkisp1_buffer, queue); + spin_unlock(¶ms_vdev->config_lock); + + if (!cur_buf) + return; + + new_params = (struct rkisp1_isp_params_cfg *)(cur_buf->vaddr[0]); + + if (isp_mis & CIF_ISP_FRAME) { + u32 isp_ctrl; + + __isp_isr_other_config(params_vdev, new_params); + __isp_isr_meas_config(params_vdev, new_params); + + /* update shadow register immediately */ + isp_ctrl = rkisp1_ioread32(params_vdev, CIF_ISP_CTRL); + isp_ctrl |= CIF_ISP_CTRL_ISP_CFG_UPD; + rkisp1_iowrite32(params_vdev, isp_ctrl, CIF_ISP_CTRL); + + spin_lock(¶ms_vdev->config_lock); + list_del(&cur_buf->queue); + spin_unlock(¶ms_vdev->config_lock); + + cur_buf->vb.sequence = cur_frame_id; + vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + } +} + +static const struct cifisp_awb_meas_config awb_params_default_config = { + { + 0, 0, RKISP1_DEFAULT_WIDTH, RKISP1_DEFAULT_HEIGHT + }, + CIFISP_AWB_MODE_YCBCR, 200, 30, 20, 20, 0, 128, 128 +}; + +static const struct cifisp_aec_config aec_params_default_config = { + CIFISP_EXP_MEASURING_MODE_0, + CIFISP_EXP_CTRL_AUTOSTOP_0, + { + RKISP1_DEFAULT_WIDTH >> 2, RKISP1_DEFAULT_HEIGHT >> 2, + RKISP1_DEFAULT_WIDTH >> 1, RKISP1_DEFAULT_HEIGHT >> 1 + } +}; + +static const struct cifisp_hst_config hst_params_default_config = { + CIFISP_HISTOGRAM_MODE_RGB_COMBINED, + 3, + { + RKISP1_DEFAULT_WIDTH >> 2, RKISP1_DEFAULT_HEIGHT >> 2, + RKISP1_DEFAULT_WIDTH >> 1, RKISP1_DEFAULT_HEIGHT >> 1 + }, + { + 0, /* To be filled in with 0x01 at runtime. */ + } +}; + +static const struct cifisp_afc_config afc_params_default_config = { + 1, + { + { + 300, 225, 200, 150 + } + }, + 4, + 14 +}; + +static +void rkisp1_params_config_parameter(struct rkisp1_isp_params_vdev *params_vdev) +{ + struct cifisp_hst_config hst = hst_params_default_config; + + spin_lock(¶ms_vdev->config_lock); + + awb_meas_config(params_vdev, &awb_params_default_config); + awb_meas_enable(params_vdev, &awb_params_default_config, true); + + aec_config(params_vdev, &aec_params_default_config); + isp_param_set_bits(params_vdev, CIF_ISP_EXP_CTRL, CIF_ISP_EXP_ENA); + + afm_config(params_vdev, &afc_params_default_config); + isp_param_set_bits(params_vdev, CIF_ISP_AFM_CTRL, CIF_ISP_AFM_ENA); + + memset(hst.hist_weight, 0x01, sizeof(hst.hist_weight)); + hst_config(params_vdev, &hst); + isp_param_set_bits(params_vdev, CIF_ISP_HIST_PROP, + ~CIF_ISP_HIST_PROP_MODE_MASK | + hst_params_default_config.mode); + + /* set the range */ + if (params_vdev->quantization == V4L2_QUANTIZATION_FULL_RANGE) + csm_config(params_vdev, true); + else + csm_config(params_vdev, false); + + /* override the default things */ + __isp_isr_other_config(params_vdev, ¶ms_vdev->cur_params); + __isp_isr_meas_config(params_vdev, ¶ms_vdev->cur_params); + + spin_unlock(¶ms_vdev->config_lock); +} + +/* Not called when the camera active, thus not isr protection. */ +void rkisp1_params_configure_isp(struct rkisp1_isp_params_vdev *params_vdev, + struct ispsd_in_fmt *in_fmt, + enum v4l2_quantization quantization) +{ + params_vdev->quantization = quantization; + params_vdev->raw_type = in_fmt->bayer_pat; + rkisp1_params_config_parameter(params_vdev); +} + +/* Not called when the camera active, thus not isr protection. */ +void rkisp1_params_disable_isp(struct rkisp1_isp_params_vdev *params_vdev) +{ + isp_param_clear_bits(params_vdev, CIF_ISP_DPCC_MODE, CIF_ISP_DPCC_ENA); + isp_param_clear_bits(params_vdev, CIF_ISP_LSC_CTRL, + CIF_ISP_LSC_CTRL_ENA); + isp_param_clear_bits(params_vdev, CIF_ISP_BLS_CTRL, CIF_ISP_BLS_ENA); + isp_param_clear_bits(params_vdev, CIF_ISP_CTRL, + CIF_ISP_CTRL_ISP_GAMMA_IN_ENA); + isp_param_clear_bits(params_vdev, CIF_ISP_CTRL, + CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA); + isp_param_clear_bits(params_vdev, CIF_ISP_DEMOSAIC, + CIF_ISP_DEMOSAIC_BYPASS); + isp_param_clear_bits(params_vdev, CIF_ISP_FILT_MODE, CIF_ISP_FLT_ENA); + awb_meas_enable(params_vdev, NULL, false); + isp_param_clear_bits(params_vdev, CIF_ISP_CTRL, + CIF_ISP_CTRL_ISP_AWB_ENA); + isp_param_clear_bits(params_vdev, CIF_ISP_EXP_CTRL, CIF_ISP_EXP_ENA); + ctk_enable(params_vdev, false); + isp_param_clear_bits(params_vdev, CIF_C_PROC_CTRL, + CIF_C_PROC_CTR_ENABLE); + hst_enable(params_vdev, NULL, false); + isp_param_clear_bits(params_vdev, CIF_ISP_AFM_CTRL, CIF_ISP_AFM_ENA); + ie_enable(params_vdev, false); + isp_param_clear_bits(params_vdev, CIF_ISP_DPF_MODE, + CIF_ISP_DPF_MODE_EN); +} + +static int rkisp1_params_enum_fmt_meta_out(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + struct video_device *video = video_devdata(file); + struct rkisp1_isp_params_vdev *params_vdev = video_get_drvdata(video); + + if (f->index > 0 || f->type != video->queue->type) + return -EINVAL; + + f->pixelformat = params_vdev->vdev_fmt.fmt.meta.dataformat; + + return 0; +} + +static int rkisp1_params_g_fmt_meta_out(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct video_device *video = video_devdata(file); + struct rkisp1_isp_params_vdev *params_vdev = video_get_drvdata(video); + struct v4l2_meta_format *meta = &f->fmt.meta; + + if (f->type != video->queue->type) + return -EINVAL; + + memset(meta, 0, sizeof(*meta)); + meta->dataformat = params_vdev->vdev_fmt.fmt.meta.dataformat; + meta->buffersize = params_vdev->vdev_fmt.fmt.meta.buffersize; + + return 0; +} + +static int rkisp1_params_querycap(struct file *file, + void *priv, struct v4l2_capability *cap) +{ + struct video_device *vdev = video_devdata(file); + + strscpy(cap->driver, DRIVER_NAME, sizeof(cap->driver)); + strscpy(cap->card, vdev->name, sizeof(cap->card)); + strscpy(cap->bus_info, "platform: " DRIVER_NAME, sizeof(cap->bus_info)); + + return 0; +} + +/* ISP params video device IOCTLs */ +static const struct v4l2_ioctl_ops rkisp1_params_ioctl = { + .vidioc_reqbufs = vb2_ioctl_reqbufs, + .vidioc_querybuf = vb2_ioctl_querybuf, + .vidioc_create_bufs = vb2_ioctl_create_bufs, + .vidioc_qbuf = vb2_ioctl_qbuf, + .vidioc_dqbuf = vb2_ioctl_dqbuf, + .vidioc_prepare_buf = vb2_ioctl_prepare_buf, + .vidioc_expbuf = vb2_ioctl_expbuf, + .vidioc_streamon = vb2_ioctl_streamon, + .vidioc_streamoff = vb2_ioctl_streamoff, + .vidioc_enum_fmt_meta_out = rkisp1_params_enum_fmt_meta_out, + .vidioc_g_fmt_meta_out = rkisp1_params_g_fmt_meta_out, + .vidioc_s_fmt_meta_out = rkisp1_params_g_fmt_meta_out, + .vidioc_try_fmt_meta_out = rkisp1_params_g_fmt_meta_out, + .vidioc_querycap = rkisp1_params_querycap, + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +static int rkisp1_params_vb2_queue_setup(struct vb2_queue *vq, + unsigned int *num_buffers, + unsigned int *num_planes, + unsigned int sizes[], + struct device *alloc_devs[]) +{ + struct rkisp1_isp_params_vdev *params_vdev = vq->drv_priv; + + *num_buffers = clamp_t(u32, *num_buffers, + RKISP1_ISP_PARAMS_REQ_BUFS_MIN, + RKISP1_ISP_PARAMS_REQ_BUFS_MAX); + + *num_planes = 1; + + sizes[0] = sizeof(struct rkisp1_isp_params_cfg); + + INIT_LIST_HEAD(¶ms_vdev->params); + params_vdev->first_params = true; + + return 0; +} + +static void rkisp1_params_vb2_buf_queue(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct rkisp1_buffer *params_buf = to_rkisp1_buffer(vbuf); + struct vb2_queue *vq = vb->vb2_queue; + struct rkisp1_isp_params_vdev *params_vdev = vq->drv_priv; + struct rkisp1_isp_params_cfg *new_params; + unsigned long flags; + + unsigned int cur_frame_id = -1; + + cur_frame_id = + atomic_read(¶ms_vdev->dev->isp_sdev.frm_sync_seq) - 1; + + if (params_vdev->first_params) { + new_params = (struct rkisp1_isp_params_cfg *) + (vb2_plane_vaddr(vb, 0)); + vbuf->sequence = cur_frame_id; + vb2_buffer_done(¶ms_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + params_vdev->first_params = false; + params_vdev->cur_params = *new_params; + return; + } + + params_buf->vaddr[0] = vb2_plane_vaddr(vb, 0); + spin_lock_irqsave(¶ms_vdev->config_lock, flags); + list_add_tail(¶ms_buf->queue, ¶ms_vdev->params); + spin_unlock_irqrestore(¶ms_vdev->config_lock, flags); +} + +static int rkisp1_params_vb2_buf_prepare(struct vb2_buffer *vb) +{ + if (vb2_plane_size(vb, 0) < sizeof(struct rkisp1_isp_params_cfg)) + return -EINVAL; + + vb2_set_plane_payload(vb, 0, sizeof(struct rkisp1_isp_params_cfg)); + + return 0; +} + +static void rkisp1_params_vb2_stop_streaming(struct vb2_queue *vq) +{ + struct rkisp1_isp_params_vdev *params_vdev = vq->drv_priv; + struct rkisp1_buffer *buf; + unsigned long flags; + unsigned int i; + + /* stop params input firstly */ + spin_lock_irqsave(¶ms_vdev->config_lock, flags); + params_vdev->streamon = false; + spin_unlock_irqrestore(¶ms_vdev->config_lock, flags); + + for (i = 0; i < RKISP1_ISP_PARAMS_REQ_BUFS_MAX; i++) { + spin_lock_irqsave(¶ms_vdev->config_lock, flags); + if (!list_empty(¶ms_vdev->params)) { + buf = list_first_entry(¶ms_vdev->params, + struct rkisp1_buffer, queue); + list_del(&buf->queue); + spin_unlock_irqrestore(¶ms_vdev->config_lock, + flags); + } else { + spin_unlock_irqrestore(¶ms_vdev->config_lock, + flags); + break; + } + + if (buf) + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + buf = NULL; + } +} + +static int +rkisp1_params_vb2_start_streaming(struct vb2_queue *queue, unsigned int count) +{ + struct rkisp1_isp_params_vdev *params_vdev = queue->drv_priv; + unsigned long flags; + + spin_lock_irqsave(¶ms_vdev->config_lock, flags); + params_vdev->streamon = true; + spin_unlock_irqrestore(¶ms_vdev->config_lock, flags); + + return 0; +} + +static struct vb2_ops rkisp1_params_vb2_ops = { + .queue_setup = rkisp1_params_vb2_queue_setup, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, + .buf_queue = rkisp1_params_vb2_buf_queue, + .buf_prepare = rkisp1_params_vb2_buf_prepare, + .start_streaming = rkisp1_params_vb2_start_streaming, + .stop_streaming = rkisp1_params_vb2_stop_streaming, + +}; + +struct v4l2_file_operations rkisp1_params_fops = { + .mmap = vb2_fop_mmap, + .unlocked_ioctl = video_ioctl2, + .poll = vb2_fop_poll, + .open = v4l2_fh_open, + .release = vb2_fop_release +}; + +static int +rkisp1_params_init_vb2_queue(struct vb2_queue *q, + struct rkisp1_isp_params_vdev *params_vdev) +{ + struct rkisp1_vdev_node *node; + + node = queue_to_node(q); + + q->type = V4L2_BUF_TYPE_META_OUTPUT; + q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; + q->drv_priv = params_vdev; + q->ops = &rkisp1_params_vb2_ops; + q->mem_ops = &vb2_vmalloc_memops; + q->buf_struct_size = sizeof(struct rkisp1_buffer); + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->lock = &node->vlock; + + return vb2_queue_init(q); +} + +static void rkisp1_init_params_vdev(struct rkisp1_isp_params_vdev *params_vdev) +{ + params_vdev->vdev_fmt.fmt.meta.dataformat = + V4L2_META_FMT_RK_ISP1_PARAMS; + params_vdev->vdev_fmt.fmt.meta.buffersize = + sizeof(struct rkisp1_isp_params_cfg); +} + +int rkisp1_register_params_vdev(struct rkisp1_isp_params_vdev *params_vdev, + struct v4l2_device *v4l2_dev, + struct rkisp1_device *dev) +{ + struct rkisp1_vdev_node *node = ¶ms_vdev->vnode; + struct video_device *vdev = &node->vdev; + int ret; + + params_vdev->dev = dev; + mutex_init(&node->vlock); + spin_lock_init(¶ms_vdev->config_lock); + + strscpy(vdev->name, "rkisp1-input-params", sizeof(vdev->name)); + + video_set_drvdata(vdev, params_vdev); + vdev->ioctl_ops = &rkisp1_params_ioctl; + vdev->fops = &rkisp1_params_fops; + vdev->release = video_device_release_empty; + /* + * Provide a mutex to v4l2 core. It will be used + * to protect all fops and v4l2 ioctls. + */ + vdev->lock = &node->vlock; + vdev->v4l2_dev = v4l2_dev; + vdev->queue = &node->buf_queue; + vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_META_OUTPUT; + vdev->vfl_dir = VFL_DIR_TX; + rkisp1_params_init_vb2_queue(vdev->queue, params_vdev); + rkisp1_init_params_vdev(params_vdev); + video_set_drvdata(vdev, params_vdev); + + node->pad.flags = MEDIA_PAD_FL_SOURCE; + ret = media_entity_pads_init(&vdev->entity, 1, &node->pad); + if (ret < 0) + goto err_release_queue; + ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1); + if (ret < 0) { + dev_err(&vdev->dev, + "could not register Video for Linux device\n"); + goto err_cleanup_media_entity; + } + return 0; +err_cleanup_media_entity: + media_entity_cleanup(&vdev->entity); +err_release_queue: + vb2_queue_release(vdev->queue); + return ret; +} + +void rkisp1_unregister_params_vdev(struct rkisp1_isp_params_vdev *params_vdev) +{ + struct rkisp1_vdev_node *node = ¶ms_vdev->vnode; + struct video_device *vdev = &node->vdev; + + video_unregister_device(vdev); + media_entity_cleanup(&vdev->entity); + vb2_queue_release(vdev->queue); +} diff --git a/drivers/media/platform/rockchip/isp1/isp_params.h b/drivers/media/platform/rockchip/isp1/isp_params.h new file mode 100644 index 000000000000..95e5a778125b --- /dev/null +++ b/drivers/media/platform/rockchip/isp1/isp_params.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Rockchip isp1 driver + * + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. + */ + +#ifndef _RKISP1_ISP_H +#define _RKISP1_ISP_H + +#include + +#include "common.h" + +/* + * struct rkisp1_isp_subdev - ISP input parameters device + * + * @cur_params: Current ISP parameters + * @first_params: the first params should take effect immediately + */ +struct rkisp1_isp_params_vdev { + struct rkisp1_vdev_node vnode; + struct rkisp1_device *dev; + + spinlock_t config_lock; + struct list_head params; + struct rkisp1_isp_params_cfg cur_params; + struct v4l2_format vdev_fmt; + bool streamon; + bool first_params; + + enum v4l2_quantization quantization; + enum rkisp1_fmt_raw_pat_type raw_type; +}; + +/* config params before ISP streaming */ +void rkisp1_params_configure_isp(struct rkisp1_isp_params_vdev *params_vdev, + struct ispsd_in_fmt *in_fmt, + enum v4l2_quantization quantization); +void rkisp1_params_disable_isp(struct rkisp1_isp_params_vdev *params_vdev); + +int rkisp1_register_params_vdev(struct rkisp1_isp_params_vdev *params_vdev, + struct v4l2_device *v4l2_dev, + struct rkisp1_device *dev); + +void rkisp1_unregister_params_vdev(struct rkisp1_isp_params_vdev *params_vdev); + +void rkisp1_params_isr(struct rkisp1_isp_params_vdev *params_vdev, u32 isp_mis); + +#endif /* _RKISP1_ISP_H */ From patchwork Tue Jul 30 18:42:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helen Mae Koike Fornazier X-Patchwork-Id: 11066563 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BA31E1399 for ; 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Tue, 30 Jul 2019 19:45:22 +0100 (BST) From: Helen Koike To: linux-rockchip@lists.infradead.org Subject: [PATCH v8 09/14] media: rkisp1: add rockchip isp1 core driver Date: Tue, 30 Jul 2019 15:42:51 -0300 Message-Id: <20190730184256.30338-10-helen.koike@collabora.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190730184256.30338-1-helen.koike@collabora.com> References: <20190730184256.30338-1-helen.koike@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190730_114529_413066_3889063C X-CRM114-Status: GOOD ( 22.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, eddie.cai.linux@gmail.com, kernel@collabora.com, heiko@sntech.de, jacob2.chen@rock-chips.com, jeffy.chen@rock-chips.com, zyc@rock-chips.com, linux-kernel@vger.kernel.org, tfiga@chromium.org, Allon Huang , Jacob Chen , hans.verkuil@cisco.com, laurent.pinchart@ideasonboard.com, sakari.ailus@linux.intel.com, zhengsq@rock-chips.com, mchehab@kernel.org, ezequiel@collabora.com, Helen Koike , linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jacob Chen Add the core driver for rockchip isp1. Signed-off-by: Jacob Chen Signed-off-by: Shunqian Zheng Signed-off-by: Yichong Zhong Signed-off-by: Jacob Chen Signed-off-by: Eddie Cai Signed-off-by: Jeffy Chen Signed-off-by: Allon Huang Signed-off-by: Tomasz Figa [fixed compilation and run time errors regarding new v4l2 async API] Signed-off-by: Laurent Pinchart [Add missing module device table] Signed-off-by: Ezequiel Garcia [update for upstream] Signed-off-by: Helen Koike --- Changes in v8: None Changes in v7: - VIDEO_ROCKCHIP_ISP1 selects VIDEOBUF2_VMALLOC - add PHY_ROCKCHIP_DPHY as a dependency for VIDEO_ROCKCHIP_ISP1 - Fix compilation and runtime errors due to bitrotting The code has bit-rotten since March 2018, fix compilation errors. The new V4L2 async notifier API requires notifiers to be initialized by a call to v4l2_async_notifier_init() before being used, do so. - Add missing module device table - use clk_bulk framework - add missing notifiers cleanups - s/strlcpy/strscpy - normalize bus_info name - fix s_stream error path, stream_cnt wans't being decremented properly - use devm_platform_ioremap_resource() helper - s/deice/device - redesign: remove mipi/csi subdevice, sensors connect directly to the isp subdevice in the media topology now. - remove "saved_state" member from rkisp1_stream struct - Reverse the order of MIs - Simplify MI interrupt handling Rather than adding unnecessary indirection, just use stream index to handle MI interrupt enable/disable/clear, since the stream index matches the order of bits now, thanks to previous patch. While at it, remove some dead code. - code styling and checkpatch fixes drivers/media/platform/Kconfig | 12 + drivers/media/platform/Makefile | 1 + drivers/media/platform/rockchip/isp1/Makefile | 7 + drivers/media/platform/rockchip/isp1/common.h | 101 +++ drivers/media/platform/rockchip/isp1/dev.c | 675 ++++++++++++++++++ drivers/media/platform/rockchip/isp1/dev.h | 97 +++ 6 files changed, 893 insertions(+) create mode 100644 drivers/media/platform/rockchip/isp1/Makefile create mode 100644 drivers/media/platform/rockchip/isp1/common.h create mode 100644 drivers/media/platform/rockchip/isp1/dev.c create mode 100644 drivers/media/platform/rockchip/isp1/dev.h diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index 89555f9a813f..e0e98937c565 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -106,6 +106,18 @@ config VIDEO_QCOM_CAMSS select VIDEOBUF2_DMA_SG select V4L2_FWNODE +config VIDEO_ROCKCHIP_ISP1 + tristate "Rockchip Image Signal Processing v1 Unit driver" + depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API + depends on ARCH_ROCKCHIP || COMPILE_TEST + select VIDEOBUF2_DMA_CONTIG + select VIDEOBUF2_VMALLOC + select V4L2_FWNODE + select PHY_ROCKCHIP_DPHY + default n + ---help--- + Support for ISP1 on the rockchip SoC. + config VIDEO_S3C_CAMIF tristate "Samsung S3C24XX/S3C64XX SoC Camera Interface driver" depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile index 7cbbd925124c..f9fcf8e7c513 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile @@ -69,6 +69,7 @@ obj-$(CONFIG_VIDEO_RENESAS_FDP1) += rcar_fdp1.o obj-$(CONFIG_VIDEO_RENESAS_JPU) += rcar_jpu.o obj-$(CONFIG_VIDEO_RENESAS_VSP1) += vsp1/ +obj-$(CONFIG_VIDEO_ROCKCHIP_ISP1) += rockchip/isp1/ obj-$(CONFIG_VIDEO_ROCKCHIP_RGA) += rockchip/rga/ obj-y += omap/ diff --git a/drivers/media/platform/rockchip/isp1/Makefile b/drivers/media/platform/rockchip/isp1/Makefile new file mode 100644 index 000000000000..72706e80fc8b --- /dev/null +++ b/drivers/media/platform/rockchip/isp1/Makefile @@ -0,0 +1,7 @@ +obj-$(CONFIG_VIDEO_ROCKCHIP_ISP1) += rockchip-isp1.o +rockchip-isp1-objs += rkisp1.o \ + dev.o \ + regs.o \ + isp_stats.o \ + isp_params.o \ + capture.o diff --git a/drivers/media/platform/rockchip/isp1/common.h b/drivers/media/platform/rockchip/isp1/common.h new file mode 100644 index 000000000000..606ce2793546 --- /dev/null +++ b/drivers/media/platform/rockchip/isp1/common.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Rockchip isp1 driver + * + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. + */ + +#ifndef _RKISP1_COMMON_H +#define _RKISP1_COMMON_H + +#include +#include +#include +#include +#include +#include + +#define RKISP1_DEFAULT_WIDTH 800 +#define RKISP1_DEFAULT_HEIGHT 600 + +#define RKISP1_MAX_STREAM 2 +#define RKISP1_STREAM_MP 0 +#define RKISP1_STREAM_SP 1 + +#define RKISP1_PLANE_Y 0 +#define RKISP1_PLANE_CB 1 +#define RKISP1_PLANE_CR 2 + +enum rkisp1_sd_type { + RKISP1_SD_SENSOR, + RKISP1_SD_PHY_CSI, + RKISP1_SD_VCM, + RKISP1_SD_FLASH, + RKISP1_SD_MAX, +}; + +/* One structure per video node */ +struct rkisp1_vdev_node { + struct vb2_queue buf_queue; + /* vfd lock */ + struct mutex vlock; + struct video_device vdev; + struct media_pad pad; +}; + +enum rkisp1_fmt_pix_type { + FMT_YUV, + FMT_RGB, + FMT_BAYER, + FMT_JPEG, + FMT_MAX +}; + +enum rkisp1_fmt_raw_pat_type { + RAW_RGGB = 0, + RAW_GRBG, + RAW_GBRG, + RAW_BGGR, +}; + +struct rkisp1_buffer { + struct vb2_v4l2_buffer vb; + struct list_head queue; + union { + u32 buff_addr[VIDEO_MAX_PLANES]; + void *vaddr[VIDEO_MAX_PLANES]; + }; +}; + +struct rkisp1_dummy_buffer { + void *vaddr; + dma_addr_t dma_addr; + u32 size; +}; + +extern int rkisp1_debug; + +static inline +struct rkisp1_vdev_node *vdev_to_node(struct video_device *vdev) +{ + return container_of(vdev, struct rkisp1_vdev_node, vdev); +} + +static inline struct rkisp1_vdev_node *queue_to_node(struct vb2_queue *q) +{ + return container_of(q, struct rkisp1_vdev_node, buf_queue); +} + +static inline struct rkisp1_buffer *to_rkisp1_buffer(struct vb2_v4l2_buffer *vb) +{ + return container_of(vb, struct rkisp1_buffer, vb); +} + +static inline struct vb2_queue *to_vb2_queue(struct file *file) +{ + struct rkisp1_vdev_node *vnode = video_drvdata(file); + + return &vnode->buf_queue; +} + +#endif /* _RKISP1_COMMON_H */ diff --git a/drivers/media/platform/rockchip/isp1/dev.c b/drivers/media/platform/rockchip/isp1/dev.c new file mode 100644 index 000000000000..2b4a67e1a3b5 --- /dev/null +++ b/drivers/media/platform/rockchip/isp1/dev.c @@ -0,0 +1,675 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Rockchip isp1 driver + * + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" +#include "regs.h" + +struct isp_match_data { + const char * const *clks; + int size; +}; + +struct sensor_async_subdev { + struct v4l2_async_subdev asd; + struct v4l2_mbus_config mbus; + unsigned int lanes; +}; + +int rkisp1_debug; +module_param_named(debug, rkisp1_debug, int, 0644); +MODULE_PARM_DESC(debug, "Debug level (0-1)"); + +/**************************** pipeline operations******************************/ + +static int __isp_pipeline_prepare(struct rkisp1_pipeline *p, + struct media_entity *me) +{ + struct rkisp1_device *dev = container_of(p, struct rkisp1_device, pipe); + struct v4l2_subdev *sd; + unsigned int i; + + p->num_subdevs = 0; + memset(p->subdevs, 0, sizeof(p->subdevs)); + + while (1) { + struct media_pad *pad = NULL; + + /* Find remote source pad */ + for (i = 0; i < me->num_pads; i++) { + struct media_pad *spad = &me->pads[i]; + + if (!(spad->flags & MEDIA_PAD_FL_SINK)) + continue; + pad = media_entity_remote_pad(spad); + if (pad) + break; + } + + if (!pad) + break; + + sd = media_entity_to_v4l2_subdev(pad->entity); + if (sd != &dev->isp_sdev.sd) + p->subdevs[p->num_subdevs++] = sd; + + me = &sd->entity; + if (me->num_pads == 1) + break; + } + return 0; +} + +static int __subdev_set_power(struct v4l2_subdev *sd, int on) +{ + int ret; + + if (!sd) + return -ENXIO; + + ret = v4l2_subdev_call(sd, core, s_power, on); + + return ret != -ENOIOCTLCMD ? ret : 0; +} + +static int __isp_pipeline_s_power(struct rkisp1_pipeline *p, bool on) +{ + struct rkisp1_device *dev = container_of(p, struct rkisp1_device, pipe); + int i, ret; + + if (on) { + __subdev_set_power(&dev->isp_sdev.sd, true); + + for (i = p->num_subdevs - 1; i >= 0; --i) { + ret = __subdev_set_power(p->subdevs[i], true); + if (ret < 0 && ret != -ENXIO) + goto err_power_off; + } + } else { + for (i = 0; i < p->num_subdevs; ++i) + __subdev_set_power(p->subdevs[i], false); + + __subdev_set_power(&dev->isp_sdev.sd, false); + } + + return 0; + +err_power_off: + for (++i; i < p->num_subdevs; ++i) + __subdev_set_power(p->subdevs[i], false); + __subdev_set_power(&dev->isp_sdev.sd, true); + return ret; +} + +static int rkisp1_pipeline_open(struct rkisp1_pipeline *p, + struct media_entity *me, + bool prepare) +{ + int ret; + + if (WARN_ON(!p || !me)) + return -EINVAL; + if (atomic_inc_return(&p->power_cnt) > 1) + return 0; + + /* go through media graphic and get subdevs */ + if (prepare) + __isp_pipeline_prepare(p, me); + + if (!p->num_subdevs) + return -EINVAL; + + ret = __isp_pipeline_s_power(p, 1); + if (ret < 0) + return ret; + + return 0; +} + +static int rkisp1_pipeline_close(struct rkisp1_pipeline *p) +{ + int ret; + + if (atomic_dec_return(&p->power_cnt) > 0) + return 0; + ret = __isp_pipeline_s_power(p, 0); + + return ret == -ENXIO ? 0 : ret; +} + +/* + * stream-on order: isp_subdev, mipi dphy, sensor + * stream-off order: mipi dphy, sensor, isp_subdev + */ +static int rkisp1_pipeline_set_stream(struct rkisp1_pipeline *p, bool on) +{ + struct rkisp1_device *dev = container_of(p, struct rkisp1_device, pipe); + int i, ret; + + if ((on && atomic_inc_return(&p->stream_cnt) > 1) || + (!on && atomic_dec_return(&p->stream_cnt) > 0)) + return 0; + + if (on) { + ret = v4l2_subdev_call(&dev->isp_sdev.sd, video, s_stream, + true); + if (ret && ret != -ENOIOCTLCMD && ret != -ENODEV) { + v4l2_err(&dev->v4l2_dev, + "s_stream failed on subdevice %s (%d)\n", + dev->isp_sdev.sd.name, + ret); + atomic_dec(&p->stream_cnt); + return ret; + } + } + + /* phy -> sensor */ + for (i = 0; i < p->num_subdevs; ++i) { + ret = v4l2_subdev_call(p->subdevs[i], video, s_stream, on); + if (on && ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV) + goto err_stream_off; + } + + if (!on) + v4l2_subdev_call(&dev->isp_sdev.sd, video, s_stream, false); + + return 0; + +err_stream_off: + for (--i; i >= 0; --i) + v4l2_subdev_call(p->subdevs[i], video, s_stream, false); + v4l2_subdev_call(&dev->isp_sdev.sd, video, s_stream, false); + atomic_dec(&p->stream_cnt); + return ret; +} + +/***************************** media controller *******************************/ +/* See http://opensource.rock-chips.com/wiki_Rockchip-isp1 for Topology */ + +static int rkisp1_create_links(struct rkisp1_device *dev) +{ + struct media_entity *source, *sink; + struct rkisp1_sensor *sensor; + unsigned int flags, pad; + int ret; + + /* sensor links(or mipi-phy) */ + list_for_each_entry(sensor, &dev->sensors, list) { + for (pad = 0; pad < sensor->sd->entity.num_pads; pad++) + if (sensor->sd->entity.pads[pad].flags & + MEDIA_PAD_FL_SOURCE) + break; + + if (pad == sensor->sd->entity.num_pads) { + dev_err(dev->dev, + "failed to find src pad for %s\n", + sensor->sd->name); + + return -ENXIO; + } + + ret = media_create_pad_link( + &sensor->sd->entity, pad, + &dev->isp_sdev.sd.entity, + RKISP1_ISP_PAD_SINK, + list_is_first(&sensor->list, &dev->sensors) ? + MEDIA_LNK_FL_ENABLED : 0); + if (ret) { + dev_err(dev->dev, + "failed to create link for %s\n", + sensor->sd->name); + return ret; + } + } + + /* params links */ + source = &dev->params_vdev.vnode.vdev.entity; + sink = &dev->isp_sdev.sd.entity; + flags = MEDIA_LNK_FL_ENABLED; + ret = media_create_pad_link(source, 0, sink, + RKISP1_ISP_PAD_SINK_PARAMS, flags); + if (ret < 0) + return ret; + + /* create isp internal links */ + /* SP links */ + source = &dev->isp_sdev.sd.entity; + sink = &dev->stream[RKISP1_STREAM_SP].vnode.vdev.entity; + ret = media_create_pad_link(source, RKISP1_ISP_PAD_SOURCE_PATH, + sink, 0, flags); + if (ret < 0) + return ret; + + /* MP links */ + source = &dev->isp_sdev.sd.entity; + sink = &dev->stream[RKISP1_STREAM_MP].vnode.vdev.entity; + ret = media_create_pad_link(source, RKISP1_ISP_PAD_SOURCE_PATH, + sink, 0, flags); + if (ret < 0) + return ret; + + /* 3A stats links */ + source = &dev->isp_sdev.sd.entity; + sink = &dev->stats_vdev.vnode.vdev.entity; + return media_create_pad_link(source, RKISP1_ISP_PAD_SOURCE_STATS, + sink, 0, flags); +} + +static int subdev_notifier_bound(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *sd, + struct v4l2_async_subdev *asd) +{ + struct rkisp1_device *isp_dev = container_of(notifier, + struct rkisp1_device, + notifier); + struct sensor_async_subdev *s_asd = container_of(asd, + struct sensor_async_subdev, asd); + struct rkisp1_sensor *sensor; + + sensor = devm_kzalloc(isp_dev->dev, sizeof(*sensor), GFP_KERNEL); + if (!sensor) + return -ENOMEM; + + sensor->lanes = s_asd->lanes; + sensor->mbus = s_asd->mbus; + sensor->sd = sd; + sensor->dphy = devm_phy_get(isp_dev->dev, "dphy"); + if (IS_ERR(sensor->dphy)) { + if (PTR_ERR(sensor->dphy) != -EPROBE_DEFER) + dev_err(isp_dev->dev, "Couldn't get the MIPI D-PHY\n"); + return PTR_ERR(sensor->dphy); + } + phy_init(sensor->dphy); + + list_add(&sensor->list, &isp_dev->sensors); + + return 0; +} + +static struct rkisp1_sensor *sd_to_sensor(struct rkisp1_device *dev, + struct v4l2_subdev *sd) +{ + struct rkisp1_sensor *sensor; + + list_for_each_entry(sensor, &dev->sensors, list) + if (sensor->sd == sd) + return sensor; + + return NULL; +} + +static void subdev_notifier_unbind(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *sd, + struct v4l2_async_subdev *asd) +{ + struct rkisp1_device *isp_dev = container_of(notifier, + struct rkisp1_device, + notifier); + struct rkisp1_sensor *sensor = sd_to_sensor(isp_dev, sd); + + /* TODO: check if a lock is required here */ + list_del(&sensor->list); + + phy_exit(sensor->dphy); +} + +static int subdev_notifier_complete(struct v4l2_async_notifier *notifier) +{ + struct rkisp1_device *dev = container_of(notifier, struct rkisp1_device, + notifier); + int ret; + + mutex_lock(&dev->media_dev.graph_mutex); + ret = rkisp1_create_links(dev); + if (ret < 0) + goto unlock; + ret = v4l2_device_register_subdev_nodes(&dev->v4l2_dev); + if (ret < 0) + goto unlock; + + v4l2_info(&dev->v4l2_dev, "Async subdev notifier completed\n"); + +unlock: + mutex_unlock(&dev->media_dev.graph_mutex); + return ret; +} + +static int rkisp1_fwnode_parse(struct device *dev, + struct v4l2_fwnode_endpoint *vep, + struct v4l2_async_subdev *asd) +{ + struct sensor_async_subdev *s_asd = + container_of(asd, struct sensor_async_subdev, asd); + + if (vep->bus_type != V4L2_MBUS_CSI2_DPHY) { + dev_err(dev, "Only CSI2 bus type is currently supported\n"); + return -EINVAL; + } + + if (vep->base.port != 0) { + dev_err(dev, "The ISP has only port 0\n"); + return -EINVAL; + } + + s_asd->mbus.type = vep->bus_type; + s_asd->mbus.flags = vep->bus.mipi_csi2.flags; + s_asd->lanes = vep->bus.mipi_csi2.num_data_lanes; + + switch (vep->bus.mipi_csi2.num_data_lanes) { + case 1: + s_asd->mbus.flags |= V4L2_MBUS_CSI2_1_LANE; + break; + case 2: + s_asd->mbus.flags |= V4L2_MBUS_CSI2_2_LANE; + break; + case 3: + s_asd->mbus.flags |= V4L2_MBUS_CSI2_3_LANE; + break; + case 4: + s_asd->mbus.flags |= V4L2_MBUS_CSI2_4_LANE; + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct v4l2_async_notifier_operations subdev_notifier_ops = { + .bound = subdev_notifier_bound, + .unbind = subdev_notifier_unbind, + .complete = subdev_notifier_complete, +}; + +static int isp_subdev_notifier(struct rkisp1_device *isp_dev) +{ + struct v4l2_async_notifier *ntf = &isp_dev->notifier; + struct device *dev = isp_dev->dev; + int ret; + + v4l2_async_notifier_init(ntf); + + ret = v4l2_async_notifier_parse_fwnode_endpoints_by_port( + dev, ntf, sizeof(struct sensor_async_subdev), 0, + rkisp1_fwnode_parse); + if (ret < 0) + return ret; + + if (list_empty(&ntf->asd_list)) + return -ENODEV; /* no endpoint */ + + ntf->ops = &subdev_notifier_ops; + + return v4l2_async_notifier_register(&isp_dev->v4l2_dev, ntf); +} + +/***************************** platform device *******************************/ + +static int rkisp1_register_platform_subdevs(struct rkisp1_device *dev) +{ + int ret; + + ret = rkisp1_register_isp_subdev(dev, &dev->v4l2_dev); + if (ret < 0) + return ret; + + ret = rkisp1_register_stream_vdevs(dev); + if (ret < 0) + goto err_unreg_isp_subdev; + + ret = rkisp1_register_stats_vdev(&dev->stats_vdev, &dev->v4l2_dev, dev); + if (ret < 0) + goto err_unreg_stream_vdev; + + ret = rkisp1_register_params_vdev(&dev->params_vdev, &dev->v4l2_dev, + dev); + if (ret < 0) + goto err_unreg_stats_vdev; + + ret = isp_subdev_notifier(dev); + if (ret < 0) { + v4l2_err(&dev->v4l2_dev, + "Failed to register subdev notifier(%d)\n", ret); + goto err_unreg_params_vdev; + } + + return 0; +err_unreg_params_vdev: + rkisp1_unregister_params_vdev(&dev->params_vdev); +err_unreg_stats_vdev: + rkisp1_unregister_stats_vdev(&dev->stats_vdev); +err_unreg_stream_vdev: + rkisp1_unregister_stream_vdevs(dev); +err_unreg_isp_subdev: + rkisp1_unregister_isp_subdev(dev); + return ret; +} + +static const char * const rk3399_isp_clks[] = { + "clk_isp", + "aclk_isp", + "hclk_isp", + "aclk_isp_wrap", + "hclk_isp_wrap", +}; + +static const char * const rk3288_isp_clks[] = { + "clk_isp", + "aclk_isp", + "hclk_isp", + "pclk_isp_in", + "sclk_isp_jpe", +}; + +static const struct isp_match_data rk3288_isp_clk_data = { + .clks = rk3288_isp_clks, + .size = ARRAY_SIZE(rk3288_isp_clks), +}; + +static const struct isp_match_data rk3399_isp_clk_data = { + .clks = rk3399_isp_clks, + .size = ARRAY_SIZE(rk3399_isp_clks), +}; + +static const struct of_device_id rkisp1_plat_of_match[] = { + { + .compatible = "rockchip,rk3288-cif-isp", + .data = &rk3288_isp_clk_data, + }, { + .compatible = "rockchip,rk3399-cif-isp", + .data = &rk3399_isp_clk_data, + }, + {}, +}; +MODULE_DEVICE_TABLE(of, rkisp1_plat_of_match); + +static irqreturn_t rkisp1_irq_handler(int irq, void *ctx) +{ + struct device *dev = ctx; + struct rkisp1_device *rkisp1_dev = dev_get_drvdata(dev); + unsigned int mis_val; + + mis_val = readl(rkisp1_dev->base_addr + CIF_ISP_MIS); + if (mis_val) + rkisp1_isp_isr(mis_val, rkisp1_dev); + + mis_val = readl(rkisp1_dev->base_addr + CIF_MIPI_MIS); + if (mis_val) + rkisp1_mipi_isr(mis_val, rkisp1_dev); + + mis_val = readl(rkisp1_dev->base_addr + CIF_MI_MIS); + if (mis_val) + rkisp1_mi_isr(mis_val, rkisp1_dev); + + return IRQ_HANDLED; +} + +static int rkisp1_plat_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + const struct isp_match_data *clk_data; + const struct of_device_id *match; + struct device *dev = &pdev->dev; + struct rkisp1_device *isp_dev; + struct v4l2_device *v4l2_dev; + unsigned int i; + int ret, irq; + + match = of_match_node(rkisp1_plat_of_match, node); + isp_dev = devm_kzalloc(dev, sizeof(*isp_dev), GFP_KERNEL); + if (!isp_dev) + return -ENOMEM; + + INIT_LIST_HEAD(&isp_dev->sensors); + + dev_set_drvdata(dev, isp_dev); + isp_dev->dev = dev; + + isp_dev->base_addr = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(isp_dev->base_addr)) + return PTR_ERR(isp_dev->base_addr); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret = devm_request_irq(dev, irq, rkisp1_irq_handler, IRQF_SHARED, + dev_driver_string(dev), dev); + if (ret < 0) { + dev_err(dev, "request irq failed: %d\n", ret); + return ret; + } + + isp_dev->irq = irq; + clk_data = match->data; + + for (i = 0; i < clk_data->size; i++) + isp_dev->clks[i].id = clk_data->clks[i]; + ret = devm_clk_bulk_get(dev, clk_data->size, isp_dev->clks); + if (ret) + return ret; + isp_dev->clk_size = clk_data->size; + + atomic_set(&isp_dev->pipe.power_cnt, 0); + atomic_set(&isp_dev->pipe.stream_cnt, 0); + isp_dev->pipe.open = rkisp1_pipeline_open; + isp_dev->pipe.close = rkisp1_pipeline_close; + isp_dev->pipe.set_stream = rkisp1_pipeline_set_stream; + + rkisp1_stream_init(isp_dev, RKISP1_STREAM_SP); + rkisp1_stream_init(isp_dev, RKISP1_STREAM_MP); + + strscpy(isp_dev->media_dev.model, "rkisp1", + sizeof(isp_dev->media_dev.model)); + isp_dev->media_dev.dev = &pdev->dev; + strscpy(isp_dev->media_dev.bus_info, + "platform: " DRIVER_NAME, sizeof(isp_dev->media_dev.bus_info)); + media_device_init(&isp_dev->media_dev); + + v4l2_dev = &isp_dev->v4l2_dev; + v4l2_dev->mdev = &isp_dev->media_dev; + strscpy(v4l2_dev->name, "rkisp1", sizeof(v4l2_dev->name)); + v4l2_ctrl_handler_init(&isp_dev->ctrl_handler, 5); + v4l2_dev->ctrl_handler = &isp_dev->ctrl_handler; + + ret = v4l2_device_register(isp_dev->dev, &isp_dev->v4l2_dev); + if (ret < 0) + return ret; + + ret = media_device_register(&isp_dev->media_dev); + if (ret < 0) { + v4l2_err(v4l2_dev, "Failed to register media device: %d\n", + ret); + goto err_unreg_v4l2_dev; + } + + /* create & register platefom subdev (from of_node) */ + ret = rkisp1_register_platform_subdevs(isp_dev); + if (ret < 0) + goto err_unreg_media_dev; + + pm_runtime_enable(&pdev->dev); + + return 0; + +err_unreg_media_dev: + media_device_unregister(&isp_dev->media_dev); +err_unreg_v4l2_dev: + v4l2_device_unregister(&isp_dev->v4l2_dev); + return ret; +} + +static int rkisp1_plat_remove(struct platform_device *pdev) +{ + struct rkisp1_device *isp_dev = platform_get_drvdata(pdev); + + pm_runtime_disable(&pdev->dev); + media_device_unregister(&isp_dev->media_dev); + v4l2_async_notifier_unregister(&isp_dev->notifier); + v4l2_async_notifier_cleanup(&isp_dev->notifier); + v4l2_device_unregister(&isp_dev->v4l2_dev); + rkisp1_unregister_params_vdev(&isp_dev->params_vdev); + rkisp1_unregister_stats_vdev(&isp_dev->stats_vdev); + rkisp1_unregister_stream_vdevs(isp_dev); + rkisp1_unregister_isp_subdev(isp_dev); + + return 0; +} + +static int __maybe_unused rkisp1_runtime_suspend(struct device *dev) +{ + struct rkisp1_device *isp_dev = dev_get_drvdata(dev); + + clk_bulk_disable_unprepare(isp_dev->clk_size, isp_dev->clks); + return pinctrl_pm_select_sleep_state(dev); +} + +static int __maybe_unused rkisp1_runtime_resume(struct device *dev) +{ + struct rkisp1_device *isp_dev = dev_get_drvdata(dev); + int ret; + + ret = pinctrl_pm_select_default_state(dev); + if (ret < 0) + return ret; + ret = clk_bulk_prepare_enable(isp_dev->clk_size, isp_dev->clks); + if (ret < 0) + return ret; + + return 0; +} + +static const struct dev_pm_ops rkisp1_plat_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(rkisp1_runtime_suspend, rkisp1_runtime_resume, NULL) +}; + +static struct platform_driver rkisp1_plat_drv = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = of_match_ptr(rkisp1_plat_of_match), + .pm = &rkisp1_plat_pm_ops, + }, + .probe = rkisp1_plat_probe, + .remove = rkisp1_plat_remove, +}; + +module_platform_driver(rkisp1_plat_drv); +MODULE_AUTHOR("Rockchip Camera/ISP team"); +MODULE_DESCRIPTION("Rockchip ISP1 platform driver"); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/media/platform/rockchip/isp1/dev.h b/drivers/media/platform/rockchip/isp1/dev.h new file mode 100644 index 000000000000..f7cbee316523 --- /dev/null +++ b/drivers/media/platform/rockchip/isp1/dev.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Rockchip isp1 driver + * + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. + */ + +#ifndef _RKISP1_DEV_H +#define _RKISP1_DEV_H + +#include + +#include "capture.h" +#include "rkisp1.h" +#include "isp_params.h" +#include "isp_stats.h" + +#define DRIVER_NAME "rkisp1" +#define ISP_VDEV_NAME DRIVER_NAME "_ispdev" +#define SP_VDEV_NAME DRIVER_NAME "_selfpath" +#define MP_VDEV_NAME DRIVER_NAME "_mainpath" +#define DMA_VDEV_NAME DRIVER_NAME "_dmapath" + +#define GRP_ID_SENSOR BIT(0) +#define GRP_ID_MIPIPHY BIT(1) +#define GRP_ID_ISP BIT(2) +#define GRP_ID_ISP_MP BIT(3) +#define GRP_ID_ISP_SP BIT(4) + +#define RKISP1_MAX_BUS_CLK 8 +#define RKISP1_MAX_SENSOR 2 +#define RKISP1_MAX_PIPELINE 4 + +/* + * struct rkisp1_pipeline - An ISP hardware pipeline + * + * Capture device call other devices via pipeline + * + * @num_subdevs: number of linked subdevs + * @power_cnt: pipeline power count + * @stream_cnt: stream power count + */ +struct rkisp1_pipeline { + struct media_pipeline pipe; + int num_subdevs; + atomic_t power_cnt; + atomic_t stream_cnt; + struct v4l2_subdev *subdevs[RKISP1_MAX_PIPELINE]; + int (*open)(struct rkisp1_pipeline *p, + struct media_entity *me, bool prepare); + int (*close)(struct rkisp1_pipeline *p); + int (*set_stream)(struct rkisp1_pipeline *p, bool on); +}; + +/* + * struct rkisp1_sensor - Sensor information + * @mbus: media bus configuration + */ +struct rkisp1_sensor { + struct v4l2_subdev *sd; + struct v4l2_mbus_config mbus; + unsigned int lanes; + struct phy *dphy; + struct list_head list; +}; + +/* + * struct rkisp1_device - ISP platform device + * @base_addr: base register address + * @active_sensor: sensor in-use, set when streaming on + * @isp_sdev: ISP sub-device + * @rkisp1_stream: capture video device + * @stats_vdev: ISP statistics output device + * @params_vdev: ISP input parameters device + */ +struct rkisp1_device { + void __iomem *base_addr; + int irq; + struct device *dev; + unsigned int clk_size; + struct clk_bulk_data clks[RKISP1_MAX_BUS_CLK]; + struct v4l2_device v4l2_dev; + struct v4l2_ctrl_handler ctrl_handler; + struct media_device media_dev; + struct v4l2_async_notifier notifier; + struct v4l2_subdev *subdevs[RKISP1_SD_MAX]; + struct rkisp1_sensor *active_sensor; + struct list_head sensors; + struct rkisp1_isp_subdev isp_sdev; + struct rkisp1_stream stream[RKISP1_MAX_STREAM]; + struct rkisp1_isp_stats_vdev stats_vdev; + struct rkisp1_isp_params_vdev params_vdev; + struct rkisp1_pipeline pipe; + struct vb2_alloc_ctx *alloc_ctx; +}; + +#endif From patchwork Tue Jul 30 18:42:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helen Mae Koike Fornazier X-Patchwork-Id: 11066569 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 76C1513AC for ; Tue, 30 Jul 2019 18:48:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6BB50284D4 for ; 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Tue, 30 Jul 2019 19:45:28 +0100 (BST) From: Helen Koike To: linux-rockchip@lists.infradead.org Subject: [PATCH v8 10/14] dt-bindings: Document the Rockchip ISP1 bindings Date: Tue, 30 Jul 2019 15:42:52 -0300 Message-Id: <20190730184256.30338-11-helen.koike@collabora.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190730184256.30338-1-helen.koike@collabora.com> References: <20190730184256.30338-1-helen.koike@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190730_114534_790121_20463C52 X-CRM114-Status: GOOD ( 12.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, eddie.cai.linux@gmail.com, kernel@collabora.com, heiko@sntech.de, Rob Herring , jacob2.chen@rock-chips.com, jeffy.chen@rock-chips.com, zyc@rock-chips.com, linux-kernel@vger.kernel.org, tfiga@chromium.org, Helen Koike , hans.verkuil@cisco.com, laurent.pinchart@ideasonboard.com, sakari.ailus@linux.intel.com, zhengsq@rock-chips.com, mchehab@kernel.org, ezequiel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jacob Chen Add DT bindings documentation for Rockchip ISP1 Signed-off-by: Jacob Chen Reviewed-by: Rob Herring [update for upstream] Signed-off-by: Helen Koike --- Changes in v8: None Changes in v7: - update document with new design and tested example .../bindings/media/rockchip-isp1.txt | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/rockchip-isp1.txt diff --git a/Documentation/devicetree/bindings/media/rockchip-isp1.txt b/Documentation/devicetree/bindings/media/rockchip-isp1.txt new file mode 100644 index 000000000000..a97fef0f189f --- /dev/null +++ b/Documentation/devicetree/bindings/media/rockchip-isp1.txt @@ -0,0 +1,71 @@ +Rockchip SoC Image Signal Processing unit v1 +---------------------------------------------- + +Rockchip ISP1 is the Camera interface for the Rockchip series of SoCs +which contains image processing, scaling, and compression funcitons. + +Required properties: +- compatible: value should be one of the following + "rockchip,rk3288-cif-isp"; + "rockchip,rk3399-cif-isp"; +- reg : offset and length of the register set for the device. +- interrupts: should contain ISP interrupt. +- clocks: phandle to the required clocks. +- clock-names: required clock name. +- iommus: required a iommu node. +- phys: the phandle for the PHY port +- phy-names: must contain "dphy" + +port node +------------------- + +The device node should contain one 'ports' child node, with children 'port' +with child 'endpoint'. +nodes, according to the bindings defined in Documentation/devicetree/bindings/ +media/video-interfaces.txt. + +- endpoint(mipi): + - remote-endpoint: Connecting to Rockchip MIPI-DPHY, + which is defined in rockchip-mipi-dphy.txt. + +The port node must contain at least one endpoint, either parallel or mipi. +It could have multiple endpoints, but please note the hardware don't support +two sensors work at a time, they are supposed to work asynchronously. + +Device node example +------------------- + + isp0: isp0@ff910000 { + compatible = "rockchip,rk3399-cif-isp"; + reg = <0x0 0xff910000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_ISP0>, + <&cru ACLK_ISP0>, <&cru ACLK_ISP0_WRAPPER>, + <&cru HCLK_ISP0>, <&cru HCLK_ISP0_WRAPPER>; + clock-names = "clk_isp", + "aclk_isp", "aclk_isp_wrap", + "hclk_isp", "hclk_isp_wrap"; + power-domains = <&power RK3399_PD_ISP0>; + iommus = <&isp0_mmu>; + phys = <&dphy>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + mipi_in_wcam: endpoint@0 { + reg = <0>; + remote-endpoint = <&wcam_out>; + data-lanes = <1 2>; + }; + + mipi_in_ucam: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out>; + data-lanes = <1>; + }; + }; + }; + }; From patchwork Tue Jul 30 18:42:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helen Mae Koike Fornazier X-Patchwork-Id: 11066573 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9548313AC for ; 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Tue, 30 Jul 2019 19:45:33 +0100 (BST) From: Helen Koike To: linux-rockchip@lists.infradead.org Subject: [PATCH v8 11/14] dt-bindings: Document the Rockchip MIPI RX D-PHY bindings Date: Tue, 30 Jul 2019 15:42:53 -0300 Message-Id: <20190730184256.30338-12-helen.koike@collabora.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190730184256.30338-1-helen.koike@collabora.com> References: <20190730184256.30338-1-helen.koike@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190730_114539_714548_4C037C12 X-CRM114-Status: GOOD ( 11.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, eddie.cai.linux@gmail.com, kernel@collabora.com, heiko@sntech.de, Rob Herring , jacob2.chen@rock-chips.com, jeffy.chen@rock-chips.com, zyc@rock-chips.com, linux-kernel@vger.kernel.org, tfiga@chromium.org, Helen Koike , hans.verkuil@cisco.com, laurent.pinchart@ideasonboard.com, sakari.ailus@linux.intel.com, zhengsq@rock-chips.com, mchehab@kernel.org, ezequiel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jacob Chen Add DT bindings documentation for Rockchip MIPI D-PHY RX Signed-off-by: Jacob Chen Reviewed-by: Rob Herring [update for upstream] Signed-off-by: Helen Koike --- Changes in v8: None Changes in v7: - updated doc with new design and tested example .../bindings/media/rockchip-mipi-dphy.txt | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt diff --git a/Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt b/Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt new file mode 100644 index 000000000000..2305d44d92db --- /dev/null +++ b/Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt @@ -0,0 +1,38 @@ +Rockchip SoC MIPI RX D-PHY +------------------------------------------------------------- + +Required properties: +- compatible: value should be one of the following + "rockchip,rk3288-mipi-dphy" + "rockchip,rk3399-mipi-dphy" +- clocks : list of clock specifiers, corresponding to entries in + clock-names property; +- clock-names: required clock name. +- #phy-cells: Number of cells in a PHY specifier; Should be 0. + +MIPI RX D-PHY use registers in "general register files", it +should be a child of the GRF. + +Optional properties: +- reg: offset and length of the register set for the device. +- rockchip,grf: MIPI TX1RX1 D-PHY not only has its own register but also + the GRF, so it is only necessary for MIPI TX1RX1 D-PHY. + +Device node example +------------------- + +grf: syscon@ff770000 { + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; + +... + + dphy: mipi-dphy { + compatible = "rockchip,rk3399-mipi-dphy"; + clocks = <&cru SCLK_MIPIDPHY_REF>, + <&cru SCLK_DPHY_RX0_CFG>, + <&cru PCLK_VIO_GRF>; + clock-names = "dphy-ref", "dphy-cfg", "grf"; + power-domains = <&power RK3399_PD_VIO>; + #phy-cells = <0>; + }; +}; From patchwork Tue Jul 30 18:42:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helen Mae Koike Fornazier X-Patchwork-Id: 11066577 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 74B1913AC for ; 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Tue, 30 Jul 2019 19:45:38 +0100 (BST) From: Helen Koike To: linux-rockchip@lists.infradead.org Subject: [PATCH v8 12/14] arm64: dts: rockchip: add isp0 node for rk3399 Date: Tue, 30 Jul 2019 15:42:54 -0300 Message-Id: <20190730184256.30338-13-helen.koike@collabora.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190730184256.30338-1-helen.koike@collabora.com> References: <20190730184256.30338-1-helen.koike@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190730_114549_586393_ABB587EA X-CRM114-Status: GOOD ( 10.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, eddie.cai.linux@gmail.com, kernel@collabora.com, heiko@sntech.de, jacob2.chen@rock-chips.com, jeffy.chen@rock-chips.com, zyc@rock-chips.com, linux-kernel@vger.kernel.org, tfiga@chromium.org, Helen Koike , hans.verkuil@cisco.com, laurent.pinchart@ideasonboard.com, sakari.ailus@linux.intel.com, zhengsq@rock-chips.com, mchehab@kernel.org, ezequiel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shunqian Zheng rk3399 have two ISP, but we havn't test isp1, so just add isp0 at present. Signed-off-by: Shunqian Zheng Signed-off-by: Jacob Chen [update for upstream] Signed-off-by: Helen Koike --- Changes in v8: None Changes in v7: - add phy properties - add ports arch/arm64/boot/dts/rockchip/rk3399.dtsi | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index cede1ad81be2..776d2bd48c06 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1698,6 +1698,31 @@ status = "disabled"; }; + isp0: isp0@ff910000 { + compatible = "rockchip,rk3399-cif-isp"; + reg = <0x0 0xff910000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_ISP0>, + <&cru ACLK_ISP0>, <&cru ACLK_ISP0_WRAPPER>, + <&cru HCLK_ISP0>, <&cru HCLK_ISP0_WRAPPER>; + clock-names = "clk_isp", + "aclk_isp", "aclk_isp_wrap", + "hclk_isp", "hclk_isp_wrap"; + power-domains = <&power RK3399_PD_ISP0>; + iommus = <&isp0_mmu>; + phys = <&mipi_dphy_rx0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + }; + }; + isp0_mmu: iommu@ff914000 { compatible = "rockchip,iommu"; reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; From patchwork Tue Jul 30 18:42:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helen Mae Koike Fornazier X-Patchwork-Id: 11066581 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F03691399 for ; Tue, 30 Jul 2019 18:48:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E67CC284D4 for ; Tue, 30 Jul 2019 18:48:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DADCC28856; Tue, 30 Jul 2019 18:48:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 96B9A284D4 for ; Tue, 30 Jul 2019 18:48:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=aZLGCnl9Zf3tnjzzPedOM7eyJSSnLeY9yyp/xhbFILI=; b=jp1smSjmzS/UUG XvQ7713mBBk2EXvaJ4iS6WpRGqjy5vZeI1QKMRayq6rNwpowBnxgXvwgKIUlRos1dMgKff8LvF7EU M/qf8OswCaIPn+vLQRPNtLYomf2TtNcHpxBzfxlcBha6SiYkyGKMHX8uEU/xYHQ8I6ehrFxXh/rIO 42ezSBHQfdIO2Tc0RQatsWgo01ru3PXPImkFxfyupirgBBeXq1kPxczyqAUs7O4H/aZq0mveaU+TE Nl7i0MimdnN0z6lKcHL7hMV0Xav36DWn7j8Ld/jaQNwSeqQZ6kuIlm33Ppo6i988UHFzP/5LI8UgY LGZS0V9kAGnmGxm9vxug==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hsXB1-0007os-Vn; Tue, 30 Jul 2019 18:48:48 +0000 Received: from bhuna.collabora.co.uk ([2a00:1098:0:82:1000:25:2eeb:e3e3]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hsX8E-000528-W8; Tue, 30 Jul 2019 18:45:56 +0000 Received: from floko.floko.floko (unknown [IPv6:2804:431:c7f1:ce2f:ec1:e6e6:2e9f:e76e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: koike) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id 765EB28B928; Tue, 30 Jul 2019 19:45:48 +0100 (BST) From: Helen Koike To: linux-rockchip@lists.infradead.org Subject: [PATCH v8 13/14] arm64: dts: rockchip: add rx0 mipi-phy for rk3399 Date: Tue, 30 Jul 2019 15:42:55 -0300 Message-Id: <20190730184256.30338-14-helen.koike@collabora.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190730184256.30338-1-helen.koike@collabora.com> References: <20190730184256.30338-1-helen.koike@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190730_114555_416255_12693749 X-CRM114-Status: UNSURE ( 9.73 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, eddie.cai.linux@gmail.com, kernel@collabora.com, heiko@sntech.de, jacob2.chen@rock-chips.com, jeffy.chen@rock-chips.com, zyc@rock-chips.com, linux-kernel@vger.kernel.org, tfiga@chromium.org, Helen Koike , hans.verkuil@cisco.com, laurent.pinchart@ideasonboard.com, sakari.ailus@linux.intel.com, zhengsq@rock-chips.com, mchehab@kernel.org, ezequiel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shunqian Zheng It's a Designware MIPI D-PHY, used for ISP0 in rk3399. Signed-off-by: Shunqian Zheng Signed-off-by: Jacob Chen [update for upstream] Signed-off-by: Helen Koike --- Changes in v8: None Changes in v7: - add phy-cells arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 776d2bd48c06..3630d95e5cd8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1385,6 +1385,17 @@ status = "disabled"; }; + mipi_dphy_rx0: mipi-dphy-rx0 { + compatible = "rockchip,rk3399-mipi-dphy"; + clocks = <&cru SCLK_MIPIDPHY_REF>, + <&cru SCLK_DPHY_RX0_CFG>, + <&cru PCLK_VIO_GRF>; + clock-names = "dphy-ref", "dphy-cfg", "grf"; + power-domains = <&power RK3399_PD_VIO>; + #phy-cells = <0>; + status = "disabled"; + }; + u2phy0: usb2-phy@e450 { compatible = "rockchip,rk3399-usb2phy"; reg = <0xe450 0x10>; From patchwork Tue Jul 30 18:42:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helen Mae Koike Fornazier X-Patchwork-Id: 11066585 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 05687174A for ; Tue, 30 Jul 2019 18:49:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F00552858F for ; Tue, 30 Jul 2019 18:49:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E3E8228864; Tue, 30 Jul 2019 18:49:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9758C2858F for ; Tue, 30 Jul 2019 18:49:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NRofMJWxU429CZHHuZZ6u0p5yzy1Qvly1q2I48w1exY=; b=I5Ijyj/C3Hh2rw 7XU/t0RZrNB3XW0QAB0UjOYH3yZaLsbx8DNVewcYD0PDxCjlQOWPsif8DDc7QUc7uKVIPeFB7gXzC I9NJIR7xboMwV3rry2qUZ6+ut0PP0c/43WZyDV3YVLaF1VfxMQ1euyjGyEJQPIFf73XVIN++2Wlo+ IbLnBozx7kSsxF8TzcwAQjMP4fDIdaXRFktsHZFZJpegDTnuV3lJk3dtubcamV3EtMHeivyhhLA7C QFBg7iFHwZR3N61q0ww3UU6zteAkxjIEXot/mcn3P4kOVPRYSW+WclSi7+gNUkUTjPMb724wrK/y2 bkvJNvvS9HAJmuU2gt6g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hsXBF-00085W-Ua; Tue, 30 Jul 2019 18:49:01 +0000 Received: from bhuna.collabora.co.uk ([46.235.227.227]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hsX8J-00055I-Hb; Tue, 30 Jul 2019 18:46:01 +0000 Received: from floko.floko.floko (unknown [IPv6:2804:431:c7f1:ce2f:ec1:e6e6:2e9f:e76e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: koike) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id A508728B911; Tue, 30 Jul 2019 19:45:53 +0100 (BST) From: Helen Koike To: linux-rockchip@lists.infradead.org Subject: [PATCH v8 14/14] MAINTAINERS: add entry for Rockchip ISP1 driver Date: Tue, 30 Jul 2019 15:42:56 -0300 Message-Id: <20190730184256.30338-15-helen.koike@collabora.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190730184256.30338-1-helen.koike@collabora.com> References: <20190730184256.30338-1-helen.koike@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190730_114559_880333_00D233D4 X-CRM114-Status: UNSURE ( 7.77 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, eddie.cai.linux@gmail.com, kernel@collabora.com, heiko@sntech.de, jacob2.chen@rock-chips.com, jeffy.chen@rock-chips.com, zyc@rock-chips.com, linux-kernel@vger.kernel.org, tfiga@chromium.org, Helen Koike , hans.verkuil@cisco.com, laurent.pinchart@ideasonboard.com, sakari.ailus@linux.intel.com, zhengsq@rock-chips.com, mchehab@kernel.org, ezequiel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add MAINTAINERS entry for the rockchip isp1 driver. Signed-off-by: Helen Koike --- Changes in v8: None Changes in v7: None MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6426db5198f0..7f38abcb4114 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13743,6 +13743,14 @@ F: drivers/hid/hid-roccat* F: include/linux/hid-roccat* F: Documentation/ABI/*/sysfs-driver-hid-roccat* +ROCKCHIP ISP V1 DRIVER +M: Helen Koike +L: linux-media@vger.kernel.org +S: Maintained +F: drivers/media/platform/rockchip/isp1/ +F: Documentation/devicetree/bindings/media/rockchip-isp1.txt +F: Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt + ROCKCHIP RASTER 2D GRAPHIC ACCELERATION UNIT DRIVER M: Jacob chen L: linux-media@vger.kernel.org