From patchwork Wed Sep 5 18:31:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 10589285 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 02B9B14E0 for ; Wed, 5 Sep 2018 18:33:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EAE332A7B5 for ; Wed, 5 Sep 2018 18:33:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DD72A2A8A0; Wed, 5 Sep 2018 18:33:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9731E2A7B5 for ; Wed, 5 Sep 2018 18:33:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E4A1E6E541; Wed, 5 Sep 2018 18:32:35 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4C5AA89A1A for ; Wed, 5 Sep 2018 18:32:32 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Sep 2018 11:32:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,334,1531810800"; d="scan'208";a="261012469" Received: from ldmartin-desk.jf.intel.com ([10.24.11.56]) by fmsmga006.fm.intel.com with ESMTP; 05 Sep 2018 11:32:30 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Wed, 5 Sep 2018 11:31:56 -0700 Message-Id: <20180905183200.18383-2-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180905183200.18383-1-lucas.demarchi@intel.com> References: <20180905183200.18383-1-lucas.demarchi@intel.com> Subject: [Intel-gfx] [PATCH libdrm v3 1/5] intel: add generic functions to check PCI ID X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rodrigo Vivi , Paulo Zanoni , dri-devel@freedesktop.org MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This will allow platforms to reuse kernel IDs instead of manually keeping them in sync. In most of the cases we only need to extend IS_9XX(). Current platforms that fit this requirement can be ported over to use this macro. Right now it's a nop since it doesn't have any PCI ID added. The i915_pciids.h header is in sync with kernel tree on drm-tip 2018y-08m-20d-21h-41m-11s. v2: - move to a separate .c so we can have the array in a single compilation unit - use a single array for all gens - add real functions to get or check gen by pciid - define our own pci device struct rather than inherit the one kernel uses: we can throw away most of the fields v3: - add comment to keep ids sorted by gen - remove misleading comment about all gens Cc: Chris Wilson Signed-off-by: Lucas De Marchi --- intel/Makefile.sources | 1 + intel/i915_pciids.h | 461 +++++++++++++++++++++++++++++++++++++++++ intel/intel_chipset.c | 78 +++++++ intel/intel_chipset.h | 9 +- intel/meson.build | 2 +- 5 files changed, 549 insertions(+), 2 deletions(-) create mode 100644 intel/i915_pciids.h create mode 100644 intel/intel_chipset.c diff --git a/intel/Makefile.sources b/intel/Makefile.sources index 6947ab74..61f43aeb 100644 --- a/intel/Makefile.sources +++ b/intel/Makefile.sources @@ -5,6 +5,7 @@ LIBDRM_INTEL_FILES := \ intel_bufmgr_gem.c \ intel_decode.c \ intel_chipset.h \ + intel_chipset.c \ mm.c \ mm.h \ uthash.h diff --git a/intel/i915_pciids.h b/intel/i915_pciids.h new file mode 100644 index 00000000..fd965ffb --- /dev/null +++ b/intel/i915_pciids.h @@ -0,0 +1,461 @@ +/* + * Copyright 2013 Intel Corporation + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef _I915_PCIIDS_H +#define _I915_PCIIDS_H + +/* + * A pci_device_id struct { + * __u32 vendor, device; + * __u32 subvendor, subdevice; + * __u32 class, class_mask; + * kernel_ulong_t driver_data; + * }; + * Don't use C99 here because "class" is reserved and we want to + * give userspace flexibility. + */ +#define INTEL_VGA_DEVICE(id, info) { \ + 0x8086, id, \ + ~0, ~0, \ + 0x030000, 0xff0000, \ + (unsigned long) info } + +#define INTEL_QUANTA_VGA_DEVICE(info) { \ + 0x8086, 0x16a, \ + 0x152d, 0x8990, \ + 0x030000, 0xff0000, \ + (unsigned long) info } + +#define INTEL_I810_IDS(info) \ + INTEL_VGA_DEVICE(0x7121, info), /* I810 */ \ + INTEL_VGA_DEVICE(0x7123, info), /* I810_DC100 */ \ + INTEL_VGA_DEVICE(0x7125, info) /* I810_E */ + +#define INTEL_I815_IDS(info) \ + INTEL_VGA_DEVICE(0x1132, info) /* I815*/ + +#define INTEL_I830_IDS(info) \ + INTEL_VGA_DEVICE(0x3577, info) + +#define INTEL_I845G_IDS(info) \ + INTEL_VGA_DEVICE(0x2562, info) + +#define INTEL_I85X_IDS(info) \ + INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \ + INTEL_VGA_DEVICE(0x358e, info) + +#define INTEL_I865G_IDS(info) \ + INTEL_VGA_DEVICE(0x2572, info) /* I865_G */ + +#define INTEL_I915G_IDS(info) \ + INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \ + INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */ + +#define INTEL_I915GM_IDS(info) \ + INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */ + +#define INTEL_I945G_IDS(info) \ + INTEL_VGA_DEVICE(0x2772, info) /* I945_G */ + +#define INTEL_I945GM_IDS(info) \ + INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \ + INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */ + +#define INTEL_I965G_IDS(info) \ + INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \ + INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \ + INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \ + INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */ + +#define INTEL_G33_IDS(info) \ + INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \ + INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \ + INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */ + +#define INTEL_I965GM_IDS(info) \ + INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \ + INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */ + +#define INTEL_GM45_IDS(info) \ + INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */ + +#define INTEL_G45_IDS(info) \ + INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \ + INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \ + INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \ + INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \ + INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \ + INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */ + +#define INTEL_PINEVIEW_IDS(info) \ + INTEL_VGA_DEVICE(0xa001, info), \ + INTEL_VGA_DEVICE(0xa011, info) + +#define INTEL_IRONLAKE_D_IDS(info) \ + INTEL_VGA_DEVICE(0x0042, info) + +#define INTEL_IRONLAKE_M_IDS(info) \ + INTEL_VGA_DEVICE(0x0046, info) + +#define INTEL_SNB_D_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x0102, info), \ + INTEL_VGA_DEVICE(0x010A, info) + +#define INTEL_SNB_D_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x0112, info), \ + INTEL_VGA_DEVICE(0x0122, info) + +#define INTEL_SNB_D_IDS(info) \ + INTEL_SNB_D_GT1_IDS(info), \ + INTEL_SNB_D_GT2_IDS(info) + +#define INTEL_SNB_M_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x0106, info) + +#define INTEL_SNB_M_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x0116, info), \ + INTEL_VGA_DEVICE(0x0126, info) + +#define INTEL_SNB_M_IDS(info) \ + INTEL_SNB_M_GT1_IDS(info), \ + INTEL_SNB_M_GT2_IDS(info) + +#define INTEL_IVB_M_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */ + +#define INTEL_IVB_M_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */ + +#define INTEL_IVB_M_IDS(info) \ + INTEL_IVB_M_GT1_IDS(info), \ + INTEL_IVB_M_GT2_IDS(info) + +#define INTEL_IVB_D_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \ + INTEL_VGA_DEVICE(0x015a, info) /* GT1 server */ + +#define INTEL_IVB_D_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \ + INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */ + +#define INTEL_IVB_D_IDS(info) \ + INTEL_IVB_D_GT1_IDS(info), \ + INTEL_IVB_D_GT2_IDS(info) + +#define INTEL_IVB_Q_IDS(info) \ + INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */ + +#define INTEL_HSW_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \ + INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \ + INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \ + INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \ + INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \ + INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \ + INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */ + +#define INTEL_HSW_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \ + INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \ + INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \ + INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \ + INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \ + INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \ + INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */ + +#define INTEL_HSW_GT3_IDS(info) \ + INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \ + INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \ + INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \ + INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \ + INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \ + INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \ + INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \ + INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ + INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */ + +#define INTEL_HSW_IDS(info) \ + INTEL_HSW_GT1_IDS(info), \ + INTEL_HSW_GT2_IDS(info), \ + INTEL_HSW_GT3_IDS(info) + +#define INTEL_VLV_IDS(info) \ + INTEL_VGA_DEVICE(0x0f30, info), \ + INTEL_VGA_DEVICE(0x0f31, info), \ + INTEL_VGA_DEVICE(0x0f32, info), \ + INTEL_VGA_DEVICE(0x0f33, info), \ + INTEL_VGA_DEVICE(0x0157, info), \ + INTEL_VGA_DEVICE(0x0155, info) + +#define INTEL_BDW_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \ + INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \ + INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \ + INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \ + INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \ + INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */ + +#define INTEL_BDW_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \ + INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \ + INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \ + INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \ + INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \ + INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */ + +#define INTEL_BDW_GT3_IDS(info) \ + INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \ + INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \ + INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \ + INTEL_VGA_DEVICE(0x162E, info), /* ULX */\ + INTEL_VGA_DEVICE(0x162A, info), /* Server */ \ + INTEL_VGA_DEVICE(0x162D, info) /* Workstation */ + +#define INTEL_BDW_RSVD_IDS(info) \ + INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \ + INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \ + INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \ + INTEL_VGA_DEVICE(0x163E, info), /* ULX */ \ + INTEL_VGA_DEVICE(0x163A, info), /* Server */ \ + INTEL_VGA_DEVICE(0x163D, info) /* Workstation */ + +#define INTEL_BDW_IDS(info) \ + INTEL_BDW_GT1_IDS(info), \ + INTEL_BDW_GT2_IDS(info), \ + INTEL_BDW_GT3_IDS(info), \ + INTEL_BDW_RSVD_IDS(info) + +#define INTEL_CHV_IDS(info) \ + INTEL_VGA_DEVICE(0x22b0, info), \ + INTEL_VGA_DEVICE(0x22b1, info), \ + INTEL_VGA_DEVICE(0x22b2, info), \ + INTEL_VGA_DEVICE(0x22b3, info) + +#define INTEL_SKL_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \ + INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \ + INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \ + INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \ + INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */ + +#define INTEL_SKL_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \ + INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \ + INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \ + INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \ + INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \ + INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \ + INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */ + +#define INTEL_SKL_GT3_IDS(info) \ + INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \ + INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3 */ + +#define INTEL_SKL_GT4_IDS(info) \ + INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \ + INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \ + INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \ + INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \ + INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4e */ + +#define INTEL_SKL_IDS(info) \ + INTEL_SKL_GT1_IDS(info), \ + INTEL_SKL_GT2_IDS(info), \ + INTEL_SKL_GT3_IDS(info), \ + INTEL_SKL_GT4_IDS(info) + +#define INTEL_BXT_IDS(info) \ + INTEL_VGA_DEVICE(0x0A84, info), \ + INTEL_VGA_DEVICE(0x1A84, info), \ + INTEL_VGA_DEVICE(0x1A85, info), \ + INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \ + INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */ + +#define INTEL_GLK_IDS(info) \ + INTEL_VGA_DEVICE(0x3184, info), \ + INTEL_VGA_DEVICE(0x3185, info) + +#define INTEL_KBL_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \ + INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \ + INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \ + INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \ + INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \ + INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \ + INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \ + INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */ + +#define INTEL_KBL_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \ + INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \ + INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \ + INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \ + INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \ + INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \ + INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \ + INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */ + +#define INTEL_KBL_GT3_IDS(info) \ + INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */ + +#define INTEL_KBL_GT4_IDS(info) \ + INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */ + +/* AML/KBL Y GT2 */ +#define INTEL_AML_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x591C, info), /* ULX GT2 */ \ + INTEL_VGA_DEVICE(0x87C0, info) /* ULX GT2 */ + +#define INTEL_KBL_IDS(info) \ + INTEL_KBL_GT1_IDS(info), \ + INTEL_KBL_GT2_IDS(info), \ + INTEL_KBL_GT3_IDS(info), \ + INTEL_KBL_GT4_IDS(info), \ + INTEL_AML_GT2_IDS(info) + +/* CFL S */ +#define INTEL_CFL_S_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \ + INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \ + INTEL_VGA_DEVICE(0x3E99, info) /* SRV GT1 */ + +#define INTEL_CFL_S_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \ + INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \ + INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \ + INTEL_VGA_DEVICE(0x3E98, info), /* SRV GT2 */ \ + INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */ + +/* CFL H */ +#define INTEL_CFL_H_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \ + INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */ + +/* CFL U GT2 */ +#define INTEL_CFL_U_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x3EA9, info) + +/* CFL U GT3 */ +#define INTEL_CFL_U_GT3_IDS(info) \ + INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x3EA8, info) /* ULT GT3 */ + +/* WHL/CFL U GT1 */ +#define INTEL_WHL_U_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x3EA1, info) + +/* WHL/CFL U GT2 */ +#define INTEL_WHL_U_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x3EA0, info) + +/* WHL/CFL U GT3 */ +#define INTEL_WHL_U_GT3_IDS(info) \ + INTEL_VGA_DEVICE(0x3EA2, info), \ + INTEL_VGA_DEVICE(0x3EA3, info), \ + INTEL_VGA_DEVICE(0x3EA4, info) + +#define INTEL_CFL_IDS(info) \ + INTEL_CFL_S_GT1_IDS(info), \ + INTEL_CFL_S_GT2_IDS(info), \ + INTEL_CFL_H_GT2_IDS(info), \ + INTEL_CFL_U_GT2_IDS(info), \ + INTEL_CFL_U_GT3_IDS(info), \ + INTEL_WHL_U_GT1_IDS(info), \ + INTEL_WHL_U_GT2_IDS(info), \ + INTEL_WHL_U_GT3_IDS(info) + +/* CNL */ +#define INTEL_CNL_IDS(info) \ + INTEL_VGA_DEVICE(0x5A51, info), \ + INTEL_VGA_DEVICE(0x5A59, info), \ + INTEL_VGA_DEVICE(0x5A41, info), \ + INTEL_VGA_DEVICE(0x5A49, info), \ + INTEL_VGA_DEVICE(0x5A52, info), \ + INTEL_VGA_DEVICE(0x5A5A, info), \ + INTEL_VGA_DEVICE(0x5A42, info), \ + INTEL_VGA_DEVICE(0x5A4A, info), \ + INTEL_VGA_DEVICE(0x5A50, info), \ + INTEL_VGA_DEVICE(0x5A40, info), \ + INTEL_VGA_DEVICE(0x5A54, info), \ + INTEL_VGA_DEVICE(0x5A5C, info), \ + INTEL_VGA_DEVICE(0x5A44, info), \ + INTEL_VGA_DEVICE(0x5A4C, info) + +/* ICL */ +#define INTEL_ICL_11_IDS(info) \ + INTEL_VGA_DEVICE(0x8A50, info), \ + INTEL_VGA_DEVICE(0x8A51, info), \ + INTEL_VGA_DEVICE(0x8A5C, info), \ + INTEL_VGA_DEVICE(0x8A5D, info), \ + INTEL_VGA_DEVICE(0x8A52, info), \ + INTEL_VGA_DEVICE(0x8A5A, info), \ + INTEL_VGA_DEVICE(0x8A5B, info), \ + INTEL_VGA_DEVICE(0x8A71, info), \ + INTEL_VGA_DEVICE(0x8A70, info) + +#endif /* _I915_PCIIDS_H */ diff --git a/intel/intel_chipset.c b/intel/intel_chipset.c new file mode 100644 index 00000000..545819ae --- /dev/null +++ b/intel/intel_chipset.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2018 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ +#include "intel_chipset.h" + +#include +#include + +#include "i915_pciids.h" + +#undef INTEL_VGA_DEVICE +#define INTEL_VGA_DEVICE(id, gen) { id, gen } + +static const struct pci_device { + uint16_t device; + uint16_t gen; +} pciids[] = { + /* Keep ids sorted by gen; latest gen first */ +}; + +bool intel_is_genx(unsigned int devid, int gen) +{ + const struct pci_device *p, + *pend = pciids + sizeof(pciids) / sizeof(pciids[0]); + + for (p = pciids; p < pend; p++) { + /* PCI IDs are sorted */ + if (p->gen < gen) + break; + + if (p->device != devid) + continue; + + if (gen == p->gen) + return true; + + break; + } + + return false; +} + +bool intel_get_genx(unsigned int devid, int *gen) +{ + const struct pci_device *p, + *pend = pciids + sizeof(pciids) / sizeof(pciids[0]); + + for (p = pciids; p < pend; p++) { + if (p->device != devid) + continue; + + if (gen) + *gen = p->gen; + + return true; + } + + return false; +} diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 4a34b7be..e4783d4e 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -568,6 +568,12 @@ #define IS_GEN11(devid) (IS_ICELAKE_11(devid)) +/* New platforms use kernel pci ids */ +#include + +bool intel_is_genx(unsigned int devid, int gen); +bool intel_get_genx(unsigned int devid, int *gen); + #define IS_9XX(dev) (IS_GEN3(dev) || \ IS_GEN4(dev) || \ IS_GEN5(dev) || \ @@ -576,6 +582,7 @@ IS_GEN8(dev) || \ IS_GEN9(dev) || \ IS_GEN10(dev) || \ - IS_GEN11(dev)) + IS_GEN11(dev) || \ + intel_get_genx(dev, NULL)) #endif /* _INTEL_CHIPSET_H */ diff --git a/intel/meson.build b/intel/meson.build index 53c7fce4..ff40ab91 100644 --- a/intel/meson.build +++ b/intel/meson.build @@ -23,7 +23,7 @@ libdrm_intel = shared_library( [ files( 'intel_bufmgr.c', 'intel_bufmgr_fake.c', 'intel_bufmgr_gem.c', - 'intel_decode.c', 'mm.c', + 'intel_decode.c', 'mm.c', 'intel_chipset.c', ), config_file, ], From patchwork Wed Sep 5 18:31:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 10589269 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 771B214E0 for ; Wed, 5 Sep 2018 18:32:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6DA072A781 for ; Wed, 5 Sep 2018 18:32:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 61EF72A883; Wed, 5 Sep 2018 18:32:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1C1F02A781 for ; Wed, 5 Sep 2018 18:32:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 71EF289BA3; Wed, 5 Sep 2018 18:32:33 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0B93C89B0B for ; Wed, 5 Sep 2018 18:32:32 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Sep 2018 11:32:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,334,1531810800"; d="scan'208";a="261012472" Received: from ldmartin-desk.jf.intel.com ([10.24.11.56]) by fmsmga006.fm.intel.com with ESMTP; 05 Sep 2018 11:32:30 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Wed, 5 Sep 2018 11:31:57 -0700 Message-Id: <20180905183200.18383-3-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180905183200.18383-1-lucas.demarchi@intel.com> References: <20180905183200.18383-1-lucas.demarchi@intel.com> Subject: [Intel-gfx] [PATCH libdrm v3 2/5] intel: make gen11 use generic gen macro X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rodrigo Vivi , Paulo Zanoni , dri-devel@freedesktop.org MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Lucas De Marchi --- intel/intel_chipset.c | 1 + intel/intel_chipset.h | 27 ++------------------------- 2 files changed, 3 insertions(+), 25 deletions(-) diff --git a/intel/intel_chipset.c b/intel/intel_chipset.c index 545819ae..a960b756 100644 --- a/intel/intel_chipset.c +++ b/intel/intel_chipset.c @@ -35,6 +35,7 @@ static const struct pci_device { uint16_t gen; } pciids[] = { /* Keep ids sorted by gen; latest gen first */ + INTEL_ICL_11_IDS(11), }; bool intel_is_genx(unsigned int devid, int gen) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index e4783d4e..db9b53b2 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -261,16 +261,6 @@ #define PCI_CHIP_CANNONLAKE_12 0x5A44 #define PCI_CHIP_CANNONLAKE_13 0x5A4C -#define PCI_CHIP_ICELAKE_11_0 0x8A50 -#define PCI_CHIP_ICELAKE_11_1 0x8A51 -#define PCI_CHIP_ICELAKE_11_2 0x8A5C -#define PCI_CHIP_ICELAKE_11_3 0x8A5D -#define PCI_CHIP_ICELAKE_11_4 0x8A52 -#define PCI_CHIP_ICELAKE_11_5 0x8A5A -#define PCI_CHIP_ICELAKE_11_6 0x8A5B -#define PCI_CHIP_ICELAKE_11_7 0x8A71 -#define PCI_CHIP_ICELAKE_11_8 0x8A70 - #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ (devid) == PCI_CHIP_I915_GM || \ (devid) == PCI_CHIP_I945_GM || \ @@ -554,26 +544,14 @@ #define IS_GEN10(devid) (IS_CANNONLAKE(devid)) -#define IS_ICELAKE_11(devid) ((devid) == PCI_CHIP_ICELAKE_11_0 || \ - (devid) == PCI_CHIP_ICELAKE_11_1 || \ - (devid) == PCI_CHIP_ICELAKE_11_2 || \ - (devid) == PCI_CHIP_ICELAKE_11_3 || \ - (devid) == PCI_CHIP_ICELAKE_11_4 || \ - (devid) == PCI_CHIP_ICELAKE_11_5 || \ - (devid) == PCI_CHIP_ICELAKE_11_6 || \ - (devid) == PCI_CHIP_ICELAKE_11_7 || \ - (devid) == PCI_CHIP_ICELAKE_11_8) - -#define IS_ICELAKE(devid) (IS_ICELAKE_11(devid)) - -#define IS_GEN11(devid) (IS_ICELAKE_11(devid)) - /* New platforms use kernel pci ids */ #include bool intel_is_genx(unsigned int devid, int gen); bool intel_get_genx(unsigned int devid, int *gen); +#define IS_GEN11(devid) intel_is_genx(devid, 11) + #define IS_9XX(dev) (IS_GEN3(dev) || \ IS_GEN4(dev) || \ IS_GEN5(dev) || \ @@ -582,7 +560,6 @@ bool intel_get_genx(unsigned int devid, int *gen); IS_GEN8(dev) || \ IS_GEN9(dev) || \ IS_GEN10(dev) || \ - IS_GEN11(dev) || \ intel_get_genx(dev, NULL)) #endif /* _INTEL_CHIPSET_H */ From patchwork Wed Sep 5 18:31:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 10589273 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D595A920 for ; Wed, 5 Sep 2018 18:32:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CDF9B2A769 for ; Wed, 5 Sep 2018 18:32:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C2D3B2A797; Wed, 5 Sep 2018 18:32:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 751112A769 for ; Wed, 5 Sep 2018 18:32:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 02AD889C59; Wed, 5 Sep 2018 18:32:34 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id C195F89B48 for ; Wed, 5 Sep 2018 18:32:32 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Sep 2018 11:32:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,334,1531810800"; d="scan'208";a="261012475" Received: from ldmartin-desk.jf.intel.com ([10.24.11.56]) by fmsmga006.fm.intel.com with ESMTP; 05 Sep 2018 11:32:30 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Wed, 5 Sep 2018 11:31:58 -0700 Message-Id: <20180905183200.18383-4-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180905183200.18383-1-lucas.demarchi@intel.com> References: <20180905183200.18383-1-lucas.demarchi@intel.com> Subject: [Intel-gfx] [PATCH libdrm v3 3/5] intel: make gen10 use generic gen macro X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rodrigo Vivi , Paulo Zanoni , dri-devel@freedesktop.org MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Lucas De Marchi --- intel/intel_chipset.c | 1 + intel/intel_chipset.h | 34 +--------------------------------- 2 files changed, 2 insertions(+), 33 deletions(-) diff --git a/intel/intel_chipset.c b/intel/intel_chipset.c index a960b756..a627928e 100644 --- a/intel/intel_chipset.c +++ b/intel/intel_chipset.c @@ -36,6 +36,7 @@ static const struct pci_device { } pciids[] = { /* Keep ids sorted by gen; latest gen first */ INTEL_ICL_11_IDS(11), + INTEL_CNL_IDS(10), }; bool intel_is_genx(unsigned int devid, int gen) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index db9b53b2..7179b623 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -246,21 +246,6 @@ #define PCI_CHIP_WHISKEYLAKE_U_GT3_2 0x3EA3 #define PCI_CHIP_WHISKEYLAKE_U_GT3_3 0x3EA4 -#define PCI_CHIP_CANNONLAKE_0 0x5A51 -#define PCI_CHIP_CANNONLAKE_1 0x5A59 -#define PCI_CHIP_CANNONLAKE_2 0x5A41 -#define PCI_CHIP_CANNONLAKE_3 0x5A49 -#define PCI_CHIP_CANNONLAKE_4 0x5A52 -#define PCI_CHIP_CANNONLAKE_5 0x5A5A -#define PCI_CHIP_CANNONLAKE_6 0x5A42 -#define PCI_CHIP_CANNONLAKE_7 0x5A4A -#define PCI_CHIP_CANNONLAKE_8 0x5A50 -#define PCI_CHIP_CANNONLAKE_9 0x5A40 -#define PCI_CHIP_CANNONLAKE_10 0x5A54 -#define PCI_CHIP_CANNONLAKE_11 0x5A5C -#define PCI_CHIP_CANNONLAKE_12 0x5A44 -#define PCI_CHIP_CANNONLAKE_13 0x5A4C - #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ (devid) == PCI_CHIP_I915_GM || \ (devid) == PCI_CHIP_I945_GM || \ @@ -527,29 +512,13 @@ IS_GEMINILAKE(devid) || \ IS_COFFEELAKE(devid)) -#define IS_CANNONLAKE(devid) ((devid) == PCI_CHIP_CANNONLAKE_0 || \ - (devid) == PCI_CHIP_CANNONLAKE_1 || \ - (devid) == PCI_CHIP_CANNONLAKE_2 || \ - (devid) == PCI_CHIP_CANNONLAKE_3 || \ - (devid) == PCI_CHIP_CANNONLAKE_4 || \ - (devid) == PCI_CHIP_CANNONLAKE_5 || \ - (devid) == PCI_CHIP_CANNONLAKE_6 || \ - (devid) == PCI_CHIP_CANNONLAKE_7 || \ - (devid) == PCI_CHIP_CANNONLAKE_8 || \ - (devid) == PCI_CHIP_CANNONLAKE_9 || \ - (devid) == PCI_CHIP_CANNONLAKE_10 || \ - (devid) == PCI_CHIP_CANNONLAKE_11 || \ - (devid) == PCI_CHIP_CANNONLAKE_12 || \ - (devid) == PCI_CHIP_CANNONLAKE_13) - -#define IS_GEN10(devid) (IS_CANNONLAKE(devid)) - /* New platforms use kernel pci ids */ #include bool intel_is_genx(unsigned int devid, int gen); bool intel_get_genx(unsigned int devid, int *gen); +#define IS_GEN10(devid) intel_is_genx(devid, 10) #define IS_GEN11(devid) intel_is_genx(devid, 11) #define IS_9XX(dev) (IS_GEN3(dev) || \ @@ -559,7 +528,6 @@ bool intel_get_genx(unsigned int devid, int *gen); IS_GEN7(dev) || \ IS_GEN8(dev) || \ IS_GEN9(dev) || \ - IS_GEN10(dev) || \ intel_get_genx(dev, NULL)) #endif /* _INTEL_CHIPSET_H */ From patchwork Wed Sep 5 18:31:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 10589275 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3CFE8920 for ; Wed, 5 Sep 2018 18:32:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 33C4E2A769 for ; Wed, 5 Sep 2018 18:32:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 27D5A2A797; Wed, 5 Sep 2018 18:32:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,UPPERCASE_50_75 autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9532C2A769 for ; Wed, 5 Sep 2018 18:32:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CB3F189C03; Wed, 5 Sep 2018 18:32:33 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9C595899F2 for ; Wed, 5 Sep 2018 18:32:32 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Sep 2018 11:32:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,334,1531810800"; d="scan'208";a="261012480" Received: from ldmartin-desk.jf.intel.com ([10.24.11.56]) by fmsmga006.fm.intel.com with ESMTP; 05 Sep 2018 11:32:30 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Wed, 5 Sep 2018 11:31:59 -0700 Message-Id: <20180905183200.18383-5-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180905183200.18383-1-lucas.demarchi@intel.com> References: <20180905183200.18383-1-lucas.demarchi@intel.com> Subject: [Intel-gfx] [PATCH libdrm v3 4/5] intel: make gen9 use generic gen macro X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rodrigo Vivi , Paulo Zanoni , dri-devel@freedesktop.org MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The 2 PCI IDs that are used for the command line overrid mechanism were left defined. The rest can be gone and then we just use the kernel defines. Signed-off-by: Lucas De Marchi --- intel/intel_chipset.c | 5 ++ intel/intel_chipset.h | 187 +----------------------------------------- 2 files changed, 6 insertions(+), 186 deletions(-) diff --git a/intel/intel_chipset.c b/intel/intel_chipset.c index a627928e..d5c33cc5 100644 --- a/intel/intel_chipset.c +++ b/intel/intel_chipset.c @@ -37,6 +37,11 @@ static const struct pci_device { /* Keep ids sorted by gen; latest gen first */ INTEL_ICL_11_IDS(11), INTEL_CNL_IDS(10), + INTEL_CFL_IDS(9), + INTEL_GLK_IDS(9), + INTEL_KBL_IDS(9), + INTEL_BXT_IDS(9), + INTEL_SKL_IDS(9), }; bool intel_is_genx(unsigned int devid, int gen) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 7179b623..9b1e64f1 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -165,86 +165,8 @@ #define PCI_CHIP_CHERRYVIEW_2 0x22b2 #define PCI_CHIP_CHERRYVIEW_3 0x22b3 -#define PCI_CHIP_SKYLAKE_DT_GT1 0x1902 -#define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906 -#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A /* Reserved */ -#define PCI_CHIP_SKYLAKE_H_GT1 0x190B -#define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E /* Reserved */ #define PCI_CHIP_SKYLAKE_DT_GT2 0x1912 -#define PCI_CHIP_SKYLAKE_FUSED0_GT2 0x1913 /* Reserved */ -#define PCI_CHIP_SKYLAKE_FUSED1_GT2 0x1915 /* Reserved */ -#define PCI_CHIP_SKYLAKE_ULT_GT2 0x1916 -#define PCI_CHIP_SKYLAKE_FUSED2_GT2 0x1917 /* Reserved */ -#define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A /* Reserved */ -#define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B -#define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D -#define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E -#define PCI_CHIP_SKYLAKE_MOBILE_GT2 0x1921 /* Reserved */ -#define PCI_CHIP_SKYLAKE_ULT_GT3_0 0x1923 -#define PCI_CHIP_SKYLAKE_ULT_GT3_1 0x1926 -#define PCI_CHIP_SKYLAKE_ULT_GT3_2 0x1927 -#define PCI_CHIP_SKYLAKE_SRV_GT4 0x192A -#define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B /* Reserved */ -#define PCI_CHIP_SKYLAKE_SRV_GT3 0x192D -#define PCI_CHIP_SKYLAKE_DT_GT4 0x1932 -#define PCI_CHIP_SKYLAKE_SRV_GT4X 0x193A -#define PCI_CHIP_SKYLAKE_H_GT4 0x193B -#define PCI_CHIP_SKYLAKE_WKS_GT4 0x193D - -#define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916 -#define PCI_CHIP_KABYLAKE_ULT_GT1_5 0x5913 -#define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906 -#define PCI_CHIP_KABYLAKE_ULT_GT3_0 0x5923 -#define PCI_CHIP_KABYLAKE_ULT_GT3_1 0x5926 -#define PCI_CHIP_KABYLAKE_ULT_GT3_2 0x5927 -#define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921 -#define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915 -#define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E -#define PCI_CHIP_KABYLAKE_ULX_GT2_0 0x591E #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 -#define PCI_CHIP_KABYLAKE_M_GT2 0x5917 -#define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 -#define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B -#define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B -#define PCI_CHIP_KABYLAKE_HALO_GT1_0 0x5908 -#define PCI_CHIP_KABYLAKE_HALO_GT1_1 0x590B -#define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A -#define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A -#define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D - -#define PCI_CHIP_AMBERLAKE_ULX_GT2_1 0x591C -#define PCI_CHIP_AMBERLAKE_ULX_GT2_2 0x87C0 - -#define PCI_CHIP_BROXTON_0 0x0A84 -#define PCI_CHIP_BROXTON_1 0x1A84 -#define PCI_CHIP_BROXTON_2 0x5A84 -#define PCI_CHIP_BROXTON_3 0x1A85 -#define PCI_CHIP_BROXTON_4 0x5A85 - -#define PCI_CHIP_GLK 0x3184 -#define PCI_CHIP_GLK_2X6 0x3185 - -#define PCI_CHIP_COFFEELAKE_S_GT1_1 0x3E90 -#define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93 -#define PCI_CHIP_COFFEELAKE_S_GT1_3 0x3E99 -#define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91 -#define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92 -#define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96 -#define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E98 -#define PCI_CHIP_COFFEELAKE_S_GT2_5 0x3E9A -#define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B -#define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94 -#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA9 -#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5 -#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6 -#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7 -#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8 - -#define PCI_CHIP_WHISKEYLAKE_U_GT1_1 0x3EA1 -#define PCI_CHIP_WHISKEYLAKE_U_GT2_1 0x3EA0 -#define PCI_CHIP_WHISKEYLAKE_U_GT3_1 0x3EA2 -#define PCI_CHIP_WHISKEYLAKE_U_GT3_2 0x3EA3 -#define PCI_CHIP_WHISKEYLAKE_U_GT3_3 0x3EA4 #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ (devid) == PCI_CHIP_I915_GM || \ @@ -405,119 +327,13 @@ #define IS_GEN8(devid) (IS_BROADWELL(devid) || \ IS_CHERRYVIEW(devid)) -#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_SRV_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_H_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_ULX_GT1) - -#define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_FUSED1_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_ULT_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_FUSED2_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_SRV_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_HALO_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_WKS_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_MOBILE_GT2) - -#define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3_0 || \ - (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_1 || \ - (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_2 || \ - (devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \ - (devid) == PCI_CHIP_SKYLAKE_SRV_GT3) - -#define IS_SKL_GT4(devid) ((devid) == PCI_CHIP_SKYLAKE_SRV_GT4 || \ - (devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \ - (devid) == PCI_CHIP_SKYLAKE_SRV_GT4X || \ - (devid) == PCI_CHIP_SKYLAKE_H_GT4 || \ - (devid) == PCI_CHIP_SKYLAKE_WKS_GT4) - -#define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \ - (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \ - (devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \ - (devid) == PCI_CHIP_KABYLAKE_ULX_GT1 || \ - (devid) == PCI_CHIP_KABYLAKE_DT_GT1 || \ - (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_0 || \ - (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_1 || \ - (devid) == PCI_CHIP_KABYLAKE_SRV_GT1) - -#define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ - (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_0 || \ - (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_M_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_WKS_GT2 || \ - (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_1 || \ - (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_2) - -#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \ - (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \ - (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2) - -#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4) - -#define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \ - IS_KBL_GT2(devid) || \ - IS_KBL_GT3(devid) || \ - IS_KBL_GT4(devid)) - -#define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ - IS_SKL_GT2(devid) || \ - IS_SKL_GT3(devid) || \ - IS_SKL_GT4(devid)) - -#define IS_BROXTON(devid) ((devid) == PCI_CHIP_BROXTON_0 || \ - (devid) == PCI_CHIP_BROXTON_1 || \ - (devid) == PCI_CHIP_BROXTON_2 || \ - (devid) == PCI_CHIP_BROXTON_3 || \ - (devid) == PCI_CHIP_BROXTON_4) - -#define IS_GEMINILAKE(devid) ((devid) == PCI_CHIP_GLK || \ - (devid) == PCI_CHIP_GLK_2X6) - -#define IS_CFL_S(devid) ((devid) == PCI_CHIP_COFFEELAKE_S_GT1_1 || \ - (devid) == PCI_CHIP_COFFEELAKE_S_GT1_2 || \ - (devid) == PCI_CHIP_COFFEELAKE_S_GT1_3 || \ - (devid) == PCI_CHIP_COFFEELAKE_S_GT2_1 || \ - (devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \ - (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3 || \ - (devid) == PCI_CHIP_COFFEELAKE_S_GT2_4 || \ - (devid) == PCI_CHIP_COFFEELAKE_S_GT2_5) - -#define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \ - (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2) - -#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \ - (devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \ - (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \ - (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \ - (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4 || \ - (devid) == PCI_CHIP_WHISKEYLAKE_U_GT1_1 || \ - (devid) == PCI_CHIP_WHISKEYLAKE_U_GT2_1 || \ - (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_1 || \ - (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_2 || \ - (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_3) - -#define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \ - IS_CFL_H(devid) || \ - IS_CFL_U(devid)) - -#define IS_GEN9(devid) (IS_SKYLAKE(devid) || \ - IS_BROXTON(devid) || \ - IS_KABYLAKE(devid) || \ - IS_GEMINILAKE(devid) || \ - IS_COFFEELAKE(devid)) - /* New platforms use kernel pci ids */ #include bool intel_is_genx(unsigned int devid, int gen); bool intel_get_genx(unsigned int devid, int *gen); +#define IS_GEN9(devid) intel_is_genx(devid, 9) #define IS_GEN10(devid) intel_is_genx(devid, 10) #define IS_GEN11(devid) intel_is_genx(devid, 11) @@ -527,7 +343,6 @@ bool intel_get_genx(unsigned int devid, int *gen); IS_GEN6(dev) || \ IS_GEN7(dev) || \ IS_GEN8(dev) || \ - IS_GEN9(dev) || \ intel_get_genx(dev, NULL)) #endif /* _INTEL_CHIPSET_H */ From patchwork Wed Sep 5 18:32:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 10589287 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2CE8614E0 for ; Wed, 5 Sep 2018 18:33:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2376C2A7B5 for ; Wed, 5 Sep 2018 18:33:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 17B702A8A0; Wed, 5 Sep 2018 18:33:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D82FB2A7B5 for ; Wed, 5 Sep 2018 18:33:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EA2C06E545; Wed, 5 Sep 2018 18:32:35 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7720A89B48 for ; Wed, 5 Sep 2018 18:32:32 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Sep 2018 11:32:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,334,1531810800"; d="scan'208";a="261012483" Received: from ldmartin-desk.jf.intel.com ([10.24.11.56]) by fmsmga006.fm.intel.com with ESMTP; 05 Sep 2018 11:32:31 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Wed, 5 Sep 2018 11:32:00 -0700 Message-Id: <20180905183200.18383-6-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180905183200.18383-1-lucas.demarchi@intel.com> References: <20180905183200.18383-1-lucas.demarchi@intel.com> Subject: [Intel-gfx] [PATCH libdrm v3 5/5] intel: get gen once for gen >= 9 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rodrigo Vivi , Paulo Zanoni , dri-devel@freedesktop.org MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP We don't need to call IS_GEN() for each gen >= 9: we can rather use the new intel_is_genx() helper to iterate the pciids array once. Signed-off-by: Lucas De Marchi --- intel/intel_bufmgr_gem.c | 8 +------- intel/intel_decode.c | 8 ++------ 2 files changed, 3 insertions(+), 13 deletions(-) diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 8c3a4b20..d6587b76 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -3656,13 +3656,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) bufmgr_gem->gen = 7; else if (IS_GEN8(bufmgr_gem->pci_device)) bufmgr_gem->gen = 8; - else if (IS_GEN9(bufmgr_gem->pci_device)) - bufmgr_gem->gen = 9; - else if (IS_GEN10(bufmgr_gem->pci_device)) - bufmgr_gem->gen = 10; - else if (IS_GEN11(bufmgr_gem->pci_device)) - bufmgr_gem->gen = 11; - else { + else if (!intel_get_genx(bufmgr_gem->pci_device, &bufmgr_gem->gen)) { free(bufmgr_gem); bufmgr_gem = NULL; goto exit; diff --git a/intel/intel_decode.c b/intel/intel_decode.c index b24861b1..0ff095bc 100644 --- a/intel/intel_decode.c +++ b/intel/intel_decode.c @@ -3823,12 +3823,8 @@ drm_intel_decode_context_alloc(uint32_t devid) ctx->devid = devid; ctx->out = stdout; - if (IS_GEN11(devid)) - ctx->gen = 11; - else if (IS_GEN10(devid)) - ctx->gen = 10; - else if (IS_GEN9(devid)) - ctx->gen = 9; + if (intel_get_genx(devid, &ctx->gen)) + ; else if (IS_GEN8(devid)) ctx->gen = 8; else if (IS_GEN7(devid))