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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.28 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:28 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 08:59:56 -0700 Message-Id: <1565020823-24223-2-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 01/28] riscv: hw: Remove superfluous "linux, phandle" property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP "linux,phandle" property is optional. Remove all instances in the sifive_u and virt machine device tree. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/sifive_u.c | 3 --- hw/riscv/virt.c | 3 --- 2 files changed, 6 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 71b8083..ef36948 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -125,7 +125,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); qemu_fdt_add_subnode(fdt, intc); qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); - qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle); qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); @@ -184,7 +183,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle); plic_phandle = qemu_fdt_get_phandle(fdt, nodename); g_free(cells); g_free(nodename); @@ -197,7 +195,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", SIFIVE_U_GEM_CLOCK_FREQ); qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle); - qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", ethclk_phandle); ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename); g_free(nodename); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 25faf3b..00be05a 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -170,11 +170,9 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle); - qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", cpu_phandle); intc_phandle = phandle++; qemu_fdt_add_subnode(fdt, intc); qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle); - qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", intc_phandle); qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); @@ -250,7 +248,6 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV); qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle); plic_phandle = qemu_fdt_get_phandle(fdt, nodename); g_free(cells); g_free(nodename); From patchwork Mon Aug 5 15:59:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077279 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 97EC41398 for ; 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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.29 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:29 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 08:59:57 -0700 Message-Id: <1565020823-24223-3-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Some of the properties only have 1 cell so we should use qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells(). Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/sifive_u.c | 16 ++++++++-------- hw/riscv/virt.c | 24 ++++++++++++------------ 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index ef36948..623ee64 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -182,7 +182,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); - qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); plic_phandle = qemu_fdt_get_phandle(fdt, nodename); g_free(cells); g_free(nodename); @@ -207,20 +207,20 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 0x0, memmap[SIFIVE_U_GEM].size); qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); - qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); qemu_fdt_setprop_cells(fdt, nodename, "clocks", ethclk_phandle, ethclk_phandle, ethclk_phandle); qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names, sizeof(ethclk_names)); - qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1); - qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0); + qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); + qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); g_free(nodename); nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", (long)memmap[SIFIVE_U_GEM].base); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0); + qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); g_free(nodename); nodename = g_strdup_printf("/soc/uart@%lx", @@ -232,8 +232,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 0x0, memmap[SIFIVE_U_UART0].size); qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", SIFIVE_U_CLOCK_FREQ / 2); - qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 00be05a..127f005 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -233,8 +233,8 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, nodename = g_strdup_printf("/soc/interrupt-controller@%lx", (long)memmap[VIRT_PLIC].base); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", - FDT_PLIC_ADDR_CELLS); + qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", + FDT_PLIC_ADDR_CELLS); qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", FDT_PLIC_INT_CELLS); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); @@ -247,7 +247,7 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV); - qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); plic_phandle = qemu_fdt_get_phandle(fdt, nodename); g_free(cells); g_free(nodename); @@ -260,19 +260,19 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 0x0, memmap[VIRT_VIRTIO].size); - qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "interrupts", VIRTIO_IRQ + i); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", VIRTIO_IRQ + i); g_free(nodename); } nodename = g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", - FDT_PCI_ADDR_CELLS); - qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells", - FDT_PCI_INT_CELLS); - qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0x2); + qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", + FDT_PCI_ADDR_CELLS); + qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", + FDT_PCI_INT_CELLS); + qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0x2); qemu_fdt_setprop_string(fdt, nodename, "compatible", "pci-host-ecam-generic"); qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci"); @@ -309,8 +309,8 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, 0x0, memmap[VIRT_UART0].base, 0x0, memmap[VIRT_UART0].size); qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400); - qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "interrupts", UART0_IRQ); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", UART0_IRQ); qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); From patchwork Mon Aug 5 15:59:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077297 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 834B71398 for ; Mon, 5 Aug 2019 16:08:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 720FC286C7 for ; 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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Group SiFive E and U cpu type defines into one header file. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- include/hw/riscv/sifive_cpu.h | 31 +++++++++++++++++++++++++++++++ include/hw/riscv/sifive_e.h | 7 +------ include/hw/riscv/sifive_u.h | 7 +------ 3 files changed, 33 insertions(+), 12 deletions(-) create mode 100644 include/hw/riscv/sifive_cpu.h diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h new file mode 100644 index 0000000..1367996 --- /dev/null +++ b/include/hw/riscv/sifive_cpu.h @@ -0,0 +1,31 @@ +/* + * SiFive CPU types + * + * Copyright (c) 2017 SiFive, Inc. + * Copyright (c) 2019 Bin Meng + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef HW_SIFIVE_CPU_H +#define HW_SIFIVE_CPU_H + +#if defined(TARGET_RISCV32) +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 +#elif defined(TARGET_RISCV64) +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 +#endif + +#endif /* HW_SIFIVE_CPU_H */ diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index d175b24..e17cdfd 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -19,6 +19,7 @@ #ifndef HW_SIFIVE_E_H #define HW_SIFIVE_E_H +#include "hw/riscv/sifive_cpu.h" #include "hw/riscv/sifive_gpio.h" #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc" @@ -83,10 +84,4 @@ enum { #define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000 #define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000 -#if defined(TARGET_RISCV32) -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 -#elif defined(TARGET_RISCV64) -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 -#endif - #endif diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 892f0ee..4abc621 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -20,6 +20,7 @@ #define HW_SIFIVE_U_H #include "hw/net/cadence_gem.h" +#include "hw/riscv/sifive_cpu.h" #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" #define RISCV_U_SOC(obj) \ @@ -77,10 +78,4 @@ enum { #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000 #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000 -#if defined(TARGET_RISCV32) -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 -#elif defined(TARGET_RISCV64) -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 -#endif - #endif From patchwork Mon Aug 5 15:59:59 2019 Content-Type: text/plain; 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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.31 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:32 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 08:59:59 -0700 Message-Id: <1565020823-24223-5-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 04/28] riscv: hart: Extract hart realize to a separate routine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Currently riscv_harts_realize() creates all harts based on the same cpu type given in the hart array property. With current implementation it can only create symmetric harts. Exact the hart realize to a separate routine in preparation for supporting heterogeneous hart arrays. Signed-off-by: Bin Meng --- hw/riscv/riscv_hart.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index ca69a1b..3dd1c6a 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -37,26 +37,33 @@ static void riscv_harts_cpu_reset(void *opaque) cpu_reset(CPU(cpu)); } +static void riscv_hart_realize(RISCVHartArrayState *s, int hart, + char *cpu_type, Error **errp) +{ + Error *err = NULL; + + object_initialize_child(OBJECT(s), "harts[*]", &s->harts[hart], + sizeof(RISCVCPU), cpu_type, + &error_abort, NULL); + s->harts[hart].env.mhartid = hart; + qemu_register_reset(riscv_harts_cpu_reset, &s->harts[hart]); + object_property_set_bool(OBJECT(&s->harts[hart]), true, + "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } +} + static void riscv_harts_realize(DeviceState *dev, Error **errp) { RISCVHartArrayState *s = RISCV_HART_ARRAY(dev); - Error *err = NULL; int n; s->harts = g_new0(RISCVCPU, s->num_harts); for (n = 0; n < s->num_harts; n++) { - object_initialize_child(OBJECT(s), "harts[*]", &s->harts[n], - sizeof(RISCVCPU), s->cpu_type, - &error_abort, NULL); - s->harts[n].env.mhartid = n; - qemu_register_reset(riscv_harts_cpu_reset, &s->harts[n]); - object_property_set_bool(OBJECT(&s->harts[n]), true, - "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } + riscv_hart_realize(s, n, s->cpu_type, errp); } } From patchwork Mon Aug 5 16:00:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077305 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ECA5114E5 for ; Mon, 5 Aug 2019 16:09:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DCDFF286C7 for ; Mon, 5 Aug 2019 16:09:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D010F28711; 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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.32 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:33 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 09:00:00 -0700 Message-Id: <1565020823-24223-6-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 05/28] riscv: hart: Support heterogeneous harts population X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP At present we only allow symmetric harts to be created. In order to support heterogeneous harts like SiFive FU540, update hart array's "cpu-type" property to allow cpu type to be set per hart, separated by delimiter ",". The frist cpu type before the delimiter is assigned to hart 0, and the second cpu type before delimiter is assigned to hart 1, and so on. If the total number of cpu types supplied in "cpu-type" property is less than number of maximum harts, the last cpu type in the property will be used to populate remaining harts. Signed-off-by: Bin Meng --- hw/riscv/riscv_hart.c | 48 +++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 45 insertions(+), 3 deletions(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 3dd1c6a..27093e0 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -58,13 +58,55 @@ static void riscv_hart_realize(RISCVHartArrayState *s, int hart, static void riscv_harts_realize(DeviceState *dev, Error **errp) { RISCVHartArrayState *s = RISCV_HART_ARRAY(dev); - int n; + char *cpu_types; + char *first_type, *last_type, *tmp_type; + int n = 0; s->harts = g_new0(RISCVCPU, s->num_harts); - for (n = 0; n < s->num_harts; n++) { - riscv_hart_realize(s, n, s->cpu_type, errp); + /* we should not touch the original s->cpu_type */ + cpu_types = g_strdup(s->cpu_type); + + /* + * Expect s->cpu_type property was initialized this way: + * + * "cpu-type-a": symmetric harts + * "cpu-type-a,cpu-type-b,cpu-type-c": heterogeneous harts + * + * For heterogeneous harts, hart cpu types are separated by delimiter ",". + * The frist cpu type before the delimiter is assigned to hart 0, and the + * second cpu type before delimiter is assigned to hart 1, and so on. + * + * If the total number of cpu types is less than s->num_harts, the last + * cpu type in s->cpu_type will be used to populate remaining harts. + */ + + first_type = strtok(cpu_types, ","); + riscv_hart_realize(s, n++, first_type, errp); + tmp_type = strtok(NULL, ","); + if (!tmp_type) { + /* symmetric harts */ + for (; n < s->num_harts; n++) { + riscv_hart_realize(s, n, first_type, errp); + } + } else { + /* heterogeneous harts */ + while (tmp_type) { + if (n >= s->num_harts) { + break; + } + riscv_hart_realize(s, n++, tmp_type, errp); + last_type = tmp_type; + tmp_type = strtok(NULL, ","); + } + + /* populate remaining harts using the last cpu type in s->cpu_type */ + for (; n < s->num_harts; n++) { + riscv_hart_realize(s, n, last_type, errp); + } } + + g_free(cpu_types); } static void riscv_harts_class_init(ObjectClass *klass, void *data) From patchwork Mon Aug 5 16:00:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077275 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7E31D14E5 for ; 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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.33 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:34 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 09:00:01 -0700 Message-Id: <1565020823-24223-7-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54 RISC-V cores. Currently the sifive_u machine only populates 4 U54 cores. Update the max cpu number to 5 to reflect the real hardware, and pass "cpu-type" to populate heterogeneous harts. The cpu nodes in the generated DTS have been updated as well. Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 37 +++++++++++++++++++++++++++---------- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 623ee64..08d406f 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -10,7 +10,7 @@ * 1) CLINT (Core Level Interruptor) * 2) PLIC (Platform Level Interrupt Controller) * - * This board currently uses a hardcoded devicetree that indicates one hart. + * This board currently uses a hardcoded devicetree that indicates five harts. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -26,6 +26,7 @@ */ #include "qemu/osdep.h" +#include "qemu/cutils.h" #include "qemu/log.h" #include "qemu/error-report.h" #include "qapi/error.h" @@ -117,7 +118,10 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", SIFIVE_U_CLOCK_FREQ); - qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); + /* cpu 0 is the management hart that does not have mmu */ + if (cpu != 0) { + qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); + } qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); @@ -157,15 +161,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, g_free(nodename); plic_phandle = phandle++; - cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); + cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4 - 2); for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { nodename = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); - cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); - cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); - cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); - cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); + /* cpu 0 is the management hart that does not have S-mode */ + if (cpu == 0) { + cells[0] = cpu_to_be32(intc_phandle); + cells[1] = cpu_to_be32(IRQ_M_EXT); + } else { + cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); + cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); + cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); + cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); + } g_free(nodename); } nodename = g_strdup_printf("/soc/interrupt-controller@%lx", @@ -315,10 +325,16 @@ static void riscv_sifive_u_soc_init(Object *obj) { MachineState *ms = MACHINE(qdev_get_machine()); SiFiveUSoCState *s = RISCV_U_SOC(obj); + char cpu_type[64]; + + /* create cpu type representing SiFive FU540 SoC */ + pstrcpy(cpu_type, sizeof(cpu_type), SIFIVE_E_CPU); + pstrcat(cpu_type, sizeof(cpu_type), ","); + pstrcat(cpu_type, sizeof(cpu_type), SIFIVE_U_CPU); object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, &error_abort, NULL); - object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type", + object_property_set_str(OBJECT(&s->cpus), cpu_type, "cpu-type", &error_abort); object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", &error_abort); @@ -407,10 +423,11 @@ static void riscv_sifive_u_machine_init(MachineClass *mc) { mc->desc = "RISC-V Board compatible with SiFive U SDK"; mc->init = riscv_sifive_u_init; - /* The real hardware has 5 CPUs, but one of them is a small embedded power + /* + * The real hardware has 5 CPUs, but one of them is a small embedded power * management CPU. */ - mc->max_cpus = 4; + mc->max_cpus = 5; } DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) From patchwork Mon Aug 5 16:00:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077249 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E7A7F1398 for ; Mon, 5 Aug 2019 16:02:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D910A22A65 for ; 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X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 07/28] riscv: sifive_u: Set the minimum number of cpus to 2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP It is not useful if we only have one management CPU. Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 08d406f..206eccc 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -428,6 +428,8 @@ static void riscv_sifive_u_machine_init(MachineClass *mc) * management CPU. */ mc->max_cpus = 5; + /* It is not useful if we only have one management CPU */ + mc->min_cpus = 2; } DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) From patchwork Mon Aug 5 16:00:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077277 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AF1E71398 for ; Mon, 5 Aug 2019 16:04:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9E3642094F for ; Mon, 5 Aug 2019 16:04:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 91CE428711; Mon, 5 Aug 2019 16:04:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2C2B02094F for ; Mon, 5 Aug 2019 16:04:33 +0000 (UTC) Received: from localhost ([::1]:55510 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hufTM-0006Zh-Fz for patchwork-qemu-devel@patchwork.kernel.org; Mon, 05 Aug 2019 12:04:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58352) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hufPb-0000HI-1q for qemu-devel@nongnu.org; Mon, 05 Aug 2019 12:00:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hufPZ-0002qX-Vq for qemu-devel@nongnu.org; Mon, 05 Aug 2019 12:00:38 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:34067) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hufPZ-0002pl-Nw; Mon, 05 Aug 2019 12:00:37 -0400 Received: by mail-pg1-x544.google.com with SMTP id n9so33750183pgc.1; Mon, 05 Aug 2019 09:00:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=HmEOrQlPGOd0Y81l931aXbkGZtqwGBdfoUEd2ZirFRk=; b=fAG6hGCDvp2ioiFiIdPyhLs4odrCu2Mi2EaultibP5/mzhilRx7U/DzeeYYshpm/F1 Wr2lFsHZSevZ36xGMJObEhM41jYxM6uVrHOp6mvH5WoUE8dk6etDdjY7hhi0RmqVJ+Vg 1cEB1rYHvGJDdJfU7PouLCwrI8XQmERQ/w/el3aohxL9yQcxCwRVrHqkueMeTxZgvszV jLXO1rHYKNCkRUe7Ws9eCsYw2n4WgGe8RMdw9guunlJUb0fdKS3+uEjXpDkhblIM4eUJ ZGh8+UL31VLym6+gAHPXW85OLr0I2OhCe1x1SdGMvfB/UrZ61YpgLNGwTc1xucy4w4nr SBLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=HmEOrQlPGOd0Y81l931aXbkGZtqwGBdfoUEd2ZirFRk=; b=euLhq9F9QLwa/O2FvsjCgg5TMtezzBfyz2fsWLh450XJxqZQqJpUJNO45mxOb12bdJ rMoBp7o9VtIikx1FArS6Qp8gy9WEtZbQDVVVsnzuYML081qBe2EbeNhi2yV+mZEUVQOn BYavK88CRjBK8g4R5aaNMFb0WfX9DgPQrg1vPlhFI9wRZFOLtMwGACO0tYKUf4ARZbll lARJY+dgic99ZchZFZRMZDbG13HdLL2DrQwKaPJdgdgIJSNUi51DEk3IXA4U8C3U5tgi GlIZsfEC9anAX9N+wMyhiudkxu3ZuctfQl/tUJ424QcSmAnwRvxRBHWPnnrv+OiHNE/S Rvyg== X-Gm-Message-State: APjAAAUUtlt47ef77y14bGVtGXUKMFXt+0OeWQ9agcHyVpYUUeertXw+ ZW0Il6aucy5aFuIp+Zols68= X-Google-Smtp-Source: APXvYqznoOYCYswgx1X853oPmpSslnBBUugTuEj9/BjbAHgLRFlkUEXCcSEZ/zxCB+TllwWx3QAo0Q== X-Received: by 2002:aa7:9afc:: with SMTP id y28mr72451044pfp.252.1565020836907; Mon, 05 Aug 2019 09:00:36 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. 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X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH 08/28] riscv: sifive_u: Update PLIC hart topology configuration string X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP With heterogeneous harts config, the PLIC hart topology configuration string are "M,MS,.." because of the monitor hart #0. Suggested-by: Fabien Chouteau Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/sifive_u.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 206eccc..b235f29 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -372,10 +372,11 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) plic_hart_config = g_malloc0(plic_hart_config_len); for (i = 0; i < ms->smp.cpus; i++) { if (i != 0) { - strncat(plic_hart_config, ",", plic_hart_config_len); + strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG, + plic_hart_config_len); + } else { + strncat(plic_hart_config, "M", plic_hart_config_len); } - strncat(plic_hart_config, SIFIVE_U_PLIC_HART_CONFIG, - plic_hart_config_len); plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); } From patchwork Mon Aug 5 16:00:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077285 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BB2251398 for ; Mon, 5 Aug 2019 16:06:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A829D286C0 for ; Mon, 5 Aug 2019 16:06:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9A2E8286D5; Mon, 5 Aug 2019 16:06:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 54F5C286C0 for ; Mon, 5 Aug 2019 16:06:29 +0000 (UTC) Received: from localhost ([::1]:55570 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hufVE-0001kB-N1 for patchwork-qemu-devel@patchwork.kernel.org; Mon, 05 Aug 2019 12:06:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58373) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hufPb-0000Jx-Pd for qemu-devel@nongnu.org; Mon, 05 Aug 2019 12:00:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hufPa-0002rJ-Qx for qemu-devel@nongnu.org; Mon, 05 Aug 2019 12:00:39 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:41882) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hufPa-0002qe-L7; Mon, 05 Aug 2019 12:00:38 -0400 Received: by mail-pf1-x441.google.com with SMTP id m30so39884295pff.8; Mon, 05 Aug 2019 09:00:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=4njfrOWQQMyLEX/rfHOtnIEzjwmjoWXLAc2Ndz0IW6c=; b=bkSpI3/5lKu6DEO+/4bYFMyPoc/GWN6bwf2h7On0Tpvl/beL252Tglz+hZtX/FHj5n OWfIHvPHALcGGaGmFSDSRQlKI6kCB7J7eyKz9mMLUjk4EbLfpnrneFtsUGoqLU0Hv1gm 7O9sbjgF8rO22e4+D7aL+qh8c108Bcz8aagxGAiyf+rPiyqudQrKgBP/xuaBnDTL/uTz mMAdoKUCUfyUfnGsMKU6JIq354IyA/RLm4U8k/7PWroBSPjnbL86f3/K22Ha3MGO3Get U+qXZf35wOeE3HAauh3Ro9DcyaJsyMU3/KXZI3lCAi5EFV0Wm1coegIgZnB3ITMiWooO lleg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=4njfrOWQQMyLEX/rfHOtnIEzjwmjoWXLAc2Ndz0IW6c=; b=j3XmeHigaZR6w4ve0/XkBThfuvnEg2NEy0221VvxM71sgZ4QxFciPre0/TRkwD+JSg nQfVc3+0YBVTtuC59mWj3Kff7B+pvytBiexpKATZpqj5+rcr3hy/SAHuJanGhN4QUx/O FOhZzq7etfVokXB2r83dTTplcOcTiEC3Jfe53p1aAj5+aSSt75FZ+7keqkJJxTGw+Em3 +3qtKz+hfgP2XBPTaey7Rd4ICUgOucAgqd5JMlnrIKpdxcwNlI/sfS7sN7W8mi/I0W9f 2OrVIwVsKqwJJ6Xz9CIxCdc+7wo9GGlMoRxcDOUhEdtaH62YU6Xp1YMJNaVapzC+Q/kj aBTw== X-Gm-Message-State: APjAAAV1BR5dvG6pxI5Ug0zi0DRyd9CqqRSqvsbeoRQbE2My3R3Qv4ic DWLW+8u2NhrWnk/Ci33P4c4= X-Google-Smtp-Source: APXvYqzKpcUeJFDxc35XZPwJ9AmRY4g0sH7xbrazO60YoJYAFLsrq39tnRsk97uzg0ZwXX+ctoeOOA== X-Received: by 2002:aa7:97aa:: with SMTP id d10mr55989869pfq.176.1565020837917; Mon, 05 Aug 2019 09:00:37 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.36 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:37 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 09:00:04 -0700 Message-Id: <1565020823-24223-10-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 09/28] riscv: sifive_u: Update UART base addresses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This updates the UART base address to match the hardware. Signed-off-by: Bin Meng Reviewed-by: Jonathan Behrens Acked-by: Alistair Francis --- hw/riscv/sifive_u.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index b235f29..9f05e09 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -60,8 +60,8 @@ static const struct MemmapEntry { [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, - [SIFIVE_U_UART0] = { 0x10013000, 0x1000 }, - [SIFIVE_U_UART1] = { 0x10023000, 0x1000 }, + [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, + [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, }; From patchwork Mon Aug 5 16:00:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077315 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 793A31398 for ; Mon, 5 Aug 2019 16:10:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6A5C7287DE for ; Mon, 5 Aug 2019 16:10:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5F30D28784; Mon, 5 Aug 2019 16:10:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1016728784 for ; Mon, 5 Aug 2019 16:10:55 +0000 (UTC) Received: from localhost ([::1]:55696 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hufZX-0006Up-9J for patchwork-qemu-devel@patchwork.kernel.org; Mon, 05 Aug 2019 12:10:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58401) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hufPc-0000Nr-U0 for qemu-devel@nongnu.org; Mon, 05 Aug 2019 12:00:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hufPb-0002sm-Sl for qemu-devel@nongnu.org; Mon, 05 Aug 2019 12:00:40 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:35138) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hufPb-0002rc-N9; Mon, 05 Aug 2019 12:00:39 -0400 Received: by mail-pf1-x444.google.com with SMTP id u14so39891751pfn.2; Mon, 05 Aug 2019 09:00:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=3wJXWQ4rYrs4QifmuLTPSjf8nx5Jdl28hrkDefUABYs=; b=jmLjBTZQ3+JJm2EYCK+LVoog+gYFbeMu/zRnUVncwCZtgtCvicuWNU7ylp2QyIViod 4YhUURCpJRMmY8CqqRXsrQvhfZIVgKXdkl+IVtf/32xYwruOsBg0vSA0DNCT5NqN7KhA l+pVQa/dnwO5VFW3hvaxc+CpDsYFhuwIko6Br+XhyQO/Fx/QJeEwsw/SywYT01abP1DT AFF128l7uvZx5WC8JkawtUm2GHQsoF/6b+p+DKZKQOVXpa0y8iRU6LpAhFwdXdbi0kB8 K4Rb/O/FPQmr3E/CnFuVKQ5Qt0lPliKF1FqKILv9nPQyQjA4H2CJHuUCb3154xiMz+aB 2Ldw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=3wJXWQ4rYrs4QifmuLTPSjf8nx5Jdl28hrkDefUABYs=; b=otoZ1CthojBUxVazBsoZUqohKqpEQo478U4qFUcKAY1Gcp6rNG9ZAKvhWcOdoLcwTt X3OErgBUthTptS52X4r6iHeXcezF58rd4T3HsICgkLI8SwDafvKB6ujzEM3TDtj1+R8J 1+qDnd/VxB9jMibiOqx+7qBYAZmkU2Yj70G0jxfLn05SYSvZm30HNbopREhjWbpAc3Pk RAkceD5SwNdZNn1PpARUCT1q46tcb2UsFAGzJjR1zxZOcFdyeaNVicpi3jHI1K9OvOZX IwTMWpP9JjSMNkgYAOFoevVhw1BHMys9fotrHZOBNhpp3RwljetlnW6WYTUjSRZ6O0BA 1gQg== X-Gm-Message-State: APjAAAVdzvsfwfJf7SmkB1AoqQ3aXfkp/VRk8skGA/etnUEI1WaK7/n0 Aj8Yfv0tB7zf8fOe1J1P8SY= X-Google-Smtp-Source: APXvYqwpsaopFxMhvQZbgHUsQ0wY20Q5+xQnWkOyujLR2jFqc4XNG++bBQZgVmOQdol7h4MDS+IZFQ== X-Received: by 2002:aa7:8b11:: with SMTP id f17mr73792043pfd.19.1565020838921; Mon, 05 Aug 2019 09:00:38 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.37 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:38 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 09:00:05 -0700 Message-Id: <1565020823-24223-11-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 10/28] riscv: sifive_u: Remove the unnecessary include of prci header X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP sifive_u machine does not use PRCI as of today. Remove the prci header inclusion. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/sifive_u.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9f05e09..dfcb525 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -40,7 +40,6 @@ #include "hw/riscv/sifive_plic.h" #include "hw/riscv/sifive_clint.h" #include "hw/riscv/sifive_uart.h" -#include "hw/riscv/sifive_prci.h" #include "hw/riscv/sifive_u.h" #include "hw/riscv/boot.h" #include "chardev/char.h" From patchwork Mon Aug 5 16:00:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077287 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 74EEB1398 for ; Mon, 5 Aug 2019 16:06:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 64EAB28711 for ; Mon, 5 Aug 2019 16:06:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 591FC28787; Mon, 5 Aug 2019 16:06:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 93ACF28711 for ; Mon, 5 Aug 2019 16:06:55 +0000 (UTC) Received: from localhost ([::1]:55576 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hufVe-0003Et-TI for patchwork-qemu-devel@patchwork.kernel.org; Mon, 05 Aug 2019 12:06:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58438) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hufPe-0000TA-HV for qemu-devel@nongnu.org; Mon, 05 Aug 2019 12:00:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hufPc-0002ty-UC for qemu-devel@nongnu.org; Mon, 05 Aug 2019 12:00:42 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:35738) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hufPc-0002t8-O4; Mon, 05 Aug 2019 12:00:40 -0400 Received: by mail-pg1-x542.google.com with SMTP id n4so4697513pgv.2; Mon, 05 Aug 2019 09:00:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=T4gWEqheZIhtcDwxIpXs5RA7DpA9pCq5dzxWFGrTfvE=; b=UyLp9KQfc/MVd4gsQy4vQYKIvfuBYhFDD5SzWi9VvUKcqsAKoV7bsfNbynpx8m8gb/ sbJCaH6iCAX8mqwm5Ce5V6VLEHm7Jj6dWxhCYqjstuhNm59jDucdVTduVroK9/JYSXj1 7rooElJNMeHtLwNkOSF88XzqYS6gB0jy0z2Hl6FnA98eW58qlCc9m7DCWjoy63lytGij 7//n9WBF+Tg+xRV3SWPYI/6tdH6pTjdtl7ZFDMWxt/om9zAvrGI5G9sgq8a73YHkO32W mNzGkybt7iHtnyCP4SSmtrcCGnuJTpDgt5TqaQvkgaxkJLdgxP4VANGjuV5gd3DBsBYz Pvvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=T4gWEqheZIhtcDwxIpXs5RA7DpA9pCq5dzxWFGrTfvE=; b=UAQF18jqd45sEi8zYSx5kz2Dh2NK+CYXN2bbAbdokafuNXBraPebwsR3rt79KY+BzF Mcp9HQDvJZSF/XCwPvu9FY7xfSJp3mKP0fp3tCrFwuU8KzCecHLOZ00ULEPZpCkp4uOh aZRJzN8KGcNzWKk3ppmVaKB6jS4dXwkEQaX1Spv+OHZHhTTdhl26ZoLgUjACIjMXNKIY rHdJEdfsRbKTae9w1v6F+PFk3L/Tcxj1Ss+Km5DUIzA/rOsDNjWw01VuZq1tEOVMPpFF dhGFPIzkoJ3tAj8DbsCMS89ot4K0cvN/rDnPLCR4KW4MrYiqPDb7vM6FUV/wJrazj8og aSrg== X-Gm-Message-State: APjAAAWgkbdfxWCBqaL/sW7DCuyjGZcril5cjM+IBnkm1T0PetYi/RKc zvBkKcULI76L02+HF0fq92w= X-Google-Smtp-Source: APXvYqwud1n6taQWJ0ssBASDFSWWp4uz+YLNBEIR1h7PwAeGjNcPNxrij3yUYCICq9uJ5F4x0Fw2Bg== X-Received: by 2002:a62:e315:: with SMTP id g21mr75883388pfh.225.1565020839923; Mon, 05 Aug 2019 09:00:39 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.38 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:39 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 09:00:06 -0700 Message-Id: <1565020823-24223-12-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Current SiFive PRCI model only works with sifive_e machine, as it only emulates registers or PRCI block in the FE310 SoC. Rename the file name to make it clear that it is for sifive_e. Signed-off-by: Bin Meng --- hw/riscv/Makefile.objs | 2 +- hw/riscv/sifive_e.c | 4 ++-- hw/riscv/{sifive_prci.c => sifive_e_prci.c} | 14 +++++++------- include/hw/riscv/{sifive_prci.h => sifive_e_prci.h} | 14 +++++++------- 4 files changed, 17 insertions(+), 17 deletions(-) rename hw/riscv/{sifive_prci.c => sifive_e_prci.c} (90%) rename include/hw/riscv/{sifive_prci.h => sifive_e_prci.h} (82%) diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs index eb9d4f9..c859697 100644 --- a/hw/riscv/Makefile.objs +++ b/hw/riscv/Makefile.objs @@ -2,9 +2,9 @@ obj-y += boot.o obj-$(CONFIG_SPIKE) += riscv_htif.o obj-$(CONFIG_HART) += riscv_hart.o obj-$(CONFIG_SIFIVE_E) += sifive_e.o +obj-$(CONFIG_SIFIVE_E) += sifive_e_prci.o obj-$(CONFIG_SIFIVE) += sifive_clint.o obj-$(CONFIG_SIFIVE) += sifive_gpio.o -obj-$(CONFIG_SIFIVE) += sifive_prci.o obj-$(CONFIG_SIFIVE) += sifive_plic.o obj-$(CONFIG_SIFIVE) += sifive_test.o obj-$(CONFIG_SIFIVE_U) += sifive_u.o diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 2a499d8..2d67670 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -41,9 +41,9 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_plic.h" #include "hw/riscv/sifive_clint.h" -#include "hw/riscv/sifive_prci.h" #include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_e.h" +#include "hw/riscv/sifive_e_prci.h" #include "hw/riscv/boot.h" #include "chardev/char.h" #include "sysemu/arch_init.h" @@ -174,7 +174,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon", memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); - sifive_prci_create(memmap[SIFIVE_E_PRCI].base); + sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base); /* GPIO */ diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_e_prci.c similarity index 90% rename from hw/riscv/sifive_prci.c rename to hw/riscv/sifive_e_prci.c index f406682..acb914d 100644 --- a/hw/riscv/sifive_prci.c +++ b/hw/riscv/sifive_e_prci.c @@ -1,5 +1,5 @@ /* - * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) + * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) * * Copyright (c) 2017 SiFive, Inc. * @@ -22,7 +22,7 @@ #include "hw/sysbus.h" #include "qemu/module.h" #include "target/riscv/cpu.h" -#include "hw/riscv/sifive_prci.h" +#include "hw/riscv/sifive_e_prci.h" static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size) { @@ -82,10 +82,10 @@ static const MemoryRegionOps sifive_prci_ops = { static void sifive_prci_init(Object *obj) { - SiFivePRCIState *s = SIFIVE_PRCI(obj); + SiFivePRCIState *s = SIFIVE_E_PRCI(obj); memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s, - TYPE_SIFIVE_PRCI, 0x8000); + TYPE_SIFIVE_E_PRCI, 0x8000); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN); @@ -97,7 +97,7 @@ static void sifive_prci_init(Object *obj) } static const TypeInfo sifive_prci_info = { - .name = TYPE_SIFIVE_PRCI, + .name = TYPE_SIFIVE_E_PRCI, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(SiFivePRCIState), .instance_init = sifive_prci_init, @@ -114,9 +114,9 @@ type_init(sifive_prci_register_types) /* * Create PRCI device. */ -DeviceState *sifive_prci_create(hwaddr addr) +DeviceState *sifive_e_prci_create(hwaddr addr) { - DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_PRCI); + DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_E_PRCI); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); return dev; diff --git a/include/hw/riscv/sifive_prci.h b/include/hw/riscv/sifive_e_prci.h similarity index 82% rename from include/hw/riscv/sifive_prci.h rename to include/hw/riscv/sifive_e_prci.h index bd51c4a..7932fe7 100644 --- a/include/hw/riscv/sifive_prci.h +++ b/include/hw/riscv/sifive_e_prci.h @@ -1,5 +1,5 @@ /* - * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) interface + * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) interface * * Copyright (c) 2017 SiFive, Inc. * @@ -16,8 +16,8 @@ * this program. If not, see . */ -#ifndef HW_SIFIVE_PRCI_H -#define HW_SIFIVE_PRCI_H +#ifndef HW_SIFIVE_E_PRCI_H +#define HW_SIFIVE_E_PRCI_H enum { SIFIVE_PRCI_HFROSCCFG = 0x0, @@ -47,10 +47,10 @@ enum { SIFIVE_PRCI_PLLOUTDIV_DIV1 = (1 << 8) }; -#define TYPE_SIFIVE_PRCI "riscv.sifive.prci" +#define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci" -#define SIFIVE_PRCI(obj) \ - OBJECT_CHECK(SiFivePRCIState, (obj), TYPE_SIFIVE_PRCI) +#define SIFIVE_E_PRCI(obj) \ + OBJECT_CHECK(SiFivePRCIState, (obj), TYPE_SIFIVE_E_PRCI) typedef struct SiFivePRCIState { /*< private >*/ @@ -64,6 +64,6 @@ typedef struct SiFivePRCIState { uint32_t plloutdiv; } SiFivePRCIState; -DeviceState *sifive_prci_create(hwaddr addr); +DeviceState *sifive_e_prci_create(hwaddr addr); #endif From patchwork Mon Aug 5 16:00:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077293 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 07FC71398 for ; Mon, 5 Aug 2019 16:07:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EB0DC286C0 for ; Mon, 5 Aug 2019 16:07:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DFDEF28711; Mon, 5 Aug 2019 16:07:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9A7D1286C0 for ; Mon, 5 Aug 2019 16:07:34 +0000 (UTC) Received: from localhost ([::1]:55600 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hufWI-0005Fa-0a for patchwork-qemu-devel@patchwork.kernel.org; Mon, 05 Aug 2019 12:07:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58443) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hufPe-0000To-T1 for qemu-devel@nongnu.org; Mon, 05 Aug 2019 12:00:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hufPd-0002v0-SF for qemu-devel@nongnu.org; Mon, 05 Aug 2019 12:00:42 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:43800) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hufPd-0002uX-MR; Mon, 05 Aug 2019 12:00:41 -0400 Received: by mail-pf1-x443.google.com with SMTP id i189so39874716pfg.10; Mon, 05 Aug 2019 09:00:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=8KdynR/OjUZU1xuClc8qRK6ENODt1avb+04qYHb5Ais=; b=r+QG7KhU9pUTlFRQUDkVP+nzR/m4yzx8Tfmh9Kvg8MJTb8stSBpsGGLHhc9fAd7yiF TuNupfpcdN7XscrV0UL/eCTyX/lAjyiuV08SETsI0rRpblleab1ilY3tlOV2NTDirv2y jBefWKJSDeWMMFU8PODfNL6Z1t76CZ/kjNLayApBKaNVmo+F26H4No1V23Ez2grFgJYN MNcLcWcP/cljYyRiu7Lv6F4lMYIz0FvsicLjrZOidVRDXdY200ARIlNeWPElvaUL2868 VQPAlFm6OYZovXWCxuBlKWrDf/ncNWK3pBpoYJL6QLjXuJQ9UuaMxR1pl3NEpO3zlPcV OUJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=8KdynR/OjUZU1xuClc8qRK6ENODt1avb+04qYHb5Ais=; b=TW3OSFb8XL0SNgqC5imhhpk85tfULK/5A9quKb6oJLnlqfsQQ55AmjHlwsBHo0Nc3F ZGvMnIVkUDGlRS8om5StYsw6cyz6+s2nCgiJoTBcl6PGFcK2kMGUufv2q0ucTm5sFfT6 dvv1TNOeSkKDqI51Xsiu74LiaDuDvCW9MR70cZXCsY75pP1boNgHHN3CXwyv4XBeyIF/ f7+D6SSrzE3WbCh7FiZ5AiD+HQr4MgDbeJ8TiS1PjE2hUNclO6t+pN//rcIDmz8DfI8B mnKZ4aA0Jn3tXTujVl0Qej6s4ulMqEfMXyEFgoeaP4zDzhjYPPi0NiR9PnJIHqHMOZyg oYlg== X-Gm-Message-State: APjAAAV6dsjwWkeS6asE8OBBU9Y/r/VIIBJHs+wH0Rw8V+WlaLQEC9Ll bkzCyMbN1Az09b7QNaTE7Lw= X-Google-Smtp-Source: APXvYqxviVTKIE4ikfxTz2ujZ++l8mcu2A1BRqTlQeIvxq8U8AOKutPEzb/d7G+PD9e54TQYAWiN/g== X-Received: by 2002:aa7:8218:: with SMTP id k24mr71035655pfi.221.1565020840983; Mon, 05 Aug 2019 09:00:40 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.39 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:40 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 09:00:07 -0700 Message-Id: <1565020823-24223-13-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP It should use SIFIVE_PRCI_HFXOSCCFG_RDY and SIFIVE_PRCI_HFXOSCCFG_EN for hfxosccfg register programming. Signed-off-by: Bin Meng Acked-by: Alistair Francis --- hw/riscv/sifive_e_prci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c index acb914d..c906f11 100644 --- a/hw/riscv/sifive_e_prci.c +++ b/hw/riscv/sifive_e_prci.c @@ -89,7 +89,7 @@ static void sifive_prci_init(Object *obj) sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN); - s->hfxosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN); + s->hfxosccfg = (SIFIVE_PRCI_HFXOSCCFG_RDY | SIFIVE_PRCI_HFXOSCCFG_EN); s->pllcfg = (SIFIVE_PRCI_PLLCFG_REFSEL | SIFIVE_PRCI_PLLCFG_BYPASS | SIFIVE_PRCI_PLLCFG_LOCK); s->plloutdiv = SIFIVE_PRCI_PLLOUTDIV_DIV1; From patchwork Mon Aug 5 16:00:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077295 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D78E514E5 for ; Mon, 5 Aug 2019 16:07:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C73B4286C7 for ; Mon, 5 Aug 2019 16:07:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BB8DF28711; Mon, 5 Aug 2019 16:07:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 64109286C7 for ; Mon, 5 Aug 2019 16:07:59 +0000 (UTC) Received: from localhost ([::1]:55606 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hufWg-0006ZQ-Of for patchwork-qemu-devel@patchwork.kernel.org; Mon, 05 Aug 2019 12:07:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58466) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hufPg-0000Wz-3J for qemu-devel@nongnu.org; Mon, 05 Aug 2019 12:00:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hufPf-0002vp-1M for qemu-devel@nongnu.org; Mon, 05 Aug 2019 12:00:44 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:42400) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hufPe-0002vN-R7; Mon, 05 Aug 2019 12:00:42 -0400 Received: by mail-pf1-x442.google.com with SMTP id q10so39857884pff.9; Mon, 05 Aug 2019 09:00:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=2MH7twmDJfeZRj3jUDtzUjwhHh0CGkZ/MkdqWVYWSCk=; b=YkT290T2q3RvuBJ0Z7qI2GlKYk5/YpRjrDAZJh6xeEbrIktmwrwvR4Bw1tLeXXfhnQ SWmJ4I1pgxElDSBQqI90YBeuN3mGAwE2TFJh1X1Mc7/1ZPT8YtdD6h6Ej1KehgD+AkGe kKSQ5jlDOKh5Mr1Ft3b8RXwnYXYzkr5UUrlgRPXih22WFrEE3FAbxC7EPQcYaeuoLQnY gZHZ/qTiTeMB/VrMZ7gZqoqEU45lmTie6npo8+MOFn3TP2D+mDQyrXbb2o/R6Fyy7KZ/ IOD59y3lXH9JxU3gM0viOhbSaD62yO2eXFFsvv4Lmt0vEgcxIi8FVEBllkmdkLii8pqy uwTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=2MH7twmDJfeZRj3jUDtzUjwhHh0CGkZ/MkdqWVYWSCk=; b=mJEaoE/v1QGNEPAz/aw0UPA0ZB4MVqADIkGQDUJrTpaShjtKUHqXaEGlE27lptH95K SwFbD/eVEBjTJ+7nmg2dV8htlDLRhRM1edsws30DlUbOXDz9Fhc+Bjv2nJv/3vR3fZTy zlytWWo+ov0sUZM23ZoPk9yGsum2mKRbuEDqMhV4fryMG5Jz7RgBgAZJbxx86Afx2uSK GVPBHN7nH8j0ilqPTLnmOZe6i724B7m9/sl7LyP/B7PN1NZYwtZEtpsS83QIE53D7AgI xD0eJWvekh9DKc42a76vH+AZBuEuG8FcA+YGoGY3fNQV4N7KI82o0aTXYVycz5CjDjTl ykJQ== X-Gm-Message-State: APjAAAW5J4Q0Uw/BWgtHqkgecTIVxYUINtYlhm/43wUmM2GBVNCMw707 bBLCyk/YsjfJVAQ6Zjv8re4= X-Google-Smtp-Source: APXvYqzLAlbXmRq6+RKapxCcfKnpTpATB3orDKl8rPmPdXLfzjaBEGJRkfmpQYft+L7BQKbqsX83jg== X-Received: by 2002:a62:79c2:: with SMTP id u185mr74960737pfc.237.1565020841964; Mon, 05 Aug 2019 09:00:41 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.41 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:41 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 09:00:08 -0700 Message-Id: <1565020823-24223-14-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 13/28] riscv: sifive_e: prci: Update the PRCI register block size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Currently the PRCI register block size is set to 0x8000, but in fact 0x1000 is enough, which is also what the manual says. Signed-off-by: Bin Meng --- hw/riscv/sifive_e_prci.c | 2 +- include/hw/riscv/sifive_e_prci.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c index c906f11..4cbce48 100644 --- a/hw/riscv/sifive_e_prci.c +++ b/hw/riscv/sifive_e_prci.c @@ -85,7 +85,7 @@ static void sifive_prci_init(Object *obj) SiFivePRCIState *s = SIFIVE_E_PRCI(obj); memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s, - TYPE_SIFIVE_E_PRCI, 0x8000); + TYPE_SIFIVE_E_PRCI, SIFIVE_E_PRCI_REG_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN); diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/riscv/sifive_e_prci.h index 7932fe7..81e506b 100644 --- a/include/hw/riscv/sifive_e_prci.h +++ b/include/hw/riscv/sifive_e_prci.h @@ -47,6 +47,8 @@ enum { SIFIVE_PRCI_PLLOUTDIV_DIV1 = (1 << 8) }; +#define SIFIVE_E_PRCI_REG_SIZE 0x1000 + #define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci" #define SIFIVE_E_PRCI(obj) \ From patchwork Mon Aug 5 16:00:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077313 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 174EB14E5 for ; Mon, 5 Aug 2019 16:10:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0758628803 for ; Mon, 5 Aug 2019 16:10:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EF5AD28818; Mon, 5 Aug 2019 16:10:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3502B2882A for ; Mon, 5 Aug 2019 16:10:28 +0000 (UTC) Received: from localhost ([::1]:55666 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hufZ5-000599-J4 for patchwork-qemu-devel@patchwork.kernel.org; Mon, 05 Aug 2019 12:10:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58505) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hufPi-0000d9-6T for qemu-devel@nongnu.org; Mon, 05 Aug 2019 12:00:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hufPg-0002wd-87 for qemu-devel@nongnu.org; Mon, 05 Aug 2019 12:00:46 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:37449) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hufPg-0002w9-0c; Mon, 05 Aug 2019 12:00:44 -0400 Received: by mail-pg1-x543.google.com with SMTP id d1so7152278pgp.4; Mon, 05 Aug 2019 09:00:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=LXiUaj0rKNY+QE8v0jzf1Ot10uVD5oH+gvpbKkbiZso=; b=bwiLiozb+mQYv1KY7A/EuyBveZFWNOvUEwl3EmAEYFylQhdZ8akVYdP4G4Bku3XXT9 MN8NiMb9muXAow96cAsgAuzWgBOzrl+iHuf+lEK1n4oJ/I5hJVkjFTNIViDIKxKM56Kd W+naZLaqTFF0wkRYMKiqThJ1sTNbMCjURIOr/+PTQf0GGr+f8NlZywG3ROxC5FxhJEqa bIV9MHegGS8kxOOjkxruIi/O2pZ07t1Z48oMikAjxq/QdS4LuPhREm+PjlWUn0abzeTI /KtLYfUtmcaJR5YYllcQ8CrbxixWwjxyWnPDeFJ1k4pRWS7NMsj4CKPXZasH3adrNDjf XfUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=LXiUaj0rKNY+QE8v0jzf1Ot10uVD5oH+gvpbKkbiZso=; b=orzsQLualGYsp3WGd2Ye/+/XsEmxw9w3WkZGrcYndf/yqWX6OCk29+MvxQ0KmSdL6t ktzDMGXy4zBxu5x3cZjqsIAl9Bu+vYXj9+cAH4QoSguA9fa6cAbvDETuzEVghWMD5ZxE 7MuoDWhzz2wgdVkFIB0tMrXxNRb0e80/Pe1LVgiIrrUg9T50Ed9A63nRkVgfqOhgWdTR EzrrNSIFAdMXw8kn42m8RjeDuKBPONxc06OhDHVQGVOO1NfZ2Xrm+Ho0f8gOwY6nfCtv tRHUdqFp3PxAgNJi0eGJ1t0Le9Mfvl5WPiYcs96z5v3tkzNSkxvfc7hYy1rB0khd+lLX lZWA== X-Gm-Message-State: APjAAAVTau1J/cPkO+jtYb6DCYBtBEzOzcqVZLjPkCxgkba8GmoViHHi df57TyO5RtxtGIIJu6FfFUc= X-Google-Smtp-Source: APXvYqz+Snvo3aVCyaLAAi69xeyRkqcPg9Y1p+40nyyCYN7cB+BxH2M6GyYfwDYFjwHbzr5opST3Kg== X-Received: by 2002:a65:64c6:: with SMTP id t6mr139994810pgv.323.1565020843084; Mon, 05 Aug 2019 09:00:43 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.41 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:42 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 09:00:09 -0700 Message-Id: <1565020823-24223-15-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 14/28] riscv: sifive: Implement PRCI model for FU540 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This adds a simple PRCI model for FU540 (sifive_u). It has different register layout from the existing PRCI model for FE310 (sifive_e). Signed-off-by: Bin Meng --- hw/riscv/Makefile.objs | 1 + hw/riscv/sifive_u_prci.c | 163 +++++++++++++++++++++++++++++++++++++++ include/hw/riscv/sifive_u_prci.h | 90 +++++++++++++++++++++ 3 files changed, 254 insertions(+) create mode 100644 hw/riscv/sifive_u_prci.c create mode 100644 include/hw/riscv/sifive_u_prci.h diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs index c859697..b95bbd5 100644 --- a/hw/riscv/Makefile.objs +++ b/hw/riscv/Makefile.objs @@ -8,6 +8,7 @@ obj-$(CONFIG_SIFIVE) += sifive_gpio.o obj-$(CONFIG_SIFIVE) += sifive_plic.o obj-$(CONFIG_SIFIVE) += sifive_test.o obj-$(CONFIG_SIFIVE_U) += sifive_u.o +obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o obj-$(CONFIG_SIFIVE) += sifive_uart.o obj-$(CONFIG_SPIKE) += spike.o obj-$(CONFIG_RISCV_VIRT) += virt.o diff --git a/hw/riscv/sifive_u_prci.c b/hw/riscv/sifive_u_prci.c new file mode 100644 index 0000000..35e5962 --- /dev/null +++ b/hw/riscv/sifive_u_prci.c @@ -0,0 +1,163 @@ +/* + * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt) + * + * Copyright (c) 2019 Bin Meng + * + * Simple model of the PRCI to emulate register reads made by the SDK BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "qemu/module.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/sifive_u_prci.h" + +static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size) +{ + SiFivePRCIState *s = opaque; + + switch (addr) { + case SIFIVE_PRCI_HFXOSCCFG: + return s->hfxosccfg; + case SIFIVE_PRCI_COREPLLCFG0: + return s->corepllcfg0; + case SIFIVE_PRCI_DDRPLLCFG0: + return s->ddrpllcfg0; + case SIFIVE_PRCI_DDRPLLCFG1: + return s->ddrpllcfg1; + case SIFIVE_PRCI_GEMGXLPLLCFG0: + return s->gemgxlpllcfg0; + case SIFIVE_PRCI_GEMGXLPLLCFG1: + return s->gemgxlpllcfg1; + case SIFIVE_PRCI_CORECLKSEL: + return s->coreclksel; + case SIFIVE_PRCI_DEVICESRESET: + return s->devicesreset; + case SIFIVE_PRCI_CLKMUXSTATUS: + return s->clkmuxstatus; + } + + hw_error("%s: read: addr=0x%x\n", __func__, (int)addr); + return 0; +} + +static void sifive_prci_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + SiFivePRCIState *s = opaque; + + switch (addr) { + case SIFIVE_PRCI_HFXOSCCFG: + s->hfxosccfg = (uint32_t) val64; + /* OSC stays ready */ + s->hfxosccfg |= SIFIVE_PRCI_HFXOSCCFG_RDY; + break; + case SIFIVE_PRCI_COREPLLCFG0: + s->corepllcfg0 = (uint32_t) val64; + /* internal feedback */ + s->corepllcfg0 |= SIFIVE_PRCI_PLLCFG0_FSE; + /* PLL stays locked */ + s->corepllcfg0 |= SIFIVE_PRCI_PLLCFG0_LOCK; + break; + case SIFIVE_PRCI_DDRPLLCFG0: + s->ddrpllcfg0 = (uint32_t) val64; + /* internal feedback */ + s->ddrpllcfg0 |= SIFIVE_PRCI_PLLCFG0_FSE; + /* PLL stays locked */ + s->ddrpllcfg0 |= SIFIVE_PRCI_PLLCFG0_LOCK; + break; + case SIFIVE_PRCI_DDRPLLCFG1: + s->ddrpllcfg1 = (uint32_t) val64; + break; + case SIFIVE_PRCI_GEMGXLPLLCFG0: + s->gemgxlpllcfg0 = (uint32_t) val64; + /* internal feedback */ + s->gemgxlpllcfg0 |= SIFIVE_PRCI_PLLCFG0_FSE; + /* PLL stays locked */ + s->gemgxlpllcfg0 |= SIFIVE_PRCI_PLLCFG0_LOCK; + break; + case SIFIVE_PRCI_GEMGXLPLLCFG1: + s->gemgxlpllcfg1 = (uint32_t) val64; + break; + case SIFIVE_PRCI_CORECLKSEL: + s->coreclksel = (uint32_t) val64; + break; + case SIFIVE_PRCI_DEVICESRESET: + s->devicesreset = (uint32_t) val64; + break; + case SIFIVE_PRCI_CLKMUXSTATUS: + s->clkmuxstatus = (uint32_t) val64; + break; + default: + hw_error("%s: bad write: addr=0x%x v=0x%x\n", + __func__, (int)addr, (int)val64); + } +} + +static const MemoryRegionOps sifive_prci_ops = { + .read = sifive_prci_read, + .write = sifive_prci_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4 + } +}; + +static void sifive_prci_init(Object *obj) +{ + SiFivePRCIState *s = SIFIVE_U_PRCI(obj); + + memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s, + TYPE_SIFIVE_U_PRCI, SIFIVE_U_PRCI_REG_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + + /* Initialize register to power-on-reset values */ + s->hfxosccfg = (SIFIVE_PRCI_HFXOSCCFG_RDY | SIFIVE_PRCI_HFXOSCCFG_EN); + s->corepllcfg0 = (SIFIVE_PRCI_PLLCFG0_DIVR | SIFIVE_PRCI_PLLCFG0_DIVF | + SIFIVE_PRCI_PLLCFG0_DIVQ | SIFIVE_PRCI_PLLCFG0_FSE | + SIFIVE_PRCI_PLLCFG0_LOCK); + s->ddrpllcfg0 = (SIFIVE_PRCI_PLLCFG0_DIVR | SIFIVE_PRCI_PLLCFG0_DIVF | + SIFIVE_PRCI_PLLCFG0_DIVQ | SIFIVE_PRCI_PLLCFG0_FSE | + SIFIVE_PRCI_PLLCFG0_LOCK); + s->gemgxlpllcfg0 = (SIFIVE_PRCI_PLLCFG0_DIVR | SIFIVE_PRCI_PLLCFG0_DIVF | + SIFIVE_PRCI_PLLCFG0_DIVQ | SIFIVE_PRCI_PLLCFG0_FSE | + SIFIVE_PRCI_PLLCFG0_LOCK); + s->coreclksel = SIFIVE_PRCI_CORECLKSEL_HFCLK; +} + +static const TypeInfo sifive_prci_info = { + .name = TYPE_SIFIVE_U_PRCI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SiFivePRCIState), + .instance_init = sifive_prci_init, +}; + +static void sifive_prci_register_types(void) +{ + type_register_static(&sifive_prci_info); +} + +type_init(sifive_prci_register_types) + + +/* Create PRCI device */ +DeviceState *sifive_u_prci_create(hwaddr addr) +{ + DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_U_PRCI); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + return dev; +} diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/riscv/sifive_u_prci.h new file mode 100644 index 0000000..f3a4656 --- /dev/null +++ b/include/hw/riscv/sifive_u_prci.h @@ -0,0 +1,90 @@ +/* + * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt) interface + * + * Copyright (c) 2019 Bin Meng + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef HW_SIFIVE_U_PRCI_H +#define HW_SIFIVE_U_PRCI_H + +enum { + SIFIVE_PRCI_HFXOSCCFG = 0x00, + SIFIVE_PRCI_COREPLLCFG0 = 0x04, + SIFIVE_PRCI_DDRPLLCFG0 = 0x0C, + SIFIVE_PRCI_DDRPLLCFG1 = 0x10, + SIFIVE_PRCI_GEMGXLPLLCFG0 = 0x1C, + SIFIVE_PRCI_GEMGXLPLLCFG1 = 0x20, + SIFIVE_PRCI_CORECLKSEL = 0x24, + SIFIVE_PRCI_DEVICESRESET = 0x28, + SIFIVE_PRCI_CLKMUXSTATUS = 0x2C +}; + +/* + * Current FU540-C000 manual says ready bit is at bit 29, but + * freedom-u540-c000-bootloader codes (ux00prci.h) says it is at bit 31. + * We have to trust the actual codes that worked. + * + * see https://github.com/sifive/freedom-u540-c000-bootloader + */ +enum { + SIFIVE_PRCI_HFXOSCCFG_EN = (1 << 30), + SIFIVE_PRCI_HFXOSCCFG_RDY = (1 << 31), +}; + +/* xxxPLLCFG0 register bits */ +enum { + SIFIVE_PRCI_PLLCFG0_DIVR = (1 << 0), + SIFIVE_PRCI_PLLCFG0_DIVF = (31 << 6), + SIFIVE_PRCI_PLLCFG0_DIVQ = (3 << 15), + SIFIVE_PRCI_PLLCFG0_FSE = (1 << 25), + SIFIVE_PRCI_PLLCFG0_LOCK = (1 << 31) +}; + +/* xxxPLLCFG1 register bits */ +enum { + SIFIVE_PRCI_PLLCFG1_CKE = (1 << 24) +}; + +enum { + SIFIVE_PRCI_CORECLKSEL_HFCLK = (1 << 0) +}; + +#define SIFIVE_U_PRCI_REG_SIZE 0x1000 + +#define TYPE_SIFIVE_U_PRCI "riscv.sifive.u.prci" + +#define SIFIVE_U_PRCI(obj) \ + OBJECT_CHECK(SiFivePRCIState, (obj), TYPE_SIFIVE_U_PRCI) + +typedef struct SiFivePRCIState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; + uint32_t hfxosccfg; + uint32_t corepllcfg0; + uint32_t ddrpllcfg0; + uint32_t ddrpllcfg1; + uint32_t gemgxlpllcfg0; + uint32_t gemgxlpllcfg1; + uint32_t coreclksel; + uint32_t devicesreset; + uint32_t clkmuxstatus; +} SiFivePRCIState; + +DeviceState *sifive_u_prci_create(hwaddr addr); + +#endif /* HW_SIFIVE_U_PRCI_H */ From patchwork Mon Aug 5 16:00:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077303 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 36CD114E5 for ; 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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.43 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:43 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 09:00:10 -0700 Message-Id: <1565020823-24223-16-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP To keep in sync with Linux kernel device tree, generate hfclk and rtcclk nodes in the device tree, to be referenced by PRCI node. Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 23 +++++++++++++++++++++++ include/hw/riscv/sifive_u.h | 2 ++ 2 files changed, 25 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index dfcb525..f619ca6 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -76,6 +76,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, char *nodename; char ethclk_names[] = "pclk\0hclk\0tx_clk"; uint32_t plic_phandle, ethclk_phandle, phandle = 1; + uint32_t hfclk_phandle, rtcclk_phandle; fdt = s->fdt = create_device_tree(&s->fdt_size); if (!fdt) { @@ -94,6 +95,28 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); + hfclk_phandle = phandle++; + nodename = g_strdup_printf("/hfclk"); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); + qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_HFCLK_FREQ); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); + g_free(nodename); + + rtcclk_phandle = phandle++; + nodename = g_strdup_printf("/rtcclk"); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); + qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_RTCCLK_FREQ); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); + g_free(nodename); + nodename = g_strdup_printf("/memory@%lx", (long)memmap[SIFIVE_U_DRAM].base); qemu_fdt_add_subnode(fdt, nodename); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 4abc621..bacd60f 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -65,6 +65,8 @@ enum { enum { SIFIVE_U_CLOCK_FREQ = 1000000000, + SIFIVE_U_HFCLK_FREQ = 33333333, + SIFIVE_U_RTCCLK_FREQ = 1000000, SIFIVE_U_GEM_CLOCK_FREQ = 125000000 }; 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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.44 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:44 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 09:00:11 -0700 Message-Id: <1565020823-24223-17-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 16/28] riscv: sifive_u: Add PRCI block to the SoC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add PRCI mmio base address and size mappings to sifive_u machine, and generate the corresponding device tree node. Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 21 ++++++++++++++++++++- include/hw/riscv/sifive_u.h | 1 + 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index f619ca6..20dee52 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -9,6 +9,7 @@ * 0) UART * 1) CLINT (Core Level Interruptor) * 2) PLIC (Platform Level Interrupt Controller) + * 3) PRCI (Power, Reset, Clock, Interrupt) * * This board currently uses a hardcoded devicetree that indicates five harts. * @@ -41,6 +42,7 @@ #include "hw/riscv/sifive_clint.h" #include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_u.h" +#include "hw/riscv/sifive_u_prci.h" #include "hw/riscv/boot.h" #include "chardev/char.h" #include "sysemu/arch_init.h" @@ -59,6 +61,7 @@ static const struct MemmapEntry { [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, + [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, @@ -75,7 +78,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, uint32_t *cells; char *nodename; char ethclk_names[] = "pclk\0hclk\0tx_clk"; - uint32_t plic_phandle, ethclk_phandle, phandle = 1; + uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1; uint32_t hfclk_phandle, rtcclk_phandle; fdt = s->fdt = create_device_tree(&s->fdt_size); @@ -182,6 +185,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, g_free(cells); g_free(nodename); + prci_phandle = phandle++; + nodename = g_strdup_printf("/soc/clock-controller@%lx", + (long)memmap[SIFIVE_U_PRCI].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + hfclk_phandle, rtcclk_phandle); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_PRCI].base, + 0x0, memmap[SIFIVE_U_PRCI].size); + qemu_fdt_setprop_string(fdt, nodename, "compatible", + "sifive,fu540-c000-prci"); + g_free(nodename); + plic_phandle = phandle++; cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4 - 2); for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { @@ -421,6 +439,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) sifive_clint_create(memmap[SIFIVE_U_CLINT].base, memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); + sifive_u_prci_create(memmap[SIFIVE_U_PRCI].base); for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index bacd60f..19d5a6f 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -51,6 +51,7 @@ enum { SIFIVE_U_MROM, SIFIVE_U_CLINT, SIFIVE_U_PLIC, + SIFIVE_U_PRCI, SIFIVE_U_UART0, SIFIVE_U_UART1, SIFIVE_U_DRAM, From patchwork Mon Aug 5 16:00:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077283 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DF7D214E5 for ; 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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.45 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:45 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 09:00:12 -0700 Message-Id: <1565020823-24223-18-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 17/28] riscv: sifive_u: Change UART node name in device tree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP OpenSBI for fu540 does DT fix up (see fu540_modify_dt()) by updating chosen "stdout-path" to point to "/soc/serial@...", and U-Boot will use this information to locate the serial node and probe its driver. However currently we generate the UART node name as "/soc/uart@...", causing U-Boot fail to find the serial node in DT. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/sifive_u.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 20dee52..8044166 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -273,7 +273,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); g_free(nodename); - nodename = g_strdup_printf("/soc/uart@%lx", + nodename = g_strdup_printf("/soc/serial@%lx", (long)memmap[SIFIVE_U_UART0].base); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); From patchwork Mon Aug 5 16:00:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077291 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 578631398 for ; Mon, 5 Aug 2019 16:07:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4069E286C0 for ; Mon, 5 Aug 2019 16:07:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 34CA3286D5; Mon, 5 Aug 2019 16:07:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7149F286C0 for ; Mon, 5 Aug 2019 16:07:30 +0000 (UTC) Received: from localhost ([::1]:55598 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hufWD-00056I-Qg for patchwork-qemu-devel@patchwork.kernel.org; Mon, 05 Aug 2019 12:07:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58598) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hufPu-0000mw-49 for qemu-devel@nongnu.org; Mon, 05 Aug 2019 12:01:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hufPr-00032l-3s for qemu-devel@nongnu.org; Mon, 05 Aug 2019 12:00:57 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:45309) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hufPn-0002yc-6g; Mon, 05 Aug 2019 12:00:52 -0400 Received: by mail-pf1-x444.google.com with SMTP id r1so39861385pfq.12; Mon, 05 Aug 2019 09:00:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=2ms6qzywynSYGndXaBF2HCSrVQr5HrR87UomFY43oOo=; b=QvC4bLRX7/Un2bwF6t1LcfjWRSrTf1kSbJlIKjKtm2omg+/8uoItJiDxknXwcda7Ns xBKevTlUYkiMm4IDCLEwr6JWz1gIiEKiTdE+G3Dl9Cpt+k5jSOm8jK+y0JuY4LEozooU EcQcHVNjPtfdt2ZYza30z0a8iIj3Gm4SkmJpDU+Fwr0ui79Va06Q1q9v42Ws2KClIg+e KiwxhszK+j82YIO+5pvdHGk7r7HsLozKgQq3SaKLN4bDy/SljiB+iCUwtrsJp5N87Kcz 5FGCDWZFVYBC0uGWMtVyYKJKhDDwAlO2kb7tyHTqHXINab4d+GmLbCc1vI7svvLYvBNQ pRtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=2ms6qzywynSYGndXaBF2HCSrVQr5HrR87UomFY43oOo=; b=HLx9jmYL9YaTZnW4HOUyKPkLCxpl6dAuCD0FirLh5LdBqIdJ4XFKKSaoxHsK/zWWI1 uwoxXvv7QYwqh8GEO6x+ILpit0nhZWcecLrPZZZmAPafx0VbxSi75vNpeeUCDCjSBBNa 8OL96TV1SaEMZtv14ISP7SEm2cFp9bLpnuaYrespW6prIoePpPEj09V4JrlO5B/5lcxx pYSLm9lTv2RCFosNK/3h5B2AcsQWTj5mpuwZ/Zm+WH2ZDBZUfLH3fF8G6nAxQfayn+RD X+izXAwZiwTaRbGc/zre1HLVj4mSiCUpthkLGIA0PexsRNW5/XG5irkVACgWzPmLmUZk fkMg== X-Gm-Message-State: APjAAAWjnghmXl7Gqs4H8PxcMoNvWJpKUx9scKgXjN+IsXI/AAy/iDyk Cs4Ae4qXa+B2dOPjgOlAH/FGY1Y7 X-Google-Smtp-Source: APXvYqxfva+PWi8e3QiT9G1GxXpJrXe+H8jP672rmwkV9AxzNlxs1PdT9YzSNNTYq6o4G1TM/+VSeg== X-Received: by 2002:aa7:96a4:: with SMTP id g4mr76499241pfk.193.1565020847412; Mon, 05 Aug 2019 09:00:47 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.46 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:46 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 09:00:13 -0700 Message-Id: <1565020823-24223-19-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 18/28] riscv: hw: Implement a model for SiFive FU540 OTP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This implements a simple model for SiFive FU540 OTP (One-Time Programmable) Memory interface, primarily for reading out the stored serial number from the first 1 KiB of the 16 KiB OTP memory reserved by SiFive for internal use. Signed-off-by: Bin Meng --- hw/riscv/Makefile.objs | 1 + hw/riscv/sifive_u_otp.c | 194 ++++++++++++++++++++++++++++++++++++++++ include/hw/riscv/sifive_u_otp.h | 90 +++++++++++++++++++ 3 files changed, 285 insertions(+) create mode 100644 hw/riscv/sifive_u_otp.c create mode 100644 include/hw/riscv/sifive_u_otp.h diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs index b95bbd5..fc3c6dd 100644 --- a/hw/riscv/Makefile.objs +++ b/hw/riscv/Makefile.objs @@ -8,6 +8,7 @@ obj-$(CONFIG_SIFIVE) += sifive_gpio.o obj-$(CONFIG_SIFIVE) += sifive_plic.o obj-$(CONFIG_SIFIVE) += sifive_test.o obj-$(CONFIG_SIFIVE_U) += sifive_u.o +obj-$(CONFIG_SIFIVE_U) += sifive_u_otp.o obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o obj-$(CONFIG_SIFIVE) += sifive_uart.o obj-$(CONFIG_SPIKE) += spike.o diff --git a/hw/riscv/sifive_u_otp.c b/hw/riscv/sifive_u_otp.c new file mode 100644 index 0000000..f21d9f4 --- /dev/null +++ b/hw/riscv/sifive_u_otp.c @@ -0,0 +1,194 @@ +/* + * QEMU SiFive U OTP (One-Time Programmable) Memory interface + * + * Copyright (c) 2019 Bin Meng + * + * Simple model of the OTP to emulate register reads made by the SDK BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "qemu/module.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/sifive_u_otp.h" + +static uint64_t sifive_otp_read(void *opaque, hwaddr addr, unsigned int size) +{ + SiFiveOTPState *s = opaque; + + switch (addr) { + case SIFIVE_OTP_PA: + return s->pa; + case SIFIVE_OTP_PAIO: + return s->paio; + case SIFIVE_OTP_PAS: + return s->pas; + case SIFIVE_OTP_PCE: + return s->pce; + case SIFIVE_OTP_PCLK: + return s->pclk; + case SIFIVE_OTP_PDIN: + return s->pdin; + case SIFIVE_OTP_PDOUT: + if ((s->pce & SIFIVE_OTP_PCE_EN) && + (s->pdstb & SIFIVE_OTP_PDSTB_EN) && + (s->ptrim & SIFIVE_OTP_PTRIM_EN)) { + return s->fuse[s->pa & SIFIVE_OTP_PA_MASK]; + } else { + return 0xff; + } + case SIFIVE_OTP_PDSTB: + return s->pdstb; + case SIFIVE_OTP_PPROG: + return s->pprog; + case SIFIVE_OTP_PTC: + return s->ptc; + case SIFIVE_OTP_PTM: + return s->ptm; + case SIFIVE_OTP_PTM_REP: + return s->ptm_rep; + case SIFIVE_OTP_PTR: + return s->ptr; + case SIFIVE_OTP_PTRIM: + return s->ptrim; + case SIFIVE_OTP_PWE: + return s->pwe; + } + + hw_error("%s: read: addr=0x%x\n", __func__, (int)addr); + return 0; +} + +static void sifive_otp_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + SiFiveOTPState *s = opaque; + + switch (addr) { + case SIFIVE_OTP_PA: + s->pa = (uint32_t) val64 & SIFIVE_OTP_PA_MASK; + break; + case SIFIVE_OTP_PAIO: + s->paio = (uint32_t) val64; + break; + case SIFIVE_OTP_PAS: + s->pas = (uint32_t) val64; + break; + case SIFIVE_OTP_PCE: + s->pce = (uint32_t) val64; + break; + case SIFIVE_OTP_PCLK: + s->pclk = (uint32_t) val64; + break; + case SIFIVE_OTP_PDIN: + s->pdin = (uint32_t) val64; + break; + case SIFIVE_OTP_PDOUT: + /* read-only */ + break; + case SIFIVE_OTP_PDSTB: + s->pdstb = (uint32_t) val64; + break; + case SIFIVE_OTP_PPROG: + s->pprog = (uint32_t) val64; + break; + case SIFIVE_OTP_PTC: + s->ptc = (uint32_t) val64; + break; + case SIFIVE_OTP_PTM: + s->ptm = (uint32_t) val64; + break; + case SIFIVE_OTP_PTM_REP: + s->ptm_rep = (uint32_t) val64; + break; + case SIFIVE_OTP_PTR: + s->ptr = (uint32_t) val64; + break; + case SIFIVE_OTP_PTRIM: + s->ptrim = (uint32_t) val64; + break; + case SIFIVE_OTP_PWE: + s->pwe = (uint32_t) val64; + break; + default: + hw_error("%s: bad write: addr=0x%x v=0x%x\n", + __func__, (int)addr, (int)val64); + } +} + +static const MemoryRegionOps sifive_otp_ops = { + .read = sifive_otp_read, + .write = sifive_otp_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4 + } +}; + +static Property sifive_otp_properties[] = { + DEFINE_PROP_UINT32("serial", SiFiveOTPState, serial, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void sifive_otp_realize(DeviceState *dev, Error **errp) +{ + SiFiveOTPState *s = SIFIVE_U_OTP(dev); + + memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_otp_ops, s, + TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); + + /* Initialize all fuses' initial value to 0xFFs */ + memset(s->fuse, 0xff, sizeof(s->fuse)); + + /* Make a valid content of serial number */ + s->fuse[SIFIVE_OTP_SERIAL_ADDR] = s->serial; + s->fuse[SIFIVE_OTP_SERIAL_ADDR + 1] = ~(s->serial); +} + +static void sifive_otp_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->props = sifive_otp_properties; + dc->realize = sifive_otp_realize; +} + +static const TypeInfo sifive_otp_info = { + .name = TYPE_SIFIVE_U_OTP, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SiFiveOTPState), + .class_init = sifive_otp_class_init, +}; + +static void sifive_otp_register_types(void) +{ + type_register_static(&sifive_otp_info); +} + +type_init(sifive_otp_register_types) + + +/* Create OTP device */ +DeviceState *sifive_u_otp_create(hwaddr addr, uint32_t serial) +{ + DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_U_OTP); + qdev_prop_set_uint32(dev, "serial", serial); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + + return dev; +} diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/riscv/sifive_u_otp.h new file mode 100644 index 0000000..16095b0 --- /dev/null +++ b/include/hw/riscv/sifive_u_otp.h @@ -0,0 +1,90 @@ +/* + * QEMU SiFive U OTP (One-Time Programmable) Memory interface + * + * Copyright (c) 2019 Bin Meng + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef HW_SIFIVE_U_OTP_H +#define HW_SIFIVE_U_OTP_H + +enum { + SIFIVE_OTP_PA = 0x00, + SIFIVE_OTP_PAIO = 0x04, + SIFIVE_OTP_PAS = 0x08, + SIFIVE_OTP_PCE = 0x0C, + SIFIVE_OTP_PCLK = 0x10, + SIFIVE_OTP_PDIN = 0x14, + SIFIVE_OTP_PDOUT = 0x18, + SIFIVE_OTP_PDSTB = 0x1C, + SIFIVE_OTP_PPROG = 0x20, + SIFIVE_OTP_PTC = 0x24, + SIFIVE_OTP_PTM = 0x28, + SIFIVE_OTP_PTM_REP = 0x2C, + SIFIVE_OTP_PTR = 0x30, + SIFIVE_OTP_PTRIM = 0x34, + SIFIVE_OTP_PWE = 0x38 +}; + +enum { + SIFIVE_OTP_PCE_EN = (1 << 0) +}; + +enum { + SIFIVE_OTP_PDSTB_EN = (1 << 0) +}; + +enum { + SIFIVE_OTP_PTRIM_EN = (1 << 0) +}; + +#define SIFIVE_OTP_PA_MASK 0xfff +#define SIFIVE_OTP_NUM_FUSES 0x1000 +#define SIFIVE_OTP_SERIAL_ADDR 0xfc + +#define SIFIVE_U_OTP_REG_SIZE 0x1000 + +#define TYPE_SIFIVE_U_OTP "riscv.sifive.u.otp" + +#define SIFIVE_U_OTP(obj) \ + OBJECT_CHECK(SiFiveOTPState, (obj), TYPE_SIFIVE_U_OTP) + +typedef struct SiFiveOTPState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; + uint32_t pa; + uint32_t paio; + uint32_t pas; + uint32_t pce; + uint32_t pclk; + uint32_t pdin; + uint32_t pdstb; + uint32_t pprog; + uint32_t ptc; + uint32_t ptm; + uint32_t ptm_rep; + uint32_t ptr; + uint32_t ptrim; + uint32_t pwe; + uint32_t fuse[SIFIVE_OTP_NUM_FUSES]; + /* config */ + uint32_t serial; +} SiFiveOTPState; + +DeviceState *sifive_u_otp_create(hwaddr addr, uint32_t serial); + +#endif /* HW_SIFIVE_U_OTP_H */ From patchwork Mon Aug 5 16:00:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077309 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1193814E5 for ; Mon, 5 Aug 2019 16:09:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 01CE9286C7 for ; Mon, 5 Aug 2019 16:09:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E7B8828711; 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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.49 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:50 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 09:00:16 -0700 Message-Id: <1565020823-24223-22-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 21/28] riscv: sifive_u: Update UART and ethernet node clock properties X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Now that we have added PRCI nodes, update existing UART and ethernet nodes to use PRCI as their clock sources, to keep in sync with the Linux kernel device tree. With above changes, the previously handcrafted "/soc/ethclk" node is no longer needed. Remove it. Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 21 +++++---------------- include/hw/riscv/sifive_u.h | 3 +-- include/hw/riscv/sifive_u_prci.h | 10 ++++++++++ 3 files changed, 16 insertions(+), 18 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index b90aa53..061d6d4 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -81,8 +81,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, int cpu; uint32_t *cells; char *nodename; - char ethclk_names[] = "pclk\0hclk\0tx_clk"; - uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1; + char ethclk_names[] = "pclk\0hclk"; + uint32_t plic_phandle, prci_phandle, phandle = 1; uint32_t hfclk_phandle, rtcclk_phandle; fdt = s->fdt = create_device_tree(&s->fdt_size); @@ -241,17 +241,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, g_free(cells); g_free(nodename); - ethclk_phandle = phandle++; - nodename = g_strdup_printf("/soc/ethclk"); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); - qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", - SIFIVE_U_GEM_CLOCK_FREQ); - qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle); - ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename); - g_free(nodename); - nodename = g_strdup_printf("/soc/ethernet@%lx", (long)memmap[SIFIVE_U_GEM].base); qemu_fdt_add_subnode(fdt, nodename); @@ -264,7 +253,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); qemu_fdt_setprop_cells(fdt, nodename, "clocks", - ethclk_phandle, ethclk_phandle, ethclk_phandle); + prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names, sizeof(ethclk_names)); qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); @@ -284,8 +273,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_UART0].base, 0x0, memmap[SIFIVE_U_UART0].size); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", - SIFIVE_U_CLOCK_FREQ / 2); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + prci_phandle, PRCI_CLK_TLCLK); qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 2f475c5..0461331 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -68,8 +68,7 @@ enum { enum { SIFIVE_U_CLOCK_FREQ = 1000000000, SIFIVE_U_HFCLK_FREQ = 33333333, - SIFIVE_U_RTCCLK_FREQ = 1000000, - SIFIVE_U_GEM_CLOCK_FREQ = 125000000 + SIFIVE_U_RTCCLK_FREQ = 1000000 }; #define SIFIVE_U_PLIC_HART_CONFIG "MS" diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/riscv/sifive_u_prci.h index f3a4656..640c641 100644 --- a/include/hw/riscv/sifive_u_prci.h +++ b/include/hw/riscv/sifive_u_prci.h @@ -87,4 +87,14 @@ typedef struct SiFivePRCIState { DeviceState *sifive_u_prci_create(hwaddr addr); +/* + * Clock indexes for use by Device Tree data and the PRCI driver. + * + * These values are from sifive-fu540-prci.h in the Linux kernel. + */ +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_TLCLK 3 + #endif /* HW_SIFIVE_U_PRCI_H */ From patchwork Mon Aug 5 16:00:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077317 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3DCDC14E5 for ; Mon, 5 Aug 2019 16:11:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2DAB528782 for ; Mon, 5 Aug 2019 16:11:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 21D75287BD; Mon, 5 Aug 2019 16:11:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D26142876B for ; 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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.51 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:51 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 09:00:17 -0700 Message-Id: <1565020823-24223-23-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH 22/28] riscv: sifive_u: Generate an aliases node in the device tree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The Linux kernel SiFive UART driver expects an aliases node to be present in the device tree, from which the driver extracts the port number from "serial#" in the aliases node. Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 061d6d4..9945b82 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -283,6 +283,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, if (cmdline) { qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); } + qemu_fdt_add_subnode(fdt, "/aliases"); + qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); g_free(nodename); } From patchwork Mon Aug 5 16:00:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077299 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 35C751398 for ; Mon, 5 Aug 2019 16:08:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 23F3B286C7 for ; Mon, 5 Aug 2019 16:08:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1570128711; Mon, 5 Aug 2019 16:08:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B28EB286C7 for ; Mon, 5 Aug 2019 16:08:34 +0000 (UTC) Received: from localhost ([::1]:55624 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hufXG-0008RY-28 for patchwork-qemu-devel@patchwork.kernel.org; Mon, 05 Aug 2019 12:08:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58649) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hufPv-0000nb-LG for qemu-devel@nongnu.org; Mon, 05 Aug 2019 12:01:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hufPu-00037O-3U for qemu-devel@nongnu.org; Mon, 05 Aug 2019 12:00:59 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:34069) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hufPr-00030h-TC; Mon, 05 Aug 2019 12:00:57 -0400 Received: by mail-pg1-x544.google.com with SMTP id n9so33750648pgc.1; Mon, 05 Aug 2019 09:00:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=n7pF8fB0WXPiBzqIF3GALSuGpVHl36mKtNGP2o/KXGU=; b=h7THoYgSVwVWU7zA+jpMbz3AN1oFtQTsO3UL9foqnyROiNEYDbq0z0E5xLfylQeo/a VfbL1lYla9sSu2glVPzIHFraWsft48R4DzHRb260CZB/Ra99mzWxaUr6pfznA9Ejqiku aFG6iB5UVpAMENeGH8WiN5pJrfnwFQkt+fqUroN0AFJiCVqjw8YISsFvFxFvyjsVM5O8 ESEQ3ZegbAaINj2zuNQ1T3txHINppVcuZSuIi9j5UdGu6ciPTIYYxWNAIJnCPExsqnfb 9fM9t/IX+oB1a8diLPneOWrdHFGwcO4pqKXFrdXVpx2Nd/3+zIiOTITm+2C8+Mkajwb/ sRPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=n7pF8fB0WXPiBzqIF3GALSuGpVHl36mKtNGP2o/KXGU=; b=IddXyHrxmv/S9diQQ+CEJrr+BLxOlw8jvlw8mp+frEDYxXJN9ri65zXtOpNT5bAY/k JVtCdtJQ2OrEN4J68dG8GiAJb47J53P0zYeKoWcLbqr2Kl1fUESD/qCmhip7MkfuDf9/ RJdfjcihpMh3bw4s4drLseipMyGsqAjnSVGkEYfGLpGxMPLL9yRm2kJw0omUSMlsltwO ZTPKHcqLyWpQuhzk1XHkUlasMdKfwil5+plVy8AFagjWKVE8SA5NkYi3RMRc0UEIHa4G R3uIBVMAWjI/7L9W/IxMrFSD+J2kjks7h0rgXRRgAZxTtYuIsXS+qGdl/xElCN/a29Lg F50A== X-Gm-Message-State: APjAAAXghA4BHbMzW+qmNNN7U6/RX3qeIHGdRGwmEEznPqt2gO8rQJ7Y f11dG1QwHHwBn00rj3t9Ubk= X-Google-Smtp-Source: APXvYqysT/Jopi8/rGV2wkOLuqFk9Iluz8/mY9rf+JCzxeNBYdGjtFHBBpM8ku7hRcb9AmcQLbCgqg== X-Received: by 2002:a62:ae01:: with SMTP id q1mr71952955pff.219.1565020853139; Mon, 05 Aug 2019 09:00:53 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.52 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:52 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 09:00:18 -0700 Message-Id: <1565020823-24223-24-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH 23/28] riscv: sifive: Move sifive_mmio_emulate() to a common place X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP sifive_mmio_emulate() is currently only used in the sifive_e machine codes. It can be helpful for other machines as well. Change it to an inline routine and move it to sifive_cpu.h, so that other machines like sifive_u can use it. Signed-off-by: Bin Meng --- hw/riscv/sifive_e.c | 8 -------- include/hw/riscv/sifive_cpu.h | 10 +++++++++- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 2d67670..7e0fe7b 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -74,14 +74,6 @@ static const struct MemmapEntry { [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 } }; -static void sifive_mmio_emulate(MemoryRegion *parent, const char *name, - uintptr_t offset, uintptr_t length) -{ - MemoryRegion *mock_mmio = g_new(MemoryRegion, 1); - memory_region_init_ram(mock_mmio, NULL, name, length, &error_fatal); - memory_region_add_subregion(parent, offset, mock_mmio); -} - static void riscv_sifive_e_init(MachineState *machine) { const struct MemmapEntry *memmap = sifive_e_memmap; diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h index 1367996..897b8f8 100644 --- a/include/hw/riscv/sifive_cpu.h +++ b/include/hw/riscv/sifive_cpu.h @@ -1,5 +1,5 @@ /* - * SiFive CPU types + * SiFive CPU types and common utilities * * Copyright (c) 2017 SiFive, Inc. * Copyright (c) 2019 Bin Meng @@ -28,4 +28,12 @@ #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 #endif +static inline void sifive_mmio_emulate(MemoryRegion *parent, const char *name, + uintptr_t offset, uintptr_t length) +{ + MemoryRegion *mock_mmio = g_new(MemoryRegion, 1); + memory_region_init_ram(mock_mmio, NULL, name, length, &error_fatal); + memory_region_add_subregion(parent, offset, mock_mmio); +} + #endif /* HW_SIFIVE_CPU_H */ From patchwork Mon Aug 5 16:00:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077319 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B69181398 for ; Mon, 5 Aug 2019 16:11:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A764128830 for ; Mon, 5 Aug 2019 16:11:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9C1BF28832; Mon, 5 Aug 2019 16:11:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2337828837 for ; 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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.53 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:53 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 09:00:19 -0700 Message-Id: <1565020823-24223-25-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 24/28] riscv: sifive_u: Fix broken GEM support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP At present the GEM support in sifive_u machine is seriously broken. - The GEM block register base was set to a weird number (0x100900FC), which for no way could work with the cadence_gem model in QEMU. - The generated DT node for GEM has a "clocks-names" which is an invalid property name. Not like other GEM variants, the FU540-specific GEM has a management block to control 10/100/1000Mbps link speed changes, that is mapped to 0x100a0000. We can simply map it into MMIO space without special handling using sifive_mmio_emulate(). Update the GEM node compatible string to use the official name used by the upstream Linux kernel, and add the management block reg base & size to the property encoding. Tested with upstream U-Boot and Linux kernel MACB drivers. Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 17 +++++++++++++---- include/hw/riscv/sifive_u.h | 3 ++- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9945b82..85cd4b5 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -3,6 +3,7 @@ * * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu * Copyright (c) 2017 SiFive, Inc. + * Copyright (c) 2019 Bin Meng * * Provides a board compatible with the SiFive Freedom U SDK: * @@ -11,6 +12,7 @@ * 2) PLIC (Platform Level Interrupt Controller) * 3) PRCI (Power, Reset, Clock, Interrupt) * 4) OTP (One-Time Programmable) memory with stored serial number + * 5) GEM (Gigabit Ethernet Controller) and management block * * This board currently uses a hardcoded devicetree that indicates five harts. * @@ -68,7 +70,8 @@ static const struct MemmapEntry { [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, [SIFIVE_U_OTP] = { 0x10070000, 0x1000 }, [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, - [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, + [SIFIVE_U_GEM] = { 0x10090000, 0x2000 }, + [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 }, }; #define SIFIVE_OTP_SERIAL 1 @@ -244,17 +247,20 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, nodename = g_strdup_printf("/soc/ethernet@%lx", (long)memmap[SIFIVE_U_GEM].base); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb"); + qemu_fdt_setprop_string(fdt, nodename, "compatible", + "sifive,fu540-c000-gem"); qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_GEM].base, - 0x0, memmap[SIFIVE_U_GEM].size); + 0x0, memmap[SIFIVE_U_GEM].size, + 0x0, memmap[SIFIVE_U_GEM_MGMT].base, + 0x0, memmap[SIFIVE_U_GEM_MGMT].size); qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); qemu_fdt_setprop_cells(fdt, nodename, "clocks", prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); - qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names, + qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, sizeof(ethclk_names)); qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); @@ -455,6 +461,9 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, plic_gpios[SIFIVE_U_GEM_IRQ]); + + sifive_mmio_emulate(system_memory, "riscv.sifive.u.gem-mgmt", + memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); } static void riscv_sifive_u_machine_init(MachineClass *mc) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 0461331..e92f1aa 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -56,7 +56,8 @@ enum { SIFIVE_U_UART1, SIFIVE_U_OTP, SIFIVE_U_DRAM, - SIFIVE_U_GEM + SIFIVE_U_GEM, + SIFIVE_U_GEM_MGMT }; enum { From patchwork Mon Aug 5 16:00:20 2019 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 25/28] riscv: sifive_u: Support loading initramfs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The loading of initramfs is currently not supported on 'sifive_u'. Add the support to make '-initrd' command line parameter useful. Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 85cd4b5..d77b3c3 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -323,7 +323,18 @@ static void riscv_sifive_u_init(MachineState *machine) memmap[SIFIVE_U_DRAM].base); if (machine->kernel_filename) { - riscv_load_kernel(machine->kernel_filename); + uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename); + + if (machine->initrd_filename) { + hwaddr start; + hwaddr end = riscv_load_initrd(machine->initrd_filename, + machine->ram_size, kernel_entry, + &start); + qemu_fdt_setprop_cell(s->fdt, "/chosen", + "linux,initrd-start", start); + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", + end); + } } /* reset vector */ From patchwork Mon Aug 5 16:00:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077321 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E5E4E14E5 for ; Mon, 5 Aug 2019 16:12:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D66332885F for ; Mon, 5 Aug 2019 16:12:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CAC1628876; Mon, 5 Aug 2019 16:12:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6E0E528877 for ; Mon, 5 Aug 2019 16:12:35 +0000 (UTC) Received: from localhost ([::1]:55750 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hufb8-0002IV-NE for patchwork-qemu-devel@patchwork.kernel.org; Mon, 05 Aug 2019 12:12:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58724) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hufQ3-0000p9-UH for qemu-devel@nongnu.org; Mon, 05 Aug 2019 12:01:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hufPw-000392-8H for qemu-devel@nongnu.org; Mon, 05 Aug 2019 12:01:03 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:44836) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hufPv-00034L-GX; Mon, 05 Aug 2019 12:00:59 -0400 Received: by mail-pl1-x641.google.com with SMTP id t14so36622438plr.11; Mon, 05 Aug 2019 09:00:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=xEY3l8h0rhtRUd3NJGUWgEZIzETm5Q+o0eADRCDJ/Z4=; b=ckyEJiaLVW2LSabNkgs0leu0TRq/0UIC39t5qbWGhnsKKSXWgGD8czIBaw1MSY6sGd xmd5tXPcKeEQcp8AUA7aW6OMmLKVymeys2WOnfF4troqEqEBlE2ZNqu+196ZzA3TsOCj bPfeDAlYTDFedvpJlGH11SY6sdmWuo4ZEPkCBGI7c/JsyT16bBIe2KPopgP7ZRCpKMYW tKJ3g6eJ0S+cewr9ihUqB770coYez742xRwuJOEdb2LiZ4cF46ERTDXHhp8U03clP0e1 zi7scN/LqiG1Ig4F+ofoDGAvLrsVaFJLTOl2zUYXNd86mT22FwgphJqIeppqFZJABHTD c48A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=xEY3l8h0rhtRUd3NJGUWgEZIzETm5Q+o0eADRCDJ/Z4=; b=T9Ic/xjPB1lNKzCmo7TZIOsBFtACZFGTw4FJL10rixrN6dLXWRu8wr3hH9wIXQzTmY OXNdXzk7VslooIYUgxmPiBfI/do8Mt4hbx0nzSi1B9UYGTL8EMOWQoz8EwrGEvv1Kwfy IoZ+7d9fb0dTYz8K3FeJPh658ULNDO6ZPPr5N8SAgXnnBeewJ7rjdzuTAg95XlxHHYC6 oBHKIhi2w9ldzFZdMp4fjqvAOraiXeB0qD7FqGmzXxQOkPg8YT+MI/ploY1nP7Xh5bZt vfMrgIT2ymmMIgLj+AIcIb2LEriEAht/BiXcS57lDgX8cXQv3PNxte6I+oYMLUO9PDaa ZZIQ== X-Gm-Message-State: APjAAAUrKnHcNwLTFAtKl2UOlg0Nc1neJuuTRSBsNNkM9aBl3eh+MNz6 tEEYbEzR80HfUvEFf8wN+fU= X-Google-Smtp-Source: APXvYqy8hGtyM0+qyaxvPuYWnu6xmdCWI073fRAUnbjjJh1aaCb8taEVO1kjO3WvvD0AAaWOU9N97A== X-Received: by 2002:a17:902:347:: with SMTP id 65mr50129040pld.232.1565020856427; Mon, 05 Aug 2019 09:00:56 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.55 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:55 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 09:00:21 -0700 Message-Id: <1565020823-24223-27-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 26/28] riscv: hw: Update PLIC device tree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This removes "reg-names" and "riscv,max-priority" properties of the PLIC node from device tree, and updates its compatible string, to keep in sync with the Linux kernel device tree. Signed-off-by: Bin Meng Reviewed-by: Jonathan Behrens --- hw/riscv/sifive_u.c | 4 +--- hw/riscv/virt.c | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index d77b3c3..5ded3a0 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -229,15 +229,13 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, (long)memmap[SIFIVE_U_PLIC].base); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,plic-1.0.0"); qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); qemu_fdt_setprop(fdt, nodename, "interrupts-extended", cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_PLIC].base, 0x0, memmap[SIFIVE_U_PLIC].size); - qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); - qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); plic_phandle = qemu_fdt_get_phandle(fdt, nodename); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 127f005..f662100 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -237,15 +237,13 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, FDT_PLIC_ADDR_CELLS); qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", FDT_PLIC_INT_CELLS); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,plic-1.0.0"); qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); qemu_fdt_setprop(fdt, nodename, "interrupts-extended", cells, s->soc.num_harts * sizeof(uint32_t) * 4); qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[VIRT_PLIC].base, 0x0, memmap[VIRT_PLIC].size); - qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); - qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV); qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); plic_phandle = qemu_fdt_get_phandle(fdt, nodename); From patchwork Mon Aug 5 16:00:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077323 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4BC081398 for ; Mon, 5 Aug 2019 16:12:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3CCBB28787 for ; Mon, 5 Aug 2019 16:12:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 30F3B28782; Mon, 5 Aug 2019 16:12:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CD6AB28787 for ; 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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.56 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:56 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 09:00:22 -0700 Message-Id: <1565020823-24223-28-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 27/28] riscv: virt: Change create_fdt() to return void X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP There is no need to return fdt at the end of create_fdt() because it's already saved in s->fdt. Other machines (sifive_u, spike) don't do it neither. Signed-off-by: Bin Meng --- hw/riscv/virt.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f662100..5935ac8 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -112,7 +112,7 @@ static void create_pcie_irq_map(void *fdt, char *nodename, 0x1800, 0, 0, 0x7); } -static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, +static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, uint64_t mem_size, const char *cmdline) { void *fdt; @@ -316,8 +316,6 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); } g_free(nodename); - - return fdt; } @@ -373,7 +371,6 @@ static void riscv_virt_board_init(MachineState *machine) size_t plic_hart_config_len; int i; unsigned int smp_cpus = machine->smp.cpus; - void *fdt; /* Initialize SOC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), @@ -392,7 +389,7 @@ static void riscv_virt_board_init(MachineState *machine) main_mem); /* create device tree */ - fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); /* boot rom */ memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", @@ -411,9 +408,9 @@ static void riscv_virt_board_init(MachineState *machine) hwaddr end = riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, &start); - qemu_fdt_setprop_cell(fdt, "/chosen", + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", end); } } From patchwork Mon Aug 5 16:00:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11077325 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0431E14E5 for ; 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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id d18sm47728793pgi.40.2019.08.05.09.00.57 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Aug 2019 09:00:57 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 5 Aug 2019 09:00:23 -0700 Message-Id: <1565020823-24223-29-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> References: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 28/28] riscv: sifive_u: Update model and compatible strings in device tree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This updates model and compatible strings to use the same strings as used in the Linux kernel device tree (hifive-unleashed-a00.dts). Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/sifive_u.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 5ded3a0..b7d4b4f 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -94,8 +94,9 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, exit(1); } - qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); - qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); + qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); + qemu_fdt_setprop_string(fdt, "/", "compatible", + "sifive,hifive-unleashed-a00"); qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);