From patchwork Fri Aug 9 18:32:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11087473 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3391E1398 for ; Fri, 9 Aug 2019 18:36:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 243A920246 for ; Fri, 9 Aug 2019 18:36:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 17995205C0; Fri, 9 Aug 2019 18:36:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C24E520246 for ; Fri, 9 Aug 2019 18:36:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D28196EE76; Fri, 9 Aug 2019 18:36:05 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id D69F66EE76 for ; Fri, 9 Aug 2019 18:36:03 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Aug 2019 11:36:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,366,1559545200"; d="scan'208";a="193444071" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by fmsmga001.fm.intel.com with ESMTP; 09 Aug 2019 11:36:01 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sat, 10 Aug 2019 00:02:15 +0530 Message-Id: <20190809183223.12031-2-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190809183223.12031-1-anshuman.gupta@intel.com> References: <20190809183223.12031-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 1/9] drm/i915/tgl: Add DC3CO required register and bits X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Adding following definition to i915_reg.h 1. DC_STATE_EN register DC3CO bit fields and masks. 2. Transcoder EXITLINE register and its bit fields and mask. Cc: Jani Nikula Cc: Imre Deak Cc: Animesh Manna Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4a947bd0a294..3e0783ebbbe6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4198,6 +4198,7 @@ enum { #define _VTOTAL_A 0x6000c #define _VBLANK_A 0x60010 #define _VSYNC_A 0x60014 +#define _EXITLINE_A 0x60018 #define _PIPEASRC 0x6001c #define _BCLRPAT_A 0x60020 #define _VSYNCSHIFT_A 0x60028 @@ -4244,11 +4245,16 @@ enum { #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) +#define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A) #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) +#define EXITLINE_ENABLE (1 << 31) +#define EXITLINE_MASK (0x1fff) +#define EXITLINE_SHIFT 0 + /* HSW+ eDP PSR registers */ #define HSW_EDP_PSR_BASE 0x64800 #define BDW_EDP_PSR_BASE 0x6f800 @@ -10040,6 +10046,8 @@ enum skl_power_gate { /* GEN9 DC */ #define DC_STATE_EN _MMIO(0x45504) #define DC_STATE_DISABLE 0 +#define DC_STATE_EN_DC3CO (1 << 30) +#define DC_STATE_DC3CO_STATUS (1 << 29) #define DC_STATE_EN_UPTO_DC5 (1 << 0) #define DC_STATE_EN_DC9 (1 << 3) #define DC_STATE_EN_UPTO_DC6 (2 << 0) From patchwork Fri Aug 9 18:32:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11087475 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B474D1398 for ; Fri, 9 Aug 2019 18:36:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A4DBD20246 for ; Fri, 9 Aug 2019 18:36:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 98F2B205C0; Fri, 9 Aug 2019 18:36:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 413B020246 for ; Fri, 9 Aug 2019 18:36:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 978496EE78; Fri, 9 Aug 2019 18:36:07 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5713F6EE79 for ; Fri, 9 Aug 2019 18:36:06 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Aug 2019 11:36:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,366,1559545200"; d="scan'208";a="193444079" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by fmsmga001.fm.intel.com with ESMTP; 09 Aug 2019 11:36:03 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sat, 10 Aug 2019 00:02:16 +0530 Message-Id: <20190809183223.12031-3-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190809183223.12031-1-anshuman.gupta@intel.com> References: <20190809183223.12031-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 2/9] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Enable dc3co state in enable_dc module param and add dc3co enable mask to allowed_dc_mask and gen9_dc_mask. v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6 independently. Cc: Jani Nikula Cc: Imre Deak Cc: Animesh Manna Signed-off-by: Anshuman Gupta --- .../drm/i915/display/intel_display_power.c | 29 ++++++++++++++----- drivers/gpu/drm/i915/i915_params.c | 3 +- 2 files changed, 23 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index e3bea2b74ce2..e2ef202aeeef 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -717,7 +717,11 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) u32 mask; mask = DC_STATE_EN_UPTO_DC5; - if (INTEL_GEN(dev_priv) >= 11) + + if (INTEL_GEN(dev_priv) >= 12) + mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6 + | DC_STATE_EN_DC9; + else if (IS_GEN(dev_priv, 11)) mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; else if (IS_GEN9_LP(dev_priv)) mask |= DC_STATE_EN_DC9; @@ -3946,14 +3950,17 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, int requested_dc; int max_dc; - if (INTEL_GEN(dev_priv) >= 11) { - max_dc = 2; + if (INTEL_GEN(dev_priv) >= 12) { + max_dc = 4; /* * DC9 has a separate HW flow from the rest of the DC states, * not depending on the DMC firmware. It's needed by system * suspend/resume, so allow it unconditionally. */ mask = DC_STATE_EN_DC9; + } else if (IS_GEN(dev_priv, 11)) { + max_dc = 2; + mask = DC_STATE_EN_DC9; } else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) { max_dc = 2; mask = 0; @@ -3972,7 +3979,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, requested_dc = enable_dc; } else if (enable_dc == -1) { requested_dc = max_dc; - } else if (enable_dc > max_dc && enable_dc <= 2) { + } else if (enable_dc > max_dc && enable_dc <= 4) { DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n", enable_dc, max_dc); requested_dc = max_dc; @@ -3981,10 +3988,16 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, requested_dc = max_dc; } - if (requested_dc > 1) - mask |= DC_STATE_EN_UPTO_DC6; - if (requested_dc > 0) - mask |= DC_STATE_EN_UPTO_DC5; + if (requested_dc == 4) { + mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6; + } else if (requested_dc == 3) { + mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5; + } else { + if (requested_dc > 1) + mask |= DC_STATE_EN_UPTO_DC6; + if (requested_dc > 0) + mask |= DC_STATE_EN_UPTO_DC5; + } DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask); diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 296452f9efe4..4f1806f65040 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -46,7 +46,8 @@ i915_param_named(modeset, int, 0400, i915_param_named_unsafe(enable_dc, int, 0400, "Enable power-saving display C-states. " - "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)"); + "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; " + "3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)"); i915_param_named_unsafe(enable_fbc, int, 0600, "Enable frame buffer compression for power savings " From patchwork Fri Aug 9 18:32:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11087477 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8D96F1398 for ; Fri, 9 Aug 2019 18:36:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7D7D220223 for ; Fri, 9 Aug 2019 18:36:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 71E9C205F6; Fri, 9 Aug 2019 18:36:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0D3D420223 for ; Fri, 9 Aug 2019 18:36:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7B7946EE79; Fri, 9 Aug 2019 18:36:10 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id F216A6EE79 for ; Fri, 9 Aug 2019 18:36:08 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Aug 2019 11:36:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,366,1559545200"; d="scan'208";a="193444088" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by fmsmga001.fm.intel.com with ESMTP; 09 Aug 2019 11:36:06 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sat, 10 Aug 2019 00:02:17 +0530 Message-Id: <20190809183223.12031-4-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190809183223.12031-1-anshuman.gupta@intel.com> References: <20190809183223.12031-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 3/9] drm/i915/tgl: Add power well to enable DC3CO state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP "DC3CO Off" power well inherits its power domains from "DC Off" power well, these power domains will disallow DC3CO when any external displays are connected and at time of modeset and aux programming. Renaming "DC Off" power well to "DC5 Off" power well. v2: commit log improvement. v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre] Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre] Moved transcoder psr2 exit line enablement from tgl_allow_dc3co() to a appropriate place haswell_crtc_enable(). [Imre] Changed the DC3CO power well enabled call back logic as recommended in review comments. [Imre] v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)] v5: using udelay() instead of waiting for DC3CO exit status. Cc: Jani Nikula Cc: Imre Deak Cc: Animesh Manna Cc: Rodrigo Vivi Signed-off-by: Anshuman Gupta --- .../drm/i915/display/intel_display_power.c | 69 ++++++++++++++++++- 1 file changed, 67 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index e2ef202aeeef..c9e92d48cdab 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -791,7 +791,26 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state) dev_priv->csr.dc_state = val & mask; } -static void bxt_enable_dc9(struct drm_i915_private *dev_priv) +static void tgl_allow_dc3co(struct drm_i915_private *dev_priv) +{ + gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO); +} + +static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv) +{ + u32 val; + + val = I915_READ(DC_STATE_EN); + val &= ~DC_STATE_DC3CO_STATUS; + I915_WRITE(DC_STATE_EN, val); + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); + /* + * Delay of 200us DC3CO Exit time B.Spec 49196 + */ + udelay(200); +} + +void bxt_enable_dc9(struct drm_i915_private *dev_priv) { assert_can_enable_dc9(dev_priv); @@ -1007,6 +1026,33 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, gen9_enable_dc5(dev_priv); } +static void tgl_dc3co_power_well_enable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + tgl_disallow_dc3co(dev_priv); +} + +static void tgl_dc3co_power_well_disable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + if (!dev_priv->psr.sink_psr2_support) + return; + + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO) + tgl_allow_dc3co(dev_priv); +} + +static bool tgl_dc3co_power_well_enabled(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + /* + * Checking alone DC_STATE_EN is not enough as DC5 power well also + * allow/disallow DC3CO to make sure both are not enabled at same time + */ + return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 && + (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); +} + static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { @@ -2611,6 +2657,12 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \ BIT_ULL(POWER_DOMAIN_INIT)) +#define TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS ( \ + TGL_PW_2_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_MODESET) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + #define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ TGL_PW_2_POWER_DOMAINS | \ BIT_ULL(POWER_DOMAIN_MODESET) | \ @@ -2715,6 +2767,13 @@ static const struct i915_power_well_ops gen9_dc_off_power_well_ops = { .is_enabled = gen9_dc_off_power_well_enabled, }; +static const struct i915_power_well_ops tgl_dc3co_power_well_ops = { + .sync_hw = i9xx_power_well_sync_hw_noop, + .enable = tgl_dc3co_power_well_enable, + .disable = tgl_dc3co_power_well_disable, + .is_enabled = tgl_dc3co_power_well_enabled, +}; + static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = { .sync_hw = i9xx_power_well_sync_hw_noop, .enable = bxt_dpio_cmn_power_well_enable, @@ -3626,11 +3685,17 @@ static const struct i915_power_well_desc tgl_power_wells[] = { }, }, { - .name = "DC off", + .name = "DC5 off", .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS, .ops = &gen9_dc_off_power_well_ops, .id = DISP_PW_ID_NONE, }, + { + .name = "DC3CO off", + .domains = TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS, + .ops = &tgl_dc3co_power_well_ops, + .id = DISP_PW_ID_NONE, + }, { .name = "power well 2", .domains = TGL_PW_2_POWER_DOMAINS, From patchwork Fri Aug 9 18:32:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11087479 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 30DAC13B1 for ; Fri, 9 Aug 2019 18:36:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 21F7120223 for ; Fri, 9 Aug 2019 18:36:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 16776205F6; Fri, 9 Aug 2019 18:36:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C903220223 for ; Fri, 9 Aug 2019 18:36:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5AD356EE7A; Fri, 9 Aug 2019 18:36:13 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 20FEC6EE7B for ; Fri, 9 Aug 2019 18:36:11 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Aug 2019 11:36:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,366,1559545200"; d="scan'208";a="193444096" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by fmsmga001.fm.intel.com with ESMTP; 09 Aug 2019 11:36:08 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sat, 10 Aug 2019 00:02:18 +0530 Message-Id: <20190809183223.12031-5-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190809183223.12031-1-anshuman.gupta@intel.com> References: <20190809183223.12031-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 4/9] drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP As per B.Specs DC5 and DC6 not allowed when DC3CO is enabled and DC3CO should be enabled only during VIDEO playback. Which essentially means both can DC5 and DC3CO can not be enabled at same time, it makes DC3CO and DC5 mutual exclusive. Cc: Jani Nikula Cc: Imre Deak Cc: Animesh Manna Cc: Rodrigo Vivi Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index c9e92d48cdab..167839060154 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -996,6 +996,10 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); + /* DC3CO and DC5/6 are mutually exclusive */ + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO) + tgl_allow_dc3co(dev_priv); + dev_priv->display.get_cdclk(dev_priv, &cdclk_state); /* Can't read out voltage_level so can't use intel_cdclk_changed() */ WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state)); @@ -1020,6 +1024,10 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, if (!dev_priv->csr.dmc_payload) return; + /* DC3CO and DC5/6 are mutually exclusive */ + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO) + tgl_disallow_dc3co(dev_priv); + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6) skl_enable_dc6(dev_priv); else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5) From patchwork Fri Aug 9 18:32:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11087481 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 55E1813B1 for ; Fri, 9 Aug 2019 18:36:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4708F20223 for ; Fri, 9 Aug 2019 18:36:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3B5D5205F6; Fri, 9 Aug 2019 18:36:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9767220223 for ; Fri, 9 Aug 2019 18:36:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 301056EE7B; Fri, 9 Aug 2019 18:36:16 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id A139C6EE7B for ; Fri, 9 Aug 2019 18:36:13 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Aug 2019 11:36:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,366,1559545200"; d="scan'208";a="193444111" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by fmsmga001.fm.intel.com with ESMTP; 09 Aug 2019 11:36:11 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sat, 10 Aug 2019 00:02:19 +0530 Message-Id: <20190809183223.12031-6-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190809183223.12031-1-anshuman.gupta@intel.com> References: <20190809183223.12031-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 5/9] drm/i915/tgl: Add helper function to prefer dc3co over dc5 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP We need to have a S/W flag based upon which driver can switch to DC3CO. If it is only edp display connected and it has psr2 capability, then set a prefer_dc3co flag to true, which will be used to switch to dc3co as well as to program DC3CO PSR2 transcoder early exitline event. Cc: Jani Nikula Cc: Imre Deak Cc: Animesh Manna Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_display.c | 5 + .../drm/i915/display/intel_display_power.c | 105 ++++++++++++++++++ .../drm/i915/display/intel_display_power.h | 5 + drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 2 +- drivers/gpu/drm/i915/intel_pm.h | 2 + 6 files changed, 119 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 647f49ca86ff..1ec204c14a10 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6448,6 +6448,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, if (WARN_ON(intel_crtc->active)) return; + /* Enable PSR2 transcoder exit line */ + if (pipe_config->has_psr2 && dev_priv->csr.prefer_dc3co) + tgl_enable_psr2_transcoder_exitline(pipe_config); intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state); @@ -13685,6 +13688,8 @@ static int intel_atomic_check(struct drm_device *dev, "[modeset]" : "[fastset]"); } + tgl_prefer_dc3co_over_dc5_check(dev_priv, state); + return 0; fail: diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 167839060154..04a02c88ff93 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -18,6 +18,7 @@ #include "intel_hotplug.h" #include "intel_sideband.h" #include "intel_tc.h" +#include "intel_pm.h" bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, enum i915_power_well_id power_well_id); @@ -791,6 +792,110 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state) dev_priv->csr.dc_state = val & mask; } +void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate) +{ + u32 linetime_us, val, exit_scanlines; + u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay; + struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev); + + if (WARN_ON(cstate->cpu_transcoder != TRANSCODER_A)) + return; + + linetime_us = fixed16_to_u32_round_up(intel_get_linetime_us(cstate)); + if (WARN_ON(!linetime_us)) + return; + /* + * DC3CO Exit time 200us B.Spec 49196 + * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 + * Exit line event need to program above calculated scan lines before + * next VBLANK. + */ + exit_scanlines = DIV_ROUND_UP(200, linetime_us) + 1; + if (WARN_ON(exit_scanlines > crtc_vdisplay)) + return; + + exit_scanlines = crtc_vdisplay - exit_scanlines; + exit_scanlines <<= EXITLINE_SHIFT; + val = I915_READ(EXITLINE(cstate->cpu_transcoder)); + val &= ~(EXITLINE_MASK | EXITLINE_ENABLE); + val |= exit_scanlines; + val |= EXITLINE_ENABLE; + I915_WRITE(EXITLINE(cstate->cpu_transcoder), val); +} + +static bool tgl_is_only_edp_connected(struct intel_crtc_state *crtc_state) +{ + struct drm_atomic_state *state = crtc_state->base.state; + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_connector *connector, *edp_connector = NULL; + struct drm_connector_state *connector_state; + int i; + + for_each_new_connector_in_state(state, connector, connector_state, i) { + if (connector_state->crtc != &crtc->base) + continue; + + if (connector->status == connector_status_connected && + connector->connector_type != DRM_MODE_CONNECTOR_eDP) + return false; + else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP && + connector->status == connector_status_connected) + edp_connector = connector; + } + + if (edp_connector) + return true; + + return false; +} + +/* + * tgl_prefer_dc3co_over_dc5_check check whether it is worth to choose + * DC3CO over DC5. Currently it just check crtc psr2 capebilty and only + * edp display should be connected. + * TODO: Prefer DC3CO over DC5 only in video playback. + */ +void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv, + struct intel_atomic_state *state) +{ + struct intel_crtc_state *crtc_state, *mode_changed_cstate; + struct intel_crtc *crtc; + int i; + u32 val; + + dev_priv->csr.prefer_dc3co = false; + + if (!IS_TIGERLAKE(dev_priv)) + return; + + if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)) + return; + + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { + if (crtc->pipe == PIPE_A) + mode_changed_cstate = crtc_state; + if (!crtc_state->has_psr2 && crtc_state->base.active) { + dev_priv->csr.prefer_dc3co = false; + return; + } else if (crtc_state->has_psr2) { + if (tgl_is_only_edp_connected(crtc_state) && + crtc_state->base.active) { + dev_priv->csr.prefer_dc3co = true; + continue; + } else { + dev_priv->csr.prefer_dc3co = false; + return; + } + } + } + + if (dev_priv->csr.prefer_dc3co) { + val = I915_READ(EXITLINE(mode_changed_cstate->cpu_transcoder)); + if (!(val & EXITLINE_ENABLE)) + mode_changed_cstate->base.mode_changed = true; + } +} + static void tgl_allow_dc3co(struct drm_i915_private *dev_priv) { gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index 97f2562fc5d3..46e1bcfa490a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -12,6 +12,8 @@ struct drm_i915_private; struct intel_encoder; +struct intel_crtc_state; +struct intel_atomic_state; enum intel_display_power_domain { POWER_DOMAIN_DISPLAY_CORE, @@ -246,6 +248,9 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915); void intel_display_power_resume_early(struct drm_i915_private *i915); void intel_display_power_suspend(struct drm_i915_private *i915); void intel_display_power_resume(struct drm_i915_private *i915); +void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv, + struct intel_atomic_state *state); +void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate); const char * intel_display_power_domain_str(struct drm_i915_private *i915, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3cdb5bf489f2..7ca0703209a4 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -332,6 +332,7 @@ struct intel_csr { u32 dc_state; u32 allowed_dc_mask; intel_wakeref_t wakeref; + bool prefer_dc3co; }; enum i915_cache_level { diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 780df8db2eba..634e43219164 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4584,7 +4584,7 @@ skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency, return ret; } -static uint_fixed_16_16_t +uint_fixed_16_16_t intel_get_linetime_us(const struct intel_crtc_state *crtc_state) { u32 pixel_rate; diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h index e3573e1e16e3..454e92c06dff 100644 --- a/drivers/gpu/drm/i915/intel_pm.h +++ b/drivers/gpu/drm/i915/intel_pm.h @@ -8,6 +8,7 @@ #include +#include "i915_drv.h" #include "i915_reg.h" struct drm_device; @@ -76,6 +77,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, i915_reg_t reg); u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, i915_reg_t reg); u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1); +uint_fixed_16_16_t intel_get_linetime_us(const struct intel_crtc_state *cstate); unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); unsigned long i915_mch_val(struct drm_i915_private *dev_priv); From patchwork Fri Aug 9 18:32:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11087483 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4193F1398 for ; Fri, 9 Aug 2019 18:36:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3343E201A4 for ; Fri, 9 Aug 2019 18:36:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 27A07205C0; Fri, 9 Aug 2019 18:36:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D3B08201A4 for ; Fri, 9 Aug 2019 18:36:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0E1316EE7C; Fri, 9 Aug 2019 18:36:17 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id D614A6EE7B for ; Fri, 9 Aug 2019 18:36:15 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Aug 2019 11:36:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,366,1559545200"; d="scan'208";a="193444119" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by fmsmga001.fm.intel.com with ESMTP; 09 Aug 2019 11:36:13 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sat, 10 Aug 2019 00:02:20 +0530 Message-Id: <20190809183223.12031-7-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190809183223.12031-1-anshuman.gupta@intel.com> References: <20190809183223.12031-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 6/9] drm/i915/tgl: Add VIDEO power domain X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The Power domain name VIDEO is inspired from the fact that DC3CO should be enabled only during VIDEO playback. POWER_DOMAIN_VIDEO is a hook to "DC5 Off" power well, which can disallow DC5/6 and allow DC3CO. Cc: Jani Nikula Cc: Imre Deak Cc: Animesh Manna Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++ drivers/gpu/drm/i915/display/intel_display_power.h | 1 + drivers/gpu/drm/i915/i915_drv.h | 6 ++++++ 3 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 04a02c88ff93..2667d205fa36 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -122,6 +122,8 @@ intel_display_power_domain_str(struct drm_i915_private *i915, return "VGA"; case POWER_DOMAIN_AUDIO: return "AUDIO"; + case POWER_DOMAIN_VIDEO: + return "VIDEO"; case POWER_DOMAIN_AUX_A: return "AUX_A"; case POWER_DOMAIN_AUX_B: @@ -2778,6 +2780,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, #define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ TGL_PW_2_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_VIDEO) | \ BIT_ULL(POWER_DOMAIN_MODESET) | \ BIT_ULL(POWER_DOMAIN_AUX_A) | \ BIT_ULL(POWER_DOMAIN_INIT)) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index 46e1bcfa490a..7f4dc8bd2ee4 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -66,6 +66,7 @@ enum intel_display_power_domain { POWER_DOMAIN_PORT_OTHER, POWER_DOMAIN_VGA, POWER_DOMAIN_AUDIO, + POWER_DOMAIN_VIDEO, POWER_DOMAIN_AUX_A, POWER_DOMAIN_AUX_B, POWER_DOMAIN_AUX_C, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7ca0703209a4..0a025c692118 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -333,6 +333,12 @@ struct intel_csr { u32 allowed_dc_mask; intel_wakeref_t wakeref; bool prefer_dc3co; + intel_wakeref_t dc5_wakeref; + /* + * Mutex to protect dc5_wakeref which make maintain proper + * power domain reference count of POWER_DOMAIN_VIDEO + */ + struct mutex dc5_mutex; }; enum i915_cache_level { From patchwork Fri Aug 9 18:32:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11087485 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 09E2D1398 for ; Fri, 9 Aug 2019 18:36:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EF46B201A4 for ; Fri, 9 Aug 2019 18:36:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E3A4D205C0; Fri, 9 Aug 2019 18:36:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D1015201A4 for ; Fri, 9 Aug 2019 18:36:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 55A136EE7D; Fri, 9 Aug 2019 18:36:19 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5CE686EE7F for ; Fri, 9 Aug 2019 18:36:18 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Aug 2019 11:36:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,366,1559545200"; d="scan'208";a="193444126" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by fmsmga001.fm.intel.com with ESMTP; 09 Aug 2019 11:36:15 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sat, 10 Aug 2019 00:02:21 +0530 Message-Id: <20190809183223.12031-8-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190809183223.12031-1-anshuman.gupta@intel.com> References: <20190809183223.12031-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 7/9] drm/i915/tgl: DC3CO PSR2 helper X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Add dc3co helper functions to enable/disable psr2 deep sleep. Disallow DC3CO state before PSR2 exit, it essentially does that by putting a reference to POWER_DOMAIN_VIDEO before PSR2 exit. Cc: Jani Nikula Cc: Imre Deak Cc: Animesh Manna Cc: José Roberto de Souza Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_psr.c | 44 ++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_psr.h | 2 ++ 2 files changed, 46 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index ad7044ea1efe..42f27df8445d 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -533,6 +533,49 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) I915_WRITE(EDP_PSR2_CTL, val); } +void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv) +{ + u32 val; + int idle_frames = 0; + + idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; + val = I915_READ(EDP_PSR2_CTL); + val &= ~EDP_PSR2_IDLE_FRAME_MASK; + val |= idle_frames; + I915_WRITE(EDP_PSR2_CTL, val); +} + +void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv) +{ + u32 val; + int idle_frames; + + /* + * Let's use 6 as the minimum to cover all known cases including the + * off-by-one issue that HW has in some cases. + */ + idle_frames = max(6, dev_priv->vbt.psr.idle_frames); + idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); + idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; + val = I915_READ(EDP_PSR2_CTL); + val &= ~EDP_PSR2_IDLE_FRAME_MASK; + val |= idle_frames; + I915_WRITE(EDP_PSR2_CTL, val); +} + +static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv) +{ + intel_wakeref_t wakeref __maybe_unused; + + /* Before PSR2 exit disallow dc3co*/ + mutex_lock(&dev_priv->csr.dc5_mutex); + wakeref = fetch_and_zero(&dev_priv->csr.dc5_wakeref); + if (wakeref) + intel_display_power_put(dev_priv, POWER_DOMAIN_VIDEO, + dev_priv->csr.dc5_wakeref); + mutex_unlock(&dev_priv->csr.dc5_mutex); +} + static bool intel_psr2_config_valid(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { @@ -789,6 +832,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv) } if (dev_priv->psr.psr2_enabled) { + tgl_disallow_dc3co_on_psr2_exit(dev_priv); val = I915_READ(EDP_PSR2_CTL); WARN_ON(!(val & EDP_PSR2_ENABLE)); I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE); diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index dc818826f36d..6fb4c385489c 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -36,5 +36,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp); int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state, u32 *out_value); bool intel_psr_enabled(struct intel_dp *intel_dp); +void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv); +void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv); #endif /* __INTEL_PSR_H__ */ From patchwork Fri Aug 9 18:32:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11087487 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 94F5E13B1 for ; Fri, 9 Aug 2019 18:36:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 84D8C201A4 for ; Fri, 9 Aug 2019 18:36:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 792F3205C0; Fri, 9 Aug 2019 18:36:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D8761201A4 for ; Fri, 9 Aug 2019 18:36:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 78CA76EE80; Fri, 9 Aug 2019 18:36:21 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 143176EE7F for ; Fri, 9 Aug 2019 18:36:21 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Aug 2019 11:36:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,366,1559545200"; d="scan'208";a="193444131" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by fmsmga001.fm.intel.com with ESMTP; 09 Aug 2019 11:36:18 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sat, 10 Aug 2019 00:02:22 +0530 Message-Id: <20190809183223.12031-9-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190809183223.12031-1-anshuman.gupta@intel.com> References: <20190809183223.12031-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 8/9] drm/i915/tgl: switch between dc3co and dc5 based on display idleness X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP DC3CO is useful power state, when DMC detects PSR2 idle frame while an active video playback, playing 30fps video on 60hz panel is the classic example of this use case. DC5 and DC6 saves more power, but can't be entered during video playback because there are not enough idle frames in a row to meet most PSR2 panel deep sleep entry requirement typically 4 frames. It will be worthy to enable DC3CO after completion of each flip and switch back to DC5 when display is idle, as driver doesn't differentiate between video playback and a normal flip. It is safer to allow DC5 after 6 idle frame, as PSR2 requires minimum 6 idle frame. v2: calculated s/w state to switch over dc3co when there is an update. [Imre] used cancel_delayed_work_sync() in order to avoid any race with already scheduled delayed work. [Imre] v3: cancel_delayed_work_sync() may blocked the commit work. Hence dropping it, dc5_idle_thread() checks the valid wakeref before putting the reference count, which avoids any chances of dropping a zero wakeref. [Imre (IRC)] Cc: Jani Nikula Cc: Imre Deak Cc: Animesh Manna Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_display.c | 4 + .../drm/i915/display/intel_display_power.c | 77 +++++++++++++++++++ .../drm/i915/display/intel_display_power.h | 5 ++ drivers/gpu/drm/i915/i915_drv.h | 1 + 4 files changed, 87 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 1ec204c14a10..906a8e6ec9e1 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -14082,6 +14082,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); } + + tgl_switch_to_dc3co_after_flip(dev_priv); intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); /* @@ -16157,6 +16159,7 @@ int intel_modeset_init(struct drm_device *dev) init_llist_head(&dev_priv->atomic_helper.free_list); INIT_WORK(&dev_priv->atomic_helper.free_work, intel_atomic_helper_free_state_worker); + INIT_DELAYED_WORK(&dev_priv->csr.idle_work, intel_dc5_idle_thread); intel_init_quirks(dev_priv); @@ -17100,6 +17103,7 @@ void intel_modeset_driver_remove(struct drm_device *dev) flush_workqueue(dev_priv->modeset_wq); flush_work(&dev_priv->atomic_helper.free_work); + flush_delayed_work(&dev_priv->csr.idle_work); WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list)); /* diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 2667d205fa36..31d0f389ac17 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -19,6 +19,7 @@ #include "intel_sideband.h" #include "intel_tc.h" #include "intel_pm.h" +#include "intel_psr.h" bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, enum i915_power_well_id power_well_id); @@ -825,6 +826,46 @@ void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate) I915_WRITE(EXITLINE(cstate->cpu_transcoder), val); } +void tgl_switch_to_dc3co_after_flip(struct drm_i915_private *dev_priv) +{ + struct intel_crtc *crtc; + struct intel_crtc_state *cstate; + u32 delay; + + if (!dev_priv->csr.prefer_dc3co) + return; + + mutex_lock(&dev_priv->psr.lock); + if (!dev_priv->psr.psr2_enabled || !dev_priv->psr.active) + goto unlock; + + /* + * As every flip go through intel_atomic_commit, so tracking a + * atomic commit will be a hint for idle frames. + * Delayed work for 6 idle frames will be enough to allow dc6 + * over dc3co for deepest power savings. + * At every atomic commit first cancel the delayed work , + * when delayed schedules that means display has been idle + * for the 6 idle frame. + */ + cancel_delayed_work(&dev_priv->csr.idle_work); + mutex_lock(&dev_priv->csr.dc5_mutex); + if (!dev_priv->csr.dc5_wakeref) { + dev_priv->csr.dc5_wakeref = + intel_display_power_get(dev_priv, POWER_DOMAIN_VIDEO); + tgl_psr2_deep_sleep_disable(dev_priv); + } + mutex_unlock(&dev_priv->csr.dc5_mutex); + crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A); + cstate = to_intel_crtc_state(crtc->base.state); + + delay = DC5_REQ_IDLE_FRAMES * intel_get_frame_time_us(cstate); + schedule_delayed_work(&dev_priv->csr.idle_work, + usecs_to_jiffies(delay)); +unlock: + mutex_unlock(&dev_priv->psr.lock); +} + static bool tgl_is_only_edp_connected(struct intel_crtc_state *crtc_state) { struct drm_atomic_state *state = crtc_state->base.state; @@ -898,6 +939,20 @@ void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv, } } +void intel_dc5_idle_thread(struct work_struct *work) +{ + intel_wakeref_t wakeref __maybe_unused; + struct drm_i915_private *dev_priv = + container_of(work, typeof(*dev_priv), csr.idle_work.work); + + mutex_lock(&dev_priv->csr.dc5_mutex); + wakeref = fetch_and_zero(&dev_priv->csr.dc5_wakeref); + if (wakeref) + intel_display_power_put(dev_priv, POWER_DOMAIN_VIDEO, wakeref); + tgl_psr2_deep_sleep_enable(dev_priv); + mutex_unlock(&dev_priv->csr.dc5_mutex); +} + static void tgl_allow_dc3co(struct drm_i915_private *dev_priv) { gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO); @@ -1168,6 +1223,27 @@ static bool tgl_dc3co_power_well_enabled(struct drm_i915_private *dev_priv, (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); } +u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate) +{ + u32 pixel_rate, crtc_htotal, crtc_vtotal; + u32 frametime_us; + + if (!cstate || !cstate->base.active) + return 0; + + pixel_rate = cstate->pixel_rate; + + if (WARN_ON(pixel_rate == 0)) + return 0; + + crtc_htotal = cstate->base.adjusted_mode.crtc_htotal; + crtc_vtotal = cstate->base.adjusted_mode.crtc_vtotal; + frametime_us = DIV_ROUND_UP(crtc_htotal * crtc_vtotal * 1000ULL, + pixel_rate); + + return frametime_us; +} + static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { @@ -4242,6 +4318,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) BUILD_BUG_ON(POWER_DOMAIN_NUM > 64); mutex_init(&power_domains->lock); + mutex_init(&dev_priv->csr.dc5_mutex); INIT_DELAYED_WORK(&power_domains->async_put_work, intel_display_power_put_async_work); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index 7f4dc8bd2ee4..91e3946e35fe 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -10,6 +10,8 @@ #include "intel_runtime_pm.h" #include "i915_reg.h" +#define DC5_REQ_IDLE_FRAMES 6 + struct drm_i915_private; struct intel_encoder; struct intel_crtc_state; @@ -249,9 +251,12 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915); void intel_display_power_resume_early(struct drm_i915_private *i915); void intel_display_power_suspend(struct drm_i915_private *i915); void intel_display_power_resume(struct drm_i915_private *i915); +void intel_dc5_idle_thread(struct work_struct *work); +u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate); void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv, struct intel_atomic_state *state); void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate); +void tgl_switch_to_dc3co_after_flip(struct drm_i915_private *dev_priv); const char * intel_display_power_domain_str(struct drm_i915_private *i915, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0a025c692118..6c86138c15b0 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -331,6 +331,7 @@ struct intel_csr { u32 mmiodata[20]; u32 dc_state; u32 allowed_dc_mask; + struct delayed_work idle_work; intel_wakeref_t wakeref; bool prefer_dc3co; intel_wakeref_t dc5_wakeref; From patchwork Fri Aug 9 18:32:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11087489 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EE86713B1 for ; Fri, 9 Aug 2019 18:36:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DF6BB201A4 for ; Fri, 9 Aug 2019 18:36:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D41BB205C0; Fri, 9 Aug 2019 18:36:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 914B4201A4 for ; Fri, 9 Aug 2019 18:36:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 156326EE7E; Fri, 9 Aug 2019 18:36:25 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 461C16EE81 for ; Fri, 9 Aug 2019 18:36:23 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Aug 2019 11:36:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,366,1559545200"; d="scan'208";a="193444136" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by fmsmga001.fm.intel.com with ESMTP; 09 Aug 2019 11:36:20 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sat, 10 Aug 2019 00:02:23 +0530 Message-Id: <20190809183223.12031-10-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190809183223.12031-1-anshuman.gupta@intel.com> References: <20190809183223.12031-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 9/9] drm/i915/tgl: Add DC3CO counter in i915_dmc_info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Adding DC3CO counter in i915_dmc_info debugfs will be useful for DC3CO validation. DMC firmware uses DMC_DEBUG3 register as DC3CO counter register on TGL, as per B.Specs DMC_DEBUG3 is general purpose register. Cc: Jani Nikula Cc: Imre Deak Cc: Animesh Manna Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index bddbbd959d1b..b2b310b4f6dc 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2431,6 +2431,12 @@ static int i915_dmc_info(struct seq_file *m, void *unused) seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), CSR_VERSION_MINOR(csr->version)); + /* + * TGL DMC f/w uses DMC_DEBUG3 register for DC3CO counter. + */ + if (IS_TIGERLAKE(dev_priv)) + seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3)); + if (INTEL_GEN(dev_priv) >= 12) { dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3e0783ebbbe6..bd91c6fd030f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7280,6 +7280,8 @@ enum { #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084) #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088) +#define DMC_DEBUG3 _MMIO(0x101090) + /* interrupts */ #define DE_MASTER_IRQ_CONTROL (1 << 31) #define DE_SPRITEB_FLIP_DONE (1 << 29)