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[92.34.205.44]) by smtp.gmail.com with ESMTPSA id a70sm19771242ljf.57.2019.08.10.00.44.42 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 10 Aug 2019 00:44:43 -0700 (PDT) From: Linus Walleij To: arm@kernel.org, soc@kernel.org Subject: [PATCH] ARM: dts: Update the NSPIRE DTS files for DRM Date: Sat, 10 Aug 2019 09:42:30 +0200 Message-Id: <20190810074230.6492-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190810_004446_416224_C84C2950 X-CRM114-Status: GOOD ( 15.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fabian Vogt , Daniel Tang , Linus Walleij , Sam Ravnborg , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The DRM subsystem graphics drivers require more granular definition of the connection between display drivers and panels, and a proper panel compatible. This utilizes the bindings merged to the DRM subsystem to properly define the display on the NSPIRE devices. We also do away with the undocumented DT binding "lcd-type". We add both the clocks to the CLCD block so the driver have full control over its clocking. Cc: Daniel Tang Cc: Fabian Vogt Tested-by: Fabian Vogt Acked-by: Sam Ravnborg Signed-off-by: Linus Walleij --- ARM SoC folks: Please apply this directly for v5.4 DTS changes. I have negotiated with the NSPIRE maintainers to do this change. This is a split from the v3 patch "ARM: nspire: Move CLCD set-up to device tree" so you can apply DTS changes separately. --- arch/arm/boot/dts/nspire-classic.dtsi | 15 ++++++++++++++- arch/arm/boot/dts/nspire-cx.dts | 15 ++++++++++++++- arch/arm/boot/dts/nspire.dtsi | 10 ++++++++-- 3 files changed, 36 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire-classic.dtsi index c53f42777851..41744cc2bc72 100644 --- a/arch/arm/boot/dts/nspire-classic.dtsi +++ b/arch/arm/boot/dts/nspire-classic.dtsi @@ -8,7 +8,11 @@ /include/ "nspire.dtsi" &lcd { - lcd-type = "classic"; + port { + clcd_pads: endpoint { + remote-endpoint = <&panel_in>; + }; + }; }; &fast_timer { @@ -69,6 +73,15 @@ #interrupt-cells = <1>; }; }; + + panel { + compatible = "ti,nspire-classic-lcd-panel"; + port { + panel_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + }; chosen { bootargs = "debug earlyprintk console=tty0 console=ttyS0,115200n8 root=/dev/ram0"; }; diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.dts index da95c3736651..0c16b04e2744 100644 --- a/arch/arm/boot/dts/nspire-cx.dts +++ b/arch/arm/boot/dts/nspire-cx.dts @@ -9,7 +9,11 @@ /include/ "nspire.dtsi" &lcd { - lcd-type = "cx"; + port { + clcd_pads: endpoint { + remote-endpoint = <&panel_in>; + }; + }; }; &fast_timer { @@ -106,6 +110,15 @@ }; }; }; + + panel { + compatible = "ti,nspire-cx-lcd-panel"; + port { + panel_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + }; chosen { bootargs = "debug earlyprintk console=tty0 console=ttyAMA0,115200n8 root=/dev/ram0"; }; diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi index c35fd6667716..d9a0fd7524dc 100644 --- a/arch/arm/boot/dts/nspire.dtsi +++ b/arch/arm/boot/dts/nspire.dtsi @@ -95,8 +95,14 @@ reg = <0xC0000000 0x1000>; interrupts = <21>; - clocks = <&apb_pclk>; - clock-names = "apb_pclk"; + /* + * We assume the same clock is fed to APB and CLCDCLK. + * There is some code to scale the clock down by a factor + * 48 for the display so likely the frequency to the + * display is 1MHz and the CLCDCLK is 48 MHz. + */ + clocks = <&apb_pclk>, <&apb_pclk>; + clock-names = "clcdclk", "apb_pclk"; }; adc: adc@C4000000 {