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[73.95.159.87]) by smtp.gmail.com with ESMTPSA id k6sm8386344iob.11.2019.08.10.14.51.56 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 10 Aug 2019 14:51:57 -0700 (PDT) Date: Sat, 10 Aug 2019 14:51:56 -0700 (PDT) From: Paul Walmsley X-X-Sender: paulw@viisi.sifive.com To: torvalds@linux-foundation.org Subject: [GIT PULL] RISC-V updates for v5.3-rc4 Message-ID: User-Agent: Alpine 2.21.9999 (DEB 301 2018-08-15) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190810_145159_113277_0A79CDB4 X-CRM114-Status: GOOD ( 10.41 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Linus, The following changes since commit e21a712a9685488f5ce80495b37b9fdbe96c230d: Linux 5.3-rc3 (2019-08-04 18:40:12 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv/for-v5.3-rc4 for you to fetch changes up to b390e0bfd2996f1215231395f4e25a4c011eeaf9: dt-bindings: riscv: fix the schema compatible string for the HiFive Unleashed board (2019-08-08 16:05:38 -0700) ---------------------------------------------------------------- RISC-V updates for v5.3-rc4 A few minor RISC-V updates for v5.3-rc4: - Remove __udivdi3() from the 32-bit Linux port, converting the only upstream user to use do_div(), per Linux policy - Convert the RISC-V standard clocksource away from per-cpu data structures, since only one is used by Linux, even on a multi-CPU system - A set of DT binding updates that remove an obsolete text binding in favor of a YAML binding, fix a bogus compatible string in the schema (thus fixing a "make dtbs_check" warning), and clarifies the future values expected in one of the RISC-V CPU properties ---------------------------------------------------------------- Atish Patra (2): RISC-V: Remove per cpu clocksource dt-bindings: Update the riscv,isa string description Palmer Dabbelt (1): RISC-V: Remove udivdi3 Paul Walmsley (3): riscv: delay: use do_div() instead of __udivdi3() dt-bindings: riscv: remove obsolete cpus.txt dt-bindings: riscv: fix the schema compatible string for the HiFive Unleashed board Documentation/devicetree/bindings/riscv/cpus.txt | 162 --------------------- Documentation/devicetree/bindings/riscv/cpus.yaml | 16 ++ .../devicetree/bindings/riscv/sifive.yaml | 2 +- arch/riscv/lib/Makefile | 2 - arch/riscv/lib/delay.c | 6 +- arch/riscv/lib/udivdi3.S | 32 ---- drivers/clocksource/timer-riscv.c | 6 +- 7 files changed, 24 insertions(+), 202 deletions(-) delete mode 100644 Documentation/devicetree/bindings/riscv/cpus.txt delete mode 100644 arch/riscv/lib/udivdi3.S