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[73.95.159.87]) by smtp.gmail.com with ESMTPSA id e12sm15282871iob.66.2019.08.16.18.25.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2019 18:25:41 -0700 (PDT) Date: Fri, 16 Aug 2019 18:25:40 -0700 (PDT) From: Paul Walmsley X-X-Sender: paulw@viisi.sifive.com To: torvalds@linux-foundation.org Subject: [GIT PULL] RISC-V updates for v5.3-rc5 Message-ID: User-Agent: Alpine 2.21.9999 (DEB 301 2018-08-15) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190816_182548_831002_F1AD60BD X-CRM114-Status: UNSURE ( 8.40 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Linus, The following changes since commit d45331b00ddb179e291766617259261c112db872: Linux 5.3-rc4 (2019-08-11 13:26:41 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv/for-v5.3-rc5 for you to fetch changes up to 69703eb9a8ae28a46cd5bce7d69ceeef6273a104: riscv: Make __fstate_clean() work correctly. (2019-08-14 13:20:46 -0700) ---------------------------------------------------------------- RISC-V updates for v5.3-rc5 These updates include: - Two patches to fix significant bugs in floating point register context handling - A minor fix in RISC-V flush_tlb_page(), to supply a valid end address to flush_tlb_range() - Two minor defconfig additions: to build the virtio hwrng driver by default (for QEMU targets), and to partially synchronize the 32-bit defconfig with the 64-bit defconfig ---------------------------------------------------------------- Alistair Francis (2): riscv: rv32_defconfig: Update the defconfig riscv: defconfig: Update the defconfig Paul Walmsley (1): riscv: fix flush_tlb_range() end address for flush_tlb_page() Vincent Chen (2): riscv: Correct the initialized flow of FP register riscv: Make __fstate_clean() work correctly. arch/riscv/configs/defconfig | 2 ++ arch/riscv/configs/rv32_defconfig | 3 +++ arch/riscv/include/asm/switch_to.h | 8 +++++++- arch/riscv/include/asm/tlbflush.h | 11 +++++++++-- arch/riscv/kernel/process.c | 11 +++++++++-- 5 files changed, 30 insertions(+), 5 deletions(-)