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Tue, 20 Aug 2019 09:24:53 -0700 Received: from rob-ult-m19940.microchip.com (10.10.85.251) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Tue, 20 Aug 2019 09:24:50 -0700 From: Codrin Ciubotariu To: , , Date: Tue, 20 Aug 2019 19:24:10 +0300 Message-ID: <20190820162411.24836-3-codrin.ciubotariu@microchip.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190820162411.24836-1-codrin.ciubotariu@microchip.com> References: <20190820162411.24836-1-codrin.ciubotariu@microchip.com> MIME-Version: 1.0 Cc: alexandre.belloni@bootlin.com, nicolas.ferre@microchip.com, tiwai@suse.com, ludovic.desroches@microchip.com, broonie@kernel.org, Codrin Ciubotariu Subject: [alsa-devel] [PATCH 1/3] ASoC: mchp-i2s-mcc: Wait for RX/TX RDY only if controller is running X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Since hw_free() can be called multiple times and not just after a stop trigger command, we should check whether the RX or TX ready interrupt was truly enabled previously. For this, we assure that the condition of the wait event is always true, except when RX/TX interrupts are enabled. Fixes: 7e0cdf545a55 ("ASoC: mchp-i2s-mcc: add driver for I2SC Multi-Channel Controller") Signed-off-by: Codrin Ciubotariu --- sound/soc/atmel/mchp-i2s-mcc.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/sound/soc/atmel/mchp-i2s-mcc.c b/sound/soc/atmel/mchp-i2s-mcc.c index 86495883ca3f..8272915fa09b 100644 --- a/sound/soc/atmel/mchp-i2s-mcc.c +++ b/sound/soc/atmel/mchp-i2s-mcc.c @@ -686,22 +686,24 @@ static int mchp_i2s_mcc_hw_free(struct snd_pcm_substream *substream, err = wait_event_interruptible_timeout(dev->wq_txrdy, dev->tx_rdy, msecs_to_jiffies(500)); + if (err == 0) { + dev_warn_once(dev->dev, + "Timeout waiting for Tx ready\n"); + regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, + MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)); + dev->tx_rdy = 1; + } } else { err = wait_event_interruptible_timeout(dev->wq_rxrdy, dev->rx_rdy, msecs_to_jiffies(500)); - } - - if (err == 0) { - u32 idra; - - dev_warn_once(dev->dev, "Timeout waiting for %s\n", - is_playback ? "Tx ready" : "Rx ready"); - if (is_playback) - idra = MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels); - else - idra = MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels); - regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, idra); + if (err == 0) { + dev_warn_once(dev->dev, + "Timeout waiting for Rx ready\n"); + regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, + MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)); + dev->rx_rdy = 1; + } } if (!mchp_i2s_mcc_is_running(dev)) { @@ -809,6 +811,8 @@ static int mchp_i2s_mcc_dai_probe(struct snd_soc_dai *dai) init_waitqueue_head(&dev->wq_txrdy); init_waitqueue_head(&dev->wq_rxrdy); + dev->tx_rdy = 1; + dev->rx_rdy = 1; snd_soc_dai_init_dma_data(dai, &dev->playback, &dev->capture); From patchwork Tue Aug 20 16:24:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Codrin Ciubotariu X-Patchwork-Id: 11104391 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3827714DB for ; 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Tue, 20 Aug 2019 09:24:47 -0700 From: Codrin Ciubotariu To: , , Date: Tue, 20 Aug 2019 19:24:09 +0300 Message-ID: <20190820162411.24836-2-codrin.ciubotariu@microchip.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190820162411.24836-1-codrin.ciubotariu@microchip.com> References: <20190820162411.24836-1-codrin.ciubotariu@microchip.com> MIME-Version: 1.0 Cc: alexandre.belloni@bootlin.com, nicolas.ferre@microchip.com, tiwai@suse.com, ludovic.desroches@microchip.com, broonie@kernel.org, Codrin Ciubotariu Subject: [alsa-devel] [PATCH 2/3] ASoC: mchp-i2s-mcc: Fix unprepare of GCLK X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" If hw_free() gets called after hw_params(), GCLK remains prepared, preventing further use of it. This patch fixes this by unpreparing the clock in hw_free() or if hw_params() gets an error. Fixes: 7e0cdf545a55 ("ASoC: mchp-i2s-mcc: add driver for I2SC Multi-Channel Controller") Signed-off-by: Codrin Ciubotariu --- sound/soc/atmel/mchp-i2s-mcc.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/sound/soc/atmel/mchp-i2s-mcc.c b/sound/soc/atmel/mchp-i2s-mcc.c index 8272915fa09b..ab7d5f98e759 100644 --- a/sound/soc/atmel/mchp-i2s-mcc.c +++ b/sound/soc/atmel/mchp-i2s-mcc.c @@ -670,8 +670,13 @@ static int mchp_i2s_mcc_hw_params(struct snd_pcm_substream *substream, } ret = regmap_write(dev->regmap, MCHP_I2SMCC_MRA, mra); - if (ret < 0) + if (ret < 0) { + if (dev->gclk_use) { + clk_unprepare(dev->gclk); + dev->gclk_use = 0; + } return ret; + } return regmap_write(dev->regmap, MCHP_I2SMCC_MRB, mrb); } @@ -710,9 +715,13 @@ static int mchp_i2s_mcc_hw_free(struct snd_pcm_substream *substream, regmap_write(dev->regmap, MCHP_I2SMCC_CR, MCHP_I2SMCC_CR_CKDIS); if (dev->gclk_running) { - clk_disable_unprepare(dev->gclk); + clk_disable(dev->gclk); dev->gclk_running = 0; } + if (dev->gclk_use) { + clk_unprepare(dev->gclk); + dev->gclk_use = 0; + } } return 0; From patchwork Tue Aug 20 16:24:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Codrin Ciubotariu X-Patchwork-Id: 11104395 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 09D5E14DB for ; Tue, 20 Aug 2019 16:28:21 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 91727230F2 for ; Tue, 20 Aug 2019 16:28:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=alsa-project.org header.i=@alsa-project.org header.b="M/GkT8mB" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 91727230F2 Authentication-Results: mail.kernel.org; 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d="scan'208";a="44306438" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Aug 2019 09:24:58 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 20 Aug 2019 09:24:56 -0700 Received: from rob-ult-m19940.microchip.com (10.10.85.251) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Tue, 20 Aug 2019 09:24:54 -0700 From: Codrin Ciubotariu To: , , Date: Tue, 20 Aug 2019 19:24:11 +0300 Message-ID: <20190820162411.24836-4-codrin.ciubotariu@microchip.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190820162411.24836-1-codrin.ciubotariu@microchip.com> References: <20190820162411.24836-1-codrin.ciubotariu@microchip.com> MIME-Version: 1.0 Cc: alexandre.belloni@bootlin.com, nicolas.ferre@microchip.com, tiwai@suse.com, ludovic.desroches@microchip.com, broonie@kernel.org, Codrin Ciubotariu Subject: [alsa-devel] [PATCH 3/3] ASoC: mchp-i2s-mcc: Fix simultaneous capture and playback in master mode X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" This controller supports capture and playback running at the same time, with the limitation that both capture and playback must be configured the same way (sample rate, sample format, number of channels, etc). For this, we have to assure that the configuration registers look the same when capture and playback are initiated. This patch fixes a bug in which the controller is in master mode and the hw_params() callback fails for the second audio stream. The fail occurs because the divisors are calculated after comparing the configuration registers for capture and playback. The fix consists in calculating the divisors before comparing the configuration registers. BCLK and LRC are then configured and started only if the controller is not already running. Fixes: 7e0cdf545a55 ("ASoC: mchp-i2s-mcc: add driver for I2SC Multi-Channel Controller") Signed-off-by: Codrin Ciubotariu --- sound/soc/atmel/mchp-i2s-mcc.c | 70 ++++++++++++++++++---------------- 1 file changed, 37 insertions(+), 33 deletions(-) diff --git a/sound/soc/atmel/mchp-i2s-mcc.c b/sound/soc/atmel/mchp-i2s-mcc.c index ab7d5f98e759..befc2a3a05b0 100644 --- a/sound/soc/atmel/mchp-i2s-mcc.c +++ b/sound/soc/atmel/mchp-i2s-mcc.c @@ -392,11 +392,11 @@ static int mchp_i2s_mcc_clk_get_rate_diff(struct clk *clk, } static int mchp_i2s_mcc_config_divs(struct mchp_i2s_mcc_dev *dev, - unsigned int bclk, unsigned int *mra) + unsigned int bclk, unsigned int *mra, + unsigned long *best_rate) { unsigned long clk_rate; unsigned long lcm_rate; - unsigned long best_rate = 0; unsigned long best_diff_rate = ~0; unsigned int sysclk; struct clk *best_clk = NULL; @@ -423,7 +423,7 @@ static int mchp_i2s_mcc_config_divs(struct mchp_i2s_mcc_dev *dev, (clk_rate == bclk || clk_rate / (bclk * 2) <= GENMASK(5, 0)); clk_rate += lcm_rate) { ret = mchp_i2s_mcc_clk_get_rate_diff(dev->gclk, clk_rate, - &best_clk, &best_rate, + &best_clk, best_rate, &best_diff_rate); if (ret) { dev_err(dev->dev, "gclk error for rate %lu: %d", @@ -437,7 +437,7 @@ static int mchp_i2s_mcc_config_divs(struct mchp_i2s_mcc_dev *dev, } ret = mchp_i2s_mcc_clk_get_rate_diff(dev->pclk, clk_rate, - &best_clk, &best_rate, + &best_clk, best_rate, &best_diff_rate); if (ret) { dev_err(dev->dev, "pclk error for rate %lu: %d", @@ -459,33 +459,17 @@ static int mchp_i2s_mcc_config_divs(struct mchp_i2s_mcc_dev *dev, dev_dbg(dev->dev, "source CLK is %s with rate %lu, diff %lu\n", best_clk == dev->pclk ? "pclk" : "gclk", - best_rate, best_diff_rate); - - /* set the rate */ - ret = clk_set_rate(best_clk, best_rate); - if (ret) { - dev_err(dev->dev, "unable to set rate %lu to %s: %d\n", - best_rate, best_clk == dev->pclk ? "PCLK" : "GCLK", - ret); - return ret; - } + *best_rate, best_diff_rate); /* Configure divisors */ if (dev->sysclk) - *mra |= MCHP_I2SMCC_MRA_IMCKDIV(best_rate / (2 * sysclk)); - *mra |= MCHP_I2SMCC_MRA_ISCKDIV(best_rate / (2 * bclk)); + *mra |= MCHP_I2SMCC_MRA_IMCKDIV(*best_rate / (2 * sysclk)); + *mra |= MCHP_I2SMCC_MRA_ISCKDIV(*best_rate / (2 * bclk)); - if (best_clk == dev->gclk) { + if (best_clk == dev->gclk) *mra |= MCHP_I2SMCC_MRA_SRCCLK_GCLK; - ret = clk_prepare(dev->gclk); - if (ret < 0) - dev_err(dev->dev, "unable to prepare GCLK: %d\n", ret); - else - dev->gclk_use = 1; - } else { + else *mra |= MCHP_I2SMCC_MRA_SRCCLK_PCLK; - dev->gclk_use = 0; - } return 0; } @@ -502,6 +486,7 @@ static int mchp_i2s_mcc_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { + unsigned long rate = 0; struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai); u32 mra = 0; u32 mrb = 0; @@ -640,6 +625,17 @@ static int mchp_i2s_mcc_hw_params(struct snd_pcm_substream *substream, return -EINVAL; } + if (set_divs) { + bclk_rate = frame_length * params_rate(params); + ret = mchp_i2s_mcc_config_divs(dev, bclk_rate, &mra, + &rate); + if (ret) { + dev_err(dev->dev, + "unable to configure the divisors: %d\n", ret); + return ret; + } + } + /* * If we are already running, the wanted setup must be * the same with the one that's currently ongoing @@ -656,19 +652,27 @@ static int mchp_i2s_mcc_hw_params(struct snd_pcm_substream *substream, return 0; } - /* Save the number of channels to know what interrupts to enable */ - dev->channels = channels; - - if (set_divs) { - bclk_rate = frame_length * params_rate(params); - ret = mchp_i2s_mcc_config_divs(dev, bclk_rate, &mra); + if (mra & MCHP_I2SMCC_MRA_SRCCLK_GCLK && !dev->gclk_use) { + /* set the rate */ + ret = clk_set_rate(dev->gclk, rate); if (ret) { - dev_err(dev->dev, "unable to configure the divisors: %d\n", - ret); + dev_err(dev->dev, + "unable to set rate %lu to GCLK: %d\n", + rate, ret); + return ret; + } + + ret = clk_prepare(dev->gclk); + if (ret < 0) { + dev_err(dev->dev, "unable to prepare GCLK: %d\n", ret); return ret; } + dev->gclk_use = 1; } + /* Save the number of channels to know what interrupts to enable */ + dev->channels = channels; + ret = regmap_write(dev->regmap, MCHP_I2SMCC_MRA, mra); if (ret < 0) { if (dev->gclk_use) {