From patchwork Tue Aug 27 00:32:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 11115887 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A59131800 for ; Tue, 27 Aug 2019 00:32:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 83588206BB for ; Tue, 27 Aug 2019 00:32:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Vr3HfuBB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726944AbfH0Ack (ORCPT ); Mon, 26 Aug 2019 20:32:40 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:41240 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726596AbfH0Acj (ORCPT ); Mon, 26 Aug 2019 20:32:39 -0400 Received: by mail-pl1-f196.google.com with SMTP id m9so10845334pls.8; Mon, 26 Aug 2019 17:32:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=kyP8YtTFMbDNG7qsSo2w5pZq5BUurmqPvqGOvI+33I4=; b=Vr3HfuBBvU+CvPCGdWp3sLwJb2EtL3a9crXIjuQJSWLjl5ksVMgCgkQNSbaHfaCgo1 4nfBkArMmecu23vp5/O6l0b6QwewovlkmdsPr5K+025s1D+TeJE19WvYtWYy/O9Qzvn9 JatA0M6TBp9aWACMyhrP6RPT+DKL1YP0HkDf/cggIQNR6bgaKLsX10Q7R64XSeQeyoAz h4hHMg83fEt4ogVHkfndekQJSxP0niAuzDW0/uzDhMJIF5Kpmr2QHomtV0JF/0tEDRQw GdXqNiD6KogTLeuPK/1R4vFN0+6MSnq5ikb/pElZ/3TadmgpmkWxNMpksCw3QXGQSYma Y7dQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=kyP8YtTFMbDNG7qsSo2w5pZq5BUurmqPvqGOvI+33I4=; b=nmVFPLiypy2JIFLj4MYqAec+izWC6itsjoEEx+YX845l3sH2AZwy+WhL2cTbA+3YvU VurK40F3AxIftXJ76m1yHWRveqYWoh05QYLus5uvPJrUI9LNI0ZlBladUyjg4rPA4dZL iL2afecsBp/gstPPNQyVc45u150YQcT8bTvdOXexWJaUVF9ldheU4M9BuXq0pSiqALxP C9Avugt/LOtP3ND+zOW934WN/TJd2x+Rq0Y0m2LV4SQ1bk4E0asY6/EKCw1/3dM6VESS F08sX/NJlclAkvtYdnOZyHWcvIfIyzJklTTfzk2kJihNRU/RXAWFfw2AiJu07xi3ZnMu qPaA== X-Gm-Message-State: APjAAAVIocUJlDAZG6KOzOwrB0A1pbI8cQ5CgESzNJOn8XFc8xihQk3o 4hyTAI7x6S3LtymO15hYbig= X-Google-Smtp-Source: APXvYqz3ZmR1zugYM2VmnZ+ecV9ZHk+8pBBQ39SEGbJDivdoJ7PQszjh2Nwlp3kG0uQUU22i6Tfntw== X-Received: by 2002:a17:902:a706:: with SMTP id w6mr6406893plq.166.1566865959290; Mon, 26 Aug 2019 17:32:39 -0700 (PDT) Received: from gli-arch.genesyslogic.com.tw (60-251-58-169.HINET-IP.hinet.net. [60.251.58.169]) by smtp.gmail.com with ESMTPSA id e13sm14828075pfl.130.2019.08.26.17.32.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2019 17:32:38 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, johnsonm@danlj.org, ben.chuang@genesyslogic.com.tw, Ben Chuang Subject: [PATCH V6 1/5] mmc: sdhci: Change timeout of loop for checking internal clock stable Date: Tue, 27 Aug 2019 08:32:42 +0800 Message-Id: <20190827003242.2298-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.22.1 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ben Chuang According to section 3.2.1 internal clock setup in SD Host Controller Simplified Specifications 4.20, the timeout of loop for checking internal clock stable is defined as 150ms. Signed-off-by: Ben Chuang Co-developed-by: Michael K Johnson Signed-off-by: Michael K Johnson Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 59acf8e3331e..bed0760a6c2a 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1636,8 +1636,8 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) clk |= SDHCI_CLOCK_INT_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); - /* Wait max 20 ms */ - timeout = ktime_add_ms(ktime_get(), 20); + /* Wait max 150 ms */ + timeout = ktime_add_ms(ktime_get(), 150); while (1) { bool timedout = ktime_after(ktime_get(), timeout); From patchwork Tue Aug 27 00:32:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 11115889 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3E04214F7 for ; Tue, 27 Aug 2019 00:32:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1BB1F2080C for ; Tue, 27 Aug 2019 00:32:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KuztGt+n" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728030AbfH0Acy (ORCPT ); Mon, 26 Aug 2019 20:32:54 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:36765 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726596AbfH0Acy (ORCPT ); Mon, 26 Aug 2019 20:32:54 -0400 Received: by mail-pl1-f195.google.com with SMTP id f19so10858364plr.3; Mon, 26 Aug 2019 17:32:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=189g0JP68z9u+Ep1GWrcVIMocc6+TBCdAX4Yd+2DXKM=; b=KuztGt+nXT1gTEb5csKxCYy4+7BmsyakHzvzGyMtFyRqmTySJrI0NB05w5Fuz9nO48 Llgge4WwGN02rS9wUnnTdnQ/8KTvKkSVAK65Xvz5ruXm9HJ/x1L8jehOEu+pr3Jswa54 zxMllUu66M0CF70bAOEpGjK/3v9U9Jk77jgDAboFs3uCWkTdLWejqzFeJULd0F7pPcr6 UlRxO4l5oBhdnM0UBeXqxOcYZV8N5GzwoAt92jTFDJWGTaer2jdvopGcTkdP7Hsou0gA lkrMHx0BxVijrWQ12Br1pQ1jJdTf+Onhh3C1RgDPJdei85GLeIvbroXUB+2PDB3DPSgq ormQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=189g0JP68z9u+Ep1GWrcVIMocc6+TBCdAX4Yd+2DXKM=; b=n19u1XSsm0hIZVvdPB8vvBY9RqSIdtkDlEI4Oi0nprZ/IZlBzDdAaSYUsjBIDqFbu3 Ho5G+KNW+F4sivtBkEbciW4vtVkTW4rMlUbNdrLl6P8U7BSkb5nU8HSX7DmJMIN7tfT8 2lHDEP/DBGW77KfzhmDG5/T7ZsYpUVrvDG14jl+bcIUP3Z/6XCsyGmyif9S/WH4ys1If kw2IRx52259qE10XGQKxPSL4XWIlX9f5B/0hOoXEeugC/o+GsUVZBU2yAKx6kih/6EHI 3u1QyAd4jZiwfTJeyNOCVe7eLTG/m6Ql4eTHyFP5K09XTeNQCSf2GW40b9AlUD5Mf8mh hIQg== X-Gm-Message-State: APjAAAXO9Z9iPkE44ZdzXObvMLEtKbCp6fP8Vk0YzSgUkkTesAF2S7V/ xZD8aeH9qrEp5pd7yJLpwQs= X-Google-Smtp-Source: APXvYqyNdNPY19KQGF32db9ueEkPRVWw5IgAFygk1tLqn7BQl/o/Or77fI0K590F0VOLTbX0RU66mQ== X-Received: by 2002:a17:902:5c3:: with SMTP id f61mr20153314plf.98.1566865973709; Mon, 26 Aug 2019 17:32:53 -0700 (PDT) Received: from gli-arch.genesyslogic.com.tw (60-251-58-169.HINET-IP.hinet.net. [60.251.58.169]) by smtp.gmail.com with ESMTPSA id l7sm7444220pff.35.2019.08.26.17.32.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2019 17:32:52 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, johnsonm@danlj.org, ben.chuang@genesyslogic.com.tw, Ben Chuang Subject: [PATCH V6 2/5] mmc: sdhci: Add PLL Enable support to internal clock setup Date: Tue, 27 Aug 2019 08:32:55 +0800 Message-Id: <20190827003255.2347-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.22.1 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ben Chuang The GL9750 and GL9755 chipsets, and possibly others, require PLL Enable setup as part of the internal clock setup as described in 3.2.1 Internal Clock Setup Sequence of SD Host Controller Simplified Specification Version 4.20. Signed-off-by: Ben Chuang Co-developed-by: Michael K Johnson Signed-off-by: Michael K Johnson Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 23 +++++++++++++++++++++++ drivers/mmc/host/sdhci.h | 1 + 2 files changed, 24 insertions(+) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index bed0760a6c2a..9106ebc7a422 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1653,6 +1653,29 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) udelay(10); } + if (host->version >= SDHCI_SPEC_410 && host->v4_mode) { + clk |= SDHCI_CLOCK_PLL_EN; + clk &= ~SDHCI_CLOCK_INT_STABLE; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + /* Wait max 150 ms */ + timeout = ktime_add_ms(ktime_get(), 150); + while (1) { + bool timedout = ktime_after(ktime_get(), timeout); + + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + if (clk & SDHCI_CLOCK_INT_STABLE) + break; + if (timedout) { + pr_err("%s: PLL clock never stabilised.\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return; + } + udelay(10); + } + } + clk |= SDHCI_CLOCK_CARD_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); } diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 199712e7adbb..72601a4d2e95 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -114,6 +114,7 @@ #define SDHCI_DIV_HI_MASK 0x300 #define SDHCI_PROG_CLOCK_MODE 0x0020 #define SDHCI_CLOCK_CARD_EN 0x0004 +#define SDHCI_CLOCK_PLL_EN 0x0008 #define SDHCI_CLOCK_INT_STABLE 0x0002 #define SDHCI_CLOCK_INT_EN 0x0001 From patchwork Tue Aug 27 00:33:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 11115891 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CBB9013B1 for ; Tue, 27 Aug 2019 00:33:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A7B722054F for ; Tue, 27 Aug 2019 00:33:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="oeNqzRpB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727124AbfH0AdI (ORCPT ); Mon, 26 Aug 2019 20:33:08 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:43659 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726596AbfH0AdH (ORCPT ); Mon, 26 Aug 2019 20:33:07 -0400 Received: by mail-pg1-f193.google.com with SMTP id k3so11576544pgb.10; Mon, 26 Aug 2019 17:33:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=qfHiLZajGyQDnbfm/jvtW9Y9R5M2p7DW5ZQEIckHoIU=; b=oeNqzRpBOf1WKNRgs/IebvxB57essXsARVv57FHwN023+Zxq5pvi28VtnBy0pUiZh5 mtKmgMfBkMPGR6j+VAQJqhwCYCB4mIVbbeaH/ctUOEh2yePgYlfsovTP/T1c10kpCA1+ gUkVUmSEDOkgYL8VT+K87l1q3Wto0QUxQYyT9vxuxtt1Jji24ZZyUCEFPxsahMBrLo3P Iofxt9xhF/RHMzWaR1W57seEoDXzdc5vfmFas68ynA9rujTU/T/jDCNoGWxNE6N9/Mtu k8mSDDhZcNet6/hVv26Di+JDN/VwR6AqlaH81dWvVeNGIvCto/rQOE4RvTkKAKMbV+dq ghzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=qfHiLZajGyQDnbfm/jvtW9Y9R5M2p7DW5ZQEIckHoIU=; b=HCx8AIJKSaQrDTELXBUczj4fZo8L3C1W6VU0VEtZlyaNk9zjrUS7ng8eFilwt4oHDQ usswQd9O4duNPO57bTe7FNIlSAZKyJo54cjzmPxsAFRR/XHS0+Gp7rm30vl+OGJfBAEs MuI235xGIlqK83GSvfcw0WT4ZxRFF+/DdYi3XXzMSa6TC8r2WXLDoylMdmdY5DUGjhk8 WxDZvFZLpYXQ5fymHCApsi1siPTBLCE37rC31W9ieVMjdtv9vNjMXvFsAsldmshyeO51 YaFgXnKrxEgUSAK42OdOm8ADZBu3O7nuukAjgKP2GSeWG+udzJdGhydKMbqekyTs7u8b BpNg== X-Gm-Message-State: APjAAAWnTiFP28oslbrDfV/dbcqM2rnq9/EuEUHTOrZDNodWDfs7pItl Z7bfErXmmVkxnEmflkw9/io= X-Google-Smtp-Source: APXvYqyG8UTLiMR0zDYDuKpQEr99DrhgoWhmcYelhIj05sV+7k3BgI16BFkxD/mmOG/Expd2e/zwpw== X-Received: by 2002:a65:41c6:: with SMTP id b6mr18694490pgq.269.1566865987217; Mon, 26 Aug 2019 17:33:07 -0700 (PDT) Received: from gli-arch.genesyslogic.com.tw (60-251-58-169.HINET-IP.hinet.net. [60.251.58.169]) by smtp.gmail.com with ESMTPSA id k3sm508582pjo.3.2019.08.26.17.33.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2019 17:33:06 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, johnsonm@danlj.org, ben.chuang@genesyslogic.com.tw, Ben Chuang Subject: [PATCH V6 3/5] PCI: Add Genesys Logic, Inc. Vendor ID Date: Tue, 27 Aug 2019 08:33:09 +0800 Message-Id: <20190827003309.2396-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.22.1 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ben Chuang Add the Genesys Logic, Inc. vendor ID to pci_ids.h. Signed-off-by: Ben Chuang Co-developed-by: Michael K Johnson Signed-off-by: Michael K Johnson Acked-by: Adrian Hunter --- include/linux/pci_ids.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 70e86148cb1e..4f7e12772a14 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2403,6 +2403,8 @@ #define PCI_DEVICE_ID_RDC_R6061 0x6061 #define PCI_DEVICE_ID_RDC_D1010 0x1010 +#define PCI_VENDOR_ID_GLI 0x17a0 + #define PCI_VENDOR_ID_LENOVO 0x17aa #define PCI_VENDOR_ID_QCOM 0x17cb From patchwork Tue Aug 27 00:33:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 11115893 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 01D6813B1 for ; Tue, 27 Aug 2019 00:33:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D2CA720673 for ; Tue, 27 Aug 2019 00:33:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="tIBrEHni" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726678AbfH0AdU (ORCPT ); Mon, 26 Aug 2019 20:33:20 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:45177 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726596AbfH0AdU (ORCPT ); Mon, 26 Aug 2019 20:33:20 -0400 Received: by mail-pg1-f193.google.com with SMTP id o13so11582690pgp.12; Mon, 26 Aug 2019 17:33:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=n7+sVYqdxpLe5mIpwExuqi9YJ4e/DMZsey8GaSh+g3U=; b=tIBrEHnigI/eO8+DqVievvAJ0iiXeG4bgq+gtA0yve51p/wWam0jg8qwhjybHbY+ZU 2eRv6vASzoerWnyQHuIc/bpYb3IbPhES/KpAYV7vOWnjkwNXszJeR05aTjissuS/D1Do WUGkKDXRmFCCisxNNd7iaW+gOpBFuh207cSazd+9H/EdlolAEFaFGyk/balsUb1APm0T wUm3nbBEpXVHLPb2/lLlSZ2mIJ34YdS7ByyzoDnRDXqZwDvUpQCIATmbz9FuGRY+UsRq bnIs5gIaD3df0UAYNi/Wl+FQUa7fuXG3pwNjtmnFvAB0BRL1Ba5GWJQGNxdlQwoyqXHB ioKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=n7+sVYqdxpLe5mIpwExuqi9YJ4e/DMZsey8GaSh+g3U=; b=isUpXBNhS5ZkrUE+RzBjhgsYoJhZMXI0DkSBSiyQi8NcG8UVUNG+kI9cB3eRVMNRJg fT3Rua+QGwdA/V2KRiqCxPMpxRRwilpEAAtH9VZkRAWuFmXDbvjuOz0HocadSLpfC9iR qr2Dr3hoJBVJE6lFUwVTpDwiaFppV0ylEJEQjUE0gfxXLX1vraPjj8wP97Kkvj8qL8ez c7WmYoNwkBS6aR1mNV65NyAH/+FEV3N+5F4XNqkk2+rm08J7+6qlt61+PuNKJm9llRn6 ndRm7PYfr1C8Ug4XCEArHnazMMTwRb0MJOBu0aZYw7GB4MQ+S5aIso3xnVdQUDfjvOFZ 1MIw== X-Gm-Message-State: APjAAAUl8bV+uvR3m74r10GZN2iCyICup/1nLVHae1najSqdUcIPAuXW yjVDwgbAZc/Ul5vejn1b88k= X-Google-Smtp-Source: APXvYqzgruKmhT1BbYpLtT/VhTwCRvQzEWzH2u04GCGwn+pKudxllttb2V56VanAeKAaFh3jIiV5vw== X-Received: by 2002:a62:d0:: with SMTP id 199mr23097357pfa.157.1566865999446; Mon, 26 Aug 2019 17:33:19 -0700 (PDT) Received: from gli-arch.genesyslogic.com.tw (60-251-58-169.HINET-IP.hinet.net. [60.251.58.169]) by smtp.gmail.com with ESMTPSA id r4sm14371142pfl.127.2019.08.26.17.33.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2019 17:33:18 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, johnsonm@danlj.org, ben.chuang@genesyslogic.com.tw, Ben Chuang Subject: [PATCH V6 4/5] mmc: sdhci: Export sdhci_abort_tuning function symbol Date: Tue, 27 Aug 2019 08:33:22 +0800 Message-Id: <20190827003322.2445-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.22.1 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ben Chuang Export sdhci_abort_tuning() function symbols which are used by other SD Host controller driver modules. Signed-off-by: Ben Chuang Co-developed-by: Michael K Johnson Signed-off-by: Michael K Johnson Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 3 ++- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 9106ebc7a422..0f2f110534db 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2328,7 +2328,7 @@ void sdhci_reset_tuning(struct sdhci_host *host) } EXPORT_SYMBOL_GPL(sdhci_reset_tuning); -static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode) +void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode) { sdhci_reset_tuning(host); @@ -2339,6 +2339,7 @@ static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode) mmc_abort_tuning(host->mmc, opcode); } +EXPORT_SYMBOL_GPL(sdhci_abort_tuning); /* * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 72601a4d2e95..437bab3af195 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -797,5 +797,6 @@ void sdhci_start_tuning(struct sdhci_host *host); void sdhci_end_tuning(struct sdhci_host *host); void sdhci_reset_tuning(struct sdhci_host *host); void sdhci_send_tuning(struct sdhci_host *host, u32 opcode); +void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode); #endif /* __SDHCI_HW_H */ From patchwork Tue Aug 27 00:33:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 11115895 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 25CC014F7 for ; Tue, 27 Aug 2019 00:33:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EB89E20673 for ; Tue, 27 Aug 2019 00:33:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="nYYRaH+H" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728391AbfH0Add (ORCPT ); Mon, 26 Aug 2019 20:33:33 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:35606 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726596AbfH0Add (ORCPT ); Mon, 26 Aug 2019 20:33:33 -0400 Received: by mail-pf1-f195.google.com with SMTP id d85so12920068pfd.2; Mon, 26 Aug 2019 17:33:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=T2qfXAOzBkKONr1D7gAvKeuCZNsV3DxCRylYnjCYyJU=; b=nYYRaH+HM1YBYw4ZVd4OOraYsb7gEf+zg5z592juVKAJIVia5DBkFjy8a+grLFHwtI 0A0ZbtdvNjEigkXCL/MzRKPoeo4p6+V26tFnqqAXipgnLkKOSMq85UPE+8/B/7nqSTnd WU1whHH+2Fc9G+xJwJ73ws6TxzNLKdQun+W/C86GMmlSbzR6JGlpYik8trZaxpmibUl+ 8ucKm3kO8o6kfmB4PcbqEeKZ+ySWtUrwXNOnWi7KExS2rFCzFh3KWfGJ38mShew4dqYw 2Bd540kJtjFq0wjTAdAAhTRfTTB2N1p9H0r3/F/yU7kjtXVXQ/hUtvd+5EQ+1BijV/T1 a0/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=T2qfXAOzBkKONr1D7gAvKeuCZNsV3DxCRylYnjCYyJU=; b=BA1UJhYNgN0tdiqEypU2RsQwnep8DJpGDjtKJHaxsy4IkPfL7yQiviZwzWlsOtb8g2 LLvrt3A0UqRav74jU9+1VG8PzR3jM+/pWek4hJCxMrgz0KwI2ZKSGIaZdpbclLUMBk6t mvhKiTnmxyJJdQrZTYk/slpw7/F+ijAYYcWrlK6otu5ZbeHGw+fdyIiBcehb3dnI2FFr X7eAxeOhPrne6nadCNp5b0zUIgkl95PScZKuc8qXkj7DeulllZl3myeynAd5ly5lS7x4 ICOGDOc04hMr0E7c1tjwaAKMM/tpXgjAHKwZ3KAQlxhfIRQlkgLmuDmpo8YOjxSjIWHJ LNNg== X-Gm-Message-State: APjAAAUlxwVAhCdlBhELCusUjCOTvLTV1JPWbWkTW3Gx/CY/glL0+Qpu Ndi084+ysuwLiS1gonpaIpzFctWd X-Google-Smtp-Source: APXvYqz8+HKbrlFf6IxI5Y5b/BT6mc7tM5Uzli66SoeFFxln9eKu4UNtls3Zc18l/oJAfC33gWlMdQ== X-Received: by 2002:a62:f245:: with SMTP id y5mr23245108pfl.156.1566866012401; Mon, 26 Aug 2019 17:33:32 -0700 (PDT) Received: from gli-arch.genesyslogic.com.tw (60-251-58-169.HINET-IP.hinet.net. [60.251.58.169]) by smtp.gmail.com with ESMTPSA id j5sm10137640pgp.59.2019.08.26.17.33.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2019 17:33:31 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, johnsonm@danlj.org, ben.chuang@genesyslogic.com.tw, Ben Chuang Subject: [PATCH V6 5/5] mmc: host: sdhci-pci: Add Genesys Logic GL975x support Date: Tue, 27 Aug 2019 08:33:35 +0800 Message-Id: <20190827003335.2494-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.22.1 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ben Chuang Add support for the GL9750 and GL9755 chipsets. Enable v4 mode and wait 5ms after set 1.8V signal enable for GL9750/ GL9755. Fix the value of SDHCI_MAX_CURRENT register and use the vendor tuning flow for GL9750. Signed-off-by: Ben Chuang Co-developed-by: Michael K Johnson Signed-off-by: Michael K Johnson --- drivers/mmc/host/Makefile | 2 +- drivers/mmc/host/sdhci-pci-core.c | 2 + drivers/mmc/host/sdhci-pci-gli.c | 354 ++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-pci.h | 5 + 4 files changed, 362 insertions(+), 1 deletion(-) create mode 100644 drivers/mmc/host/sdhci-pci-gli.c diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 73578718f119..661445415090 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -13,7 +13,7 @@ obj-$(CONFIG_MMC_MXS) += mxs-mmc.o obj-$(CONFIG_MMC_SDHCI) += sdhci.o obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o sdhci-pci-y += sdhci-pci-core.o sdhci-pci-o2micro.o sdhci-pci-arasan.o \ - sdhci-pci-dwc-mshc.o + sdhci-pci-dwc-mshc.o sdhci-pci-gli.o obj-$(subst m,y,$(CONFIG_MMC_SDHCI_PCI)) += sdhci-pci-data.o obj-$(CONFIG_MMC_SDHCI_ACPI) += sdhci-acpi.o obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c index 4154ee11b47d..e5835fbf73bc 100644 --- a/drivers/mmc/host/sdhci-pci-core.c +++ b/drivers/mmc/host/sdhci-pci-core.c @@ -1682,6 +1682,8 @@ static const struct pci_device_id pci_ids[] = { SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), + SDHCI_PCI_DEVICE(GLI, 9750, gl9750), + SDHCI_PCI_DEVICE(GLI, 9755, gl9755), SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), /* Generic SD host controller */ {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c new file mode 100644 index 000000000000..d0ca3c60f8de --- /dev/null +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -0,0 +1,354 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Genesys Logic, Inc. + * + * Authors: Ben Chuang + * + * Version: v0.9.0 (2019-08-08) + */ + +#include +#include +#include +#include +#include +#include "sdhci.h" +#include "sdhci-pci.h" + +/* Genesys Logic extra registers */ +#define SDHCI_GLI_9750_WT 0x800 +#define SDHCI_GLI_9750_WT_EN BIT(0) +#define GLI_9750_WT_EN_ON 0x1 +#define GLI_9750_WT_EN_OFF 0x0 + +#define SDHCI_GLI_9750_DRIVING 0x860 +#define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0) +#define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26) +#define GLI_9750_DRIVING_1_VALUE 0xFFF +#define GLI_9750_DRIVING_2_VALUE 0x3 + +#define SDHCI_GLI_9750_PLL 0x864 +#define SDHCI_GLI_9750_PLL_TX2_INV BIT(23) +#define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20) +#define GLI_9750_PLL_TX2_INV_VALUE 0x1 +#define GLI_9750_PLL_TX2_DLY_VALUE 0x0 + +#define SDHCI_GLI_9750_SW_CTRL 0x874 +#define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6) +#define GLI_9750_SW_CTRL_4_VALUE 0x3 + +#define SDHCI_GLI_9750_MISC 0x878 +#define SDHCI_GLI_9750_MISC_TX1_INV BIT(2) +#define SDHCI_GLI_9750_MISC_RX_INV BIT(3) +#define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4) +#define GLI_9750_MISC_TX1_INV_VALUE 0x0 +#define GLI_9750_MISC_RX_INV_ON 0x1 +#define GLI_9750_MISC_RX_INV_OFF 0x0 +#define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF +#define GLI_9750_MISC_TX1_DLY_VALUE 0x5 + +#define SDHCI_GLI_9750_TUNING_CONTROL 0x540 +#define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4) +#define GLI_9750_TUNING_CONTROL_EN_ON 0x1 +#define GLI_9750_TUNING_CONTROL_EN_OFF 0x0 +#define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16) +#define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19) +#define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1 +#define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2 + +#define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544 +#define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0) +#define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1 + +#define GLI_MAX_TUNING_LOOP 40 + +/* Genesys Logic chipset */ +static inline void gl9750_wt_on(struct sdhci_host *host) +{ + u32 wt_value = 0; + u32 wt_enable = 0; + + wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); + wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); + + if (wt_enable == GLI_9750_WT_EN_ON) + return; + + wt_value &= ~SDHCI_GLI_9750_WT_EN; + wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON); + + sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); +} + +static inline void gl9750_wt_off(struct sdhci_host *host) +{ + u32 wt_value = 0; + u32 wt_enable = 0; + + wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); + wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); + + if (wt_enable == GLI_9750_WT_EN_OFF) + return; + + wt_value &= ~SDHCI_GLI_9750_WT_EN; + wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF); + + sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); +} + +static void gli_set_9750(struct sdhci_host *host) +{ + u32 driving_value = 0; + u32 pll_value = 0; + u32 sw_ctrl_value = 0; + u32 misc_value = 0; + u32 parameter_value = 0; + u32 control_value = 0; + + u16 ctrl2 = 0; + + gl9750_wt_on(host); + + driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); + pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); + sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); + misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); + parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS); + control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); + + driving_value &= ~(SDHCI_GLI_9750_DRIVING_1); + driving_value &= ~(SDHCI_GLI_9750_DRIVING_2); + driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1, + GLI_9750_DRIVING_1_VALUE); + driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2, + GLI_9750_DRIVING_2_VALUE); + sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING); + + sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4; + sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4, + GLI_9750_SW_CTRL_4_VALUE); + sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL); + + /* reset the tuning flow after reinit and before starting tuning */ + pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; + pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; + pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, + GLI_9750_PLL_TX2_INV_VALUE); + pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, + GLI_9750_PLL_TX2_DLY_VALUE); + + misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV; + misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; + misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY; + misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV, + GLI_9750_MISC_TX1_INV_VALUE); + misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, + GLI_9750_MISC_RX_INV_VALUE); + misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY, + GLI_9750_MISC_TX1_DLY_VALUE); + + parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY; + parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY, + GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE); + + control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1; + control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2; + control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1, + GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE); + control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2, + GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE); + + sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); + sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); + + /* disable tuned clk */ + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; + sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); + + /* enable tuning parameters control */ + control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; + control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, + GLI_9750_TUNING_CONTROL_EN_ON); + sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); + + /* write tuning parameters */ + sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS); + + /* disable tuning parameters control */ + control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; + control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, + GLI_9750_TUNING_CONTROL_EN_OFF); + sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); + + /* clear tuned clk */ + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; + sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); + + udelay(1); + + gl9750_wt_off(host); +} + +static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b) +{ + u32 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); + + gl9750_wt_on(host); + + misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); + if (b) { + misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; + misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, + GLI_9750_MISC_RX_INV_ON); + sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); + } else { + misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; + misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, + GLI_9750_MISC_RX_INV_OFF); + sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); + } + + gl9750_wt_off(host); +} + +static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode) +{ + int i; + int rx_inv = 0; + + for (rx_inv = 0; rx_inv < 2; rx_inv++) { + if (rx_inv & 0x1) + gli_set_9750_rx_inv(host, true); + else + gli_set_9750_rx_inv(host, false); + + sdhci_start_tuning(host); + + for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) { + u16 ctrl; + + sdhci_send_tuning(host, opcode); + + if (!host->tuning_done) { + if (rx_inv == 1) { + pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", + mmc_hostname(host->mmc)); + sdhci_abort_tuning(host, opcode); + return -ETIMEDOUT; + } + sdhci_abort_tuning(host, opcode); + break; + } + + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { + if (ctrl & SDHCI_CTRL_TUNED_CLK) + return 0; /* Success! */ + break; + } + } + } + + pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", + mmc_hostname(host->mmc)); + sdhci_reset_tuning(host); + return -EAGAIN; +} + +static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode) +{ + host->mmc->retune_period = 0; + if (host->tuning_mode == SDHCI_TUNING_MODE_1) + host->mmc->retune_period = host->tuning_count; + + gli_set_9750(host); + host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); + sdhci_end_tuning(host); + + return 0; +} + +static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) +{ + struct sdhci_host *host = slot->host; + + slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; + sdhci_enable_v4_mode(host); + + return 0; +} + +static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot) +{ + struct sdhci_host *host = slot->host; + + slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; + sdhci_enable_v4_mode(host); + + return 0; +} + +static void sdhci_gli_voltage_switch(struct sdhci_host *host) +{ + usleep_range(5000, 5500); +} + +static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask) +{ + sdhci_reset(host, mask); + gli_set_9750(host); +} + +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS +static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg) +{ + u32 value; + + value = readl(host->ioaddr + reg); + if (unlikely(reg == SDHCI_MAX_CURRENT)) { + if (!(value & 0xff)) + value |= 0xc8; + } + return value; +} +#endif + +static const struct sdhci_ops sdhci_gl9755_ops = { + .set_clock = sdhci_set_clock, + .enable_dma = sdhci_pci_enable_dma, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, + .voltage_switch = sdhci_gli_voltage_switch, +}; + +const struct sdhci_pci_fixes sdhci_gl9755 = { + .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, + .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, + .probe_slot = gli_probe_slot_gl9755, + .ops = &sdhci_gl9755_ops, +}; + +static const struct sdhci_ops sdhci_gl9750_ops = { +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS + .read_l = sdhci_gl9750_readl, +#endif + .set_clock = sdhci_set_clock, + .enable_dma = sdhci_pci_enable_dma, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_gl9750_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, + .voltage_switch = sdhci_gli_voltage_switch, + .platform_execute_tuning = gl9750_execute_tuning, +}; + +const struct sdhci_pci_fixes sdhci_gl9750 = { + .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, + .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, + .probe_slot = gli_probe_slot_gl9750, + .ops = &sdhci_gl9750_ops, +}; + diff --git a/drivers/mmc/host/sdhci-pci.h b/drivers/mmc/host/sdhci-pci.h index e5dc6e44c7a4..738ba5afcc20 100644 --- a/drivers/mmc/host/sdhci-pci.h +++ b/drivers/mmc/host/sdhci-pci.h @@ -65,6 +65,9 @@ #define PCI_DEVICE_ID_SYNOPSYS_DWC_MSHC 0xc202 +#define PCI_DEVICE_ID_GLI_9755 0x9755 +#define PCI_DEVICE_ID_GLI_9750 0x9750 + /* * PCI device class and mask */ @@ -185,5 +188,7 @@ int sdhci_pci_enable_dma(struct sdhci_host *host); extern const struct sdhci_pci_fixes sdhci_arasan; extern const struct sdhci_pci_fixes sdhci_snps; extern const struct sdhci_pci_fixes sdhci_o2; +extern const struct sdhci_pci_fixes sdhci_gl9750; +extern const struct sdhci_pci_fixes sdhci_gl9755; #endif /* __SDHCI_PCI_H */