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x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.22.1 x-originating-ip: [78.144.179.23] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 644dbfb9-d19c-4f71-0d22-08d72e29952d x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600166)(711020)(4605104)(1401327)(2017052603328)(7193020);SRVR:MWHPR2201MB1311; x-ms-traffictypediagnostic: MWHPR2201MB1311: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:3173; x-forefront-prvs: 014617085B x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(396003)(39840400004)(376002)(136003)(366004)(346002)(199004)(189003)(2501003)(14454004)(386003)(102836004)(42882007)(6506007)(186003)(52116002)(476003)(2616005)(486006)(44832011)(26005)(2351001)(6916009)(1076003)(478600001)(5660300002)(71190400001)(66446008)(64756008)(66556008)(71200400001)(66476007)(2906002)(107886003)(66946007)(8936002)(81156014)(6116002)(66066001)(5640700003)(8676002)(6486002)(50226002)(316002)(6512007)(256004)(6436002)(53936002)(99286004)(25786009)(305945005)(36756003)(7736002)(4326008)(81166006)(3846002);DIR:OUT;SFP:1102;SCL:1;SRVR:MWHPR2201MB1311;H:MWHPR2201MB1277.namprd22.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: wavecomp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: om0E0F18SrW1kEdTCx0zOidTtzdd+n05OOiz+Z60XW1etCFp2VrZYZrXH7yRzNxdFs13TUutKX2hZRIUOfnTKnNd4lIFhaMFqpQcURf1/jt9+iAERrqGvziIn5rLf2mefGDwvYWz8zFlJ6CVAV00RR9nMIQZIePGAhigubdU+3ZUsUsdVpye4VgQrriINqc444zXFS4dUoFwIuduBjTQG4SKLzKjejxa5yAjH+c/s+TjdI3NmZhVewji9oNHivmniZgcV7RiSHM3aakDgIkJmv7PNECMq4LJtZkfePPQi1Ph437vjxqC7mB0WEbE5YmFWVsDjjD9fFbA6Eu8vkqDbiPg6843omC2hEDtdj1HGIJXSmRNheMTAHAWZMO3XX/KSOBa3vrCu7+IHLFn5/YZTg6UREFXwcEDh+JsZvHiPX8= MIME-Version: 1.0 X-OriginatorOrg: mips.com X-MS-Exchange-CrossTenant-Network-Message-Id: 644dbfb9-d19c-4f71-0d22-08d72e29952d X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Aug 2019 15:40:43.1397 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 4J4QbC3zpRQIlAp3t0DcEzCTAXUGKAAb6OQOBUI4xa9VUlLEUmv9dPf8Ng4TxNF1HAuTNnFYFBAc1eYYuhEa/g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR2201MB1311 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Currently areas where we need to determine whether the TLB is R3k-style need to check for either of CONFIG_CPU_R3000 || CONFIG_CPU_TX39XX. Introduce a new CONFIG_CPU_R3K_TLB & select it from both of the above, allowing us to simplify checks for R3k-style TLBs by only checking for this new Kconfig option. Signed-off-by: Paul Burton Reviewed-by: Philippe Mathieu-Daudé --- arch/mips/Kconfig | 7 ++++++- arch/mips/include/asm/pgtable-32.h | 4 ++-- arch/mips/include/asm/pgtable-bits.h | 6 +++--- arch/mips/include/asm/pgtable.h | 4 ++-- arch/mips/mm/Makefile | 5 +++-- 5 files changed, 16 insertions(+), 10 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 31c7044e34e6..3f18aa018a0c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1575,6 +1575,7 @@ config CPU_R3000 depends on SYS_HAS_CPU_R3000 select CPU_HAS_WB select CPU_HAS_LOAD_STORE_LR + select CPU_R3K_TLB select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_HIGHMEM help @@ -1590,6 +1591,7 @@ config CPU_TX39XX depends on SYS_HAS_CPU_TX39XX select CPU_SUPPORTS_32BIT_KERNEL select CPU_HAS_LOAD_STORE_LR + select CPU_R3K_TLB config CPU_VR41XX bool "R41xx" @@ -2280,6 +2282,9 @@ config CPU_R2300_FPU depends on MIPS_FP_SUPPORT default y if CPU_R3000 || CPU_TX39XX +config CPU_R3K_TLB + bool + config CPU_R4K_FPU bool depends on MIPS_FP_SUPPORT @@ -2287,7 +2292,7 @@ config CPU_R4K_FPU config CPU_R4K_CACHE_TLB bool - default y if !(CPU_R3000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON) + default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON) config MIPS_MT_SMP bool "MIPS MT SMP support (1 TC on each available VPE)" diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h index e600570789f4..ba967148b016 100644 --- a/arch/mips/include/asm/pgtable-32.h +++ b/arch/mips/include/asm/pgtable-32.h @@ -221,7 +221,7 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) #define pte_unmap(pte) ((void)(pte)) -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) +#if defined(CONFIG_CPU_R3K_TLB) /* Swap entries must have VALID bit cleared. */ #define __swp_type(x) (((x).val >> 10) & 0x1f) @@ -266,6 +266,6 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */ -#endif /* defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) */ +#endif /* defined(CONFIG_CPU_R3K_TLB) */ #endif /* _ASM_PGTABLE_32_H */ diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index c2c1060b43ef..5f1ced8cba07 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -82,7 +82,7 @@ enum pgtable_bits { _PAGE_SPECIAL_SHIFT, }; -#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) +#elif defined(CONFIG_CPU_R3K_TLB) /* Page table bits used for r3k systems */ enum pgtable_bits { @@ -151,7 +151,7 @@ enum pgtable_bits { #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) +#if defined(CONFIG_CPU_R3K_TLB) # define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT) # define _CACHE_MASK _CACHE_UNCACHED # define _PFN_SHIFT PAGE_SHIFT @@ -209,7 +209,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) /* * Cache attributes */ -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) +#if defined(CONFIG_CPU_R3K_TLB) #define _CACHE_CACHABLE_NONCOHERENT 0 #define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index d60f47a9088c..4dca733d5076 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -199,7 +199,7 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt static inline void set_pte(pte_t *ptep, pte_t pteval) { *ptep = pteval; -#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX) +#if !defined(CONFIG_CPU_R3K_TLB) if (pte_val(pteval) & _PAGE_GLOBAL) { pte_t *buddy = ptep_buddy(ptep); /* @@ -218,7 +218,7 @@ static inline void set_pte(pte_t *ptep, pte_t pteval) static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { htw_stop(); -#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX) +#if !defined(CONFIG_CPU_R3K_TLB) /* Preserve global status for the pair */ if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL) set_pte_at(mm, addr, ptep, __pte(_PAGE_GLOBAL)); diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 949d43eefda1..46f483e952c8 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -28,10 +28,11 @@ obj-$(CONFIG_HIGHMEM) += highmem.o obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o obj-$(CONFIG_DMA_NONCOHERENT) += dma-noncoherent.o +obj-$(CONFIG_CPU_R3K_TLB) += tlb-r3k.o obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o +obj-$(CONFIG_CPU_R3000) += c-r3k.o obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o -obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o +obj-$(CONFIG_CPU_TX39XX) += c-tx39.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o From patchwork Sat Aug 31 15:40:44 2019 Content-Type: text/plain; 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received-spf: None (protection.outlook.com: wavecomp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: mmcho0xPzZGd1qXWdn6DJrwWOznCEqulFzo9cAq3xUirj7aM8XbO0PiVxtLcIC75llh5t34xZNRzEta8ZcHiCojO6Zh2o83NxyVcIKR4AIKHQgcWW5K2DMF11qe864X1KrgI11aZWsFsgcRF9r7HPkgn3x5T/5gOM32cDFXft7HyDxQdOQrmjrz+dxEqzDipF4RxuEHjsovqwE+hwIhpPQwy+w2w8aLLJbSGDz4gg/mXoNz8gQ+eG1rkFa1Hs2kmARRC82KRattCv7zJrL8x5DoNHSvg13EVgjsPD9EJQo8VRBZ5NIdjHzb6bTZCvqlPEymDVMVZQpePeUvXU+0jKfKkHwTYv4HPIjvVPiEF5RQP3gk31AZ8dGToOI0A/kq2ycYuornNBl07abb2gvZWp87WdZJAk5umE9bIW3dc6+U= MIME-Version: 1.0 X-OriginatorOrg: mips.com X-MS-Exchange-CrossTenant-Network-Message-Id: 47ab72a2-61c1-47fd-9550-08d72e299651 X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Aug 2019 15:40:44.9039 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ERDEtui8uu8EmEENuhJON7lm0076XcPgcvX23HvNzp7fYSJcQq2SE6WBPYbjsANPz/D2yWVNqTH5zGNEwV6HbA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR2201MB1311 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org We already know whether a CPU has r3k style exceptions, including TLB exceptions, by checking cpu_has_3kex. Remove the list of CPU types in build_tlb_refill_handler() & check cpu_has_3kex instead. Signed-off-by: Paul Burton --- arch/mips/mm/tlbex.c | 52 +++++++++++++++++++------------------------- 1 file changed, 22 insertions(+), 30 deletions(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 071d48593464..6e3ca9cc5249 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -2607,14 +2607,7 @@ void build_tlb_refill_handler(void) check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); #endif - switch (current_cpu_type()) { - case CPU_R2000: - case CPU_R3000: - case CPU_R3000A: - case CPU_R3081E: - case CPU_TX3912: - case CPU_TX3922: - case CPU_TX3927: + if (cpu_has_3kex) { #ifndef CONFIG_MIPS_PGD_C0_CONTEXT if (cpu_has_local_ebase) build_r3000_tlb_refill_handler(); @@ -2631,30 +2624,29 @@ void build_tlb_refill_handler(void) #else panic("No R3000 TLB refill handler"); #endif - break; + return; + } - default: - if (cpu_has_ldpte) - setup_pw(); + if (cpu_has_ldpte) + setup_pw(); - if (!run_once) { - scratch_reg = allocate_kscratch(); - build_setup_pgd(); - build_r4000_tlb_load_handler(); - build_r4000_tlb_store_handler(); - build_r4000_tlb_modify_handler(); - if (cpu_has_ldpte) - build_loongson3_tlb_refill_handler(); - else if (!cpu_has_local_ebase) - build_r4000_tlb_refill_handler(); - flush_tlb_handlers(); - run_once++; - } - if (cpu_has_local_ebase) + if (!run_once) { + scratch_reg = allocate_kscratch(); + build_setup_pgd(); + build_r4000_tlb_load_handler(); + build_r4000_tlb_store_handler(); + build_r4000_tlb_modify_handler(); + if (cpu_has_ldpte) + build_loongson3_tlb_refill_handler(); + else if (!cpu_has_local_ebase) build_r4000_tlb_refill_handler(); - if (cpu_has_xpa) - config_xpa_params(); - if (cpu_has_htw) - config_htw_params(); + flush_tlb_handlers(); + run_once++; } + if (cpu_has_local_ebase) + build_r4000_tlb_refill_handler(); + if (cpu_has_xpa) + config_xpa_params(); + if (cpu_has_htw) + config_htw_params(); } From patchwork Sat Aug 31 15:40:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 11124931 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 29532112C for ; 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Sat, 31 Aug 2019 15:40:46 +0000 Received: from MWHPR2201MB1277.namprd22.prod.outlook.com ([fe80::f9e8:5e8c:7194:fad3]) by MWHPR2201MB1277.namprd22.prod.outlook.com ([fe80::f9e8:5e8c:7194:fad3%11]) with mapi id 15.20.2220.013; Sat, 31 Aug 2019 15:40:46 +0000 From: Paul Burton To: "linux-mips@vger.kernel.org" CC: Paul Burton Subject: [PATCH 3/3] MIPS: tlbex: Remove cpu_has_local_ebase Thread-Topic: [PATCH 3/3] MIPS: tlbex: Remove cpu_has_local_ebase Thread-Index: AQHVYBJ0xEIBPHvDYUCMR3MGJkqWlQ== Date: Sat, 31 Aug 2019 15:40:46 +0000 Message-ID: <20190831154027.6943-3-paul.burton@mips.com> References: <20190831154027.6943-1-paul.burton@mips.com> In-Reply-To: <20190831154027.6943-1-paul.burton@mips.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: LO2P265CA0161.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:9::29) To MWHPR2201MB1277.namprd22.prod.outlook.com (2603:10b6:301:18::12) authentication-results: spf=none (sender IP is ) smtp.mailfrom=pburton@wavecomp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.22.1 x-originating-ip: [78.144.179.23] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 87039808-faa3-4fed-d535-08d72e29974f x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600166)(711020)(4605104)(1401327)(2017052603328)(7193020);SRVR:MWHPR2201MB1311; x-ms-traffictypediagnostic: MWHPR2201MB1311: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:4303; x-forefront-prvs: 014617085B x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(396003)(39840400004)(376002)(136003)(366004)(346002)(199004)(189003)(2501003)(14454004)(386003)(102836004)(42882007)(6506007)(186003)(52116002)(476003)(2616005)(486006)(44832011)(26005)(11346002)(446003)(76176011)(2351001)(6916009)(1076003)(478600001)(5660300002)(71190400001)(66446008)(64756008)(66556008)(71200400001)(66476007)(2906002)(107886003)(66946007)(8936002)(81156014)(6116002)(66066001)(5640700003)(8676002)(6486002)(50226002)(316002)(6512007)(256004)(6436002)(53936002)(99286004)(25786009)(305945005)(36756003)(7736002)(4326008)(81166006)(3846002);DIR:OUT;SFP:1102;SCL:1;SRVR:MWHPR2201MB1311;H:MWHPR2201MB1277.namprd22.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: wavecomp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: r4KnfjbpFgCvMdAPsNSgKrs3ksMhSAqxJaUmDTKLX3R6Iwf3sEh24DJJz1XgAPQ7mmMwk3PNVv3QO78u8i6Jo8jrvj5RldVQpAGCNTd0TPgYdfbzWjnBi89fiwqhMsqBXaTswpoGcbrgfQhLC50v6kMTZ/6fOhgshUCoqpJetwD4PRzWiUZCv1V0ESytCZOuh767n/ndFUUPLqrYgT6iTsgRRcpBlRwL/99sPsdqeUTrrwslrZ1ISdHOuqcn9/EK8B3HQ3VwOk/YpZ9YQ/ZOXqySy61PR7dSj5ILpsVe5oteEMEU5rqnwdVs6NCpbzpoHXyiYIUNjO4+otnIsuicBjIsgtWq9nF7JJUWsQF5DOY5XBzMJL/feTvh7jK+oiea0+hWgUckFGOnUX18rTZnCS4bJnT2OzgzMS6qvR1PZ/k= MIME-Version: 1.0 X-OriginatorOrg: mips.com X-MS-Exchange-CrossTenant-Network-Message-Id: 87039808-faa3-4fed-d535-08d72e29974f X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Aug 2019 15:40:46.5771 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: GyqOPZlNTZcc7kwjz3AIq0hYHpdlcCGxv938YVLD2MnKFA+7xFJcbAiDhlBnEWszjjN/UFzUpNzsE/Siuq+U2Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR2201MB1311 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The cpu_has_local_ebase macro is, confusingly, not used to indicate whether the EBase register is local to a CPU or not. Instead it indicates whether we want to generate the TLB refill exception vector each time a CPU is brought online. Doing this makes little sense on any system, since we always use the same value for EBase & thus we cannot have different TLB refill exception handlers per CPU. Regenerating the code is not only pointless but also can be actively harmful, as commit 8759934e2b6b ("MIPS: Build uasm-generated code only once to avoid CPU Hotplug problem") described. That commit introduced cpu_has_local_ebase to disable the handler regeneration for Loongson machines, but this is by no means a Loongson-specific problem. Remove cpu_has_local_ebase & simply generate the TLB refill handler once during boot, just like the rest of the TLB exception handlers. Signed-off-by: Paul Burton Reviewed-by: Philippe Mathieu-Daudé --- arch/mips/include/asm/cpu-features.h | 3 --- arch/mips/include/asm/mach-dec/cpu-feature-overrides.h | 1 - .../include/asm/mach-loongson64/cpu-feature-overrides.h | 1 - arch/mips/mm/tlbex.c | 9 ++------- 4 files changed, 2 insertions(+), 12 deletions(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 4e2bea8875f5..983a6a7f43a1 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -243,9 +243,6 @@ #ifndef cpu_has_pindexed_dcache #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) #endif -#ifndef cpu_has_local_ebase -#define cpu_has_local_ebase 1 -#endif /* * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors diff --git a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h index 1c11310bc8ad..00beb69bfab9 100644 --- a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h @@ -32,7 +32,6 @@ #define cpu_has_vtag_icache 0 #define cpu_has_ic_fills_f_dc 0 #define cpu_has_pindexed_dcache 0 -#define cpu_has_local_ebase 0 #define cpu_icache_snoops_remote_store 1 #define cpu_has_mips_4 0 #define cpu_has_mips_5 0 diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h index 581915ce231c..4aca25f2ff06 100644 --- a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h @@ -43,7 +43,6 @@ #define cpu_has_vint 0 #define cpu_has_vtag_icache 0 #define cpu_has_watch 1 -#define cpu_has_local_ebase 0 #ifdef CONFIG_CPU_LOONGSON3 #define cpu_has_wsbh 1 diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 6e3ca9cc5249..e01cb33bfa1a 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -2609,12 +2609,9 @@ void build_tlb_refill_handler(void) if (cpu_has_3kex) { #ifndef CONFIG_MIPS_PGD_C0_CONTEXT - if (cpu_has_local_ebase) - build_r3000_tlb_refill_handler(); if (!run_once) { - if (!cpu_has_local_ebase) - build_r3000_tlb_refill_handler(); build_setup_pgd(); + build_r3000_tlb_refill_handler(); build_r3000_tlb_load_handler(); build_r3000_tlb_store_handler(); build_r3000_tlb_modify_handler(); @@ -2638,13 +2635,11 @@ void build_tlb_refill_handler(void) build_r4000_tlb_modify_handler(); if (cpu_has_ldpte) build_loongson3_tlb_refill_handler(); - else if (!cpu_has_local_ebase) + else build_r4000_tlb_refill_handler(); flush_tlb_handlers(); run_once++; } - if (cpu_has_local_ebase) - build_r4000_tlb_refill_handler(); if (cpu_has_xpa) config_xpa_params(); if (cpu_has_htw)