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received-spf: None (protection.outlook.com: wavecomp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: GgAcsCruhsJjAhif7g/vsxfwjMte8TKDGu6rKlY/m8439/8nX7DQVfL3YBXMBhKZkcXok/QYGpU35jA2DEmblRJ7UwfNIWwLUvBWDKQ/g4LljfGTtEPJB2tCrejgq4RrIGG22b/cN4Po9snwEzWSIaA9wZ6A/nc06HwzxkcP8PlWYJ/fZP19PwG0es7BQB2i4bbKCXKf8fe0Yy7TRXSmpdrkg9coa1b3hIWfHNxGP0FOl2oIgQ0WinLttlTqT06sxjetwqmL8TPU8WBMWjUUgo0TmCH1UBrimE8M+Tv5PavTr1b16dSKtfySESI/h7ki4yXsTuURxN9Xg+ZFZ3QqDyVxM5aHIdzgaBMJDJQOHCMYGUZW9aPYDlxdOhOzMt9K3xT0VTE7zIUlEQ7xMwsYPgzkDuoQVaZY5I9SjvCeBtk= MIME-Version: 1.0 X-OriginatorOrg: mips.com X-MS-Exchange-CrossTenant-Network-Message-Id: d9786fee-dc71-4517-78f6-08d72e29c280 X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Aug 2019 15:41:59.0999 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: IflHQJCOTXEGv58XYz/KZ4oaXolwA5vCE1CwicPTdaNOKTMuVJkFITm43q5M5EVXS/ynKvd7Q7PPrWItZtVF9w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR2201MB1311 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org _CACHE_CACHABLE_NONCOHERENT is defined as 3<<_CACHE_SHIFT by default, so there's no need to define it as such specifically for Loongson. _CACHE_CACHABLE_COHERENT is not used anywhere in the kernel, so there's no need to define it at all. Finally the comment found alongside these definitions seems incorrect - it suggests that we're defining _CACHE_CACHABLE_NONCOHERENT such that it actually provides coherence, but the opposite seems to be true & instead the unused _CACHE_CACHABLE_COHERENT is defined as the typically incoherent value. Delete the whole thing, which will have no effect on the compiled code anyway. Signed-off-by: Paul Burton Cc: Huacai Chen Signed-off-by: Paul Burton Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang --- arch/mips/include/asm/pgtable-bits.h | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index 5f1ced8cba07..409ae01ed7be 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -221,13 +221,6 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) -#elif defined(CONFIG_CPU_LOONGSON3) - -/* Using COHERENT flag for NONCOHERENT doesn't hurt. */ - -#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */ -#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */ - #elif defined(CONFIG_MACH_INGENIC) /* Ingenic uses the WA bit to achieve write-combine memory writes */