From patchwork Sun Sep 1 12:45:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Karlman X-Patchwork-Id: 11125211 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CA3D016B1 for ; Sun, 1 Sep 2019 12:45:50 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9E11C2342E for ; Sun, 1 Sep 2019 12:45:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="e8phW0ZD" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9E11C2342E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kwiboo.se Authentication-Results: mail.kernel.org; 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mx.microsoft.com 1; spf=none; dmarc=none; dkim=none; arc=none Received: from HE1EUR01FT057.eop-EUR01.prod.protection.outlook.com (10.152.0.59) by HE1EUR01HT179.eop-EUR01.prod.protection.outlook.com (10.152.1.126) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2220.16; Sun, 1 Sep 2019 12:45:42 +0000 Received: from HE1PR06MB4011.eurprd06.prod.outlook.com (10.152.0.52) by HE1EUR01FT057.mail.protection.outlook.com (10.152.0.208) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2220.16 via Frontend Transport; Sun, 1 Sep 2019 12:45:42 +0000 Received: from HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088]) by HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088%3]) with mapi id 15.20.2199.021; Sun, 1 Sep 2019 12:45:42 +0000 From: Jonas Karlman To: Ezequiel Garcia Subject: [PATCH 01/12] media: hantro: Fix H264 max frmsize supported on RK3288 Thread-Topic: [PATCH 01/12] media: hantro: Fix H264 max frmsize supported on RK3288 Thread-Index: AQHVYMMqh0O1621DYkuOLEeadywFIw== Date: Sun, 1 Sep 2019 12:45:42 +0000 Message-ID: References: In-Reply-To: Accept-Language: sv-SE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR05CA0343.eurprd05.prod.outlook.com (2603:10a6:7:92::38) To HE1PR06MB4011.eurprd06.prod.outlook.com (2603:10a6:7:9c::32) x-incomingtopheadermarker: OriginalChecksum:E1514A37C9D7278A24BB76B869499CC712EEAC020295903F4667AD66EA69CB9B; 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X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [40.92.64.56 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Kocialkowski , Jonas Karlman , "linux-kernel@vger.kernel.org" , Hans Verkuil , "linux-rockchip@lists.infradead.org" , Boris Brezillon , Philipp Zabel , Mauro Carvalho Chehab , "linux-media@vger.kernel.org" Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org TRM specify supported image size 48x48 to 4096x2304 at step size 16 pixels, change frmsize max_width/max_height to match TRM. Fixes: 760327930e10 ("media: hantro: Enable H264 decoding on rk3288") Signed-off-by: Jonas Karlman --- drivers/staging/media/hantro/rk3288_vpu_hw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/hantro/rk3288_vpu_hw.c b/drivers/staging/media/hantro/rk3288_vpu_hw.c index 6bfcc47d1e58..ebb017b8a334 100644 --- a/drivers/staging/media/hantro/rk3288_vpu_hw.c +++ b/drivers/staging/media/hantro/rk3288_vpu_hw.c @@ -67,10 +67,10 @@ static const struct hantro_fmt rk3288_vpu_dec_fmts[] = { .max_depth = 2, .frmsize = { .min_width = 48, - .max_width = 3840, + .max_width = 4096, .step_width = H264_MB_DIM, .min_height = 48, - .max_height = 2160, + .max_height = 2304, .step_height = H264_MB_DIM, }, }, From patchwork Sun Sep 1 12:45:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Karlman X-Patchwork-Id: 11125213 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C689516B1 for ; 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Sun, 1 Sep 2019 12:45:42 +0000 Received: from HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088]) by HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088%3]) with mapi id 15.20.2199.021; Sun, 1 Sep 2019 12:45:42 +0000 From: Jonas Karlman To: Ezequiel Garcia Subject: [PATCH 02/12] media: hantro: Do not reorder H264 scaling list Thread-Topic: [PATCH 02/12] media: hantro: Do not reorder H264 scaling list Thread-Index: AQHVYMMq6YIWopjAr0aH2udYAseNuA== Date: Sun, 1 Sep 2019 12:45:42 +0000 Message-ID: References: <20190901124531.23645-1-jonas@kwiboo.se> In-Reply-To: <20190901124531.23645-1-jonas@kwiboo.se> Accept-Language: sv-SE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR05CA0343.eurprd05.prod.outlook.com (2603:10a6:7:92::38) To HE1PR06MB4011.eurprd06.prod.outlook.com (2603:10a6:7:9c::32) x-incomingtopheadermarker: OriginalChecksum:94139BD92D4B6A7610A355ABD0C5C5D13E1EF91C454E923A5ECEE17C7364C21A; UpperCasedChecksum:488F5FE270DE9730CFE88A52E7ABFBFCEE65275B567FCF83F55AFA38CBF86A6B; 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The HW also only support 8x8 scaling list for the Y component, indices 0 and 3 in the scaling list supplied from userspace. Remove reordering and write the scaling matrix in an order expected by the VPU, also only allocate memory for the two 8x8 lists used. Fixes: a9471e25629b ("media: hantro: Add core bits to support H264 decoding") Signed-off-by: Jonas Karlman --- drivers/staging/media/hantro/hantro_h264.c | 64 +++++++--------------- 1 file changed, 20 insertions(+), 44 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c index 0d758e0c0f99..e2d01145ac4f 100644 --- a/drivers/staging/media/hantro/hantro_h264.c +++ b/drivers/staging/media/hantro/hantro_h264.c @@ -20,7 +20,7 @@ /* Size with u32 units. */ #define CABAC_INIT_BUFFER_SIZE (460 * 2) #define POC_BUFFER_SIZE 34 -#define SCALING_LIST_SIZE (6 * 16 + 6 * 64) +#define SCALING_LIST_SIZE (6 * 16 + 2 * 64) #define POC_CMP(p0, p1) ((p0) < (p1) ? -1 : 1) @@ -194,57 +194,33 @@ static const u32 h264_cabac_table[] = { 0x1f0c2517, 0x1f261440 }; -/* - * NOTE: The scaling lists are in zig-zag order, apply inverse scanning process - * to get the values in matrix order. In addition, the hardware requires bytes - * swapped within each subsequent 4 bytes. Both arrays below include both - * transformations. - */ -static const u32 zig_zag_4x4[] = { - 3, 2, 7, 11, 6, 1, 0, 5, 10, 15, 14, 9, 4, 8, 13, 12 -}; - -static const u32 zig_zag_8x8[] = { - 3, 2, 11, 19, 10, 1, 0, 9, 18, 27, 35, 26, 17, 8, 7, 6, - 15, 16, 25, 34, 43, 51, 42, 33, 24, 23, 14, 5, 4, 13, 22, 31, - 32, 41, 50, 59, 58, 49, 40, 39, 30, 21, 12, 20, 29, 38, 47, 48, - 57, 56, 55, 46, 37, 28, 36, 45, 54, 63, 62, 53, 44, 52, 61, 60 -}; - static void reorder_scaling_list(struct hantro_ctx *ctx) { const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; const struct v4l2_ctrl_h264_scaling_matrix *scaling = ctrls->scaling; - const size_t num_list_4x4 = ARRAY_SIZE(scaling->scaling_list_4x4); - const size_t list_len_4x4 = ARRAY_SIZE(scaling->scaling_list_4x4[0]); - const size_t num_list_8x8 = ARRAY_SIZE(scaling->scaling_list_8x8); - const size_t list_len_8x8 = ARRAY_SIZE(scaling->scaling_list_8x8[0]); struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu; - u8 *dst = tbl->scaling_list; - const u8 *src; - int i, j; - - BUILD_BUG_ON(ARRAY_SIZE(zig_zag_4x4) != list_len_4x4); - BUILD_BUG_ON(ARRAY_SIZE(zig_zag_8x8) != list_len_8x8); - BUILD_BUG_ON(ARRAY_SIZE(tbl->scaling_list) != - num_list_4x4 * list_len_4x4 + - num_list_8x8 * list_len_8x8); - - src = &scaling->scaling_list_4x4[0][0]; - for (i = 0; i < num_list_4x4; ++i) { - for (j = 0; j < list_len_4x4; ++j) - dst[zig_zag_4x4[j]] = src[j]; - src += list_len_4x4; - dst += list_len_4x4; + u32 *dst = (u32 *)tbl->scaling_list; + u32 i, j, tmp; + + for (i = 0; i < ARRAY_SIZE(scaling->scaling_list_4x4); i++) { + for (j = 0; j < ARRAY_SIZE(scaling->scaling_list_4x4[0]) / 4; j++) { + tmp = (scaling->scaling_list_4x4[i][4 * j + 0] << 24) | + (scaling->scaling_list_4x4[i][4 * j + 1] << 16) | + (scaling->scaling_list_4x4[i][4 * j + 2] << 8) | + (scaling->scaling_list_4x4[i][4 * j + 3]); + *dst++ = tmp; + } } - src = &scaling->scaling_list_8x8[0][0]; - for (i = 0; i < num_list_8x8; ++i) { - for (j = 0; j < list_len_8x8; ++j) - dst[zig_zag_8x8[j]] = src[j]; - src += list_len_8x8; - dst += list_len_8x8; + for (i = 0; i < ARRAY_SIZE(scaling->scaling_list_8x8); i += 3) { + for (j = 0; j < ARRAY_SIZE(scaling->scaling_list_8x8[0]) / 4; j++) { + tmp = (scaling->scaling_list_8x8[i][4 * j + 0] << 24) | + (scaling->scaling_list_8x8[i][4 * j + 1] << 16) | + (scaling->scaling_list_8x8[i][4 * j + 2] << 8) | + (scaling->scaling_list_8x8[i][4 * j + 3]); + *dst++ = tmp; + } } } From patchwork Sun Sep 1 12:45:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Karlman X-Patchwork-Id: 11125215 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F0A811395 for ; Sun, 1 Sep 2019 12:45:52 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C35AB233A2 for ; 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Sun, 1 Sep 2019 12:45:43 +0000 Received: from HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088]) by HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088%3]) with mapi id 15.20.2199.021; Sun, 1 Sep 2019 12:45:43 +0000 From: Jonas Karlman To: Ezequiel Garcia Subject: [PATCH 03/12] media: hantro: Fix H264 motion vector buffer offset Thread-Topic: [PATCH 03/12] media: hantro: Fix H264 motion vector buffer offset Thread-Index: AQHVYMMqTL16PRzVbkakeBcuIqgT/g== Date: Sun, 1 Sep 2019 12:45:43 +0000 Message-ID: References: <20190901124531.23645-1-jonas@kwiboo.se> In-Reply-To: <20190901124531.23645-1-jonas@kwiboo.se> Accept-Language: sv-SE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR05CA0343.eurprd05.prod.outlook.com (2603:10a6:7:92::38) To HE1PR06MB4011.eurprd06.prod.outlook.com (2603:10a6:7:9c::32) x-incomingtopheadermarker: OriginalChecksum:7B3B7B4361546BE563588277909E8130A217913F21AEC558698F98757A841C47; UpperCasedChecksum:62E16AB91CC13DA896C7ED5FE7A5F6CF9B54B9F7E43A760B5B5C0B2C667E4B2F; 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Wrong offset for both destination and motion vector buffer are used for the bottom field of field encoded content, wrong offset is also used for 4:0:0 (monochrome) content. Fix this by always setting the motion vector address to the expected 384 MBs offset for 4:2:0 and 256 MBs offset for 4:0:0 content. Also use correct destination and motion vector buffer offset for the bottom field of field encoded content. While at it also extend the check for 4:0:0 (monochrome) to include an additional check for High Profile (100). Fixes: dea0a82f3d22 ("media: hantro: Add support for H264 decoding on G1") Signed-off-by: Jonas Karlman --- .../staging/media/hantro/hantro_g1_h264_dec.c | 33 +++++++++++-------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c index 7ab534936843..159bd67e0a36 100644 --- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c +++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c @@ -19,6 +19,9 @@ #include "hantro_hw.h" #include "hantro_v4l2.h" +#define MV_OFFSET_420 384 +#define MV_OFFSET_400 256 + static void set_params(struct hantro_ctx *ctx) { const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; @@ -49,8 +52,8 @@ static void set_params(struct hantro_ctx *ctx) vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0); /* Decoder control register 1. */ - reg = G1_REG_DEC_CTRL1_PIC_MB_WIDTH(sps->pic_width_in_mbs_minus1 + 1) | - G1_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(sps->pic_height_in_map_units_minus1 + 1) | + reg = G1_REG_DEC_CTRL1_PIC_MB_WIDTH(H264_MB_WIDTH(ctx->dst_fmt.width)) | + G1_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(H264_MB_HEIGHT(ctx->dst_fmt.height)) | G1_REG_DEC_CTRL1_REF_FRAMES(sps->max_num_ref_frames); vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1); @@ -79,7 +82,7 @@ static void set_params(struct hantro_ctx *ctx) reg |= G1_REG_DEC_CTRL4_CABAC_E; if (sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) reg |= G1_REG_DEC_CTRL4_DIR_8X8_INFER_E; - if (sps->chroma_format_idc == 0) + if (sps->profile_idc >= 100 && sps->chroma_format_idc == 0) reg |= G1_REG_DEC_CTRL4_BLACKWHITE_E; if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) reg |= G1_REG_DEC_CTRL4_WEIGHT_PRED_E; @@ -233,6 +236,7 @@ static void set_buffers(struct hantro_ctx *ctx) struct vb2_v4l2_buffer *src_buf, *dst_buf; struct hantro_dev *vpu = ctx->dev; dma_addr_t src_dma, dst_dma; + unsigned int offset = MV_OFFSET_420; src_buf = hantro_get_src_buf(ctx); dst_buf = hantro_get_dst_buf(ctx); @@ -243,19 +247,20 @@ static void set_buffers(struct hantro_ctx *ctx) /* Destination (decoded frame) buffer. */ dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); + if (ctrls->slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) + dst_dma += ALIGN(ctx->dst_fmt.width, H264_MB_DIM); vdpu_write_relaxed(vpu, dst_dma, G1_REG_ADDR_DST); - /* Higher profiles require DMV buffer appended to reference frames. */ - if (ctrls->sps->profile_idc > 66) { - size_t pic_size = ctx->h264_dec.pic_size; - size_t mv_offset = round_up(pic_size, 8); - - if (ctrls->slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) - mv_offset += 32 * H264_MB_WIDTH(ctx->dst_fmt.width); - - vdpu_write_relaxed(vpu, dst_dma + mv_offset, - G1_REG_ADDR_DIR_MV); - } + /* Motion vector buffer is located after the decoded frame. */ + dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); + if (ctrls->sps->profile_idc >= 100 && ctrls->sps->chroma_format_idc == 0) + offset = MV_OFFSET_400; + dst_dma += offset * H264_MB_WIDTH(ctx->dst_fmt.width) * + H264_MB_HEIGHT(ctx->dst_fmt.height); + if (ctrls->slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) + dst_dma += 32 * H264_MB_WIDTH(ctx->dst_fmt.width) * + H264_MB_HEIGHT(ctx->dst_fmt.height); + vdpu_write_relaxed(vpu, dst_dma, G1_REG_ADDR_DIR_MV); /* Auxiliary buffer prepared in hantro_g1_h264_dec_prepare_table(). */ vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, G1_REG_ADDR_QTABLE); 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mx.microsoft.com 1; spf=none; dmarc=none; dkim=none; arc=none Received: from HE1EUR01FT057.eop-EUR01.prod.protection.outlook.com (10.152.0.54) by HE1EUR01HT115.eop-EUR01.prod.protection.outlook.com (10.152.1.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2220.16; Sun, 1 Sep 2019 12:45:44 +0000 Received: from HE1PR06MB4011.eurprd06.prod.outlook.com (10.152.0.52) by HE1EUR01FT057.mail.protection.outlook.com (10.152.0.208) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2220.16 via Frontend Transport; Sun, 1 Sep 2019 12:45:44 +0000 Received: from HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088]) by HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088%3]) with mapi id 15.20.2199.021; Sun, 1 Sep 2019 12:45:44 +0000 From: Jonas Karlman To: Ezequiel Garcia Subject: [PATCH 04/12] media: hantro: Reduce H264 extra space for motion vectors Thread-Topic: [PATCH 04/12] media: hantro: Reduce H264 extra space for motion vectors Thread-Index: AQHVYMMrEJfGZ9HbrUSVxD/h4ic69A== Date: Sun, 1 Sep 2019 12:45:44 +0000 Message-ID: References: <20190901124531.23645-1-jonas@kwiboo.se> In-Reply-To: <20190901124531.23645-1-jonas@kwiboo.se> Accept-Language: sv-SE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR05CA0343.eurprd05.prod.outlook.com (2603:10a6:7:92::38) To HE1PR06MB4011.eurprd06.prod.outlook.com (2603:10a6:7:9c::32) x-incomingtopheadermarker: OriginalChecksum:B4297240E09998F234978948D481396A76F9DCABC8A70EBCDF478E74D986C822; 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Memory layout is as follow: +-------------------+ | Y-plane 256 MBs | +-------------------+ | UV-plane 128 MBs | +-------------------+ | MV buffer 64 MBs | +-------------------+ | MC sync 32 bytes | +-------------------+ Reduce the extra space allocated now that motion vector buffer offset no longer is based on the extra space. Only use extra space for 64 MBs of motion vector buffer and 32 bytes for multi-core sync. Fixes: a9471e25629b ("media: hantro: Add core bits to support H264 decoding") Signed-off-by: Jonas Karlman --- drivers/staging/media/hantro/hantro_v4l2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c index 3dae52abb96c..3a360a6a17e2 100644 --- a/drivers/staging/media/hantro/hantro_v4l2.c +++ b/drivers/staging/media/hantro/hantro_v4l2.c @@ -242,12 +242,12 @@ static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f, /* * The H264 decoder needs extra space on the output buffers * to store motion vectors. This is needed for reference - * frames. + * frames. 32 extra bytes is used for multi-core sync. */ if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE) pix_mp->plane_fmt[0].sizeimage += - 128 * DIV_ROUND_UP(pix_mp->width, 16) * - DIV_ROUND_UP(pix_mp->height, 16); + 64 * H264_MB_WIDTH(pix_mp->width) * + H264_MB_WIDTH(pix_mp->height) + 32; } else if (!pix_mp->plane_fmt[0].sizeimage) { /* * For coded formats the application can specify From patchwork Sun Sep 1 12:45:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Karlman X-Patchwork-Id: 11125221 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 043511395 for ; Sun, 1 Sep 2019 12:45:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D4DA922CF7 for ; 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Sun, 1 Sep 2019 12:45:44 +0000 Received: from HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088]) by HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088%3]) with mapi id 15.20.2199.021; Sun, 1 Sep 2019 12:45:44 +0000 From: Jonas Karlman To: Ezequiel Garcia Subject: [PATCH 05/12] media: hantro: Remove now unused H264 pic_size Thread-Topic: [PATCH 05/12] media: hantro: Remove now unused H264 pic_size Thread-Index: AQHVYMMrCo9i+f9sg02oBWTfIBVkPQ== Date: Sun, 1 Sep 2019 12:45:44 +0000 Message-ID: References: <20190901124531.23645-1-jonas@kwiboo.se> In-Reply-To: <20190901124531.23645-1-jonas@kwiboo.se> Accept-Language: sv-SE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR05CA0343.eurprd05.prod.outlook.com (2603:10a6:7:92::38) To HE1PR06MB4011.eurprd06.prod.outlook.com (2603:10a6:7:9c::32) x-incomingtopheadermarker: OriginalChecksum:95667DAB35749EFC04A8482C14F54C6523A849737CBAB6E68B4B41D909D53276; UpperCasedChecksum:FC7E59BAC9D96BA2BF50DC2F46FACF2FDA90106D35557E70C43D4309E2924096; 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X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a01:111:f400:fe1f:0:0:0:80f listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Kocialkowski , Jonas Karlman , "linux-kernel@vger.kernel.org" , Hans Verkuil , "linux-rockchip@lists.infradead.org" , Boris Brezillon , Philipp Zabel , Mauro Carvalho Chehab , "linux-media@vger.kernel.org" Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org pic_size in hantro_h264_dec_hw_ctx struct is no longer used, lets remove it. Signed-off-by: Jonas Karlman --- drivers/staging/media/hantro/hantro_h264.c | 5 ----- drivers/staging/media/hantro/hantro_hw.h | 3 --- 2 files changed, 8 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c index e2d01145ac4f..a77cc28e180a 100644 --- a/drivers/staging/media/hantro/hantro_h264.c +++ b/drivers/staging/media/hantro/hantro_h264.c @@ -603,7 +603,6 @@ int hantro_h264_dec_init(struct hantro_ctx *ctx) struct hantro_h264_dec_hw_ctx *h264_dec = &ctx->h264_dec; struct hantro_aux_buf *priv = &h264_dec->priv; struct hantro_h264_dec_priv_tbl *tbl; - struct v4l2_pix_format_mplane pix_mp; priv->cpu = dma_alloc_coherent(vpu->dev, sizeof(*tbl), &priv->dma, GFP_KERNEL); @@ -614,9 +613,5 @@ int hantro_h264_dec_init(struct hantro_ctx *ctx) tbl = priv->cpu; memcpy(tbl->cabac_table, h264_cabac_table, sizeof(tbl->cabac_table)); - v4l2_fill_pixfmt_mp(&pix_mp, ctx->dst_fmt.pixelformat, - ctx->dst_fmt.width, ctx->dst_fmt.height); - h264_dec->pic_size = pix_mp.plane_fmt[0].sizeimage; - return 0; } diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h index 2fab655bf098..8adad8ac9b1d 100644 --- a/drivers/staging/media/hantro/hantro_hw.h +++ b/drivers/staging/media/hantro/hantro_hw.h @@ -80,15 +80,12 @@ struct hantro_h264_dec_reflists { * @dpb: DPB * @reflists: P/B0/B1 reflists * @ctrls: V4L2 controls attached to a run - * @pic_size: Size in bytes of decoded picture, this is needed - * to pass the location of motion vectors. */ struct hantro_h264_dec_hw_ctx { struct hantro_aux_buf priv; struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE]; struct hantro_h264_dec_reflists reflists; struct hantro_h264_dec_ctrls ctrls; - size_t pic_size; }; /** From patchwork Sun Sep 1 12:45:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Karlman X-Patchwork-Id: 11125227 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DC4901395 for ; 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Sun, 1 Sep 2019 12:45:45 +0000 Received: from HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088]) by HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088%3]) with mapi id 15.20.2199.021; Sun, 1 Sep 2019 12:45:45 +0000 From: Jonas Karlman To: Ezequiel Garcia Subject: [PATCH 06/12] media: hantro: Set H264 FIELDPIC_FLAG_E flag correctly Thread-Topic: [PATCH 06/12] media: hantro: Set H264 FIELDPIC_FLAG_E flag correctly Thread-Index: AQHVYMMsvCjvoOyW3U6yRGSkSyG0lw== Date: Sun, 1 Sep 2019 12:45:45 +0000 Message-ID: References: <20190901124531.23645-1-jonas@kwiboo.se> In-Reply-To: <20190901124531.23645-1-jonas@kwiboo.se> Accept-Language: sv-SE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR05CA0343.eurprd05.prod.outlook.com (2603:10a6:7:92::38) To HE1PR06MB4011.eurprd06.prod.outlook.com (2603:10a6:7:9c::32) x-incomingtopheadermarker: OriginalChecksum:A0A8E5305A12CD36BFEBD027A8E03E128424E67FDEACDD106AF03D11AD1F1354; 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The PIC_FIELDMODE_E bit is correctly set based on the field_pic_flag. Fix this by setting the FIELDPIC_FLAG_E bit when frame_mbs_only is not set. Fixes: dea0a82f3d22 ("media: hantro: Add support for H264 decoding on G1") Signed-off-by: Jonas Karlman --- drivers/staging/media/hantro/hantro_g1_h264_dec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c index 159bd67e0a36..16f21d258f6a 100644 --- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c +++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c @@ -64,7 +64,7 @@ static void set_params(struct hantro_ctx *ctx) /* always use the matrix sent from userspace */ reg |= G1_REG_DEC_CTRL2_TYPE1_QUANT_E; - if (slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) + if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)) reg |= G1_REG_DEC_CTRL2_FIELDPIC_FLAG_E; vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2); From patchwork Sun Sep 1 12:45:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Karlman X-Patchwork-Id: 11125231 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1A6C21890 for ; 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Sun, 1 Sep 2019 12:45:46 +0000 Received: from HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088]) by HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088%3]) with mapi id 15.20.2199.021; Sun, 1 Sep 2019 12:45:46 +0000 From: Jonas Karlman To: Ezequiel Garcia Subject: [RFC 07/12] media: uapi: h264: Add DPB entry field reference flags Thread-Topic: [RFC 07/12] media: uapi: h264: Add DPB entry field reference flags Thread-Index: AQHVYMMs779kKb2gpUmKyBZ5xgDGWg== Date: Sun, 1 Sep 2019 12:45:46 +0000 Message-ID: References: <20190901124531.23645-1-jonas@kwiboo.se> In-Reply-To: <20190901124531.23645-1-jonas@kwiboo.se> Accept-Language: sv-SE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR05CA0343.eurprd05.prod.outlook.com (2603:10a6:7:92::38) To HE1PR06MB4011.eurprd06.prod.outlook.com (2603:10a6:7:9c::32) x-incomingtopheadermarker: OriginalChecksum:83E7D2462D52362643210F04D4B083E4417427BDD4934DAE0C8EEE0CAD8005B5; UpperCasedChecksum:2D1EC6E1A2062056363E892C78A3CE9FDE7683372DBD665986B0939F5237E99C; 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X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [40.92.66.105 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Kocialkowski , Jonas Karlman , "linux-kernel@vger.kernel.org" , Hans Verkuil , "linux-rockchip@lists.infradead.org" , Boris Brezillon , Philipp Zabel , Mauro Carvalho Chehab , "linux-media@vger.kernel.org" Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Add DPB entry flags to help indicate when a reference frame is a field picture and how the DPB entry is referenced, top or bottom field or full frame. Signed-off-by: Jonas Karlman --- Documentation/media/uapi/v4l/ext-ctrls-codec.rst | 12 ++++++++++++ include/media/h264-ctrls.h | 4 ++++ 2 files changed, 16 insertions(+) diff --git a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst index bc5dd8e76567..eb6c32668ad7 100644 --- a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst +++ b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst @@ -2022,6 +2022,18 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type - * - ``V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM`` - 0x00000004 - The DPB entry is a long term reference frame + * - ``V4L2_H264_DPB_ENTRY_FLAG_FIELD_PICTURE`` + - 0x00000008 + - The DPB entry is a field picture + * - ``V4L2_H264_DPB_ENTRY_FLAG_REF_TOP`` + - 0x00000010 + - The DPB entry is a top field reference + * - ``V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM`` + - 0x00000020 + - The DPB entry is a bottom field reference + * - ``V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME`` + - 0x00000030 + - The DPB entry is a reference frame ``V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE (enum)`` Specifies the decoding mode to use. Currently exposes slice-based and diff --git a/include/media/h264-ctrls.h b/include/media/h264-ctrls.h index e877bf1d537c..76020ebd1e6c 100644 --- a/include/media/h264-ctrls.h +++ b/include/media/h264-ctrls.h @@ -185,6 +185,10 @@ struct v4l2_ctrl_h264_slice_params { #define V4L2_H264_DPB_ENTRY_FLAG_VALID 0x01 #define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE 0x02 #define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM 0x04 +#define V4L2_H264_DPB_ENTRY_FLAG_FIELD_PICTURE 0x08 +#define V4L2_H264_DPB_ENTRY_FLAG_REF_TOP 0x10 +#define V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM 0x20 +#define V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME 0x30 struct v4l2_h264_dpb_entry { __u64 reference_ts; From patchwork Sun Sep 1 12:45:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Karlman X-Patchwork-Id: 11125233 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7B5A61395 for ; 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Sun, 1 Sep 2019 12:45:46 +0000 Received: from HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088]) by HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088%3]) with mapi id 15.20.2199.021; Sun, 1 Sep 2019 12:45:46 +0000 From: Jonas Karlman To: Ezequiel Garcia Subject: [RFC 08/12] media: hantro: Fix H264 decoding of field encoded content Thread-Topic: [RFC 08/12] media: hantro: Fix H264 decoding of field encoded content Thread-Index: AQHVYMMtmxM+aDjHykiwJVJ++y1ATQ== Date: Sun, 1 Sep 2019 12:45:46 +0000 Message-ID: References: <20190901124531.23645-1-jonas@kwiboo.se> In-Reply-To: <20190901124531.23645-1-jonas@kwiboo.se> Accept-Language: sv-SE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR05CA0343.eurprd05.prod.outlook.com (2603:10a6:7:92::38) To HE1PR06MB4011.eurprd06.prod.outlook.com (2603:10a6:7:9c::32) x-incomingtopheadermarker: OriginalChecksum:4812CE2D88DC80F58B5D07C6DB10716EC976C5630B466CF409E068C0A52F9A17; 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+ const struct v4l2_ctrl_h264_slice_params *slice; struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; const u8 *b0_reflist, *b1_reflist, *p_reflist; struct hantro_dev *vpu = ctx->dev; - u32 dpb_longterm = 0; - u32 dpb_valid = 0; int reg_num; u32 reg; int i; - /* - * Set up bit maps of valid and long term DPBs. - * NOTE: The bits are reversed, i.e. MSb is DPB 0. - */ - for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) { - if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) - dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); + dec_param = ctx->h264_dec.ctrls.decode; + slice = ctx->h264_dec.ctrls.slices; - if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) - dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); - } - vdpu_write_relaxed(vpu, dpb_valid << 16, G1_REG_VALID_REF); - vdpu_write_relaxed(vpu, dpb_longterm << 16, G1_REG_LT_REF); + vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_valid, G1_REG_VALID_REF); + vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_longterm, G1_REG_LT_REF); /* * Set up reference frame picture numbers. @@ -223,10 +215,8 @@ static void set_ref(struct hantro_ctx *ctx) /* Set up addresses of DPB buffers. */ for (i = 0; i < HANTRO_H264_DPB_SIZE; i++) { - struct vb2_buffer *buf = hantro_h264_get_ref_buf(ctx, i); - - vdpu_write_relaxed(vpu, vb2_dma_contig_plane_dma_addr(buf, 0), - G1_REG_ADDR_REF(i)); + dma_addr_t addr = hantro_h264_get_ref_dma_addr(ctx, i); + vdpu_write_relaxed(vpu, addr, G1_REG_ADDR_REF(i)); } } diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c index a77cc28e180a..85c86d728b1a 100644 --- a/drivers/staging/media/hantro/hantro_h264.c +++ b/drivers/staging/media/hantro/hantro_h264.c @@ -228,17 +228,65 @@ static void prepare_table(struct hantro_ctx *ctx) { const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode; + const struct v4l2_ctrl_h264_slice_params *slices = ctrls->slices; struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu; const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; + u32 dpb_longterm = 0; + u32 dpb_valid = 0; int i; + /* + * Set up bit maps of valid and long term DPBs. + * NOTE: The bits are reversed, i.e. MSb is DPB 0. + */ + if ((slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) || (slices[0].flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) { + for (i = 0; i < HANTRO_H264_DPB_SIZE * 2; ++i) { + // check for correct reference use + u32 flag = (i & 0x1) ? V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM : V4L2_H264_DPB_ENTRY_FLAG_REF_TOP; + if (dpb[i / 2].flags & flag) + dpb_valid |= BIT(HANTRO_H264_DPB_SIZE * 2 - 1 - i); + + if (dpb[i / 2].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) + dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE * 2 - 1 - i); + } + + ctx->h264_dec.dpb_valid = dpb_valid; + ctx->h264_dec.dpb_longterm = dpb_longterm; + } else { + for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) { + if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) + dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); + + if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) + dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); + } + + ctx->h264_dec.dpb_valid = dpb_valid << 16; + ctx->h264_dec.dpb_longterm = dpb_longterm << 16; + } + for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) { - tbl->poc[i * 2] = dpb[i].top_field_order_cnt; - tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt; + if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) { + tbl->poc[i * 2] = dpb[i].top_field_order_cnt; + tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt; + } else { + tbl->poc[i * 2] = 0; + tbl->poc[i * 2 + 1] = 0; + } } - tbl->poc[32] = dec_param->top_field_order_cnt; - tbl->poc[33] = dec_param->bottom_field_order_cnt; + if ((slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) || !(slices[0].flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) { + if ((slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC)) + tbl->poc[32] = (slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) ? + dec_param->bottom_field_order_cnt : + dec_param->top_field_order_cnt; + else + tbl->poc[32] = min(dec_param->top_field_order_cnt, dec_param->bottom_field_order_cnt); + tbl->poc[33] = 0; + } else { + tbl->poc[32] = dec_param->top_field_order_cnt; + tbl->poc[33] = dec_param->bottom_field_order_cnt; + } reorder_scaling_list(ctx); } @@ -251,51 +299,36 @@ struct hantro_h264_reflist_builder { u8 num_valid; }; -static s32 get_poc(enum v4l2_field field, s32 top_field_order_cnt, - s32 bottom_field_order_cnt) -{ - switch (field) { - case V4L2_FIELD_TOP: - return top_field_order_cnt; - case V4L2_FIELD_BOTTOM: - return bottom_field_order_cnt; - default: - break; - } - - return min(top_field_order_cnt, bottom_field_order_cnt); -} - static void init_reflist_builder(struct hantro_ctx *ctx, struct hantro_h264_reflist_builder *b) { const struct v4l2_ctrl_h264_decode_params *dec_param; - struct vb2_v4l2_buffer *buf = hantro_get_dst_buf(ctx); + const struct v4l2_ctrl_h264_slice_params *slices; const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; - struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q; unsigned int i; dec_param = ctx->h264_dec.ctrls.decode; + slices = ctx->h264_dec.ctrls.slices; memset(b, 0, sizeof(*b)); b->dpb = dpb; - b->curpoc = get_poc(buf->field, dec_param->top_field_order_cnt, - dec_param->bottom_field_order_cnt); + b->curpoc = (slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) ? + dec_param->bottom_field_order_cnt : + dec_param->top_field_order_cnt; for (i = 0; i < ARRAY_SIZE(ctx->h264_dec.dpb); i++) { - int buf_idx; - - if (!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) + u32 ref_flag = dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME; + if (!ref_flag) continue; - buf_idx = vb2_find_timestamp(cap_q, dpb[i].reference_ts, 0); - if (buf_idx < 0) - continue; + if (ref_flag == V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME) + b->pocs[i] = min(dpb[i].bottom_field_order_cnt, dpb[i].top_field_order_cnt); + else if (ref_flag == V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM) + b->pocs[i] = dpb[i].bottom_field_order_cnt; + else if (ref_flag == V4L2_H264_DPB_ENTRY_FLAG_REF_TOP) + b->pocs[i] = dpb[i].top_field_order_cnt; - buf = to_vb2_v4l2_buffer(vb2_get_buffer(cap_q, buf_idx)); - b->pocs[i] = get_poc(buf->field, dpb[i].top_field_order_cnt, - dpb[i].bottom_field_order_cnt); b->unordered_reflist[b->num_valid] = i; b->num_valid++; } @@ -448,8 +481,7 @@ build_b_ref_lists(const struct hantro_h264_reflist_builder *builder, static bool dpb_entry_match(const struct v4l2_h264_dpb_entry *a, const struct v4l2_h264_dpb_entry *b) { - return a->top_field_order_cnt == b->top_field_order_cnt && - a->bottom_field_order_cnt == b->bottom_field_order_cnt; + return a->reference_ts == b->reference_ts; } static void update_dpb(struct hantro_ctx *ctx) @@ -463,13 +495,13 @@ static void update_dpb(struct hantro_ctx *ctx) /* Disable all entries by default. */ for (i = 0; i < ARRAY_SIZE(ctx->h264_dec.dpb); i++) - ctx->h264_dec.dpb[i].flags &= ~V4L2_H264_DPB_ENTRY_FLAG_ACTIVE; + ctx->h264_dec.dpb[i].flags = 0; /* Try to match new DPB entries with existing ones by their POCs. */ for (i = 0; i < ARRAY_SIZE(dec_param->dpb); i++) { const struct v4l2_h264_dpb_entry *ndpb = &dec_param->dpb[i]; - if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) + if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_VALID)) continue; /* @@ -480,8 +512,7 @@ static void update_dpb(struct hantro_ctx *ctx) struct v4l2_h264_dpb_entry *cdpb; cdpb = &ctx->h264_dec.dpb[j]; - if (cdpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE || - !dpb_entry_match(cdpb, ndpb)) + if (!dpb_entry_match(cdpb, ndpb)) continue; *cdpb = *ndpb; @@ -541,6 +572,25 @@ struct vb2_buffer *hantro_h264_get_ref_buf(struct hantro_ctx *ctx, return buf; } +dma_addr_t hantro_h264_get_ref_dma_addr(struct hantro_ctx *ctx, + unsigned int dpb_idx) +{ + struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; + const struct v4l2_ctrl_h264_decode_params *dec_param = ctx->h264_dec.ctrls.decode; + const struct v4l2_ctrl_h264_slice_params *slices = ctx->h264_dec.ctrls.slices; + + struct vb2_buffer *buf = hantro_h264_get_ref_buf(ctx, dpb_idx); + s32 cur_poc = slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD ? + dec_param->bottom_field_order_cnt : + dec_param->top_field_order_cnt; + u32 flags = dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD_PICTURE ? 0x2 : 0; + flags |= abs(dpb[dpb_idx].top_field_order_cnt - cur_poc) < + abs(dpb[dpb_idx].bottom_field_order_cnt - cur_poc) ? + 0x1 : 0; + + return vb2_dma_contig_plane_dma_addr(buf, 0) | flags; +} + int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx) { struct hantro_h264_dec_hw_ctx *h264_ctx = &ctx->h264_dec; diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h index 8adad8ac9b1d..d58f2a36ca40 100644 --- a/drivers/staging/media/hantro/hantro_hw.h +++ b/drivers/staging/media/hantro/hantro_hw.h @@ -86,6 +86,8 @@ struct hantro_h264_dec_hw_ctx { struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE]; struct hantro_h264_dec_reflists reflists; struct hantro_h264_dec_ctrls ctrls; + u32 dpb_longterm; + u32 dpb_valid; }; /** @@ -157,6 +159,8 @@ void hantro_jpeg_enc_exit(struct hantro_ctx *ctx); struct vb2_buffer *hantro_h264_get_ref_buf(struct hantro_ctx *ctx, unsigned int dpb_idx); +dma_addr_t hantro_h264_get_ref_dma_addr(struct hantro_ctx *ctx, + unsigned int dpb_idx); int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx); void hantro_g1_h264_dec_run(struct hantro_ctx *ctx); int hantro_h264_dec_init(struct hantro_ctx *ctx); From patchwork Sun Sep 1 12:45:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Karlman X-Patchwork-Id: 11125241 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 458FC16B1 for ; Sun, 1 Sep 2019 12:46:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 202492339D for ; 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Sun, 1 Sep 2019 12:45:47 +0000 Received: from HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088]) by HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088%3]) with mapi id 15.20.2199.021; Sun, 1 Sep 2019 12:45:47 +0000 From: Jonas Karlman To: Ezequiel Garcia Subject: [RFC 09/12] media: hantro: Refactor G1 H264 code Thread-Topic: [RFC 09/12] media: hantro: Refactor G1 H264 code Thread-Index: AQHVYMMt6S6DYZer7kW/prgSt9wEcg== Date: Sun, 1 Sep 2019 12:45:47 +0000 Message-ID: References: <20190901124531.23645-1-jonas@kwiboo.se> In-Reply-To: <20190901124531.23645-1-jonas@kwiboo.se> Accept-Language: sv-SE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR05CA0343.eurprd05.prod.outlook.com (2603:10a6:7:92::38) To HE1PR06MB4011.eurprd06.prod.outlook.com (2603:10a6:7:9c::32) x-incomingtopheadermarker: OriginalChecksum:B4C7CA06B254E5D062300427D4773F24B6670FC6B03A4439CA03D3C536D94F63; UpperCasedChecksum:9C3770E98E46D674140D89E7EF4CA3155D7DC4BB8F3F0586E06E0722FDC4A6FB; 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X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [40.92.64.32 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Kocialkowski , Jonas Karlman , "linux-kernel@vger.kernel.org" , Hans Verkuil , "linux-rockchip@lists.infradead.org" , Boris Brezillon , Philipp Zabel , Mauro Carvalho Chehab , "linux-media@vger.kernel.org" Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Use generated code from my rockchip-vpu-regtool This need code cleanup and formatting Signed-off-by: Jonas Karlman --- .../staging/media/hantro/hantro_g1_h264_dec.c | 661 +++++++++++------- drivers/staging/media/hantro/hantro_h264.c | 14 + drivers/staging/media/hantro/hantro_hw.h | 2 + 3 files changed, 439 insertions(+), 238 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c index bc628ef73b29..4b82b9fd5252 100644 --- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c +++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Rockchip RK3288 VPU codec driver + * Hantro VPU codec driver * * Copyright (c) 2014 Rockchip Electronics Co., Ltd. * Hertz Wong @@ -15,273 +15,458 @@ #include -#include "hantro_g1_regs.h" #include "hantro_hw.h" #include "hantro_v4l2.h" #define MV_OFFSET_420 384 #define MV_OFFSET_400 256 -static void set_params(struct hantro_ctx *ctx) -{ - const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; - const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode; - const struct v4l2_ctrl_h264_slice_params *slices = ctrls->slices; - const struct v4l2_ctrl_h264_sps *sps = ctrls->sps; - const struct v4l2_ctrl_h264_pps *pps = ctrls->pps; - struct vb2_v4l2_buffer *src_buf = hantro_get_src_buf(ctx); - struct hantro_dev *vpu = ctx->dev; - u32 reg; - - /* Decoder control register 0. */ - reg = G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(0x0); - if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) - reg |= G1_REG_DEC_CTRL0_SEQ_MBAFF_E; - reg |= G1_REG_DEC_CTRL0_PICORD_COUNT_E; - if (dec_param->nal_ref_idc) - reg |= G1_REG_DEC_CTRL0_WRITE_MVS_E; - - if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) && - (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD || - slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC)) - reg |= G1_REG_DEC_CTRL0_PIC_INTERLACE_E; - if (slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) - reg |= G1_REG_DEC_CTRL0_PIC_FIELDMODE_E; - if (!(slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD)) - reg |= G1_REG_DEC_CTRL0_PIC_TOPFIELD_E; - vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0); - - /* Decoder control register 1. */ - reg = G1_REG_DEC_CTRL1_PIC_MB_WIDTH(H264_MB_WIDTH(ctx->dst_fmt.width)) | - G1_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(H264_MB_HEIGHT(ctx->dst_fmt.height)) | - G1_REG_DEC_CTRL1_REF_FRAMES(sps->max_num_ref_frames); - vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1); - - /* Decoder control register 2. */ - reg = G1_REG_DEC_CTRL2_CH_QP_OFFSET(pps->chroma_qp_index_offset) | - G1_REG_DEC_CTRL2_CH_QP_OFFSET2(pps->second_chroma_qp_index_offset); - - /* always use the matrix sent from userspace */ - reg |= G1_REG_DEC_CTRL2_TYPE1_QUANT_E; - - if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)) - reg |= G1_REG_DEC_CTRL2_FIELDPIC_FLAG_E; - vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2); - - /* Decoder control register 3. */ - reg = G1_REG_DEC_CTRL3_START_CODE_E | - G1_REG_DEC_CTRL3_INIT_QP(pps->pic_init_qp_minus26 + 26) | - G1_REG_DEC_CTRL3_STREAM_LEN(vb2_get_plane_payload(&src_buf->vb2_buf, 0)); - vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL3); - - /* Decoder control register 4. */ - reg = G1_REG_DEC_CTRL4_FRAMENUM_LEN(sps->log2_max_frame_num_minus4 + 4) | - G1_REG_DEC_CTRL4_FRAMENUM(slices[0].frame_num) | - G1_REG_DEC_CTRL4_WEIGHT_BIPR_IDC(pps->weighted_bipred_idc); - if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) - reg |= G1_REG_DEC_CTRL4_CABAC_E; - if (sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) - reg |= G1_REG_DEC_CTRL4_DIR_8X8_INFER_E; - if (sps->profile_idc >= 100 && sps->chroma_format_idc == 0) - reg |= G1_REG_DEC_CTRL4_BLACKWHITE_E; - if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) - reg |= G1_REG_DEC_CTRL4_WEIGHT_PRED_E; - vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL4); - - /* Decoder control register 5. */ - reg = G1_REG_DEC_CTRL5_REFPIC_MK_LEN(slices[0].dec_ref_pic_marking_bit_size) | - G1_REG_DEC_CTRL5_IDR_PIC_ID(slices[0].idr_pic_id); - if (pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) - reg |= G1_REG_DEC_CTRL5_CONST_INTRA_E; - if (pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT) - reg |= G1_REG_DEC_CTRL5_FILT_CTRL_PRES; - if (pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT) - reg |= G1_REG_DEC_CTRL5_RDPIC_CNT_PRES; - if (pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) - reg |= G1_REG_DEC_CTRL5_8X8TRANS_FLAG_E; - if (dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC) - reg |= G1_REG_DEC_CTRL5_IDR_PIC_E; - vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL5); - - /* Decoder control register 6. */ - reg = G1_REG_DEC_CTRL6_PPS_ID(slices[0].pic_parameter_set_id) | - G1_REG_DEC_CTRL6_REFIDX0_ACTIVE(pps->num_ref_idx_l0_default_active_minus1 + 1) | - G1_REG_DEC_CTRL6_REFIDX1_ACTIVE(pps->num_ref_idx_l1_default_active_minus1 + 1) | - G1_REG_DEC_CTRL6_POC_LENGTH(slices[0].pic_order_cnt_bit_size); - vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL6); - - /* Error concealment register. */ - vdpu_write_relaxed(vpu, 0, G1_REG_ERR_CONC); - - /* Prediction filter tap register. */ - vdpu_write_relaxed(vpu, - G1_REG_PRED_FLT_PRED_BC_TAP_0_0(1) | - G1_REG_PRED_FLT_PRED_BC_TAP_0_1(-5 & 0x3ff) | - G1_REG_PRED_FLT_PRED_BC_TAP_0_2(20), - G1_REG_PRED_FLT); - - /* Reference picture buffer control register. */ - vdpu_write_relaxed(vpu, 0, G1_REG_REF_BUF_CTRL); - - /* Reference picture buffer control register 2. */ - vdpu_write_relaxed(vpu, G1_REG_REF_BUF_CTRL2_APF_THRESHOLD(8), - G1_REG_REF_BUF_CTRL2); -} +#define G1_SWREG(nr) ((nr) * 4) + +#define G1_REG_RLC_VLC_BASE G1_SWREG(12) +#define G1_REG_DEC_OUT_BASE G1_SWREG(13) +#define G1_REG_REFER0_BASE G1_SWREG(14) +#define G1_REG_REFER1_BASE G1_SWREG(15) +#define G1_REG_REFER2_BASE G1_SWREG(16) +#define G1_REG_REFER3_BASE G1_SWREG(17) +#define G1_REG_REFER4_BASE G1_SWREG(18) +#define G1_REG_REFER5_BASE G1_SWREG(19) +#define G1_REG_REFER6_BASE G1_SWREG(20) +#define G1_REG_REFER7_BASE G1_SWREG(21) +#define G1_REG_REFER8_BASE G1_SWREG(22) +#define G1_REG_REFER9_BASE G1_SWREG(23) +#define G1_REG_REFER10_BASE G1_SWREG(24) +#define G1_REG_REFER11_BASE G1_SWREG(25) +#define G1_REG_REFER12_BASE G1_SWREG(26) +#define G1_REG_REFER13_BASE G1_SWREG(27) +#define G1_REG_REFER14_BASE G1_SWREG(28) +#define G1_REG_REFER15_BASE G1_SWREG(29) +#define G1_REG_QTABLE_BASE G1_SWREG(40) +#define G1_REG_DIR_MV_BASE G1_SWREG(41) +#define G1_REG_DEC_E(v) ((v) ? BIT(0) : 0) + +#define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) +#define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) +#define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) +#define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) +#define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) +#define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0) +#define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0) +#define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11)) +#define G1_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(10) : 0) +#define G1_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(9) : 0) +#define G1_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(8) : 0) +#define G1_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(6) : 0) +#define G1_REG_DEC_SCMD_DIS(v) ((v) ? BIT(5) : 0) +#define G1_REG_DEC_MAX_BURST(v) (((v) << 0) & GENMASK(4, 0)) + +#define G1_REG_DEC_MODE(v) (((v) << 28) & GENMASK(31, 28)) +#define G1_REG_RLC_MODE_E(v) ((v) ? BIT(27) : 0) +#define G1_REG_PIC_INTERLACE_E(v) ((v) ? BIT(23) : 0) +#define G1_REG_PIC_FIELDMODE_E(v) ((v) ? BIT(22) : 0) +#define G1_REG_PIC_TOPFIELD_E(v) ((v) ? BIT(19) : 0) +#define G1_REG_FILTERING_DIS(v) ((v) ? BIT(14) : 0) +#define G1_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(13) : 0) +#define G1_REG_WRITE_MVS_E(v) ((v) ? BIT(12) : 0) +#define G1_REG_SEQ_MBAFF_E(v) ((v) ? BIT(10) : 0) +#define G1_REG_PICORD_COUNT_E(v) ((v) ? BIT(9) : 0) +#define G1_REG_DEC_AXI_WR_ID(v) (((v) << 0) & GENMASK(7, 0)) + +#define G1_REG_PIC_MB_WIDTH(v) (((v) << 23) & GENMASK(31, 23)) +#define G1_REG_PIC_MB_HEIGHT_P(v) (((v) << 11) & GENMASK(18, 11)) +#define G1_REG_REF_FRAMES(v) (((v) << 0) & GENMASK(4, 0)) + +#define G1_REG_STRM_START_BIT(v) (((v) << 26) & GENMASK(31, 26)) +#define G1_REG_TYPE1_QUANT_E(v) ((v) ? BIT(24) : 0) +#define G1_REG_CH_QP_OFFSET(v) (((v) << 19) & GENMASK(23, 19)) +#define G1_REG_CH_QP_OFFSET2(v) (((v) << 14) & GENMASK(18, 14)) +#define G1_REG_FIELDPIC_FLAG_E(v) ((v) ? BIT(0) : 0) + +#define G1_REG_START_CODE_E(v) ((v) ? BIT(31) : 0) +#define G1_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) +#define G1_REG_CH_8PIX_ILEAV_E(v) ((v) ? BIT(24) : 0) +#define G1_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) + +#define G1_REG_CABAC_E(v) ((v) ? BIT(31) : 0) +#define G1_REG_BLACKWHITE_E(v) ((v) ? BIT(30) : 0) +#define G1_REG_DIR_8X8_INFER_E(v) ((v) ? BIT(29) : 0) +#define G1_REG_WEIGHT_PRED_E(v) ((v) ? BIT(28) : 0) +#define G1_REG_WEIGHT_BIPR_IDC(v) (((v) << 26) & GENMASK(27, 26)) +#define G1_REG_FRAMENUM_LEN(v) (((v) << 16) & GENMASK(20, 16)) +#define G1_REG_FRAMENUM(v) (((v) << 0) & GENMASK(15, 0)) + +#define G1_REG_CONST_INTRA_E(v) ((v) ? BIT(31) : 0) +#define G1_REG_FILT_CTRL_PRES(v) ((v) ? BIT(30) : 0) +#define G1_REG_RDPIC_CNT_PRES(v) ((v) ? BIT(29) : 0) +#define G1_REG_8X8TRANS_FLAG_E(v) ((v) ? BIT(28) : 0) +#define G1_REG_REFPIC_MK_LEN(v) (((v) << 17) & GENMASK(27, 17)) +#define G1_REG_IDR_PIC_E(v) ((v) ? BIT(16) : 0) +#define G1_REG_IDR_PIC_ID(v) (((v) << 0) & GENMASK(15, 0)) + +#define G1_REG_PPS_ID(v) (((v) << 24) & GENMASK(31, 24)) +#define G1_REG_REFIDX1_ACTIVE(v) (((v) << 19) & GENMASK(23, 19)) +#define G1_REG_REFIDX0_ACTIVE(v) (((v) << 14) & GENMASK(18, 14)) +#define G1_REG_POC_LENGTH(v) (((v) << 0) & GENMASK(7, 0)) + +#define G1_REG_PINIT_RLIST_F9(v) (((v) << 25) & GENMASK(29, 25)) +#define G1_REG_PINIT_RLIST_F8(v) (((v) << 20) & GENMASK(24, 20)) +#define G1_REG_PINIT_RLIST_F7(v) (((v) << 15) & GENMASK(19, 15)) +#define G1_REG_PINIT_RLIST_F6(v) (((v) << 10) & GENMASK(14, 10)) +#define G1_REG_PINIT_RLIST_F5(v) (((v) << 5) & GENMASK(9, 5)) +#define G1_REG_PINIT_RLIST_F4(v) (((v) << 0) & GENMASK(4, 0)) + +#define G1_REG_PINIT_RLIST_F15(v) (((v) << 25) & GENMASK(29, 25)) +#define G1_REG_PINIT_RLIST_F14(v) (((v) << 20) & GENMASK(24, 20)) +#define G1_REG_PINIT_RLIST_F13(v) (((v) << 15) & GENMASK(19, 15)) +#define G1_REG_PINIT_RLIST_F12(v) (((v) << 10) & GENMASK(14, 10)) +#define G1_REG_PINIT_RLIST_F11(v) (((v) << 5) & GENMASK(9, 5)) +#define G1_REG_PINIT_RLIST_F10(v) (((v) << 0) & GENMASK(4, 0)) + +#define G1_REG_REFER1_NBR(v) (((v) << 16) & GENMASK(31, 16)) +#define G1_REG_REFER0_NBR(v) (((v) << 0) & GENMASK(15, 0)) + +#define G1_REG_REFER3_NBR(v) (((v) << 16) & GENMASK(31, 16)) +#define G1_REG_REFER2_NBR(v) (((v) << 0) & GENMASK(15, 0)) + +#define G1_REG_REFER5_NBR(v) (((v) << 16) & GENMASK(31, 16)) +#define G1_REG_REFER4_NBR(v) (((v) << 0) & GENMASK(15, 0)) + +#define G1_REG_REFER7_NBR(v) (((v) << 16) & GENMASK(31, 16)) +#define G1_REG_REFER6_NBR(v) (((v) << 0) & GENMASK(15, 0)) + +#define G1_REG_REFER9_NBR(v) (((v) << 16) & GENMASK(31, 16)) +#define G1_REG_REFER8_NBR(v) (((v) << 0) & GENMASK(15, 0)) + +#define G1_REG_REFER11_NBR(v) (((v) << 16) & GENMASK(31, 16)) +#define G1_REG_REFER10_NBR(v) (((v) << 0) & GENMASK(15, 0)) + +#define G1_REG_REFER13_NBR(v) (((v) << 16) & GENMASK(31, 16)) +#define G1_REG_REFER12_NBR(v) (((v) << 0) & GENMASK(15, 0)) + +#define G1_REG_REFER15_NBR(v) (((v) << 16) & GENMASK(31, 16)) +#define G1_REG_REFER14_NBR(v) (((v) << 0) & GENMASK(15, 0)) + +#define G1_REG_REFER_LTERM_E(v) (((v) << 0) & GENMASK(31, 0)) + +#define G1_REG_REFER_VALID_E(v) (((v) << 0) & GENMASK(31, 0)) + +#define G1_REG_BINIT_RLIST_B2(v) (((v) << 25) & GENMASK(29, 25)) +#define G1_REG_BINIT_RLIST_F2(v) (((v) << 20) & GENMASK(24, 20)) +#define G1_REG_BINIT_RLIST_B1(v) (((v) << 15) & GENMASK(19, 15)) +#define G1_REG_BINIT_RLIST_F1(v) (((v) << 10) & GENMASK(14, 10)) +#define G1_REG_BINIT_RLIST_B0(v) (((v) << 5) & GENMASK(9, 5)) +#define G1_REG_BINIT_RLIST_F0(v) (((v) << 0) & GENMASK(4, 0)) + +#define G1_REG_BINIT_RLIST_B5(v) (((v) << 25) & GENMASK(29, 25)) +#define G1_REG_BINIT_RLIST_F5(v) (((v) << 20) & GENMASK(24, 20)) +#define G1_REG_BINIT_RLIST_B4(v) (((v) << 15) & GENMASK(19, 15)) +#define G1_REG_BINIT_RLIST_F4(v) (((v) << 10) & GENMASK(14, 10)) +#define G1_REG_BINIT_RLIST_B3(v) (((v) << 5) & GENMASK(9, 5)) +#define G1_REG_BINIT_RLIST_F3(v) (((v) << 0) & GENMASK(4, 0)) + +#define G1_REG_BINIT_RLIST_B8(v) (((v) << 25) & GENMASK(29, 25)) +#define G1_REG_BINIT_RLIST_F8(v) (((v) << 20) & GENMASK(24, 20)) +#define G1_REG_BINIT_RLIST_B7(v) (((v) << 15) & GENMASK(19, 15)) +#define G1_REG_BINIT_RLIST_F7(v) (((v) << 10) & GENMASK(14, 10)) +#define G1_REG_BINIT_RLIST_B6(v) (((v) << 5) & GENMASK(9, 5)) +#define G1_REG_BINIT_RLIST_F6(v) (((v) << 0) & GENMASK(4, 0)) + +#define G1_REG_BINIT_RLIST_B11(v) (((v) << 25) & GENMASK(29, 25)) +#define G1_REG_BINIT_RLIST_F11(v) (((v) << 20) & GENMASK(24, 20)) +#define G1_REG_BINIT_RLIST_B10(v) (((v) << 15) & GENMASK(19, 15)) +#define G1_REG_BINIT_RLIST_F10(v) (((v) << 10) & GENMASK(14, 10)) +#define G1_REG_BINIT_RLIST_B9(v) (((v) << 5) & GENMASK(9, 5)) +#define G1_REG_BINIT_RLIST_F9(v) (((v) << 0) & GENMASK(4, 0)) + +#define G1_REG_BINIT_RLIST_B14(v) (((v) << 25) & GENMASK(29, 25)) +#define G1_REG_BINIT_RLIST_F14(v) (((v) << 20) & GENMASK(24, 20)) +#define G1_REG_BINIT_RLIST_B13(v) (((v) << 15) & GENMASK(19, 15)) +#define G1_REG_BINIT_RLIST_F13(v) (((v) << 10) & GENMASK(14, 10)) +#define G1_REG_BINIT_RLIST_B12(v) (((v) << 5) & GENMASK(9, 5)) +#define G1_REG_BINIT_RLIST_F12(v) (((v) << 0) & GENMASK(4, 0)) + +#define G1_REG_PINIT_RLIST_F3(v) (((v) << 25) & GENMASK(29, 25)) +#define G1_REG_PINIT_RLIST_F2(v) (((v) << 20) & GENMASK(24, 20)) +#define G1_REG_PINIT_RLIST_F1(v) (((v) << 15) & GENMASK(19, 15)) +#define G1_REG_PINIT_RLIST_F0(v) (((v) << 10) & GENMASK(14, 10)) +#define G1_REG_BINIT_RLIST_B15(v) (((v) << 5) & GENMASK(9, 5)) +#define G1_REG_BINIT_RLIST_F15(v) (((v) << 0) & GENMASK(4, 0)) + +#define G1_REG_STARTMB_X(v) (((v) << 23) & GENMASK(31, 23)) +#define G1_REG_STARTMB_Y(v) (((v) << 15) & GENMASK(22, 15)) + +#define G1_REG_PRED_BC_TAP_0_0(v) (((v) << 22) & GENMASK(31, 22)) +#define G1_REG_PRED_BC_TAP_0_1(v) (((v) << 12) & GENMASK(21, 12)) +#define G1_REG_PRED_BC_TAP_0_2(v) (((v) << 2) & GENMASK(11, 2)) + +#define G1_REG_REFBU_E(v) ((v) ? BIT(31) : 0) + +#define G1_REG_APF_THRESHOLD(v) (((v) << 0) & GENMASK(13, 0)) +>>>>>>> b22734fb5e2c... Ymedia: hantro: Refactor G1 H264 code -static void set_ref(struct hantro_ctx *ctx) +void hantro_g1_h264_dec_run(struct hantro_ctx *ctx) { + struct hantro_dev *vpu = ctx->dev; + struct vb2_v4l2_buffer *src_buf, *dst_buf; + const struct hantro_h264_dec_ctrls *ctrls; const struct v4l2_ctrl_h264_decode_params *dec_param; - const struct v4l2_ctrl_h264_slice_params *slice; - struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; + const struct v4l2_ctrl_h264_slice_params *slices; + const struct v4l2_ctrl_h264_sps *sps; + const struct v4l2_ctrl_h264_pps *pps; const u8 *b0_reflist, *b1_reflist, *p_reflist; - struct hantro_dev *vpu = ctx->dev; - int reg_num; + dma_addr_t addr; u32 reg; - int i; - - dec_param = ctx->h264_dec.ctrls.decode; - slice = ctx->h264_dec.ctrls.slices; - - vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_valid, G1_REG_VALID_REF); - vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_longterm, G1_REG_LT_REF); - - /* - * Set up reference frame picture numbers. - * - * Each G1_REG_REF_PIC(x) register contains numbers of two - * subsequential reference pictures. - */ - for (i = 0; i < HANTRO_H264_DPB_SIZE; i += 2) { - reg = 0; - if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) - reg |= G1_REG_REF_PIC_REFER0_NBR(dpb[i].pic_num); - else - reg |= G1_REG_REF_PIC_REFER0_NBR(dpb[i].frame_num); - - if (dpb[i + 1].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) - reg |= G1_REG_REF_PIC_REFER1_NBR(dpb[i + 1].pic_num); - else - reg |= G1_REG_REF_PIC_REFER1_NBR(dpb[i + 1].frame_num); - - vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(i / 2)); - } + unsigned int offset = MV_OFFSET_420; + + /* Prepare the H264 decoder context. */ + if (hantro_h264_dec_prepare_run(ctx)) + return; + + src_buf = hantro_get_src_buf(ctx); + dst_buf = hantro_get_dst_buf(ctx); + + ctrls = &ctx->h264_dec.ctrls; + dec_param = ctrls->decode; + slices = ctrls->slices; + sps = ctrls->sps; + pps = ctrls->pps; b0_reflist = ctx->h264_dec.reflists.b0; b1_reflist = ctx->h264_dec.reflists.b1; p_reflist = ctx->h264_dec.reflists.p; - /* - * Each G1_REG_BD_REF_PIC(x) register contains three entries - * of each forward and backward picture list. - */ - reg_num = 0; - for (i = 0; i < 15; i += 3) { - reg = G1_REG_BD_REF_PIC_BINIT_RLIST_F0(b0_reflist[i]) | - G1_REG_BD_REF_PIC_BINIT_RLIST_F1(b0_reflist[i + 1]) | - G1_REG_BD_REF_PIC_BINIT_RLIST_F2(b0_reflist[i + 2]) | - G1_REG_BD_REF_PIC_BINIT_RLIST_B0(b1_reflist[i]) | - G1_REG_BD_REF_PIC_BINIT_RLIST_B1(b1_reflist[i + 1]) | - G1_REG_BD_REF_PIC_BINIT_RLIST_B2(b1_reflist[i + 2]); - vdpu_write_relaxed(vpu, reg, G1_REG_BD_REF_PIC(reg_num++)); - } - - /* - * G1_REG_BD_P_REF_PIC register contains last entries (index 15) - * of forward and backward reference picture lists and first 4 entries - * of P forward picture list. - */ - reg = G1_REG_BD_P_REF_PIC_BINIT_RLIST_F15(b0_reflist[15]) | - G1_REG_BD_P_REF_PIC_BINIT_RLIST_B15(b1_reflist[15]) | - G1_REG_BD_P_REF_PIC_PINIT_RLIST_F0(p_reflist[0]) | - G1_REG_BD_P_REF_PIC_PINIT_RLIST_F1(p_reflist[1]) | - G1_REG_BD_P_REF_PIC_PINIT_RLIST_F2(p_reflist[2]) | - G1_REG_BD_P_REF_PIC_PINIT_RLIST_F3(p_reflist[3]); - vdpu_write_relaxed(vpu, reg, G1_REG_BD_P_REF_PIC); - - /* - * Each G1_REG_FWD_PIC(x) register contains six consecutive - * entries of P forward picture list, starting from index 4. - */ - reg_num = 0; - for (i = 4; i < HANTRO_H264_DPB_SIZE; i += 6) { - reg = G1_REG_FWD_PIC_PINIT_RLIST_F0(p_reflist[i]) | - G1_REG_FWD_PIC_PINIT_RLIST_F1(p_reflist[i + 1]) | - G1_REG_FWD_PIC_PINIT_RLIST_F2(p_reflist[i + 2]) | - G1_REG_FWD_PIC_PINIT_RLIST_F3(p_reflist[i + 3]) | - G1_REG_FWD_PIC_PINIT_RLIST_F4(p_reflist[i + 4]) | - G1_REG_FWD_PIC_PINIT_RLIST_F5(p_reflist[i + 5]); - vdpu_write_relaxed(vpu, reg, G1_REG_FWD_PIC(reg_num++)); - } - - /* Set up addresses of DPB buffers. */ - for (i = 0; i < HANTRO_H264_DPB_SIZE; i++) { - dma_addr_t addr = hantro_h264_get_ref_dma_addr(ctx, i); - vdpu_write_relaxed(vpu, addr, G1_REG_ADDR_REF(i)); - } -} + reg = G1_REG_DEC_AXI_RD_ID(0xff) | + G1_REG_DEC_TIMEOUT_E(1) | + G1_REG_DEC_STRSWAP32_E(1) | + G1_REG_DEC_STRENDIAN_E(1) | + G1_REG_DEC_INSWAP32_E(1) | + G1_REG_DEC_OUTSWAP32_E(1) | + G1_REG_DEC_DATA_DISC_E(0) | + G1_REG_DEC_LATENCY(0) | + G1_REG_DEC_CLK_GATE_E(1) | + G1_REG_DEC_IN_ENDIAN(0) | + G1_REG_DEC_OUT_ENDIAN(1) | + G1_REG_DEC_ADV_PRE_DIS(0) | + G1_REG_DEC_SCMD_DIS(0) | + G1_REG_DEC_MAX_BURST(16); + vdpu_write_relaxed(vpu, reg, G1_SWREG(2)); + + reg = G1_REG_DEC_MODE(0) | + G1_REG_RLC_MODE_E(0) | + G1_REG_PIC_INTERLACE_E(!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) && (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD || slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC)) | + G1_REG_PIC_FIELDMODE_E(slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) | + G1_REG_PIC_TOPFIELD_E(!(slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD)) | + G1_REG_FILTERING_DIS(0) | + G1_REG_PIC_FIXED_QUANT(0) | + G1_REG_WRITE_MVS_E(dec_param->nal_ref_idc) | + G1_REG_SEQ_MBAFF_E(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) | + G1_REG_PICORD_COUNT_E(1) | + G1_REG_DEC_AXI_WR_ID(0); + vdpu_write_relaxed(vpu, reg, G1_SWREG(3)); + + reg = G1_REG_PIC_MB_WIDTH(H264_MB_WIDTH(ctx->dst_fmt.width)) | + G1_REG_PIC_MB_HEIGHT_P(H264_MB_HEIGHT(ctx->dst_fmt.height)) | + G1_REG_REF_FRAMES(sps->max_num_ref_frames); + vdpu_write_relaxed(vpu, reg, G1_SWREG(4)); + + reg = G1_REG_STRM_START_BIT(0) | + G1_REG_TYPE1_QUANT_E(1) | + G1_REG_CH_QP_OFFSET(pps->chroma_qp_index_offset) | + G1_REG_CH_QP_OFFSET2(pps->second_chroma_qp_index_offset) | + G1_REG_FIELDPIC_FLAG_E(!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)); + vdpu_write_relaxed(vpu, reg, G1_SWREG(5)); + + reg = G1_REG_START_CODE_E(1) | + G1_REG_INIT_QP(pps->pic_init_qp_minus26 + 26) | + G1_REG_CH_8PIX_ILEAV_E(0) | + G1_REG_STREAM_LEN(vb2_get_plane_payload(&src_buf->vb2_buf, 0)); + vdpu_write_relaxed(vpu, reg, G1_SWREG(6)); + + reg = G1_REG_CABAC_E(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) | + G1_REG_BLACKWHITE_E(sps->profile_idc >= 100 && sps->chroma_format_idc == 0) | + G1_REG_DIR_8X8_INFER_E(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) | + G1_REG_WEIGHT_PRED_E(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) | + G1_REG_WEIGHT_BIPR_IDC(pps->weighted_bipred_idc) | + G1_REG_FRAMENUM_LEN(sps->log2_max_frame_num_minus4 + 4) | + G1_REG_FRAMENUM(slices[0].frame_num); + vdpu_write_relaxed(vpu, reg, G1_SWREG(7)); + + reg = G1_REG_CONST_INTRA_E(pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) | + G1_REG_FILT_CTRL_PRES(pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT) | + G1_REG_RDPIC_CNT_PRES(pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT) | + G1_REG_8X8TRANS_FLAG_E(pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) | + G1_REG_REFPIC_MK_LEN(slices[0].dec_ref_pic_marking_bit_size) | + G1_REG_IDR_PIC_E(dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC) | + G1_REG_IDR_PIC_ID(slices[0].idr_pic_id); + vdpu_write_relaxed(vpu, reg, G1_SWREG(8)); + + reg = G1_REG_PPS_ID(slices[0].pic_parameter_set_id) | + G1_REG_REFIDX1_ACTIVE(pps->num_ref_idx_l1_default_active_minus1 + 1) | + G1_REG_REFIDX0_ACTIVE(pps->num_ref_idx_l0_default_active_minus1 + 1) | + G1_REG_POC_LENGTH(slices[0].pic_order_cnt_bit_size); + vdpu_write_relaxed(vpu, reg, G1_SWREG(9)); + + reg = G1_REG_PINIT_RLIST_F9(p_reflist[9]) | + G1_REG_PINIT_RLIST_F8(p_reflist[8]) | + G1_REG_PINIT_RLIST_F7(p_reflist[7]) | + G1_REG_PINIT_RLIST_F6(p_reflist[6]) | + G1_REG_PINIT_RLIST_F5(p_reflist[5]) | + G1_REG_PINIT_RLIST_F4(p_reflist[4]); + vdpu_write_relaxed(vpu, reg, G1_SWREG(10)); + + reg = G1_REG_PINIT_RLIST_F15(p_reflist[15]) | + G1_REG_PINIT_RLIST_F14(p_reflist[14]) | + G1_REG_PINIT_RLIST_F13(p_reflist[13]) | + G1_REG_PINIT_RLIST_F12(p_reflist[12]) | + G1_REG_PINIT_RLIST_F11(p_reflist[11]) | + G1_REG_PINIT_RLIST_F10(p_reflist[10]); + vdpu_write_relaxed(vpu, reg, G1_SWREG(11)); + + reg = G1_REG_REFER1_NBR(hantro_h264_get_ref_nbr(ctx, 1)) | + G1_REG_REFER0_NBR(hantro_h264_get_ref_nbr(ctx, 0)); + vdpu_write_relaxed(vpu, reg, G1_SWREG(30)); + + reg = G1_REG_REFER3_NBR(hantro_h264_get_ref_nbr(ctx, 3)) | + G1_REG_REFER2_NBR(hantro_h264_get_ref_nbr(ctx, 2)); + vdpu_write_relaxed(vpu, reg, G1_SWREG(31)); + + reg = G1_REG_REFER5_NBR(hantro_h264_get_ref_nbr(ctx, 5)) | + G1_REG_REFER4_NBR(hantro_h264_get_ref_nbr(ctx, 4)); + vdpu_write_relaxed(vpu, reg, G1_SWREG(32)); + + reg = G1_REG_REFER7_NBR(hantro_h264_get_ref_nbr(ctx, 7)) | + G1_REG_REFER6_NBR(hantro_h264_get_ref_nbr(ctx, 6)); + vdpu_write_relaxed(vpu, reg, G1_SWREG(33)); + + reg = G1_REG_REFER9_NBR(hantro_h264_get_ref_nbr(ctx, 9)) | + G1_REG_REFER8_NBR(hantro_h264_get_ref_nbr(ctx, 8)); + vdpu_write_relaxed(vpu, reg, G1_SWREG(34)); + + reg = G1_REG_REFER11_NBR(hantro_h264_get_ref_nbr(ctx, 11)) | + G1_REG_REFER10_NBR(hantro_h264_get_ref_nbr(ctx, 10)); + vdpu_write_relaxed(vpu, reg, G1_SWREG(35)); + + reg = G1_REG_REFER13_NBR(hantro_h264_get_ref_nbr(ctx, 13)) | + G1_REG_REFER12_NBR(hantro_h264_get_ref_nbr(ctx, 12)); + vdpu_write_relaxed(vpu, reg, G1_SWREG(36)); + + reg = G1_REG_REFER15_NBR(hantro_h264_get_ref_nbr(ctx, 15)) | + G1_REG_REFER14_NBR(hantro_h264_get_ref_nbr(ctx, 14)); + vdpu_write_relaxed(vpu, reg, G1_SWREG(37)); + + reg = G1_REG_REFER_LTERM_E(ctx->h264_dec.dpb_longterm); + vdpu_write_relaxed(vpu, reg, G1_SWREG(38)); + + reg = G1_REG_REFER_VALID_E(ctx->h264_dec.dpb_valid); + vdpu_write_relaxed(vpu, reg, G1_SWREG(39)); + + reg = G1_REG_BINIT_RLIST_B2(b1_reflist[2]) | + G1_REG_BINIT_RLIST_F2(b0_reflist[2]) | + G1_REG_BINIT_RLIST_B1(b1_reflist[1]) | + G1_REG_BINIT_RLIST_F1(b0_reflist[1]) | + G1_REG_BINIT_RLIST_B0(b1_reflist[0]) | + G1_REG_BINIT_RLIST_F0(b0_reflist[0]); + vdpu_write_relaxed(vpu, reg, G1_SWREG(42)); + + reg = G1_REG_BINIT_RLIST_B5(b1_reflist[5]) | + G1_REG_BINIT_RLIST_F5(b0_reflist[5]) | + G1_REG_BINIT_RLIST_B4(b1_reflist[4]) | + G1_REG_BINIT_RLIST_F4(b0_reflist[4]) | + G1_REG_BINIT_RLIST_B3(b1_reflist[3]) | + G1_REG_BINIT_RLIST_F3(b0_reflist[3]); + vdpu_write_relaxed(vpu, reg, G1_SWREG(43)); + + reg = G1_REG_BINIT_RLIST_B8(b1_reflist[8]) | + G1_REG_BINIT_RLIST_F8(b0_reflist[8]) | + G1_REG_BINIT_RLIST_B7(b1_reflist[7]) | + G1_REG_BINIT_RLIST_F7(b0_reflist[7]) | + G1_REG_BINIT_RLIST_B6(b1_reflist[6]) | + G1_REG_BINIT_RLIST_F6(b0_reflist[6]); + vdpu_write_relaxed(vpu, reg, G1_SWREG(44)); + + reg = G1_REG_BINIT_RLIST_B11(b1_reflist[11]) | + G1_REG_BINIT_RLIST_F11(b0_reflist[11]) | + G1_REG_BINIT_RLIST_B10(b1_reflist[10]) | + G1_REG_BINIT_RLIST_F10(b0_reflist[10]) | + G1_REG_BINIT_RLIST_B9(b1_reflist[9]) | + G1_REG_BINIT_RLIST_F9(b0_reflist[9]); + vdpu_write_relaxed(vpu, reg, G1_SWREG(45)); + + reg = G1_REG_BINIT_RLIST_B14(b1_reflist[14]) | + G1_REG_BINIT_RLIST_F14(b0_reflist[14]) | + G1_REG_BINIT_RLIST_B13(b1_reflist[13]) | + G1_REG_BINIT_RLIST_F13(b0_reflist[13]) | + G1_REG_BINIT_RLIST_B12(b1_reflist[12]) | + G1_REG_BINIT_RLIST_F12(b0_reflist[12]); + vdpu_write_relaxed(vpu, reg, G1_SWREG(46)); + + reg = G1_REG_PINIT_RLIST_F3(p_reflist[3]) | + G1_REG_PINIT_RLIST_F2(p_reflist[2]) | + G1_REG_PINIT_RLIST_F1(p_reflist[1]) | + G1_REG_PINIT_RLIST_F0(p_reflist[0]) | + G1_REG_BINIT_RLIST_B15(b1_reflist[15]) | + G1_REG_BINIT_RLIST_F15(b0_reflist[15]); + vdpu_write_relaxed(vpu, reg, G1_SWREG(47)); + + reg = G1_REG_STARTMB_X(0) | + G1_REG_STARTMB_Y(0); + vdpu_write_relaxed(vpu, reg, G1_SWREG(48)); + + reg = G1_REG_PRED_BC_TAP_0_0(1) | + G1_REG_PRED_BC_TAP_0_1((u32)-5) | + G1_REG_PRED_BC_TAP_0_2(20); + vdpu_write_relaxed(vpu, reg, G1_SWREG(49)); + + reg = G1_REG_REFBU_E(0); + vdpu_write_relaxed(vpu, reg, G1_SWREG(51)); + + reg = G1_REG_APF_THRESHOLD(8); + vdpu_write_relaxed(vpu, reg, G1_SWREG(55)); -static void set_buffers(struct hantro_ctx *ctx) -{ - const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; - struct vb2_v4l2_buffer *src_buf, *dst_buf; - struct hantro_dev *vpu = ctx->dev; - dma_addr_t src_dma, dst_dma; - unsigned int offset = MV_OFFSET_420; - - src_buf = hantro_get_src_buf(ctx); - dst_buf = hantro_get_dst_buf(ctx); + /* Auxiliary buffer prepared in hantro_g1_h264_dec_prepare_table(). */ + vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, G1_REG_QTABLE_BASE); /* Source (stream) buffer. */ - src_dma = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); - vdpu_write_relaxed(vpu, src_dma, G1_REG_ADDR_STR); + addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); + vdpu_write_relaxed(vpu, addr, G1_REG_RLC_VLC_BASE); /* Destination (decoded frame) buffer. */ - dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); + addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); if (ctrls->slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) - dst_dma += ALIGN(ctx->dst_fmt.width, H264_MB_DIM); - vdpu_write_relaxed(vpu, dst_dma, G1_REG_ADDR_DST); + addr += ALIGN(ctx->dst_fmt.width, H264_MB_DIM); + vdpu_write_relaxed(vpu, addr, G1_REG_DEC_OUT_BASE); /* Motion vector buffer is located after the decoded frame. */ - dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); - if (ctrls->sps->profile_idc >= 100 && ctrls->sps->chroma_format_idc == 0) + addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); + if (sps->profile_idc >= 100 && sps->chroma_format_idc == 0) offset = MV_OFFSET_400; - dst_dma += offset * H264_MB_WIDTH(ctx->dst_fmt.width) * + addr += offset * H264_MB_WIDTH(ctx->dst_fmt.width) * H264_MB_HEIGHT(ctx->dst_fmt.height); if (ctrls->slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) - dst_dma += 32 * H264_MB_WIDTH(ctx->dst_fmt.width) * + addr += 32 * H264_MB_WIDTH(ctx->dst_fmt.width) * H264_MB_HEIGHT(ctx->dst_fmt.height); - vdpu_write_relaxed(vpu, dst_dma, G1_REG_ADDR_DIR_MV); - - /* Auxiliary buffer prepared in hantro_g1_h264_dec_prepare_table(). */ - vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, G1_REG_ADDR_QTABLE); -} - -void hantro_g1_h264_dec_run(struct hantro_ctx *ctx) -{ - struct hantro_dev *vpu = ctx->dev; - - /* Prepare the H264 decoder context. */ - if (hantro_h264_dec_prepare_run(ctx)) - return; - - /* Configure hardware registers. */ - set_params(ctx); - set_ref(ctx); - set_buffers(ctx); + vdpu_write_relaxed(vpu, addr, G1_REG_DIR_MV_BASE); + + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 0), G1_REG_REFER0_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 1), G1_REG_REFER1_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 2), G1_REG_REFER2_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 3), G1_REG_REFER3_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 4), G1_REG_REFER4_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 5), G1_REG_REFER5_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 6), G1_REG_REFER6_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 7), G1_REG_REFER7_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 8), G1_REG_REFER8_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 9), G1_REG_REFER9_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 10), G1_REG_REFER10_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 11), G1_REG_REFER11_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 12), G1_REG_REFER12_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 13), G1_REG_REFER13_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 14), G1_REG_REFER14_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 15), G1_REG_REFER15_BASE); hantro_finish_run(ctx); /* Start decoding! */ - vdpu_write_relaxed(vpu, - G1_REG_CONFIG_DEC_AXI_RD_ID(0xffu) | - G1_REG_CONFIG_DEC_TIMEOUT_E | - G1_REG_CONFIG_DEC_OUT_ENDIAN | - G1_REG_CONFIG_DEC_STRENDIAN_E | - G1_REG_CONFIG_DEC_MAX_BURST(16) | - G1_REG_CONFIG_DEC_OUTSWAP32_E | - G1_REG_CONFIG_DEC_INSWAP32_E | - G1_REG_CONFIG_DEC_STRSWAP32_E | - G1_REG_CONFIG_DEC_CLK_GATE_E, - G1_REG_CONFIG); - vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT); + reg = G1_REG_DEC_E(1); + vdpu_write(vpu, reg, G1_SWREG(1)); } diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c index 85c86d728b1a..03b37e00b6fd 100644 --- a/drivers/staging/media/hantro/hantro_h264.c +++ b/drivers/staging/media/hantro/hantro_h264.c @@ -591,6 +591,20 @@ dma_addr_t hantro_h264_get_ref_dma_addr(struct hantro_ctx *ctx, return vb2_dma_contig_plane_dma_addr(buf, 0) | flags; } +u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, + unsigned int dpb_idx) +{ + const struct v4l2_h264_dpb_entry *dpb = &ctx->h264_dec.dpb[dpb_idx]; + + if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) + return 0; + + if (dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) + return dpb->pic_num; + + return dpb->frame_num; +} + int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx) { struct hantro_h264_dec_hw_ctx *h264_ctx = &ctx->h264_dec; diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h index d58f2a36ca40..51de2fee2233 100644 --- a/drivers/staging/media/hantro/hantro_hw.h +++ b/drivers/staging/media/hantro/hantro_hw.h @@ -161,6 +161,8 @@ struct vb2_buffer *hantro_h264_get_ref_buf(struct hantro_ctx *ctx, unsigned int dpb_idx); dma_addr_t hantro_h264_get_ref_dma_addr(struct hantro_ctx *ctx, unsigned int dpb_idx); +u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, + unsigned int dpb_idx); int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx); void hantro_g1_h264_dec_run(struct hantro_ctx *ctx); int hantro_h264_dec_init(struct hantro_ctx *ctx); From patchwork Sun Sep 1 12:45:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Karlman X-Patchwork-Id: 11125237 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9D8261395 for ; Sun, 1 Sep 2019 12:46:09 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7773B23429 for ; Sun, 1 Sep 2019 12:46:09 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Sun, 1 Sep 2019 12:45:48 +0000 Received: from HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088]) by HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088%3]) with mapi id 15.20.2199.021; Sun, 1 Sep 2019 12:45:48 +0000 From: Jonas Karlman To: Ezequiel Garcia Subject: [RFC 10/12] media: hantro: Add support for H264 decoding on RK3399 Thread-Topic: [RFC 10/12] media: hantro: Add support for H264 decoding on RK3399 Thread-Index: AQHVYMMtg5M5ndr2ZkScDZ0tFJAWDw== Date: Sun, 1 Sep 2019 12:45:48 +0000 Message-ID: References: <20190901124531.23645-1-jonas@kwiboo.se> In-Reply-To: <20190901124531.23645-1-jonas@kwiboo.se> Accept-Language: sv-SE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR05CA0343.eurprd05.prod.outlook.com (2603:10a6:7:92::38) To HE1PR06MB4011.eurprd06.prod.outlook.com (2603:10a6:7:9c::32) x-incomingtopheadermarker: OriginalChecksum:47A84D3F827669B0689E991CC05BEE1A3366AA89E8485A8457F6471EC0AA3AE1; UpperCasedChecksum:4F657246377D395C615F9ACA1B8EBFC6486F1A2DFC634F0A2C183A0189D9182C; SizeAsReceived:7903; Count:50 x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-tmn: [SJOEu5rMWvsiJKkxLWAsEIl0ZZP28EYL] x-microsoft-original-message-id: <20190901124531.23645-10-jonas@kwiboo.se> x-ms-publictraffictype: Email x-incomingheadercount: 50 x-eopattributedmessage: 0 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(5050001)(7020095)(20181119110)(201702061078)(5061506573)(5061507331)(1603103135)(2017031320274)(2017031322404)(2017031323274)(2017031324274)(1601125500)(1603101475)(1701031045); SRVR:HE1EUR01HT077; x-ms-traffictypediagnostic: HE1EUR01HT077: x-microsoft-antispam-message-info: s6IYQNeYSefO1n1orj0S7gp89RTCofH2m4vTpMxBeqk5tGkb1hLwJicmCrp2N+OKHJ8RsZxBTjzS8YCc+HZj6/icW5TkPk1v+z1jBxHisYAy/NTcCoI6GEuQnnyC/1QOG5Rh3jLfMWvMUQtmpePBrSHfHiWJQSFl6H6BWbbeDZDA93c56EE+hPTWpa/S/NRY x-ms-exchange-transport-forked: True MIME-Version: 1.0 X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-CrossTenant-Network-Message-Id: 2a109ab1-670f-49fe-ac47-08d72eda502a X-MS-Exchange-CrossTenant-rms-persistedconsumerorg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Sep 2019 12:45:48.2819 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Internet X-MS-Exchange-CrossTenant-id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1EUR01HT077 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190901_054551_847569_49E08C00 X-CRM114-Status: GOOD ( 12.48 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [40.92.65.60 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Kocialkowski , Jonas Karlman , "linux-kernel@vger.kernel.org" , Hans Verkuil , "linux-rockchip@lists.infradead.org" , Boris Brezillon , Philipp Zabel , Mauro Carvalho Chehab , "linux-media@vger.kernel.org" Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Rockchip RK3399 SoC has the same Hantro G1 IP block as RK3288, but the registers are entirely different. In a similar fashion as MPEG-2 and VP8 decoding, it's simpler to just add a separate implementation. Signed-off-by: Jonas Karlman --- drivers/staging/media/hantro/Makefile | 1 + .../staging/media/hantro/hantro_g1_h264_dec.c | 1 - drivers/staging/media/hantro/hantro_hw.h | 1 + .../media/hantro/rk3399_vpu_hw_h264_dec.c | 486 ++++++++++++++++++ 4 files changed, 488 insertions(+), 1 deletion(-) create mode 100644 drivers/staging/media/hantro/rk3399_vpu_hw_h264_dec.c diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile index 5d6b0383d280..8d33b0e8aa6c 100644 --- a/drivers/staging/media/hantro/Makefile +++ b/drivers/staging/media/hantro/Makefile @@ -8,6 +8,7 @@ hantro-vpu-y += \ hantro_g1_mpeg2_dec.o \ hantro_g1_vp8_dec.o \ rk3399_vpu_hw_jpeg_enc.o \ + rk3399_vpu_hw_h264_dec.o \ rk3399_vpu_hw_mpeg2_dec.o \ rk3399_vpu_hw_vp8_dec.o \ hantro_jpeg.o \ diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c index 4b82b9fd5252..ec2736fb473d 100644 --- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c +++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c @@ -202,7 +202,6 @@ #define G1_REG_REFBU_E(v) ((v) ? BIT(31) : 0) #define G1_REG_APF_THRESHOLD(v) (((v) << 0) & GENMASK(13, 0)) ->>>>>>> b22734fb5e2c... Ymedia: hantro: Refactor G1 H264 code void hantro_g1_h264_dec_run(struct hantro_ctx *ctx) { diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h index 51de2fee2233..00161a4f22ac 100644 --- a/drivers/staging/media/hantro/hantro_hw.h +++ b/drivers/staging/media/hantro/hantro_hw.h @@ -165,6 +165,7 @@ u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, unsigned int dpb_idx); int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx); void hantro_g1_h264_dec_run(struct hantro_ctx *ctx); +void rk3399_vpu_h264_dec_run(struct hantro_ctx *ctx); int hantro_h264_dec_init(struct hantro_ctx *ctx); void hantro_h264_dec_exit(struct hantro_ctx *ctx); diff --git a/drivers/staging/media/hantro/rk3399_vpu_hw_h264_dec.c b/drivers/staging/media/hantro/rk3399_vpu_hw_h264_dec.c new file mode 100644 index 000000000000..8e480a68ca3d --- /dev/null +++ b/drivers/staging/media/hantro/rk3399_vpu_hw_h264_dec.c @@ -0,0 +1,486 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Hantro VPU codec driver + * + * Copyright (c) 2014 Rockchip Electronics Co., Ltd. + * Hertz Wong + * Herman Chen + * + * Copyright (C) 2014 Google, Inc. + * Tomasz Figa + */ + +#include +#include + +#include + +#include "hantro_hw.h" +#include "hantro_v4l2.h" + +#define MV_OFFSET_420 384 +#define MV_OFFSET_400 256 + +#define VDPU_SWREG(nr) ((nr) * 4) + +#define VDPU_REG_DEC_OUT_BASE VDPU_SWREG(63) +#define VDPU_REG_RLC_VLC_BASE VDPU_SWREG(64) +#define VDPU_REG_QTABLE_BASE VDPU_SWREG(61) +#define VDPU_REG_DIR_MV_BASE VDPU_SWREG(62) +#define VDPU_REG_REFER0_BASE VDPU_SWREG(84) +#define VDPU_REG_REFER1_BASE VDPU_SWREG(85) +#define VDPU_REG_REFER2_BASE VDPU_SWREG(86) +#define VDPU_REG_REFER3_BASE VDPU_SWREG(87) +#define VDPU_REG_REFER4_BASE VDPU_SWREG(88) +#define VDPU_REG_REFER5_BASE VDPU_SWREG(89) +#define VDPU_REG_REFER6_BASE VDPU_SWREG(90) +#define VDPU_REG_REFER7_BASE VDPU_SWREG(91) +#define VDPU_REG_REFER8_BASE VDPU_SWREG(92) +#define VDPU_REG_REFER9_BASE VDPU_SWREG(93) +#define VDPU_REG_REFER10_BASE VDPU_SWREG(94) +#define VDPU_REG_REFER11_BASE VDPU_SWREG(95) +#define VDPU_REG_REFER12_BASE VDPU_SWREG(96) +#define VDPU_REG_REFER13_BASE VDPU_SWREG(97) +#define VDPU_REG_REFER14_BASE VDPU_SWREG(98) +#define VDPU_REG_REFER15_BASE VDPU_SWREG(99) +#define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) + +#define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) +#define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) +#define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) +#define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) +#define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) + +#define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) +#define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) + +#define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) +#define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) +#define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0)) + +#define VDPU_REG_DEC_MODE(v) (((v) << 0) & GENMASK(3, 0)) + +#define VDPU_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(5) : 0) +#define VDPU_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(4) : 0) +#define VDPU_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(3) : 0) +#define VDPU_REG_DEC_INSWAP32_E(v) ((v) ? BIT(2) : 0) +#define VDPU_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(1) : 0) +#define VDPU_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(0) : 0) + +#define VDPU_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(22) : 0) +#define VDPU_REG_DEC_MAX_BURST(v) (((v) << 16) & GENMASK(20, 16)) +#define VDPU_REG_DEC_AXI_WR_ID(v) (((v) << 8) & GENMASK(15, 8)) +#define VDPU_REG_DEC_AXI_RD_ID(v) (((v) << 0) & GENMASK(7, 0)) + +#define VDPU_REG_START_CODE_E(v) ((v) ? BIT(22) : 0) +#define VDPU_REG_CH_8PIX_ILEAV_E(v) ((v) ? BIT(21) : 0) +#define VDPU_REG_RLC_MODE_E(v) ((v) ? BIT(20) : 0) +#define VDPU_REG_PIC_INTERLACE_E(v) ((v) ? BIT(17) : 0) +#define VDPU_REG_PIC_FIELDMODE_E(v) ((v) ? BIT(16) : 0) +#define VDPU_REG_PIC_TOPFIELD_E(v) ((v) ? BIT(13) : 0) +#define VDPU_REG_WRITE_MVS_E(v) ((v) ? BIT(10) : 0) +#define VDPU_REG_SEQ_MBAFF_E(v) ((v) ? BIT(7) : 0) +#define VDPU_REG_PICORD_COUNT_E(v) ((v) ? BIT(6) : 0) +#define VDPU_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(5) : 0) +#define VDPU_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(4) : 0) + +#define VDPU_REG_PRED_BC_TAP_0_0(v) (((v) << 22) & GENMASK(31, 22)) +#define VDPU_REG_PRED_BC_TAP_0_1(v) (((v) << 12) & GENMASK(21, 12)) +#define VDPU_REG_PRED_BC_TAP_0_2(v) (((v) << 2) & GENMASK(11, 2)) + +#define VDPU_REG_REFBU_E(v) ((v) ? BIT(31) : 0) + +#define VDPU_REG_PINIT_RLIST_F9(v) (((v) << 25) & GENMASK(29, 25)) +#define VDPU_REG_PINIT_RLIST_F8(v) (((v) << 20) & GENMASK(24, 20)) +#define VDPU_REG_PINIT_RLIST_F7(v) (((v) << 15) & GENMASK(19, 15)) +#define VDPU_REG_PINIT_RLIST_F6(v) (((v) << 10) & GENMASK(14, 10)) +#define VDPU_REG_PINIT_RLIST_F5(v) (((v) << 5) & GENMASK(9, 5)) +#define VDPU_REG_PINIT_RLIST_F4(v) (((v) << 0) & GENMASK(4, 0)) + +#define VDPU_REG_PINIT_RLIST_F15(v) (((v) << 25) & GENMASK(29, 25)) +#define VDPU_REG_PINIT_RLIST_F14(v) (((v) << 20) & GENMASK(24, 20)) +#define VDPU_REG_PINIT_RLIST_F13(v) (((v) << 15) & GENMASK(19, 15)) +#define VDPU_REG_PINIT_RLIST_F12(v) (((v) << 10) & GENMASK(14, 10)) +#define VDPU_REG_PINIT_RLIST_F11(v) (((v) << 5) & GENMASK(9, 5)) +#define VDPU_REG_PINIT_RLIST_F10(v) (((v) << 0) & GENMASK(4, 0)) + +#define VDPU_REG_REFER1_NBR(v) (((v) << 16) & GENMASK(31, 16)) +#define VDPU_REG_REFER0_NBR(v) (((v) << 0) & GENMASK(15, 0)) + +#define VDPU_REG_REFER3_NBR(v) (((v) << 16) & GENMASK(31, 16)) +#define VDPU_REG_REFER2_NBR(v) (((v) << 0) & GENMASK(15, 0)) + +#define VDPU_REG_REFER5_NBR(v) (((v) << 16) & GENMASK(31, 16)) +#define VDPU_REG_REFER4_NBR(v) (((v) << 0) & GENMASK(15, 0)) + +#define VDPU_REG_REFER7_NBR(v) (((v) << 16) & GENMASK(31, 16)) +#define VDPU_REG_REFER6_NBR(v) (((v) << 0) & GENMASK(15, 0)) + +#define VDPU_REG_REFER9_NBR(v) (((v) << 16) & GENMASK(31, 16)) +#define VDPU_REG_REFER8_NBR(v) (((v) << 0) & GENMASK(15, 0)) + +#define VDPU_REG_REFER11_NBR(v) (((v) << 16) & GENMASK(31, 16)) +#define VDPU_REG_REFER10_NBR(v) (((v) << 0) & GENMASK(15, 0)) + +#define VDPU_REG_REFER13_NBR(v) (((v) << 16) & GENMASK(31, 16)) +#define VDPU_REG_REFER12_NBR(v) (((v) << 0) & GENMASK(15, 0)) + +#define VDPU_REG_REFER15_NBR(v) (((v) << 16) & GENMASK(31, 16)) +#define VDPU_REG_REFER14_NBR(v) (((v) << 0) & GENMASK(15, 0)) + +#define VDPU_REG_BINIT_RLIST_F5(v) (((v) << 25) & GENMASK(29, 25)) +#define VDPU_REG_BINIT_RLIST_F4(v) (((v) << 20) & GENMASK(24, 20)) +#define VDPU_REG_BINIT_RLIST_F3(v) (((v) << 15) & GENMASK(19, 15)) +#define VDPU_REG_BINIT_RLIST_F2(v) (((v) << 10) & GENMASK(14, 10)) +#define VDPU_REG_BINIT_RLIST_F1(v) (((v) << 5) & GENMASK(9, 5)) +#define VDPU_REG_BINIT_RLIST_F0(v) (((v) << 0) & GENMASK(4, 0)) + +#define VDPU_REG_BINIT_RLIST_F11(v) (((v) << 25) & GENMASK(29, 25)) +#define VDPU_REG_BINIT_RLIST_F10(v) (((v) << 20) & GENMASK(24, 20)) +#define VDPU_REG_BINIT_RLIST_F9(v) (((v) << 15) & GENMASK(19, 15)) +#define VDPU_REG_BINIT_RLIST_F8(v) (((v) << 10) & GENMASK(14, 10)) +#define VDPU_REG_BINIT_RLIST_F7(v) (((v) << 5) & GENMASK(9, 5)) +#define VDPU_REG_BINIT_RLIST_F6(v) (((v) << 0) & GENMASK(4, 0)) + +#define VDPU_REG_BINIT_RLIST_F15(v) (((v) << 15) & GENMASK(19, 15)) +#define VDPU_REG_BINIT_RLIST_F14(v) (((v) << 10) & GENMASK(14, 10)) +#define VDPU_REG_BINIT_RLIST_F13(v) (((v) << 5) & GENMASK(9, 5)) +#define VDPU_REG_BINIT_RLIST_F12(v) (((v) << 0) & GENMASK(4, 0)) + +#define VDPU_REG_BINIT_RLIST_B5(v) (((v) << 25) & GENMASK(29, 25)) +#define VDPU_REG_BINIT_RLIST_B4(v) (((v) << 20) & GENMASK(24, 20)) +#define VDPU_REG_BINIT_RLIST_B3(v) (((v) << 15) & GENMASK(19, 15)) +#define VDPU_REG_BINIT_RLIST_B2(v) (((v) << 10) & GENMASK(14, 10)) +#define VDPU_REG_BINIT_RLIST_B1(v) (((v) << 5) & GENMASK(9, 5)) +#define VDPU_REG_BINIT_RLIST_B0(v) (((v) << 0) & GENMASK(4, 0)) + +#define VDPU_REG_BINIT_RLIST_B11(v) (((v) << 25) & GENMASK(29, 25)) +#define VDPU_REG_BINIT_RLIST_B10(v) (((v) << 20) & GENMASK(24, 20)) +#define VDPU_REG_BINIT_RLIST_B9(v) (((v) << 15) & GENMASK(19, 15)) +#define VDPU_REG_BINIT_RLIST_B8(v) (((v) << 10) & GENMASK(14, 10)) +#define VDPU_REG_BINIT_RLIST_B7(v) (((v) << 5) & GENMASK(9, 5)) +#define VDPU_REG_BINIT_RLIST_B6(v) (((v) << 0) & GENMASK(4, 0)) + +#define VDPU_REG_BINIT_RLIST_B15(v) (((v) << 15) & GENMASK(19, 15)) +#define VDPU_REG_BINIT_RLIST_B14(v) (((v) << 10) & GENMASK(14, 10)) +#define VDPU_REG_BINIT_RLIST_B13(v) (((v) << 5) & GENMASK(9, 5)) +#define VDPU_REG_BINIT_RLIST_B12(v) (((v) << 0) & GENMASK(4, 0)) + +#define VDPU_REG_PINIT_RLIST_F3(v) (((v) << 15) & GENMASK(19, 15)) +#define VDPU_REG_PINIT_RLIST_F2(v) (((v) << 10) & GENMASK(14, 10)) +#define VDPU_REG_PINIT_RLIST_F1(v) (((v) << 5) & GENMASK(9, 5)) +#define VDPU_REG_PINIT_RLIST_F0(v) (((v) << 0) & GENMASK(4, 0)) + +#define VDPU_REG_REFER_LTERM_E(v) (((v) << 0) & GENMASK(31, 0)) + +#define VDPU_REG_REFER_VALID_E(v) (((v) << 0) & GENMASK(31, 0)) + +#define VDPU_REG_STRM_START_BIT(v) (((v) << 0) & GENMASK(5, 0)) + +#define VDPU_REG_CH_QP_OFFSET2(v) (((v) << 22) & GENMASK(26, 22)) +#define VDPU_REG_CH_QP_OFFSET(v) (((v) << 17) & GENMASK(21, 17)) +#define VDPU_REG_PIC_MB_HEIGHT_P(v) (((v) << 9) & GENMASK(16, 9)) +#define VDPU_REG_PIC_MB_WIDTH(v) (((v) << 0) & GENMASK(8, 0)) + +#define VDPU_REG_WEIGHT_BIPR_IDC(v) (((v) << 16) & GENMASK(17, 16)) +#define VDPU_REG_REF_FRAMES(v) (((v) << 0) & GENMASK(4, 0)) + +#define VDPU_REG_FILT_CTRL_PRES(v) ((v) ? BIT(31) : 0) +#define VDPU_REG_RDPIC_CNT_PRES(v) ((v) ? BIT(30) : 0) +#define VDPU_REG_FRAMENUM_LEN(v) (((v) << 16) & GENMASK(20, 16)) +#define VDPU_REG_FRAMENUM(v) (((v) << 0) & GENMASK(15, 0)) + +#define VDPU_REG_REFPIC_MK_LEN(v) (((v) << 16) & GENMASK(26, 16)) +#define VDPU_REG_IDR_PIC_ID(v) (((v) << 0) & GENMASK(15, 0)) + +#define VDPU_REG_PPS_ID(v) (((v) << 24) & GENMASK(31, 24)) +#define VDPU_REG_REFIDX1_ACTIVE(v) (((v) << 19) & GENMASK(23, 19)) +#define VDPU_REG_REFIDX0_ACTIVE(v) (((v) << 14) & GENMASK(18, 14)) +#define VDPU_REG_POC_LENGTH(v) (((v) << 0) & GENMASK(7, 0)) + +#define VDPU_REG_IDR_PIC_E(v) ((v) ? BIT(8) : 0) +#define VDPU_REG_DIR_8X8_INFER_E(v) ((v) ? BIT(7) : 0) +#define VDPU_REG_BLACKWHITE_E(v) ((v) ? BIT(6) : 0) +#define VDPU_REG_CABAC_E(v) ((v) ? BIT(5) : 0) +#define VDPU_REG_WEIGHT_PRED_E(v) ((v) ? BIT(4) : 0) +#define VDPU_REG_CONST_INTRA_E(v) ((v) ? BIT(3) : 0) +#define VDPU_REG_8X8TRANS_FLAG_E(v) ((v) ? BIT(2) : 0) +#define VDPU_REG_TYPE1_QUANT_E(v) ((v) ? BIT(1) : 0) +#define VDPU_REG_FIELDPIC_FLAG_E(v) ((v) ? BIT(0) : 0) + +void rk3399_vpu_h264_dec_run(struct hantro_ctx *ctx) +{ + struct hantro_dev *vpu = ctx->dev; + struct vb2_v4l2_buffer *src_buf, *dst_buf; + const struct hantro_h264_dec_ctrls *ctrls; + const struct v4l2_ctrl_h264_decode_params *dec_param; + const struct v4l2_ctrl_h264_slice_params *slices; + const struct v4l2_ctrl_h264_sps *sps; + const struct v4l2_ctrl_h264_pps *pps; + const u8 *b0_reflist, *b1_reflist, *p_reflist; + dma_addr_t addr; + u32 reg; + unsigned int offset = MV_OFFSET_420; + + /* Prepare the H264 decoder context. */ + if (hantro_h264_dec_prepare_run(ctx)) + return; + + src_buf = hantro_get_src_buf(ctx); + dst_buf = hantro_get_dst_buf(ctx); + + ctrls = &ctx->h264_dec.ctrls; + dec_param = ctrls->decode; + slices = ctrls->slices; + sps = ctrls->sps; + pps = ctrls->pps; + + b0_reflist = ctx->h264_dec.reflists.b0; + b1_reflist = ctx->h264_dec.reflists.b1; + p_reflist = ctx->h264_dec.reflists.p; + + reg = VDPU_REG_DEC_ADV_PRE_DIS(0) | + VDPU_REG_DEC_SCMD_DIS(0) | + VDPU_REG_FILTERING_DIS(0) | + VDPU_REG_PIC_FIXED_QUANT(0) | + VDPU_REG_DEC_LATENCY(0); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50)); + + reg = VDPU_REG_INIT_QP(pps->pic_init_qp_minus26 + 26) | + VDPU_REG_STREAM_LEN(vb2_get_plane_payload(&src_buf->vb2_buf, 0)); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51)); + + reg = VDPU_REG_APF_THRESHOLD(8) | + VDPU_REG_STARTMB_X(0) | + VDPU_REG_STARTMB_Y(0); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52)); + + reg = VDPU_REG_DEC_MODE(0); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53)); + + reg = VDPU_REG_DEC_STRENDIAN_E(1) | + VDPU_REG_DEC_STRSWAP32_E(1) | + VDPU_REG_DEC_OUTSWAP32_E(1) | + VDPU_REG_DEC_INSWAP32_E(1) | + VDPU_REG_DEC_OUT_ENDIAN(1) | + VDPU_REG_DEC_IN_ENDIAN(0); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54)); + + reg = VDPU_REG_DEC_DATA_DISC_E(0) | + VDPU_REG_DEC_MAX_BURST(16) | + VDPU_REG_DEC_AXI_WR_ID(0) | + VDPU_REG_DEC_AXI_RD_ID(0xff); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56)); + + reg = VDPU_REG_START_CODE_E(1) | + VDPU_REG_CH_8PIX_ILEAV_E(0) | + VDPU_REG_RLC_MODE_E(0) | + VDPU_REG_PIC_INTERLACE_E(!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) && (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD || slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC)) | + VDPU_REG_PIC_FIELDMODE_E(slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) | + VDPU_REG_PIC_TOPFIELD_E(!(slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD)) | + VDPU_REG_WRITE_MVS_E(dec_param->nal_ref_idc) | + VDPU_REG_SEQ_MBAFF_E(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) | + VDPU_REG_PICORD_COUNT_E(1) | + VDPU_REG_DEC_TIMEOUT_E(1) | + VDPU_REG_DEC_CLK_GATE_E(1); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57)); + + reg = VDPU_REG_PRED_BC_TAP_0_0(1) | + VDPU_REG_PRED_BC_TAP_0_1((u32)-5) | + VDPU_REG_PRED_BC_TAP_0_2(20); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(59)); + + reg = VDPU_REG_REFBU_E(0); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(65)); + + reg = VDPU_REG_PINIT_RLIST_F9(p_reflist[9]) | + VDPU_REG_PINIT_RLIST_F8(p_reflist[8]) | + VDPU_REG_PINIT_RLIST_F7(p_reflist[7]) | + VDPU_REG_PINIT_RLIST_F6(p_reflist[6]) | + VDPU_REG_PINIT_RLIST_F5(p_reflist[5]) | + VDPU_REG_PINIT_RLIST_F4(p_reflist[4]); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(74)); + + reg = VDPU_REG_PINIT_RLIST_F15(p_reflist[15]) | + VDPU_REG_PINIT_RLIST_F14(p_reflist[14]) | + VDPU_REG_PINIT_RLIST_F13(p_reflist[13]) | + VDPU_REG_PINIT_RLIST_F12(p_reflist[12]) | + VDPU_REG_PINIT_RLIST_F11(p_reflist[11]) | + VDPU_REG_PINIT_RLIST_F10(p_reflist[10]); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(75)); + + reg = VDPU_REG_REFER1_NBR(hantro_h264_get_ref_nbr(ctx, 1)) | + VDPU_REG_REFER0_NBR(hantro_h264_get_ref_nbr(ctx, 0)); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(76)); + + reg = VDPU_REG_REFER3_NBR(hantro_h264_get_ref_nbr(ctx, 3)) | + VDPU_REG_REFER2_NBR(hantro_h264_get_ref_nbr(ctx, 2)); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(77)); + + reg = VDPU_REG_REFER5_NBR(hantro_h264_get_ref_nbr(ctx, 5)) | + VDPU_REG_REFER4_NBR(hantro_h264_get_ref_nbr(ctx, 4)); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(78)); + + reg = VDPU_REG_REFER7_NBR(hantro_h264_get_ref_nbr(ctx, 7)) | + VDPU_REG_REFER6_NBR(hantro_h264_get_ref_nbr(ctx, 6)); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(79)); + + reg = VDPU_REG_REFER9_NBR(hantro_h264_get_ref_nbr(ctx, 9)) | + VDPU_REG_REFER8_NBR(hantro_h264_get_ref_nbr(ctx, 8)); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(80)); + + reg = VDPU_REG_REFER11_NBR(hantro_h264_get_ref_nbr(ctx, 11)) | + VDPU_REG_REFER10_NBR(hantro_h264_get_ref_nbr(ctx, 10)); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(81)); + + reg = VDPU_REG_REFER13_NBR(hantro_h264_get_ref_nbr(ctx, 13)) | + VDPU_REG_REFER12_NBR(hantro_h264_get_ref_nbr(ctx, 12)); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(82)); + + reg = VDPU_REG_REFER15_NBR(hantro_h264_get_ref_nbr(ctx, 15)) | + VDPU_REG_REFER14_NBR(hantro_h264_get_ref_nbr(ctx, 14)); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(83)); + + reg = VDPU_REG_BINIT_RLIST_F5(b0_reflist[5]) | + VDPU_REG_BINIT_RLIST_F4(b0_reflist[4]) | + VDPU_REG_BINIT_RLIST_F3(b0_reflist[3]) | + VDPU_REG_BINIT_RLIST_F2(b0_reflist[2]) | + VDPU_REG_BINIT_RLIST_F1(b0_reflist[1]) | + VDPU_REG_BINIT_RLIST_F0(b0_reflist[0]); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(100)); + + reg = VDPU_REG_BINIT_RLIST_F11(b0_reflist[11]) | + VDPU_REG_BINIT_RLIST_F10(b0_reflist[10]) | + VDPU_REG_BINIT_RLIST_F9(b0_reflist[9]) | + VDPU_REG_BINIT_RLIST_F8(b0_reflist[8]) | + VDPU_REG_BINIT_RLIST_F7(b0_reflist[7]) | + VDPU_REG_BINIT_RLIST_F6(b0_reflist[6]); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(101)); + + reg = VDPU_REG_BINIT_RLIST_F15(b0_reflist[15]) | + VDPU_REG_BINIT_RLIST_F14(b0_reflist[14]) | + VDPU_REG_BINIT_RLIST_F13(b0_reflist[13]) | + VDPU_REG_BINIT_RLIST_F12(b0_reflist[12]); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(102)); + + reg = VDPU_REG_BINIT_RLIST_B5(b1_reflist[5]) | + VDPU_REG_BINIT_RLIST_B4(b1_reflist[4]) | + VDPU_REG_BINIT_RLIST_B3(b1_reflist[3]) | + VDPU_REG_BINIT_RLIST_B2(b1_reflist[2]) | + VDPU_REG_BINIT_RLIST_B1(b1_reflist[1]) | + VDPU_REG_BINIT_RLIST_B0(b1_reflist[0]); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(103)); + + reg = VDPU_REG_BINIT_RLIST_B11(b1_reflist[11]) | + VDPU_REG_BINIT_RLIST_B10(b1_reflist[10]) | + VDPU_REG_BINIT_RLIST_B9(b1_reflist[9]) | + VDPU_REG_BINIT_RLIST_B8(b1_reflist[8]) | + VDPU_REG_BINIT_RLIST_B7(b1_reflist[7]) | + VDPU_REG_BINIT_RLIST_B6(b1_reflist[6]); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(104)); + + reg = VDPU_REG_BINIT_RLIST_B15(b1_reflist[15]) | + VDPU_REG_BINIT_RLIST_B14(b1_reflist[14]) | + VDPU_REG_BINIT_RLIST_B13(b1_reflist[13]) | + VDPU_REG_BINIT_RLIST_B12(b1_reflist[12]); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(105)); + + reg = VDPU_REG_PINIT_RLIST_F3(p_reflist[3]) | + VDPU_REG_PINIT_RLIST_F2(p_reflist[2]) | + VDPU_REG_PINIT_RLIST_F1(p_reflist[1]) | + VDPU_REG_PINIT_RLIST_F0(p_reflist[0]); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(106)); + + reg = VDPU_REG_REFER_LTERM_E(ctx->h264_dec.dpb_longterm); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(107)); + + reg = VDPU_REG_REFER_VALID_E(ctx->h264_dec.dpb_valid); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(108)); + + reg = VDPU_REG_STRM_START_BIT(0); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(109)); + + reg = VDPU_REG_CH_QP_OFFSET2(pps->second_chroma_qp_index_offset) | + VDPU_REG_CH_QP_OFFSET(pps->chroma_qp_index_offset) | + VDPU_REG_PIC_MB_HEIGHT_P(H264_MB_HEIGHT(ctx->dst_fmt.height)) | + VDPU_REG_PIC_MB_WIDTH(H264_MB_WIDTH(ctx->dst_fmt.width)); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(110)); + + reg = VDPU_REG_WEIGHT_BIPR_IDC(pps->weighted_bipred_idc) | + VDPU_REG_REF_FRAMES(sps->max_num_ref_frames); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(111)); + + reg = VDPU_REG_FILT_CTRL_PRES(pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT) | + VDPU_REG_RDPIC_CNT_PRES(pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT) | + VDPU_REG_FRAMENUM_LEN(sps->log2_max_frame_num_minus4 + 4) | + VDPU_REG_FRAMENUM(slices[0].frame_num); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(112)); + + reg = VDPU_REG_REFPIC_MK_LEN(slices[0].dec_ref_pic_marking_bit_size) | + VDPU_REG_IDR_PIC_ID(slices[0].idr_pic_id); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(113)); + + reg = VDPU_REG_PPS_ID(slices[0].pic_parameter_set_id) | + VDPU_REG_REFIDX1_ACTIVE(pps->num_ref_idx_l1_default_active_minus1 + 1) | + VDPU_REG_REFIDX0_ACTIVE(pps->num_ref_idx_l0_default_active_minus1 + 1) | + VDPU_REG_POC_LENGTH(slices[0].pic_order_cnt_bit_size); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(114)); + + reg = VDPU_REG_IDR_PIC_E(dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC) | + VDPU_REG_DIR_8X8_INFER_E(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) | + VDPU_REG_BLACKWHITE_E(sps->profile_idc >= 100 && sps->chroma_format_idc == 0) | + VDPU_REG_CABAC_E(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) | + VDPU_REG_WEIGHT_PRED_E(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) | + VDPU_REG_CONST_INTRA_E(pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) | + VDPU_REG_8X8TRANS_FLAG_E(pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) | + VDPU_REG_TYPE1_QUANT_E(1) | + VDPU_REG_FIELDPIC_FLAG_E(!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)); + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(115)); + + /* Auxiliary buffer prepared in hantro_g1_h264_dec_prepare_table(). */ + vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, VDPU_REG_QTABLE_BASE); + + /* Source (stream) buffer. */ + addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); + vdpu_write_relaxed(vpu, addr, VDPU_REG_RLC_VLC_BASE); + + /* Destination (decoded frame) buffer. */ + addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); + if (ctrls->slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) + addr += ALIGN(ctx->dst_fmt.width, H264_MB_DIM); + vdpu_write_relaxed(vpu, addr, VDPU_REG_DEC_OUT_BASE); + + /* Motion vector buffer is located after the decoded frame. */ + addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); + if (sps->profile_idc >= 100 && sps->chroma_format_idc == 0) + offset = MV_OFFSET_400; + addr += offset * H264_MB_WIDTH(ctx->dst_fmt.width) * + H264_MB_HEIGHT(ctx->dst_fmt.height); + if (ctrls->slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) + addr += 32 * H264_MB_WIDTH(ctx->dst_fmt.width) * + H264_MB_HEIGHT(ctx->dst_fmt.height); + vdpu_write_relaxed(vpu, addr, VDPU_REG_DIR_MV_BASE); + + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 0), VDPU_REG_REFER0_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 1), VDPU_REG_REFER1_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 2), VDPU_REG_REFER2_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 3), VDPU_REG_REFER3_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 4), VDPU_REG_REFER4_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 5), VDPU_REG_REFER5_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 6), VDPU_REG_REFER6_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 7), VDPU_REG_REFER7_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 8), VDPU_REG_REFER8_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 9), VDPU_REG_REFER9_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 10), VDPU_REG_REFER10_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 11), VDPU_REG_REFER11_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 12), VDPU_REG_REFER12_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 13), VDPU_REG_REFER13_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 14), VDPU_REG_REFER14_BASE); + vdpu_write_relaxed(vpu, hantro_h264_get_ref_dma_addr(ctx, 15), VDPU_REG_REFER15_BASE); + + hantro_finish_run(ctx); + + /* Start decoding! */ + reg = vdpu_read(vpu, VDPU_SWREG(57)) | VDPU_REG_DEC_E(1); + vdpu_write(vpu, reg, VDPU_SWREG(57)); +} From patchwork Sun Sep 1 12:45:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Karlman X-Patchwork-Id: 11125235 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 200FF1395 for ; Sun, 1 Sep 2019 12:46:07 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F10202339D for ; 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Sun, 1 Sep 2019 12:45:49 +0000 Received: from HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088]) by HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088%3]) with mapi id 15.20.2199.021; Sun, 1 Sep 2019 12:45:49 +0000 From: Jonas Karlman To: Ezequiel Garcia Subject: [RFC 11/12] media: hantro: Enable H264 decoding on RK3399 Thread-Topic: [RFC 11/12] media: hantro: Enable H264 decoding on RK3399 Thread-Index: AQHVYMMuDWI6fDhY3EmqNKbABGOY+w== Date: Sun, 1 Sep 2019 12:45:48 +0000 Message-ID: References: <20190901124531.23645-1-jonas@kwiboo.se> In-Reply-To: <20190901124531.23645-1-jonas@kwiboo.se> Accept-Language: sv-SE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR05CA0343.eurprd05.prod.outlook.com (2603:10a6:7:92::38) To HE1PR06MB4011.eurprd06.prod.outlook.com (2603:10a6:7:9c::32) x-incomingtopheadermarker: OriginalChecksum:58F41166596F3235D42F35F244D9FADAB9DFBCD681998D37F5038BFB7FAB7343; UpperCasedChecksum:78D786937ABD3FE721B438A70BBDB1E29F071D4732E5CF2F2516808C47EBBB22; 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X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a01:111:f400:fe1f:0:0:0:812 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Kocialkowski , Jonas Karlman , "linux-kernel@vger.kernel.org" , Hans Verkuil , "linux-rockchip@lists.infradead.org" , Boris Brezillon , Philipp Zabel , Mauro Carvalho Chehab , "linux-media@vger.kernel.org" Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org The RK3399 SoC has two VPU blocks capable of H264 decoding, VPU2 and RKVDEC, this enables support for H264 decoding using the VPU2 block. Signed-off-by: Jonas Karlman --- drivers/staging/media/hantro/rk3399_vpu_hw.c | 21 +++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/staging/media/hantro/rk3399_vpu_hw.c b/drivers/staging/media/hantro/rk3399_vpu_hw.c index 14d14bc6b12b..47ca51b75a0d 100644 --- a/drivers/staging/media/hantro/rk3399_vpu_hw.c +++ b/drivers/staging/media/hantro/rk3399_vpu_hw.c @@ -60,6 +60,19 @@ static const struct hantro_fmt rk3399_vpu_dec_fmts[] = { .fourcc = V4L2_PIX_FMT_NV12, .codec_mode = HANTRO_MODE_NONE, }, + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, + .codec_mode = HANTRO_MODE_H264_DEC, + .max_depth = 2, + .frmsize = { + .min_width = 48, + .max_width = 4096, + .step_width = H264_MB_DIM, + .min_height = 48, + .max_height = 2304, + .step_height = H264_MB_DIM, + }, + }, { .fourcc = V4L2_PIX_FMT_MPEG2_SLICE, .codec_mode = HANTRO_MODE_MPEG2_DEC, @@ -161,6 +174,12 @@ static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = { .init = hantro_jpeg_enc_init, .exit = hantro_jpeg_enc_exit, }, + [HANTRO_MODE_H264_DEC] = { + .run = rk3399_vpu_h264_dec_run, + .reset = rk3399_vpu_dec_reset, + .init = hantro_h264_dec_init, + .exit = hantro_h264_dec_exit, + }, [HANTRO_MODE_MPEG2_DEC] = { .run = rk3399_vpu_mpeg2_dec_run, .reset = rk3399_vpu_dec_reset, @@ -196,7 +215,7 @@ const struct hantro_variant rk3399_vpu_variant = { .dec_fmts = rk3399_vpu_dec_fmts, .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | - HANTRO_VP8_DECODER, + HANTRO_VP8_DECODER | HANTRO_H264_DECODER, .codec_ops = rk3399_vpu_codec_ops, .irqs = rk3399_irqs, .num_irqs = ARRAY_SIZE(rk3399_irqs), From patchwork Sun Sep 1 12:45:49 2019 Content-Type: text/plain; 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mx.microsoft.com 1; spf=none; dmarc=none; dkim=none; arc=none Received: from HE1EUR01FT057.eop-EUR01.prod.protection.outlook.com (10.152.0.55) by HE1EUR01HT092.eop-EUR01.prod.protection.outlook.com (10.152.0.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2220.16; Sun, 1 Sep 2019 12:45:49 +0000 Received: from HE1PR06MB4011.eurprd06.prod.outlook.com (10.152.0.52) by HE1EUR01FT057.mail.protection.outlook.com (10.152.0.208) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2220.16 via Frontend Transport; Sun, 1 Sep 2019 12:45:49 +0000 Received: from HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088]) by HE1PR06MB4011.eurprd06.prod.outlook.com ([fe80::a0ba:e766:2a23:2088%3]) with mapi id 15.20.2199.021; Sun, 1 Sep 2019 12:45:49 +0000 From: Jonas Karlman To: Ezequiel Garcia Subject: [RFC 12/12] media: hantro: Enable H264 decoding on RK3328 Thread-Topic: [RFC 12/12] media: hantro: Enable H264 decoding on RK3328 Thread-Index: AQHVYMMuvZQ1uHpGmUOTBIxTdNJunA== Date: Sun, 1 Sep 2019 12:45:49 +0000 Message-ID: References: <20190901124531.23645-1-jonas@kwiboo.se> In-Reply-To: <20190901124531.23645-1-jonas@kwiboo.se> Accept-Language: sv-SE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR05CA0343.eurprd05.prod.outlook.com (2603:10a6:7:92::38) To HE1PR06MB4011.eurprd06.prod.outlook.com (2603:10a6:7:9c::32) x-incomingtopheadermarker: OriginalChecksum:DC266DF213D4E8D0C3D1E2D5093F387F19B067E3DACF8FC4F0FD73990B771076; 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X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [40.92.66.34 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Kocialkowski , Jonas Karlman , "linux-kernel@vger.kernel.org" , Hans Verkuil , "linux-rockchip@lists.infradead.org" , Boris Brezillon , Philipp Zabel , Mauro Carvalho Chehab , "linux-media@vger.kernel.org" Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org RK3328 SoC has the same decoder IP block as RK3399, lets enable H264 decoding on RK3328. Signed-off-by: Jonas Karlman --- drivers/staging/media/hantro/rk3399_vpu_hw.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/staging/media/hantro/rk3399_vpu_hw.c b/drivers/staging/media/hantro/rk3399_vpu_hw.c index 47ca51b75a0d..08b965129377 100644 --- a/drivers/staging/media/hantro/rk3399_vpu_hw.c +++ b/drivers/staging/media/hantro/rk3399_vpu_hw.c @@ -232,7 +232,8 @@ const struct hantro_variant rk3328_vpu_variant = { .dec_offset = 0x400, .dec_fmts = rk3399_vpu_dec_fmts, .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), - .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER, + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | + HANTRO_H264_DECODER, .codec_ops = rk3399_vpu_codec_ops, .irqs = rk3328_irqs, .num_irqs = ARRAY_SIZE(rk3328_irqs),