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BL0PR12MB2355; 20:la6UMO1jfKJ4JCvIbws4xcH1kc5yJlFzPzQJ7IjdpqfrkEWxeZTVyem7LZRvT81FkqROOK282CgwNg0OMY4tOoJXehNeLlzQ51b425qLN33ajlVLJtP1i/jcxfcw5fZlhHe8ywyLWObVU5BeddX98RMrSDoeI6OyShGvSyXErbn/hGjeaFMM+yhf6BDjaSwLpjVyTaLhx8rBp+aLKK/zRrklFAspnShPK+2c/vJTjNWpRbHhtEyTrCsDT69vPBcT X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2018 08:07:24.9105 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 85ddcce6-b2c8-4c77-eb32-08d616f473b5 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB2355 Cc: "moderated list:SOUND - SOC LAYER / DYNAMIC AUDIO POWER MANAGEM..." , Kuninori Morimoto , open list , Takashi Iwai , Liam Girdwood , djkurtz@chromium.org, Mark Brown , Wei Yongjun , "Mukunda, Vijendar" , Alexander.Deucher@amd.com, akshu.agrawal@amd.com Subject: [alsa-devel] [PATCH 1/2] ASoC: AMD: Fix simultaneous playback and capture on different channel X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP If capture and playback are started on different channel (I2S/BT) there is a possibilty that channel information passed from machine driver is overwritten before the configuration is done in dma driver. Example: 113.597588: cz_max_startup: ---playback sets BT channel 113.597694: cz_dmic1_startup: ---capture sets I2S channel 113.597979: acp_dma_hw_params: ---configures capture for I2S channel 113.598114: acp_dma_hw_params: ---configures playback for I2S channel This is fixed by having lock between startup and prepare. This ensures no other codec startup gets called between a codec's startup(where channel info is set) and hw_params(where channel info is read). Signed-off-by: Akshu Agrawal --- sound/soc/amd/acp-da7219-max98357a.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/sound/soc/amd/acp-da7219-max98357a.c b/sound/soc/amd/acp-da7219-max98357a.c index 3879ccc..b98ffbc 100644 --- a/sound/soc/amd/acp-da7219-max98357a.c +++ b/sound/soc/amd/acp-da7219-max98357a.c @@ -47,6 +47,7 @@ static struct snd_soc_jack cz_jack; static struct clk *da7219_dai_clk; +static struct mutex instance_lock; extern int bt_uart_enable; static int cz_da7219_init(struct snd_soc_pcm_runtime *rtd) @@ -150,6 +151,7 @@ static int cz_da7219_startup(struct snd_pcm_substream *substream) snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &constraints_rates); + mutex_lock(&instance_lock); machine->i2s_instance = I2S_SP_INSTANCE; machine->capture_channel = CAP_CHANNEL1; return da7219_clk_enable(substream); @@ -160,6 +162,12 @@ static void cz_da7219_shutdown(struct snd_pcm_substream *substream) da7219_clk_disable(); } +static int cz_da7219_prepare(struct snd_pcm_substream *substream) +{ + mutex_unlock(&instance_lock); + return 0; +} + static int cz_max_startup(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; @@ -177,6 +185,7 @@ static int cz_max_startup(struct snd_pcm_substream *substream) snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &constraints_rates); + mutex_lock(&instance_lock); machine->i2s_instance = I2S_BT_INSTANCE; return da7219_clk_enable(substream); } @@ -186,6 +195,12 @@ static void cz_max_shutdown(struct snd_pcm_substream *substream) da7219_clk_disable(); } +static int cz_max_prepare(struct snd_pcm_substream *substream) +{ + mutex_unlock(&instance_lock); + return 0; +} + static int cz_dmic0_startup(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; @@ -203,6 +218,7 @@ static int cz_dmic0_startup(struct snd_pcm_substream *substream) snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &constraints_rates); + mutex_lock(&instance_lock); machine->i2s_instance = I2S_BT_INSTANCE; return da7219_clk_enable(substream); } @@ -224,6 +240,7 @@ static int cz_dmic1_startup(struct snd_pcm_substream *substream) snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &constraints_rates); + mutex_lock(&instance_lock); machine->i2s_instance = I2S_SP_INSTANCE; machine->capture_channel = CAP_CHANNEL0; return da7219_clk_enable(substream); @@ -234,24 +251,34 @@ static void cz_dmic_shutdown(struct snd_pcm_substream *substream) da7219_clk_disable(); } +static int cz_dmic_prepare(struct snd_pcm_substream *substream) +{ + mutex_unlock(&instance_lock); + return 0; +} + static const struct snd_soc_ops cz_da7219_cap_ops = { .startup = cz_da7219_startup, .shutdown = cz_da7219_shutdown, + .prepare = cz_da7219_prepare, }; static const struct snd_soc_ops cz_max_play_ops = { .startup = cz_max_startup, .shutdown = cz_max_shutdown, + .prepare = cz_max_prepare, }; static const struct snd_soc_ops cz_dmic0_cap_ops = { .startup = cz_dmic0_startup, .shutdown = cz_dmic_shutdown, + .prepare = cz_dmic_prepare, }; static const struct snd_soc_ops cz_dmic1_cap_ops = { .startup = cz_dmic1_startup, .shutdown = cz_dmic_shutdown, + .prepare = cz_dmic_prepare, }; static struct snd_soc_dai_link cz_dai_7219_98357[] = { @@ -409,6 +436,7 @@ static int cz_probe(struct platform_device *pdev) card = &cz_card; cz_card.dev = &pdev->dev; platform_set_drvdata(pdev, card); + mutex_init(&instance_lock); snd_soc_card_set_drvdata(card, machine); ret = devm_snd_soc_register_card(&pdev->dev, &cz_card); if (ret) { From patchwork Mon Sep 10 08:06:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshu Agrawal X-Patchwork-Id: 10593673 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0A908921 for ; Mon, 10 Sep 2018 08:07:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EF4AE28CE2 for ; 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There could be cases where dma stop errored out leaving dma channel in reset state. We need to ensure that before the start of another dma, channel is out of the reset state. Signed-off-by: Akshu Agrawal --- sound/soc/amd/acp-pcm-dma.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c index e359938..77b265b 100644 --- a/sound/soc/amd/acp-pcm-dma.c +++ b/sound/soc/amd/acp-pcm-dma.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -184,6 +185,24 @@ static void config_dma_descriptor_in_sram(void __iomem *acp_mmio, acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data); } +static void pre_config_reset(void __iomem *acp_mmio, u16 ch_num) +{ + u32 dma_ctrl; + int ret; + + /* clear the reset bit */ + dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); + dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; + acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); + /* check the reset bit before programming configuration registers */ + ret = readl_poll_timeout(acp_mmio + ((mmACP_DMA_CNTL_0 + ch_num) * 4), + dma_ctrl, + !(dma_ctrl & ACP_DMA_CNTL_0__DMAChRst_MASK), + 100, ACP_DMA_RESET_TIME); + if (ret < 0) + pr_err("Failed to clear reset of channel : %d\n", ch_num); +} + /* * Initialize the DMA descriptor information for transfer between * system memory <-> ACP SRAM @@ -236,6 +255,7 @@ static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, &dmadscr[i]); } + pre_config_reset(acp_mmio, ch); config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1, NUM_DSCRS_PER_CHANNEL, @@ -275,6 +295,7 @@ static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size, config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, &dmadscr[i]); } + pre_config_reset(acp_mmio, ch); /* Configure the DMA channel with the above descriptore */ config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1, NUM_DSCRS_PER_CHANNEL,