From patchwork Fri Sep 6 02:30:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 11134259 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1E7D413B1 for ; Fri, 6 Sep 2019 02:30:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 14735206CD for ; Fri, 6 Sep 2019 02:30:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UxkPlG2W" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733236AbfIFCaq (ORCPT ); Thu, 5 Sep 2019 22:30:46 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:41685 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726600AbfIFCap (ORCPT ); Thu, 5 Sep 2019 22:30:45 -0400 Received: by mail-pg1-f194.google.com with SMTP id x15so2566129pgg.8; Thu, 05 Sep 2019 19:30:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0a/Ttcv1b84BQ/BKZwWZSK7rdmYU6EM1Hc5Czp/KOEk=; b=UxkPlG2WM83W1pxPHvlBQybqMy/Ip+uOUKj9BojUJh1kRjXsIuycCD4K8m+SMOCESi Lqmz2Zl4X+e97nFYKqNfnryHkvtqRuFRqk0B7LcanYGX7WDdDEboErSzvySOZPIIHEYH nE5tCa99wN6qoo/Oh34Qp++ltMBIphkQNW685B1orE/uChL1YQdnvc+b78vlFbFXDMCs 3ajHZxoGC9Q6XpDVDO7xC3+frmotedXB/gQUrwAVxJA9CHu7QR7NO//nGWUIBaqMIbih q2Ffph6mF7Q1fjljvVquHgc93cH0tL5T5OaUnqsiFFpN+VmNXO1fYuzP+YcYE6H5YUs8 IXDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0a/Ttcv1b84BQ/BKZwWZSK7rdmYU6EM1Hc5Czp/KOEk=; b=uNgRTLQB6cY3ldN4cdnKa5x8crOGDGQQ4sYGw5qtGJyS5L4GhZqs+IxaR+22fP8ieB 3tYtZ4wDXhlSYwO+Lh5b2aY61kBSy+VIMzOLqfO7YD0fUQc8vaxcl9BK7e+yQmCChOV1 GDhI3GaaLPvT+U00FQ15ga8LYr4Bn0BFQrmRWX1bXi8opFvz4ALy/RG1JDDk0YXAWkrm MGyVWQTNlWvz6kPMbtwasXyEeg0B7mPUWCaaqgJ+UDAahWJGhqnuK9NzIQRsR9tC2LJx FACq/aVj3SGj+FgCyiiQvu+y960XB+UoU4QCx808dGfkvYAQ08Gj9PvcC46LzgcR2qpB YqAA== X-Gm-Message-State: APjAAAXfFD3ecppZBYv1jYnfVZUNhXCL+m4exfPPyXrdtWWNYl8YmYUV 4TjfyUsVvaSw88v11L9LFJ4= X-Google-Smtp-Source: APXvYqwm4tjf7WnLpHEUc9EpYP827c7f4BjQ4DfBF1iTCTT7lk1ufs65JFqjDHatpY10182Jj7vmSg== X-Received: by 2002:a17:90a:1150:: with SMTP id d16mr7548068pje.2.1567737045194; Thu, 05 Sep 2019 19:30:45 -0700 (PDT) Received: from gli-arch.genesyslogic.com.tw (60-251-58-169.HINET-IP.hinet.net. [60.251.58.169]) by smtp.gmail.com with ESMTPSA id o129sm4228000pfg.1.2019.09.05.19.30.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2019 19:30:44 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, johnsonm@danlj.org, ben.chuang@genesyslogic.com.tw, Ben Chuang Subject: [PATCH V8 1/5] mmc: sdhci: Change timeout of loop for checking internal clock stable Date: Fri, 6 Sep 2019 10:30:53 +0800 Message-Id: <0c090d866e2b4cd7966672b1b6cf5667a5ce39dd.1567734321.git.benchuanggli@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ben Chuang According to section 3.2.1 internal clock setup in SD Host Controller Simplified Specifications 4.20, the timeout of loop for checking internal clock stable is defined as 150ms. Signed-off-by: Ben Chuang Co-developed-by: Michael K Johnson Signed-off-by: Michael K Johnson Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 59acf8e3331e..bed0760a6c2a 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1636,8 +1636,8 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) clk |= SDHCI_CLOCK_INT_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); - /* Wait max 20 ms */ - timeout = ktime_add_ms(ktime_get(), 20); + /* Wait max 150 ms */ + timeout = ktime_add_ms(ktime_get(), 150); while (1) { bool timedout = ktime_after(ktime_get(), timeout); From patchwork Fri Sep 6 02:31:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 11134261 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D8F1513BD for ; Fri, 6 Sep 2019 02:30:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D2F162053B for ; Fri, 6 Sep 2019 02:30:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Lq9PdVaJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391173AbfIFCa5 (ORCPT ); Thu, 5 Sep 2019 22:30:57 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:38029 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726600AbfIFCa5 (ORCPT ); Thu, 5 Sep 2019 22:30:57 -0400 Received: by mail-pl1-f193.google.com with SMTP id w11so2356248plp.5; Thu, 05 Sep 2019 19:30:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bsBBaQCwC1K7f7nPpRPamyzrfm3OUMCwJTP3+3GPnBU=; b=Lq9PdVaJYwXMc5V8oaUrkt16H+GBnYxx4VScdKbcw2LuIV4+CVuAXLpvrxZBJrbnoC 3uhzl3/63DyGxIVcM/TAkZ91+/2u4tOkJCGH3BpFLkNGxZdCCcjIFQ4Bjv+W5QeCff4c DkAhNpermZi/NRSagLmqSP5UDha0P0P7IEGJJerMbPZot7IWbnvNkcNk2AsDsbWo8ZSz eiVNL/bIHf1lh1VG1GJ1g4nOhDNn/x15/gi/TtHs06e544MLkDJhYxC/ebs7pgR2XrPe ArzBfp45c+z7b55c+GnWdpMa175TfxULVekKnApNKC74RV6ImmCbVA7iUx5fttZD3Hyo GSpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bsBBaQCwC1K7f7nPpRPamyzrfm3OUMCwJTP3+3GPnBU=; b=IDEgnfaOJim/Lzw9MXVXRyrgugJB1IpJCG004WOZzF2Zo3fnp3GEJkXL2/PRCKiD++ q+NXOd67yIxR+3U5HKlJKGvIMruoPx1bxAwt24sA4cjgcq94vfcP0uv/n5bzHjLDdssb Tdsu4wuEyZkdk1gFcXPbW/9NLcfI9UOo2tL+kuoGM/l/5m72aVl7YjuKtQH4FJus9B/x ZtWstXRGpNoPVfs0KID7sc9p4qNhBa/eQRiYeAlxslT1McPjUwrq7hKAUvq89zzU0EaG 2KkNkj4MPpdhyxQHbhYMDgYlb7UWmvKEzcgIcFUn9ShJwjIseToa0HtWGVyNnT1cXOsG SPWw== X-Gm-Message-State: APjAAAVI+0H1WaSHjb6brUbIEVR7mCUM2Fi6lQWLs154l0rGNIFQ/uE/ ObWM5rY7PumPCoE9PxrC5TI= X-Google-Smtp-Source: APXvYqxoxw+3o9j7fMXe2GWIV41M865vHkQ0QGF2Y1hqYHo3O0KZNCeIR4W5jK0DNG6BYvm4bsAE+g== X-Received: by 2002:a17:902:30d:: with SMTP id 13mr6953820pld.284.1567737056988; Thu, 05 Sep 2019 19:30:56 -0700 (PDT) Received: from gli-arch.genesyslogic.com.tw (60-251-58-169.HINET-IP.hinet.net. [60.251.58.169]) by smtp.gmail.com with ESMTPSA id i190sm18146pfb.71.2019.09.05.19.30.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2019 19:30:56 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, johnsonm@danlj.org, ben.chuang@genesyslogic.com.tw, Ben Chuang Subject: [PATCH V8 2/5] mmc: sdhci: Add PLL Enable support to internal clock setup Date: Fri, 6 Sep 2019 10:31:05 +0800 Message-Id: X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ben Chuang The GL9750 and GL9755 chipsets, and possibly others, require PLL Enable setup as part of the internal clock setup as described in 3.2.1 Internal Clock Setup Sequence of SD Host Controller Simplified Specification Version 4.20. Signed-off-by: Ben Chuang Co-developed-by: Michael K Johnson Signed-off-by: Michael K Johnson Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 23 +++++++++++++++++++++++ drivers/mmc/host/sdhci.h | 1 + 2 files changed, 24 insertions(+) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index bed0760a6c2a..9106ebc7a422 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1653,6 +1653,29 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) udelay(10); } + if (host->version >= SDHCI_SPEC_410 && host->v4_mode) { + clk |= SDHCI_CLOCK_PLL_EN; + clk &= ~SDHCI_CLOCK_INT_STABLE; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + /* Wait max 150 ms */ + timeout = ktime_add_ms(ktime_get(), 150); + while (1) { + bool timedout = ktime_after(ktime_get(), timeout); + + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + if (clk & SDHCI_CLOCK_INT_STABLE) + break; + if (timedout) { + pr_err("%s: PLL clock never stabilised.\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return; + } + udelay(10); + } + } + clk |= SDHCI_CLOCK_CARD_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); } diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 199712e7adbb..72601a4d2e95 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -114,6 +114,7 @@ #define SDHCI_DIV_HI_MASK 0x300 #define SDHCI_PROG_CLOCK_MODE 0x0020 #define SDHCI_CLOCK_CARD_EN 0x0004 +#define SDHCI_CLOCK_PLL_EN 0x0008 #define SDHCI_CLOCK_INT_STABLE 0x0002 #define SDHCI_CLOCK_INT_EN 0x0001 From patchwork Fri Sep 6 02:32:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 11134263 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D7F1D13B1 for ; Fri, 6 Sep 2019 02:31:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D0DC12070C for ; Fri, 6 Sep 2019 02:31:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="sRr1SYAa" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387968AbfIFCb7 (ORCPT ); Thu, 5 Sep 2019 22:31:59 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:33845 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726600AbfIFCb6 (ORCPT ); Thu, 5 Sep 2019 22:31:58 -0400 Received: by mail-pg1-f196.google.com with SMTP id n9so2590653pgc.1; Thu, 05 Sep 2019 19:31:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X/gqa9V2L+P7ZTpCq0TlKj9v1dS5cmC4kjSw+65uCNc=; b=sRr1SYAaudA+kSuECzIoCIqqyWi5BJ8VPufG6rrkCb0hcSgGoItmXtoEhstYNM1aau G/Qr1cEupkKZJIg/tiAd8xEm0ViGPoSH3EJs6Oh2MTQGVD+yqf/ZYejaKK+tsT4VrNrW EEFJUxFS+cPTzHrfYTiPwrxPMM1iM4BmcFp8ritwJtKuOVupgJIHPFvgv98NS2FSvyBp kNwtOSSaCkRClJWnxRUoVbtjno7PLd+vLYgl0DyrNxfJc6RJ4JGqKYLQxdLPnweNY8Gz f51JrKAX4cf2VNV2GCTKqwgpYOC90z+EG/jtcXd+K7Wc9qx5Nq1TcTc+oBPDt5AlqqMa TByQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X/gqa9V2L+P7ZTpCq0TlKj9v1dS5cmC4kjSw+65uCNc=; b=SCTUBTPookhohDfALGsrqNy8Nml2MySUmKdip77lyp0hCWSCs2hutpQJmLRf/rVgGQ hDNdMkjxr3Uv7Kc/LmVy54qmjVa0cyxFUW9UbevH7etqWwBTsepS91nKo//dWQKQG8QS JgAkU5he7t6b7NWpYC6OYL1SDS4Uhg0TEmEhsZJo/dR3Bz11B0Y3h2Rs9VFdQiCOgQea id0CtvNWXQXntG/R51mB8PWeQhxGbxitxkVu3//+iOkUOBjCABrDUKjmpEs1CoMYCKim F2ZKiv7w6FiV6vqVFiTBPcf9RJDp1OSZHOzBRawGoOEvCSc1X7xeVmpdEVfusnzcNzDF cc7w== X-Gm-Message-State: APjAAAU0Q5bGm93Lm2Yz6ZzWXJBVdrCrelnNeXHV/1dzCNSO9c9pQpld iqtApOz66/n7dteg1enbx3A= X-Google-Smtp-Source: APXvYqxUvQF2FpuosJop/9aRW+1znZiDlir3wLoqBBUzScNDRpySke+xlxehhodmtxC6o1pU/7P6fg== X-Received: by 2002:aa7:8510:: with SMTP id v16mr7814724pfn.113.1567737118419; Thu, 05 Sep 2019 19:31:58 -0700 (PDT) Received: from gli-arch.genesyslogic.com.tw (60-251-58-169.HINET-IP.hinet.net. [60.251.58.169]) by smtp.gmail.com with ESMTPSA id k5sm5852121pfp.109.2019.09.05.19.31.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2019 19:31:57 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, johnsonm@danlj.org, ben.chuang@genesyslogic.com.tw, Ben Chuang Subject: [PATCH V8 3/5] PCI: Add Genesys Logic, Inc. Vendor ID Date: Fri, 6 Sep 2019 10:32:06 +0800 Message-Id: <860ef173fe110630d91e384ae44d7ad42cb72d3a.1567734321.git.benchuanggli@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ben Chuang Add the Genesys Logic, Inc. vendor ID to pci_ids.h. Signed-off-by: Ben Chuang Co-developed-by: Michael K Johnson Signed-off-by: Michael K Johnson Acked-by: Adrian Hunter --- include/linux/pci_ids.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 70e86148cb1e..4f7e12772a14 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2403,6 +2403,8 @@ #define PCI_DEVICE_ID_RDC_R6061 0x6061 #define PCI_DEVICE_ID_RDC_D1010 0x1010 +#define PCI_VENDOR_ID_GLI 0x17a0 + #define PCI_VENDOR_ID_LENOVO 0x17aa #define PCI_VENDOR_ID_QCOM 0x17cb From patchwork Fri Sep 6 02:32:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 11134265 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CE46713B1 for ; Fri, 6 Sep 2019 02:32:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C69562070C for ; Fri, 6 Sep 2019 02:32:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dS5ZfROF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732672AbfIFCcP (ORCPT ); Thu, 5 Sep 2019 22:32:15 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:34079 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726600AbfIFCcO (ORCPT ); Thu, 5 Sep 2019 22:32:14 -0400 Received: by mail-pl1-f195.google.com with SMTP id d3so2375249plr.1; Thu, 05 Sep 2019 19:32:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+363ozv7hHWtnDZ7Q+OUTPSDfOt22ArWkNBA2J7l/rE=; b=dS5ZfROFghyniETTIersxbAr8Bj66TmNb2OqDTLsPycKxwqcrBV08/bF5y48sucgSE +ooQ+tqt2RGwbOGMslvWVQXiHJ6So+teUEt8MxliZag5O9FiUvQY9PTj4KBNc34Z941J rCkDfsgsU/Iplurfctr7UcCEFQUE2gPqZOoaXnHPxu/PAcyscM4/j+XnYwDe9JjJ3p0y lfU22ilkRUAlJvp/FuJ/CnSYU0zDc0tN3yOG6+YiHIbLiVDTvc0H8i8Uy4ueTTPxu2Uo Jqd97gWflwKfRQ3wJOfCbusAxpP952fdY0z+ni4s6Cd4hAM4XmtMWLMGGo/wVs+2v0n6 VAqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+363ozv7hHWtnDZ7Q+OUTPSDfOt22ArWkNBA2J7l/rE=; b=ZuwKgDTAtAhQuZZLYGZv3xnQvgHzIjXemKu6d99QKlVOciip0AFq2ds4PVlIcy0Zt6 n/1T6qPFiPLmILkW6FPRQCXdJneoxyVJJSECxqA649sj+YlWJmGxriiQH/23Y4y3jyp6 NlDCu6zkRVccoTy3FGfvrvcHXoo70e3g00V1ALruRbn6bKitcqO4dEAucRdDvdcgv+bU bLtNEwH/glMc1l4E2pWK91WOrtXsdPCTlrZ4N1OU0hdrmwgAU93vDoeEEABWmc56cDFg PszMUkTETVsPfj4z0IJuXCbLZvCVPLrmSeLJ/5RahLhBnOrfzmfHJsmsc9Jbe5dj2xms jFaQ== X-Gm-Message-State: APjAAAWNqeD7ycsZVBY3FSv/q6r5Y8uuY+Ww5Bi6Q9dKApIe1Nqsl5R+ vUMGAM2ofXrYgUQvJeO5Lio= X-Google-Smtp-Source: APXvYqxed7C6ImU9htYUulA/MMFbq9ztOqgZHE25K0Mb7LpnO+bv0q6cjA24s6bUSZiinFwboMmXyA== X-Received: by 2002:a17:902:bc4c:: with SMTP id t12mr6818012plz.90.1567737133927; Thu, 05 Sep 2019 19:32:13 -0700 (PDT) Received: from gli-arch.genesyslogic.com.tw (60-251-58-169.HINET-IP.hinet.net. [60.251.58.169]) by smtp.gmail.com with ESMTPSA id l3sm5161332pjq.24.2019.09.05.19.32.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2019 19:32:13 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, johnsonm@danlj.org, ben.chuang@genesyslogic.com.tw, Ben Chuang Subject: [PATCH V8 4/5] mmc: sdhci: Export sdhci_abort_tuning function symbol Date: Fri, 6 Sep 2019 10:32:18 +0800 Message-Id: <8495caa6af2bcfb916e57e626dd2d9eaeb0310c5.1567734321.git.benchuanggli@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ben Chuang Export sdhci_abort_tuning() function symbols which are used by other SD Host controller driver modules. Signed-off-by: Ben Chuang Co-developed-by: Michael K Johnson Signed-off-by: Michael K Johnson Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 3 ++- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 9106ebc7a422..0f2f110534db 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2328,7 +2328,7 @@ void sdhci_reset_tuning(struct sdhci_host *host) } EXPORT_SYMBOL_GPL(sdhci_reset_tuning); -static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode) +void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode) { sdhci_reset_tuning(host); @@ -2339,6 +2339,7 @@ static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode) mmc_abort_tuning(host->mmc, opcode); } +EXPORT_SYMBOL_GPL(sdhci_abort_tuning); /* * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 72601a4d2e95..437bab3af195 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -797,5 +797,6 @@ void sdhci_start_tuning(struct sdhci_host *host); void sdhci_end_tuning(struct sdhci_host *host); void sdhci_reset_tuning(struct sdhci_host *host); void sdhci_send_tuning(struct sdhci_host *host, u32 opcode); +void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode); #endif /* __SDHCI_HW_H */ From patchwork Fri Sep 6 02:33:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 11134267 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 044C413B1 for ; Fri, 6 Sep 2019 02:33:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E0D8120820 for ; Fri, 6 Sep 2019 02:33:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="nF54xOvF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391974AbfIFCdT (ORCPT ); Thu, 5 Sep 2019 22:33:19 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:46406 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731491AbfIFCdT (ORCPT ); Thu, 5 Sep 2019 22:33:19 -0400 Received: by mail-pf1-f194.google.com with SMTP id q5so3247521pfg.13; Thu, 05 Sep 2019 19:33:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pPbuLaJBt7uR0wPIXo36o1repAm77znOz8JRwWFns+8=; b=nF54xOvFuxUJeItxdO04c6E77l92fUy2rFij1n2ikg6VT8VJSDCz02+Hl+n+u2AOZD NFHdalVJseIfCNV8jdRbnX5CKqnU+9z/Ad2xIHPBv2gtwiTD/zUEvurBaO83fncZl/kI VI6T3yT8OEtlds7Flzj4Ry/2+I5yQoG377vNwWq7NLVod8nt00w7IuQ4OrmDibcchqOa MK1aDKnNOU66UWR7R8C2CilALzbqz78NqjU4KSG9o408P9QeKAp/QlB4AS79d8nxLiO3 xJgbxfrp6cDl085KnfyCG/eQ/ZQVgOgPYf/1m0VLGKG881ZrP/CUQr236acX3rKBqSXO Czzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pPbuLaJBt7uR0wPIXo36o1repAm77znOz8JRwWFns+8=; b=nBw5wPw2w35GN3mmUFIQCt5++UlAXtRvNmQeIRdmPbZstO/tHMALSq844wkshFxnJ/ pTEwxDZwQiohMlVd8leJ5dSACQmHoRO2YpMcIret7NN+l1JpZC+aIrlGgo2bnV6Kq3LT jc+36/384fzPhsrNEV+2oiFFEJLewBe3TOLC06ZYSoyviDli5OWvZz2QF7Vn3l+1jdC3 2E4JPLlEJ/1RGFNC83hF2FyRkVg+jlCSlGVONtfI3p0w7Nx74F1tcNu9p/dkWrPTevWG 4+9T93xFrGUzXXnXo6XS+bZIPEzK3aWt+iIq1V2AMV+j/R1zLIn3s86W9t+FfMUhDG9G aYew== X-Gm-Message-State: APjAAAULpFABLOQnSPlgcEXDWxRR61SqHhWKCsxlXftXtJjl/GdrS5pu n5WAVcY00X8a5PqCcYdFxqs= X-Google-Smtp-Source: APXvYqxGQqLySiqDHscaX2XrYZYJXb4kbCdXEJMfrmkbhnk9KUl2XtSolAUbFoSafbbsXnVaWKW1Cw== X-Received: by 2002:a17:90a:248c:: with SMTP id i12mr7436448pje.130.1567737197987; Thu, 05 Sep 2019 19:33:17 -0700 (PDT) Received: from gli-arch.genesyslogic.com.tw (60-251-58-169.HINET-IP.hinet.net. [60.251.58.169]) by smtp.gmail.com with ESMTPSA id f74sm8025150pfa.34.2019.09.05.19.33.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2019 19:33:17 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, johnsonm@danlj.org, ben.chuang@genesyslogic.com.tw, Ben Chuang Subject: [PATCH V8 5/5] mmc: host: sdhci-pci: Add Genesys Logic GL975x support Date: Fri, 6 Sep 2019 10:33:26 +0800 Message-Id: <13ba23b2b159a88bb385b6a1e8ead5fe5ea53156.1567734321.git.benchuanggli@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ben Chuang Add support for the GL9750 and GL9755 chipsets. Enable v4 mode and wait 5ms after set 1.8V signal enable for GL9750/ GL9755. Fix the value of SDHCI_MAX_CURRENT register and use the vendor tuning flow for GL9750. Co-developed-by: Michael K Johnson Signed-off-by: Michael K Johnson Signed-off-by: Ben Chuang --- drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/Makefile | 2 +- drivers/mmc/host/sdhci-pci-core.c | 2 + drivers/mmc/host/sdhci-pci-gli.c | 355 ++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-pci.h | 5 + 5 files changed, 364 insertions(+), 1 deletion(-) create mode 100644 drivers/mmc/host/sdhci-pci-gli.c diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 931770f17087..9fbfff514d6c 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -94,6 +94,7 @@ config MMC_SDHCI_PCI depends on MMC_SDHCI && PCI select MMC_CQHCI select IOSF_MBI if X86 + select MMC_SDHCI_IO_ACCESSORS help This selects the PCI Secure Digital Host Controller Interface. Most controllers found today are PCI devices. diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 73578718f119..661445415090 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -13,7 +13,7 @@ obj-$(CONFIG_MMC_MXS) += mxs-mmc.o obj-$(CONFIG_MMC_SDHCI) += sdhci.o obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o sdhci-pci-y += sdhci-pci-core.o sdhci-pci-o2micro.o sdhci-pci-arasan.o \ - sdhci-pci-dwc-mshc.o + sdhci-pci-dwc-mshc.o sdhci-pci-gli.o obj-$(subst m,y,$(CONFIG_MMC_SDHCI_PCI)) += sdhci-pci-data.o obj-$(CONFIG_MMC_SDHCI_ACPI) += sdhci-acpi.o obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c index 4154ee11b47d..e5835fbf73bc 100644 --- a/drivers/mmc/host/sdhci-pci-core.c +++ b/drivers/mmc/host/sdhci-pci-core.c @@ -1682,6 +1682,8 @@ static const struct pci_device_id pci_ids[] = { SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), + SDHCI_PCI_DEVICE(GLI, 9750, gl9750), + SDHCI_PCI_DEVICE(GLI, 9755, gl9755), SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), /* Generic SD host controller */ {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c new file mode 100644 index 000000000000..94462b94abec --- /dev/null +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Genesys Logic, Inc. + * + * Authors: Ben Chuang + * + * Version: v0.9.0 (2019-08-08) + */ + +#include +#include +#include +#include +#include +#include "sdhci.h" +#include "sdhci-pci.h" + +/* Genesys Logic extra registers */ +#define SDHCI_GLI_9750_WT 0x800 +#define SDHCI_GLI_9750_WT_EN BIT(0) +#define GLI_9750_WT_EN_ON 0x1 +#define GLI_9750_WT_EN_OFF 0x0 + +#define SDHCI_GLI_9750_DRIVING 0x860 +#define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0) +#define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26) +#define GLI_9750_DRIVING_1_VALUE 0xFFF +#define GLI_9750_DRIVING_2_VALUE 0x3 + +#define SDHCI_GLI_9750_PLL 0x864 +#define SDHCI_GLI_9750_PLL_TX2_INV BIT(23) +#define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20) +#define GLI_9750_PLL_TX2_INV_VALUE 0x1 +#define GLI_9750_PLL_TX2_DLY_VALUE 0x0 + +#define SDHCI_GLI_9750_SW_CTRL 0x874 +#define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6) +#define GLI_9750_SW_CTRL_4_VALUE 0x3 + +#define SDHCI_GLI_9750_MISC 0x878 +#define SDHCI_GLI_9750_MISC_TX1_INV BIT(2) +#define SDHCI_GLI_9750_MISC_RX_INV BIT(3) +#define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4) +#define GLI_9750_MISC_TX1_INV_VALUE 0x0 +#define GLI_9750_MISC_RX_INV_ON 0x1 +#define GLI_9750_MISC_RX_INV_OFF 0x0 +#define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF +#define GLI_9750_MISC_TX1_DLY_VALUE 0x5 + +#define SDHCI_GLI_9750_TUNING_CONTROL 0x540 +#define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4) +#define GLI_9750_TUNING_CONTROL_EN_ON 0x1 +#define GLI_9750_TUNING_CONTROL_EN_OFF 0x0 +#define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16) +#define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19) +#define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1 +#define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2 + +#define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544 +#define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0) +#define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1 + +#define GLI_MAX_TUNING_LOOP 40 + +/* Genesys Logic chipset */ +static inline void gl9750_wt_on(struct sdhci_host *host) +{ + u32 wt_value; + u32 wt_enable; + + wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); + wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); + + if (wt_enable == GLI_9750_WT_EN_ON) + return; + + wt_value &= ~SDHCI_GLI_9750_WT_EN; + wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON); + + sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); +} + +static inline void gl9750_wt_off(struct sdhci_host *host) +{ + u32 wt_value; + u32 wt_enable; + + wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); + wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); + + if (wt_enable == GLI_9750_WT_EN_OFF) + return; + + wt_value &= ~SDHCI_GLI_9750_WT_EN; + wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF); + + sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); +} + +static void gli_set_9750(struct sdhci_host *host) +{ + u32 driving_value; + u32 pll_value; + u32 sw_ctrl_value; + u32 misc_value; + u32 parameter_value; + u32 control_value; + u16 ctrl2; + + gl9750_wt_on(host); + + driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); + pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); + sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); + misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); + parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS); + control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); + + driving_value &= ~(SDHCI_GLI_9750_DRIVING_1); + driving_value &= ~(SDHCI_GLI_9750_DRIVING_2); + driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1, + GLI_9750_DRIVING_1_VALUE); + driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2, + GLI_9750_DRIVING_2_VALUE); + sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING); + + sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4; + sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4, + GLI_9750_SW_CTRL_4_VALUE); + sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL); + + /* reset the tuning flow after reinit and before starting tuning */ + pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; + pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; + pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, + GLI_9750_PLL_TX2_INV_VALUE); + pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, + GLI_9750_PLL_TX2_DLY_VALUE); + + misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV; + misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; + misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY; + misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV, + GLI_9750_MISC_TX1_INV_VALUE); + misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, + GLI_9750_MISC_RX_INV_VALUE); + misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY, + GLI_9750_MISC_TX1_DLY_VALUE); + + parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY; + parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY, + GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE); + + control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1; + control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2; + control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1, + GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE); + control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2, + GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE); + + sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); + sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); + + /* disable tuned clk */ + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; + sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); + + /* enable tuning parameters control */ + control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; + control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, + GLI_9750_TUNING_CONTROL_EN_ON); + sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); + + /* write tuning parameters */ + sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS); + + /* disable tuning parameters control */ + control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; + control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, + GLI_9750_TUNING_CONTROL_EN_OFF); + sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); + + /* clear tuned clk */ + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; + sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); + + gl9750_wt_off(host); +} + +static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b) +{ + u32 misc_value; + + gl9750_wt_on(host); + + misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); + if (b) { + misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; + misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, + GLI_9750_MISC_RX_INV_ON); + sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); + } else { + misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; + misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, + GLI_9750_MISC_RX_INV_OFF); + sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); + } + + gl9750_wt_off(host); +} + +static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode) +{ + int i; + int rx_inv; + + for (rx_inv = 0; rx_inv < 2; rx_inv++) { + gli_set_9750_rx_inv(host, !!rx_inv); + sdhci_start_tuning(host); + + for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) { + u16 ctrl; + + sdhci_send_tuning(host, opcode); + + if (!host->tuning_done) { + sdhci_abort_tuning(host, opcode); + break; + } + + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { + if (ctrl & SDHCI_CTRL_TUNED_CLK) + return 0; /* Success! */ + break; + } + } + } + if (!host->tuning_done) { + pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", + mmc_hostname(host->mmc)); + return -ETIMEDOUT; + } + + pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", + mmc_hostname(host->mmc)); + sdhci_reset_tuning(host); + + return -EAGAIN; +} + +static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode) +{ + host->mmc->retune_period = 0; + if (host->tuning_mode == SDHCI_TUNING_MODE_1) + host->mmc->retune_period = host->tuning_count; + + gli_set_9750(host); + host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); + sdhci_end_tuning(host); + + return 0; +} + +static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) +{ + struct sdhci_host *host = slot->host; + + slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; + sdhci_enable_v4_mode(host); + + return 0; +} + +static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot) +{ + struct sdhci_host *host = slot->host; + + slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; + sdhci_enable_v4_mode(host); + + return 0; +} + +static void sdhci_gli_voltage_switch(struct sdhci_host *host) +{ + /* + * Accroding to Section 3.6.1 signal voltage switch procedure in + * SD Host Controller Simplified Spec. 4.20, the step 6~8 are the + * following: + * (6) Set 1.8V Signal Enable in the Host Control 2 register. + * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this + * period. + * (8) If 1.8V Signal Enable is cleared by Host Controller, go to + * step (12). + * + * Wait 5ms after set 1.8V signal enable in Host Control 2 register + * to ensure 1.8V signal enable bit is set by GL9750/GL9755. + */ + usleep_range(5000, 5500); +} + +static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask) +{ + sdhci_reset(host, mask); + gli_set_9750(host); +} + +static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg) +{ + u32 value; + + value = readl(host->ioaddr + reg); + if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff))) + value |= 0xc8; + + return value; +} + +static const struct sdhci_ops sdhci_gl9755_ops = { + .set_clock = sdhci_set_clock, + .enable_dma = sdhci_pci_enable_dma, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, + .voltage_switch = sdhci_gli_voltage_switch, +}; + +const struct sdhci_pci_fixes sdhci_gl9755 = { + .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, + .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, + .probe_slot = gli_probe_slot_gl9755, + .ops = &sdhci_gl9755_ops, +}; + +static const struct sdhci_ops sdhci_gl9750_ops = { + .read_l = sdhci_gl9750_readl, + .set_clock = sdhci_set_clock, + .enable_dma = sdhci_pci_enable_dma, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_gl9750_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, + .voltage_switch = sdhci_gli_voltage_switch, + .platform_execute_tuning = gl9750_execute_tuning, +}; + +const struct sdhci_pci_fixes sdhci_gl9750 = { + .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, + .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, + .probe_slot = gli_probe_slot_gl9750, + .ops = &sdhci_gl9750_ops, +}; + diff --git a/drivers/mmc/host/sdhci-pci.h b/drivers/mmc/host/sdhci-pci.h index e5dc6e44c7a4..738ba5afcc20 100644 --- a/drivers/mmc/host/sdhci-pci.h +++ b/drivers/mmc/host/sdhci-pci.h @@ -65,6 +65,9 @@ #define PCI_DEVICE_ID_SYNOPSYS_DWC_MSHC 0xc202 +#define PCI_DEVICE_ID_GLI_9755 0x9755 +#define PCI_DEVICE_ID_GLI_9750 0x9750 + /* * PCI device class and mask */ @@ -185,5 +188,7 @@ int sdhci_pci_enable_dma(struct sdhci_host *host); extern const struct sdhci_pci_fixes sdhci_arasan; extern const struct sdhci_pci_fixes sdhci_snps; extern const struct sdhci_pci_fixes sdhci_o2; +extern const struct sdhci_pci_fixes sdhci_gl9750; +extern const struct sdhci_pci_fixes sdhci_gl9755; #endif /* __SDHCI_PCI_H */