From patchwork Sat Sep 7 17:14:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11136551 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6B40C1395 for ; Sat, 7 Sep 2019 17:21:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 52805208C3 for ; Sat, 7 Sep 2019 17:21:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 52805208C3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4C34D89DB2; Sat, 7 Sep 2019 17:21:35 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id F219389DB4 for ; Sat, 7 Sep 2019 17:21:33 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Sep 2019 10:21:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,478,1559545200"; d="scan'208";a="191111429" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by FMSMGA003.fm.intel.com with ESMTP; 07 Sep 2019 10:21:31 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sat, 7 Sep 2019 22:44:37 +0530 Message-Id: <20190907171443.16181-2-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190907171443.16181-1-anshuman.gupta@intel.com> References: <20190907171443.16181-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7 1/7] drm/i915/tgl: Add DC3CO required register and bits X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Adding following definition to i915_reg.h 1. DC_STATE_EN register DC3CO bit fields and masks. 2. Transcoder EXITLINE register and its bit fields and mask. Cc: Jani Nikula Cc: Imre Deak Cc: Animesh Manna Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 006cffd56be2..273a4ed8b3e9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4135,6 +4135,7 @@ enum { #define _VTOTAL_A 0x6000c #define _VBLANK_A 0x60010 #define _VSYNC_A 0x60014 +#define _EXITLINE_A 0x60018 #define _PIPEASRC 0x6001c #define _BCLRPAT_A 0x60020 #define _VSYNCSHIFT_A 0x60028 @@ -4181,11 +4182,16 @@ enum { #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) +#define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A) #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) +#define EXITLINE_ENABLE (1 << 31) +#define EXITLINE_MASK (0x1fff) +#define EXITLINE_SHIFT 0 + /* * HSW+ eDP PSR registers * @@ -10114,6 +10120,8 @@ enum skl_power_gate { /* GEN9 DC */ #define DC_STATE_EN _MMIO(0x45504) #define DC_STATE_DISABLE 0 +#define DC_STATE_EN_DC3CO (1 << 30) +#define DC_STATE_DC3CO_STATUS (1 << 29) #define DC_STATE_EN_UPTO_DC5 (1 << 0) #define DC_STATE_EN_DC9 (1 << 3) #define DC_STATE_EN_UPTO_DC6 (2 << 0) From patchwork Sat Sep 7 17:14:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11136553 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 402B31395 for ; Sat, 7 Sep 2019 17:21:38 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 27B3A208C3 for ; Sat, 7 Sep 2019 17:21:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 27B3A208C3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9E72189DB4; Sat, 7 Sep 2019 17:21:37 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6C3FB89DB4 for ; Sat, 7 Sep 2019 17:21:36 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Sep 2019 10:21:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,478,1559545200"; d="scan'208";a="191111433" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by FMSMGA003.fm.intel.com with ESMTP; 07 Sep 2019 10:21:34 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sat, 7 Sep 2019 22:44:38 +0530 Message-Id: <20190907171443.16181-3-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190907171443.16181-1-anshuman.gupta@intel.com> References: <20190907171443.16181-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7 2/7] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enable dc3co state in enable_dc module param and add dc3co enable mask to allowed_dc_mask and gen9_dc_mask. v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6 independently. Cc: Jani Nikula Cc: Imre Deak Cc: Animesh Manna Signed-off-by: Anshuman Gupta --- .../drm/i915/display/intel_display_power.c | 29 ++++++++++++++----- drivers/gpu/drm/i915/i915_params.c | 3 +- 2 files changed, 23 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index ce88a27229ef..496fa1b53ffb 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -698,7 +698,11 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) u32 mask; mask = DC_STATE_EN_UPTO_DC5; - if (INTEL_GEN(dev_priv) >= 11) + + if (INTEL_GEN(dev_priv) >= 12) + mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6 + | DC_STATE_EN_DC9; + else if (IS_GEN(dev_priv, 11)) mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; else if (IS_GEN9_LP(dev_priv)) mask |= DC_STATE_EN_DC9; @@ -3927,14 +3931,17 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, int requested_dc; int max_dc; - if (INTEL_GEN(dev_priv) >= 11) { - max_dc = 2; + if (INTEL_GEN(dev_priv) >= 12) { + max_dc = 4; /* * DC9 has a separate HW flow from the rest of the DC states, * not depending on the DMC firmware. It's needed by system * suspend/resume, so allow it unconditionally. */ mask = DC_STATE_EN_DC9; + } else if (IS_GEN(dev_priv, 11)) { + max_dc = 2; + mask = DC_STATE_EN_DC9; } else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) { max_dc = 2; mask = 0; @@ -3953,7 +3960,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, requested_dc = enable_dc; } else if (enable_dc == -1) { requested_dc = max_dc; - } else if (enable_dc > max_dc && enable_dc <= 2) { + } else if (enable_dc > max_dc && enable_dc <= 4) { DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n", enable_dc, max_dc); requested_dc = max_dc; @@ -3962,10 +3969,16 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, requested_dc = max_dc; } - if (requested_dc > 1) - mask |= DC_STATE_EN_UPTO_DC6; - if (requested_dc > 0) - mask |= DC_STATE_EN_UPTO_DC5; + if (requested_dc == 4) { + mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6; + } else if (requested_dc == 3) { + mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5; + } else { + if (requested_dc > 1) + mask |= DC_STATE_EN_UPTO_DC6; + if (requested_dc > 0) + mask |= DC_STATE_EN_UPTO_DC5; + } DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask); diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 296452f9efe4..4f1806f65040 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -46,7 +46,8 @@ i915_param_named(modeset, int, 0400, i915_param_named_unsafe(enable_dc, int, 0400, "Enable power-saving display C-states. " - "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)"); + "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; " + "3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)"); i915_param_named_unsafe(enable_fbc, int, 0600, "Enable frame buffer compression for power savings " From patchwork Sat Sep 7 17:14:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11136557 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D101813BD for ; Sat, 7 Sep 2019 17:21:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B80C4208C3 for ; Sat, 7 Sep 2019 17:21:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B80C4208C3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4421389DB5; Sat, 7 Sep 2019 17:21:41 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 00CB789DB7 for ; Sat, 7 Sep 2019 17:21:39 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Sep 2019 10:21:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,478,1559545200"; d="scan'208";a="191111438" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by FMSMGA003.fm.intel.com with ESMTP; 07 Sep 2019 10:21:36 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sat, 7 Sep 2019 22:44:39 +0530 Message-Id: <20190907171443.16181-4-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190907171443.16181-1-anshuman.gupta@intel.com> References: <20190907171443.16181-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7 3/7] drm/i915/tgl: Enable DC3CO state in "DC Off" power well X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add max_dc_state and tgl_set_target_dc_state() API in order to enable DC3CO state with existing DC states. max_dc_state will enable/disable the desired DC state in DC_STATE_EN reg when "DC Off" power well gets disable/enable. v2: commit log improvement. v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre] Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre] Moved transcoder psr2 exit line enablement from tgl_allow_dc3co() to a appropriate place haswell_crtc_enable(). [Imre] Changed the DC3CO power well enabled call back logic as recommended in review comments. [Imre] v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)] v5: using udelay() instead of waiting for DC3CO exit status. v6: Fixed minor unwanted change. v7: Removed DC3CO powerwell and POWER_DOMAIN_VIDEO. Cc: Jani Nikula Cc: Imre Deak Cc: Animesh Manna Signed-off-by: Anshuman Gupta --- .../drm/i915/display/intel_display_power.c | 111 ++++++++++++++---- .../drm/i915/display/intel_display_power.h | 3 + drivers/gpu/drm/i915/i915_drv.h | 1 + 3 files changed, 95 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 496fa1b53ffb..83b10f61ee42 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -772,6 +772,29 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state) dev_priv->csr.dc_state = val & mask; } +static void tgl_allow_dc3co(struct drm_i915_private *dev_priv) +{ + if (!dev_priv->psr.sink_psr2_support) + return; + + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO) + gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO); +} + +static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv) +{ + u32 val; + + val = I915_READ(DC_STATE_EN); + val &= ~DC_STATE_DC3CO_STATUS; + I915_WRITE(DC_STATE_EN, val); + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); + /* + * Delay of 200us DC3CO Exit time B.Spec 49196 + */ + udelay(200); +} + static void bxt_enable_dc9(struct drm_i915_private *dev_priv) { assert_can_enable_dc9(dev_priv); @@ -939,7 +962,8 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0; + return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 && + (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); } static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) @@ -955,24 +979,32 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv) { struct intel_cdclk_state cdclk_state = {}; - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); + if (dev_priv->csr.max_dc_state & DC_STATE_EN_DC3CO) { + tgl_disallow_dc3co(dev_priv); + } else { + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); - dev_priv->display.get_cdclk(dev_priv, &cdclk_state); - /* Can't read out voltage_level so can't use intel_cdclk_changed() */ - WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state)); + dev_priv->display.get_cdclk(dev_priv, &cdclk_state); + /* + * Can't read out voltage_level so can't use + * intel_cdclk_changed() + */ + WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, + &cdclk_state)); - gen9_assert_dbuf_enabled(dev_priv); + gen9_assert_dbuf_enabled(dev_priv); - if (IS_GEN9_LP(dev_priv)) - bxt_verify_ddi_phy_power_wells(dev_priv); + if (IS_GEN9_LP(dev_priv)) + bxt_verify_ddi_phy_power_wells(dev_priv); - if (INTEL_GEN(dev_priv) >= 11) - /* - * DMC retains HW context only for port A, the other combo - * PHY's HW context for port B is lost after DC transitions, - * so we need to restore it manually. - */ - intel_combo_phy_init(dev_priv); + if (INTEL_GEN(dev_priv) >= 11) + /* + * DMC retains HW context only for port A, the other + * combo PHY's HW context for port B is lost after + * DC transitions, so we need to restore it manually. + */ + intel_combo_phy_init(dev_priv); + } } static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, @@ -987,10 +1019,48 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, if (!dev_priv->csr.dmc_payload) return; - if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6) - skl_enable_dc6(dev_priv); - else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5) - gen9_enable_dc5(dev_priv); + if (dev_priv->csr.max_dc_state & DC_STATE_EN_DC3CO) { + tgl_allow_dc3co(dev_priv); + } else if (dev_priv->csr.max_dc_state & DC_STATE_EN_UPTO_DC5_DC6_MASK) { + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6) + skl_enable_dc6(dev_priv); + else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5) + gen9_enable_dc5(dev_priv); + } +} + +void tgl_set_target_dc_state(struct drm_i915_private *dev_priv, u32 state, + bool psr2_deep_sleep) +{ + struct i915_power_well *power_well; + bool dc_off_enabled; + struct i915_power_domains *power_domains = &dev_priv->power_domains; + + mutex_lock(&power_domains->lock); + power_well = lookup_power_well(dev_priv, TGL_DISP_DC_OFF); + + if (!power_well) + goto unlock; + + dc_off_enabled = power_well->desc->ops->is_enabled(dev_priv, + power_well); + if (state == dev_priv->csr.max_dc_state) + goto unlock; + + if (!dc_off_enabled) { + /* + * Need to disable the DC off power well to + * effect target DC state. + */ + power_well->desc->ops->enable(dev_priv, power_well); + dev_priv->csr.max_dc_state = state; + power_well->desc->ops->disable(dev_priv, power_well); + goto unlock; + } + dev_priv->csr.max_dc_state = state; + +unlock: + mutex_unlock(&power_domains->lock); } static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv, @@ -3610,7 +3680,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { .name = "DC off", .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS, .ops = &gen9_dc_off_power_well_ops, - .id = DISP_PW_ID_NONE, + .id = TGL_DISP_DC_OFF, }, { .name = "power well 2", @@ -4039,6 +4109,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv, i915_modparams.enable_dc); + dev_priv->csr.max_dc_state = DC_STATE_EN_UPTO_DC5_DC6_MASK; BUILD_BUG_ON(POWER_DOMAIN_NUM > 64); mutex_init(&power_domains->lock); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index 737b5def7fc6..69ebde992342 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -100,6 +100,7 @@ enum i915_power_well_id { SKL_DISP_PW_MISC_IO, SKL_DISP_PW_1, SKL_DISP_PW_2, + TGL_DISP_DC_OFF, }; #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) @@ -256,6 +257,8 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915); void intel_display_power_resume_early(struct drm_i915_private *i915); void intel_display_power_suspend(struct drm_i915_private *i915); void intel_display_power_resume(struct drm_i915_private *i915); +void tgl_set_target_dc_state(struct drm_i915_private *dev_priv, u32 state, + bool psr2_deep_sleep); const char * intel_display_power_domain_str(enum intel_display_power_domain domain); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index db7480831e52..999da5d2da0b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -336,6 +336,7 @@ struct intel_csr { i915_reg_t mmioaddr[20]; u32 mmiodata[20]; u32 dc_state; + u32 max_dc_state; u32 allowed_dc_mask; intel_wakeref_t wakeref; }; From patchwork Sat Sep 7 17:14:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11136559 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3D27713BD for ; Sat, 7 Sep 2019 17:21:45 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 24438208C3 for ; Sat, 7 Sep 2019 17:21:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 24438208C3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9D49189DB7; Sat, 7 Sep 2019 17:21:44 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id B723189DB7 for ; Sat, 7 Sep 2019 17:21:42 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Sep 2019 10:21:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,478,1559545200"; d="scan'208";a="191111447" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by FMSMGA003.fm.intel.com with ESMTP; 07 Sep 2019 10:21:40 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sat, 7 Sep 2019 22:44:40 +0530 Message-Id: <20190907171443.16181-5-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190907171443.16181-1-anshuman.gupta@intel.com> References: <20190907171443.16181-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7 4/7] drm/i915/tgl: Do modeset to enable and configure DC3CO exitline. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" DC3CO enabling B.Specs sequence requires to enable end configure exit scanlines to TRANS_EXITLINE register, programming this register has to be part of modeset sequence as this can't be change when transcoder or port is enabled. When system boots with only eDP panel there may not be real modeset as BIOS has already programmed the necessary registers, therefore it needs to force a modeset at bootup to enable and configure DC3CO exitline. Cc: Jani Nikula Cc: Imre Deak Cc: Animesh Manna Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_display.c | 5 + .../drm/i915/display/intel_display_power.c | 108 ++++++++++++++++++ .../drm/i915/display/intel_display_power.h | 7 ++ .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/intel_pm.c | 2 +- drivers/gpu/drm/i915/intel_pm.h | 2 + 7 files changed, 126 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 3b5275ab66cf..84488f87d058 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7409,6 +7409,8 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; int clock_limit = dev_priv->max_dotclk_freq; + tgl_dc3co_crtc_compute_config(dev_priv, pipe_config); + if (INTEL_GEN(dev_priv) < 4) { clock_limit = dev_priv->max_cdclk_freq * 9 / 10; @@ -10474,6 +10476,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, pipe_config->pixel_multiplier = 1; } + tgl_dc3co_crtc_get_config(pipe_config); + out: for_each_power_domain(power_domain, power_domain_mask) intel_display_power_put(dev_priv, @@ -12739,6 +12743,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(pixel_multiplier); PIPE_CONF_CHECK_I(output_format); + PIPE_CONF_CHECK_BOOL(has_dc3co_exitline); PIPE_CONF_CHECK_BOOL(has_hdmi_sink); if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 83b10f61ee42..ecce118b5b0e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -19,6 +19,7 @@ #include "intel_hotplug.h" #include "intel_sideband.h" #include "intel_tc.h" +#include "intel_pm.h" bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, enum i915_power_well_id power_well_id); @@ -772,6 +773,113 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state) dev_priv->csr.dc_state = val & mask; } +void tgl_disable_psr2_transcoder_exitline(const struct intel_crtc_state *cstate) +{ + struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev); + u32 val; + + if (!IS_TIGERLAKE(dev_priv)) + return; + + val = I915_READ(EXITLINE(cstate->cpu_transcoder)); + val &= ~EXITLINE_ENABLE; + I915_WRITE(EXITLINE(cstate->cpu_transcoder), val); +} + +void tgl_enable_psr2_transcoder_exitline(const struct intel_crtc_state *cstate) +{ + u32 linetime_us, val, exit_scanlines; + u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay; + struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev); + + if (!IS_TIGERLAKE(dev_priv)) + return; + + linetime_us = fixed16_to_u32_round_up(intel_get_linetime_us(cstate)); + if (WARN_ON(!linetime_us)) + return; + /* + * DC3CO Exit time 200us B.Spec 49196 + * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 + * Exit line event need to program above calculated scan lines before + * next VBLANK. + */ + exit_scanlines = DIV_ROUND_UP(200, linetime_us) + 1; + if (WARN_ON(exit_scanlines > crtc_vdisplay)) + return; + + exit_scanlines = crtc_vdisplay - exit_scanlines; + exit_scanlines <<= EXITLINE_SHIFT; + val = I915_READ(EXITLINE(cstate->cpu_transcoder)); + val &= ~(EXITLINE_MASK | EXITLINE_ENABLE); + val |= exit_scanlines; + val |= EXITLINE_ENABLE; + I915_WRITE(EXITLINE(cstate->cpu_transcoder), val); +} + +static bool tgl_dc3co_is_edp_connected(struct intel_crtc_state *crtc_state) +{ + struct drm_atomic_state *state = crtc_state->base.state; + struct drm_connector *connector; + struct drm_connector_state *connector_state; + int i; + + for_each_new_connector_in_state(state, connector, connector_state, i) { + if (connector->status == connector_status_connected && + connector->connector_type == DRM_MODE_CONNECTOR_eDP) { + return true; + } + } + + return false; +} + +/* + * DC3CO requires to enable exitline and program DC3CO requires + * exit scanlines to TRANS_EXITLINE register, which should only + * change before transcoder or port are enabled. + * This requires to disable the fastset at boot for eDP output. + */ +void tgl_dc3co_crtc_compute_config(struct drm_i915_private *dev_priv, + struct intel_crtc_state *crtc_state) +{ + if (!IS_TIGERLAKE(dev_priv)) + return; + + if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)) + return; + + dev_priv->csr.dc3co_crtc = NULL; + + if (crtc_state->has_psr2 && crtc_state->base.active) { + if (tgl_dc3co_is_edp_connected(crtc_state)) { + crtc_state->has_dc3co_exitline = true; + dev_priv->csr.dc3co_crtc = + to_intel_crtc(crtc_state->base.crtc); + } + } +} + +void tgl_dc3co_crtc_get_config(struct intel_crtc_state *crtc_state) +{ + u32 val; + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); + + if (!IS_TIGERLAKE(dev_priv)) + return; + + if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)) + return; + + if (crtc_state->cpu_transcoder == TRANSCODER_A) { + val = I915_READ(EXITLINE(crtc_state->cpu_transcoder)); + if (val & EXITLINE_ENABLE) + crtc_state->has_dc3co_exitline = true; + else + crtc_state->has_dc3co_exitline = false; + } +} + static void tgl_allow_dc3co(struct drm_i915_private *dev_priv) { if (!dev_priv->psr.sink_psr2_support) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index 69ebde992342..d77a5a53f543 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -12,6 +12,8 @@ struct drm_i915_private; struct intel_encoder; +struct intel_crtc_state; +struct intel_atomic_state; enum intel_display_power_domain { POWER_DOMAIN_DISPLAY_CORE, @@ -259,6 +261,11 @@ void intel_display_power_suspend(struct drm_i915_private *i915); void intel_display_power_resume(struct drm_i915_private *i915); void tgl_set_target_dc_state(struct drm_i915_private *dev_priv, u32 state, bool psr2_deep_sleep); +void tgl_dc3co_crtc_compute_config(struct drm_i915_private *dev_priv, + struct intel_crtc_state *crtc_state); +void tgl_dc3co_crtc_get_config(struct intel_crtc_state *crtc_state); +void tgl_disable_psr2_transcoder_exitline(const struct intel_crtc_state *state); +void tgl_enable_psr2_transcoder_exitline(const struct intel_crtc_state *state); const char * intel_display_power_domain_str(enum intel_display_power_domain domain); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index d5cc4b810d9e..22f8fe0a34d0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -871,6 +871,7 @@ struct intel_crtc_state { bool has_psr; bool has_psr2; + bool has_dc3co_exitline; /* * Frequence the dpll for the port should run at. Differs from the diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 999da5d2da0b..3218b0319852 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -339,6 +339,8 @@ struct intel_csr { u32 max_dc_state; u32 allowed_dc_mask; intel_wakeref_t wakeref; + /* cache the crtc on which DC3CO will be allowed */ + struct intel_crtc *dc3co_crtc; }; enum i915_cache_level { diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 528e90ed5de4..7352c0cb88d0 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4588,7 +4588,7 @@ skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency, return ret; } -static uint_fixed_16_16_t +uint_fixed_16_16_t intel_get_linetime_us(const struct intel_crtc_state *crtc_state) { u32 pixel_rate; diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h index e3573e1e16e3..454e92c06dff 100644 --- a/drivers/gpu/drm/i915/intel_pm.h +++ b/drivers/gpu/drm/i915/intel_pm.h @@ -8,6 +8,7 @@ #include +#include "i915_drv.h" #include "i915_reg.h" struct drm_device; @@ -76,6 +77,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, i915_reg_t reg); u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, i915_reg_t reg); u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1); +uint_fixed_16_16_t intel_get_linetime_us(const struct intel_crtc_state *cstate); unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); unsigned long i915_mch_val(struct drm_i915_private *dev_priv); From patchwork Sat Sep 7 17:14:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11136561 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7FA981395 for ; Sat, 7 Sep 2019 17:21:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 65F0A208C3 for ; Sat, 7 Sep 2019 17:21:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 65F0A208C3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A1C889DBC; Sat, 7 Sep 2019 17:21:47 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2CFA589DBF for ; Sat, 7 Sep 2019 17:21:45 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Sep 2019 10:21:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,478,1559545200"; d="scan'208";a="191111451" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by FMSMGA003.fm.intel.com with ESMTP; 07 Sep 2019 10:21:42 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sat, 7 Sep 2019 22:44:41 +0530 Message-Id: <20190907171443.16181-6-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190907171443.16181-1-anshuman.gupta@intel.com> References: <20190907171443.16181-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7 5/7] drm/i915/tgl: DC3CO PSR2 helper X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add dc3co helper functions to enable/disable psr2 deep sleep. Adhere B.Specs by disallow DC3CO state before PSR2 exit. Enable PSR2 exitline event and program the desired scanlines to exit DC3CO in intel_psr_enable function at modeset path. Disable the DC3CO exitline in order to maintian consistent pipe config state in encoder disable path. v1: moved calling of tgl_enable_psr2_transcoder_exitline() to intel_psr_enable(). [Imre] Cc: Jani Nikula Cc: Imre Deak Cc: Animesh Manna Cc: José Roberto de Souza Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_psr.c | 51 ++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_psr.h | 2 + 2 files changed, 53 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b3c7eef53bf3..95b12946c72a 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -534,6 +534,48 @@ transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) return trans == TRANSCODER_EDP; } +static void psr2_program_idle_frames(struct drm_i915_private *dev_priv, + u32 idle_frames) +{ + u32 val; + + idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; + val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)); + val &= ~EDP_PSR2_IDLE_FRAME_MASK; + val |= idle_frames; + I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val); +} + +void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv) +{ + int idle_frames = 0; + + psr2_program_idle_frames(dev_priv, idle_frames); +} + +void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv) +{ + int idle_frames; + + /* + * Let's use 6 as the minimum to cover all known cases including the + * off-by-one issue that HW has in some cases. + */ + idle_frames = max(6, dev_priv->vbt.psr.idle_frames); + idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); + psr2_program_idle_frames(dev_priv, idle_frames); +} + +static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv) +{ + if (!IS_TIGERLAKE(dev_priv)) + return; + + cancel_delayed_work(&dev_priv->csr.idle_work); + /* Before PSR2 exit disallow dc3co*/ + tgl_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6, true); +} + static bool intel_psr2_config_valid(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { @@ -799,6 +841,10 @@ void intel_psr_enable(struct intel_dp *intel_dp, WARN_ON(dev_priv->drrs.dp); + /* Enable PSR2 transcoder exit line */ + if (crtc_state->has_psr2) + tgl_enable_psr2_transcoder_exitline(crtc_state); + mutex_lock(&dev_priv->psr.lock); if (!psr_global_enabled(dev_priv->psr.debug)) { @@ -829,6 +875,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv) } if (dev_priv->psr.psr2_enabled) { + tgl_disallow_dc3co_on_psr2_exit(dev_priv); val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)); WARN_ON(!(val & EDP_PSR2_ENABLE)); val &= ~EDP_PSR2_ENABLE; @@ -895,6 +942,10 @@ void intel_psr_disable(struct intel_dp *intel_dp, if (WARN_ON(!CAN_PSR(dev_priv))) return; + /* Disable PSR2 transcoder exit line */ + if (old_crtc_state->has_psr2) + tgl_disable_psr2_transcoder_exitline(old_crtc_state); + mutex_lock(&dev_priv->psr.lock); intel_psr_disable_locked(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index 46e4de8b8cd5..75a9862f36fd 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -35,5 +35,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp); int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state, u32 *out_value); bool intel_psr_enabled(struct intel_dp *intel_dp); +void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv); +void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv); #endif /* __INTEL_PSR_H__ */ From patchwork Sat Sep 7 17:14:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11136563 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9378C1395 for ; Sat, 7 Sep 2019 17:21:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7AFAF208C3 for ; Sat, 7 Sep 2019 17:21:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7AFAF208C3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 188EB89DBD; Sat, 7 Sep 2019 17:21:49 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id CE48589DBD for ; Sat, 7 Sep 2019 17:21:47 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Sep 2019 10:21:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,478,1559545200"; d="scan'208";a="191111459" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by FMSMGA003.fm.intel.com with ESMTP; 07 Sep 2019 10:21:45 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sat, 7 Sep 2019 22:44:42 +0530 Message-Id: <20190907171443.16181-7-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190907171443.16181-1-anshuman.gupta@intel.com> References: <20190907171443.16181-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7 6/7] drm/i915/tgl: switch between dc3co and dc5 based on display idleness X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" DC3CO is useful power state, when DMC detects PSR2 idle frame while an active video playback, playing 30fps video on 60hz panel is the classic example of this use case. DC5 and DC6 saves more power, but can't be entered during video playback because there are not enough idle frames in a row to meet most PSR2 panel deep sleep entry requirement typically 4 frames. It will be worthy to enable DC3CO after completion of each flip and switch back to DC5 when display is idle, as driver doesn't differentiate between video playback and a normal flip. It is safer to allow DC5 after 6 idle frame, as PSR2 requires minimum 6 idle frame. v2: calculated s/w state to switch over dc3co when there is an update. [Imre] used cancel_delayed_work_sync() in order to avoid any race with already scheduled delayed work. [Imre] v3: cancel_delayed_work_sync() may blocked the commit work. Hence dropping it, dc5_idle_thread() checks the valid wakeref before putting the reference count, which avoids any chances of dropping a zero wakeref. [Imre (IRC)] v4: use frontbuffer flush mechanism. [Imre] Cc: Jani Nikula Cc: Imre Deak Cc: Animesh Manna Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_display.c | 2 + .../drm/i915/display/intel_display_power.c | 79 +++++++++++++++++++ .../drm/i915/display/intel_display_power.h | 6 ++ .../gpu/drm/i915/display/intel_frontbuffer.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 1 + 5 files changed, 89 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 84488f87d058..2754e8ee693f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -16206,6 +16206,7 @@ int intel_modeset_init(struct drm_device *dev) init_llist_head(&dev_priv->atomic_helper.free_list); INIT_WORK(&dev_priv->atomic_helper.free_work, intel_atomic_helper_free_state_worker); + INIT_DELAYED_WORK(&dev_priv->csr.idle_work, tgl_dc5_idle_thread); intel_init_quirks(dev_priv); @@ -17147,6 +17148,7 @@ void intel_modeset_driver_remove(struct drm_device *dev) flush_workqueue(dev_priv->modeset_wq); flush_work(&dev_priv->atomic_helper.free_work); + flush_delayed_work(&dev_priv->csr.idle_work); WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list)); /* diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index ecce118b5b0e..c110f04c9733 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -20,6 +20,7 @@ #include "intel_sideband.h" #include "intel_tc.h" #include "intel_pm.h" +#include "intel_psr.h" bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, enum i915_power_well_id power_well_id); @@ -773,6 +774,27 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state) dev_priv->csr.dc_state = val & mask; } +static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate) +{ + u32 pixel_rate, crtc_htotal, crtc_vtotal; + u32 frametime_us; + + if (!cstate || !cstate->base.active) + return 0; + + pixel_rate = cstate->pixel_rate; + + if (WARN_ON(pixel_rate == 0)) + return 0; + + crtc_htotal = cstate->base.adjusted_mode.crtc_htotal; + crtc_vtotal = cstate->base.adjusted_mode.crtc_vtotal; + frametime_us = DIV_ROUND_UP(crtc_htotal * crtc_vtotal * 1000ULL, + pixel_rate); + + return frametime_us; +} + void tgl_disable_psr2_transcoder_exitline(const struct intel_crtc_state *cstate) { struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev); @@ -817,6 +839,49 @@ void tgl_enable_psr2_transcoder_exitline(const struct intel_crtc_state *cstate) I915_WRITE(EXITLINE(cstate->cpu_transcoder), val); } +void tgl_dc3co_flush(struct drm_i915_private *dev_priv, + unsigned int frontbuffer_bits, enum fb_op_origin origin) +{ + struct intel_crtc_state *cstate; + u32 delay; + unsigned int busy_frontbuffer_bits; + + if (!IS_TIGERLAKE(dev_priv)) + return; + + if (origin != ORIGIN_FLIP) + return; + + if (!dev_priv->csr.dc3co_crtc) + return; + + cstate = to_intel_crtc_state(dev_priv->csr.dc3co_crtc->base.state); + frontbuffer_bits &= + INTEL_FRONTBUFFER_ALL_MASK(dev_priv->csr.dc3co_crtc->pipe); + busy_frontbuffer_bits &= ~frontbuffer_bits; + + mutex_lock(&dev_priv->psr.lock); + + if (!dev_priv->psr.psr2_enabled || !dev_priv->psr.active) + goto unlock; + + /* + * At every flip frontbuffer flush first cancel the delayed work, + * when delayed schedules that means display has been idle + * for the 6 idle frame. + */ + if (!busy_frontbuffer_bits) { + cancel_delayed_work(&dev_priv->csr.idle_work); + tgl_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO, false); + delay = DC5_REQ_IDLE_FRAMES * intel_get_frame_time_us(cstate); + schedule_delayed_work(&dev_priv->csr.idle_work, + usecs_to_jiffies(delay)); + } + +unlock: + mutex_unlock(&dev_priv->psr.lock); +} + static bool tgl_dc3co_is_edp_connected(struct intel_crtc_state *crtc_state) { struct drm_atomic_state *state = crtc_state->base.state; @@ -880,6 +945,14 @@ void tgl_dc3co_crtc_get_config(struct intel_crtc_state *crtc_state) } } +void tgl_dc5_idle_thread(struct work_struct *work) +{ + struct drm_i915_private *dev_priv = + container_of(work, typeof(*dev_priv), csr.idle_work.work); + + tgl_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6, true); +} + static void tgl_allow_dc3co(struct drm_i915_private *dev_priv) { if (!dev_priv->psr.sink_psr2_support) @@ -1155,6 +1228,9 @@ void tgl_set_target_dc_state(struct drm_i915_private *dev_priv, u32 state, if (state == dev_priv->csr.max_dc_state) goto unlock; + if (!psr2_deep_sleep) + tgl_psr2_deep_sleep_disable(dev_priv); + if (!dc_off_enabled) { /* * Need to disable the DC off power well to @@ -1167,6 +1243,9 @@ void tgl_set_target_dc_state(struct drm_i915_private *dev_priv, u32 state, } dev_priv->csr.max_dc_state = state; + if (psr2_deep_sleep) + tgl_psr2_deep_sleep_enable(dev_priv); + unlock: mutex_unlock(&power_domains->lock); } diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index d77a5a53f543..df096d64c744 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -9,6 +9,9 @@ #include "intel_display.h" #include "intel_runtime_pm.h" #include "i915_reg.h" +#include "intel_frontbuffer.h" + +#define DC5_REQ_IDLE_FRAMES 6 struct drm_i915_private; struct intel_encoder; @@ -266,6 +269,9 @@ void tgl_dc3co_crtc_compute_config(struct drm_i915_private *dev_priv, void tgl_dc3co_crtc_get_config(struct intel_crtc_state *crtc_state); void tgl_disable_psr2_transcoder_exitline(const struct intel_crtc_state *state); void tgl_enable_psr2_transcoder_exitline(const struct intel_crtc_state *state); +void tgl_dc3co_flush(struct drm_i915_private *dev_priv, + unsigned int frontbuffer_bits, enum fb_op_origin origin); +void tgl_dc5_idle_thread(struct work_struct *work); const char * intel_display_power_domain_str(enum intel_display_power_domain domain); diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c index fc40dc1fdbcc..c3b10f6e4382 100644 --- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c +++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c @@ -90,6 +90,7 @@ static void frontbuffer_flush(struct drm_i915_private *i915, might_sleep(); intel_edp_drrs_flush(i915, frontbuffer_bits); intel_psr_flush(i915, frontbuffer_bits, origin); + tgl_dc3co_flush(i915, frontbuffer_bits, origin); intel_fbc_flush(i915, frontbuffer_bits, origin); } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3218b0319852..fe71119a458e 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -338,6 +338,7 @@ struct intel_csr { u32 dc_state; u32 max_dc_state; u32 allowed_dc_mask; + struct delayed_work idle_work; intel_wakeref_t wakeref; /* cache the crtc on which DC3CO will be allowed */ struct intel_crtc *dc3co_crtc; From patchwork Sat Sep 7 17:14:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11136565 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B913013BD for ; Sat, 7 Sep 2019 17:21:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9FD3F208C3 for ; Sat, 7 Sep 2019 17:21:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9FD3F208C3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 234B989DBF; Sat, 7 Sep 2019 17:21:52 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 19DBF89DBF for ; Sat, 7 Sep 2019 17:21:50 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Sep 2019 10:21:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,478,1559545200"; d="scan'208";a="191111463" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by FMSMGA003.fm.intel.com with ESMTP; 07 Sep 2019 10:21:47 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sat, 7 Sep 2019 22:44:43 +0530 Message-Id: <20190907171443.16181-8-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190907171443.16181-1-anshuman.gupta@intel.com> References: <20190907171443.16181-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7 7/7] drm/i915/tgl: Add DC3CO counter in i915_dmc_info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Adding DC3CO counter in i915_dmc_info debugfs will be useful for DC3CO validation. DMC firmware uses DMC_DEBUG3 register as DC3CO counter register on TGL, as per B.Specs DMC_DEBUG3 is general purpose register. Cc: Jani Nikula Cc: Imre Deak Cc: Animesh Manna Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 708855e051b5..161c4bcd3756 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2397,6 +2397,12 @@ static int i915_dmc_info(struct seq_file *m, void *unused) seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), CSR_VERSION_MINOR(csr->version)); + /* + * TGL DMC f/w uses DMC_DEBUG3 register for DC3CO counter. + */ + if (IS_TIGERLAKE(dev_priv)) + seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3)); + if (INTEL_GEN(dev_priv) >= 12) { dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 273a4ed8b3e9..0fb86a78c4a4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7251,6 +7251,8 @@ enum { #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084) #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088) +#define DMC_DEBUG3 _MMIO(0x101090) + /* interrupts */ #define DE_MASTER_IRQ_CONTROL (1 << 31) #define DE_SPRITEB_FLIP_DONE (1 << 29)