From patchwork Tue Sep 10 12:25:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pankaj Dubey X-Patchwork-Id: 11139383 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4057C112B for ; Tue, 10 Sep 2019 12:25:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E365520872 for ; Tue, 10 Sep 2019 12:25:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="oYktEStV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391846AbfIJMZS (ORCPT ); Tue, 10 Sep 2019 08:25:18 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:17335 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727734AbfIJMZS (ORCPT ); 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Tue, 10 Sep 2019 21:25:14 +0900 (KST) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20190910122514epcas5p4f00c0f999333dd7707c0a353fd06b57f~DE0yGlI5T2388523885epcas5p4g; Tue, 10 Sep 2019 12:25:14 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20190910122514epsmtrp1252b912ff7ce89f6c0f53d30f5a9afd8~DE0yF0WIu1251612516epsmtrp1J; Tue, 10 Sep 2019 12:25:14 +0000 (GMT) X-AuditID: b6c32a4a-655ff7000000114d-eb-5d77962abc28 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 7F.B6.03706.A26977D5; Tue, 10 Sep 2019 21:25:14 +0900 (KST) Received: from ubuntu.sa.corp.samsungelectronics.net (unknown [107.108.83.125]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20190910122513epsmtip2cee3ff68d6694ff80315d5f5f7355488~DE0w1qlZA0913509135epsmtip2K; Tue, 10 Sep 2019 12:25:13 +0000 (GMT) From: Pankaj Dubey To: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, lorenzo.pieralisi@arm.com, bhelgaas@google.com, Anvesh Salveru , Pankaj Dubey Subject: [PATCH 1/2] PCI: dwc: Add support to disable GEN3 equalization Date: Tue, 10 Sep 2019 17:55:01 +0530 Message-Id: <1568118302-10505-1-git-send-email-pankaj.dubey@samsung.com> X-Mailer: git-send-email 2.7.4 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLIsWRmVeSWpSXmKPExsWy7bCmhq7WtPJYgwuzrC3O7lrIarGkKcNi 190OdosVX2ayW1zeNYfN4uy842wWb36/YLdYtPULuwOHx5p5axg9ds66y+6xYFOpR9+WVYwe W/Z/ZvT4vEkugC2KyyYlNSezLLVI3y6BK2PeT8GCQ8IVlxdNZmlgvCHQxcjJISFgIjG77xNb FyMXh5DAbkaJBSfmskI4nxglDm3cwwThfGOUeDnvOhtMy9beaWC2kMBeRonGR1YQRS1MEl9b /zGDJNgEdCWevJ8LZosIWEs0vFoFNpYZZMe/iZeBHA4OYQF3iVtfKkBqWARUJQ7f/MwEEuYV 8JDoWuYIsUtO4ua5TmYIewKbxKcThiAlEgIuEh82mECEhSVeHd/CDmFLSbzsb4Oy8yV+LJ7E DLJVQqCFUWLycZDPQBL2EgeuzGEBmcMsoCmxfpc+SJhZgE+i9/cTJojxvBIdbUIQ1WoS35+f gbpARuJh81ImCNtD4v6uqcyQUIiVmLz5PfsERplZCEMXMDKuYpRMLSjOTU8tNi0wykst1ytO zC0uzUvXS87P3cQIjnQtrx2My875HGIU4GBU4uF90FYeK8SaWFZcmXuIUYKDWUmE93pfaawQ b0piZVVqUX58UWlOavEhRmkOFiVx3kmsV2OEBNITS1KzU1MLUotgskwcnFINjCX71Vq7eHve rfy0sDU2OyD3iSNTnpn8/0cLpx5eHB50tPuPCF+F0lM9lXtfbi2Jurrq8RWdmuTlMou5+BxT pwWLzKhifZCqM2f/2curgqcYGqnKPTIT7tgX8KKr7I+05UZW5t2ZBVEFgqG+m14oLTU04mRe OcGgRvHoZo3+R5XHOHfXV1r+UWIpzkg01GIuKk4EAEqYAdDwAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprELMWRmVeSWpSXmKPExsWy7bCSvK7WtPJYg8aVihZndy1ktVjSlGGx 624Hu8WKLzPZLS7vmsNmcXbecTaLN79fsFss2vqF3YHDY828NYweO2fdZfdYsKnUo2/LKkaP Lfs/M3p83iQXwBbFZZOSmpNZllqkb5fAlTHvp2DBIeGKy4smszQw3hDoYuTkkBAwkdjaO42t i5GLQ0hgN6PEjvb5zBAJGYnJq1ewQtjCEiv/PWeHKGpikvjd3sUEkmAT0JV48n4uWIOIgK1E w98OZpAiZoGDjBJXlu4DKuLgEBZwl7j1pQKkhkVAVeLwzc9gYV4BD4muZY4Q8+Ukbp7rZJ7A yLOAkWEVo2RqQXFuem6xYYFhXmq5XnFibnFpXrpecn7uJkZwSGlp7mC8vCT+EKMAB6MSD++D tvJYIdbEsuLK3EOMEhzMSiK81/tKY4V4UxIrq1KL8uOLSnNSiw8xSnOwKInzPs07FikkkJ5Y kpqdmlqQWgSTZeLglGpgLJDr3e5wW7Z927E9xtNeydocnWArcs1cI2zN7R1LVijP9jNRydgm GCiZm3JDuXE3/7X2b3qdnzpWq1/3y738uFTl1Hnji+uVS0Lvdkxu5WM/orfqj8Zz49f3crPt i9lM30bP2ZBoMaFn9xY7D5bA20fWWqR/e9m+xmsb56EGlyxpoUqBy/eClViKMxINtZiLihMB 57g6VCUCAAA= X-CMS-MailID: 20190910122514epcas5p4f00c0f999333dd7707c0a353fd06b57f X-Msg-Generator: CA CMS-TYPE: 105P X-CMS-RootMailID: 20190910122514epcas5p4f00c0f999333dd7707c0a353fd06b57f References: Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Anvesh Salveru In some platforms, PCIe PHY may have issues which will prevent linkup to happen in GEN3 or high speed. In case equalization fails, link will fallback to GEN1. Designware controller has support for disabling GEN3 equalization if required. This patch enables the designware driver to disable the PCIe GEN3 equalization by writing into PCIE_PORT_GEN3_RELATED. Platform drivers can disable equalization by setting the dwc_pci_quirk flag DWC_EQUALIZATION_DISABLE. Signed-off-by: Anvesh Salveru Signed-off-by: Pankaj Dubey --- drivers/pci/controller/dwc/pcie-designware.c | 7 +++++++ drivers/pci/controller/dwc/pcie-designware.h | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 7d25102..bf82091 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -466,4 +466,11 @@ void dw_pcie_setup(struct dw_pcie *pci) break; } dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + + val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED); + + if (pci->dwc_pci_quirk & DWC_EQUALIZATION_DISABLE) + val |= PORT_LOGIC_GEN3_EQ_DISABLE; + + dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index ffed084..a1453c5 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -29,6 +29,9 @@ #define LINK_WAIT_MAX_IATU_RETRIES 5 #define LINK_WAIT_IATU 9 +/* Parameters for PCIe Quirks */ +#define DWC_EQUALIZATION_DISABLE 0x1 + /* Synopsys-specific PCIe configuration registers */ #define PCIE_PORT_LINK_CONTROL 0x710 #define PORT_LINK_MODE_MASK GENMASK(21, 16) @@ -60,6 +63,9 @@ #define PCIE_MSI_INTR0_MASK 0x82C #define PCIE_MSI_INTR0_STATUS 0x830 +#define PCIE_PORT_GEN3_RELATED 0x890 +#define PORT_LOGIC_GEN3_EQ_DISABLE BIT(16) + #define PCIE_ATU_VIEWPORT 0x900 #define PCIE_ATU_REGION_INBOUND BIT(31) #define PCIE_ATU_REGION_OUTBOUND 0 @@ -244,6 +250,7 @@ struct dw_pcie { struct dw_pcie_ep ep; const struct dw_pcie_ops *ops; unsigned int version; + unsigned int dwc_pci_quirk; }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) From patchwork Tue Sep 10 12:25:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pankaj Dubey X-Patchwork-Id: 11139385 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 762E4912 for ; Tue, 10 Sep 2019 12:25:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 493EA20872 for ; Tue, 10 Sep 2019 12:25:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="Hdbv8mQZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2392145AbfIJMZY (ORCPT ); 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Tue, 10 Sep 2019 12:25:18 +0000 (GMT) From: Pankaj Dubey To: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, lorenzo.pieralisi@arm.com, bhelgaas@google.com, Anvesh Salveru , Pankaj Dubey Subject: [PATCH 2/2] PCI: dwc: Add support to disable equalization phase 2 and 3 Date: Tue, 10 Sep 2019 17:55:02 +0530 Message-Id: <1568118302-10505-2-git-send-email-pankaj.dubey@samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568118302-10505-1-git-send-email-pankaj.dubey@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTYRjm2znbOQ6Xh6n4tkpilKTgLQoOFBUkeLqIFUGQrVp5cNI2x+ac BoKlzAtmpikoU7wra2pNE51athrDcjPUsAhLyW4miimtEGftIv17nve5vC8fH4kJl3ERma7M ZNVKqVzM4+N9zyMjo+OqdZK4ktl9tMPSyKVbbstoy0wRQXes1RD0pMXAox31dh69uP6NoJse rxHHSMZUb0LMQO0MwTSYtUxZrxExvU9XEbNqDj/Du8g/nMrK07NYdeyRq3yZ+345rrIHZTeY J4k81CMoQQEkUAegaqUGlSA+KaQGEVQNuzg+8hNB69Ic4SO/EEw79MRWxOlwcn3CMII/lRP+ fAEH8h/ZMI+LR0XD/HKdF4dQhyBvwehNYJ4l7nuT/whJBlPnYNN42ePBqb2gr57hebCAYuDh s3r/tnB45yz29gRQJ2CtoxDz9ABl4sHYdJPflAA9rw1+HAwL9l4/FsH3u1tnZ8Dv5gp/uABB pb2O6xOOwsiUAfcchFGR0G2J9YwxahvcWZ/neMZACaBIL/S5I8D1dQzz4Z0wl9/K8WEG2tsm /M9lQNDjLuWWo121/1sbEDKi7axKo0hjNQdV+5WsLkYjVWi0yrSY6xkKM/J+g6iT/ajNedqK KBKJAwWzep1EyJVmaXIUVgQkJg4RTJdpJUJBqjTnJqvOuKLWylmNFe0gcXGYoIL75pKQSpNm sjdYVsWqt1QOGSDKQ1UpzOepa6PNF5Ytr9oH3ibdEi3FS/pGSuM2jjeOjSdtWKtD3SubexJ4 UKyzMfTQC3lnv41bOJr/5CPKdeHGwJeZEbnuLsb2fr3GQGgJY6wstP3Hl5bBRTi7Ue4OItju T6bCB47ZcXz1gyjRlZIt2Z08dB5PP6XsTEzuChPjGpk0PgpTa6R/AQ8YL5oCAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrLLMWRmVeSWpSXmKPExsWy7bCSvK7BtPJYg42dYhZndy1ktVjSlGGx 624Hu8WKLzPZLS7vmsNmcXbecTaLN79fsFss2vqF3YHDY828NYweO2fdZfdYsKnUo2/LKkaP Lfs/M3p83iQXwBbFZZOSmpNZllqkb5fAlfFvygSWguP8FQs2XWZvYNzM28XIySEhYCJx7uw5 1i5GLg4hgd2MEu/W9bFCJGQkJq9eAWULS6z895wdoqiJSWJd9yZGkASbgK7Ek/dzmUFsEQFb iYa/HcwgRcwCBxklrizdxwSSEBYIkJi44gELiM0ioCrRNu0uG4jNK+AhseHgPHaIDXISN891 gg3iFPCU+LKiHcwWAqrZeuMM0wRGvgWMDKsYJVMLinPTc4sNC4zyUsv1ihNzi0vz0vWS83M3 MYIDUUtrB+OJE/GHGAU4GJV4eB+0lccKsSaWFVfmHmKU4GBWEuG93lcaK8SbklhZlVqUH19U mpNafIhRmoNFSZxXPv9YpJBAemJJanZqakFqEUyWiYNTqoHR7YilZFznxXsqL2uXXan9ufLr k7Tvbnr/stMYLsW2/mRbxcx+eFNlSMf3ozxxHptNvp3cPu0bk8ScgEzVGasnMFsEvJjMx+Pf Ziykmel7uGOP+LFiu4qYxEO+Crd31Sg8/N39seeQQP+9NzL/XMwnrXuqtsUlcn2N5bkrPxzN pIU+r3RZWaSjxFKckWioxVxUnAgAvZpz20ACAAA= X-CMS-MailID: 20190910122520epcas5p1faeb16f7c38ee057ce93783a637e6bf4 X-Msg-Generator: CA CMS-TYPE: 105P X-CMS-RootMailID: 20190910122520epcas5p1faeb16f7c38ee057ce93783a637e6bf4 References: <1568118302-10505-1-git-send-email-pankaj.dubey@samsung.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Anvesh Salveru In some platforms, PCIe PHY may have issues which will prevent linkup to happen in GEN3 or high speed. In case equalization fails, link will fallback to GEN1. Designware controller gives flexibility to disable GEN3 equalization completely or only phase 2 and 3. Platform drivers can disable equalization phase 2 and 3, by setting dwc_pci_quirk flag DWC_EQUALIZATION_DISABLE. Signed-off-by: Anvesh Salveru Signed-off-by: Pankaj Dubey --- drivers/pci/controller/dwc/pcie-designware.c | 3 +++ drivers/pci/controller/dwc/pcie-designware.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index bf82091..97a8268 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -472,5 +472,8 @@ void dw_pcie_setup(struct dw_pcie *pci) if (pci->dwc_pci_quirk & DWC_EQUALIZATION_DISABLE) val |= PORT_LOGIC_GEN3_EQ_DISABLE; + if (pci->dwc_pci_quirk & DWC_EQ_PHASE_2_3_DISABLE) + val |= PORT_LOGIC_GEN3_EQ_PHASE_2_3_DISABLE; + dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index a1453c5..b541508 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -31,6 +31,7 @@ /* Parameters for PCIe Quirks */ #define DWC_EQUALIZATION_DISABLE 0x1 +#define DWC_EQ_PHASE_2_3_DISABLE 0x2 /* Synopsys-specific PCIe configuration registers */ #define PCIE_PORT_LINK_CONTROL 0x710 @@ -65,6 +66,7 @@ #define PCIE_PORT_GEN3_RELATED 0x890 #define PORT_LOGIC_GEN3_EQ_DISABLE BIT(16) +#define PORT_LOGIC_GEN3_EQ_PHASE_2_3_DISABLE BIT(9) #define PCIE_ATU_VIEWPORT 0x900 #define PCIE_ATU_REGION_INBOUND BIT(31)