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Thu, 12 Sep 2019 14:40:36 -0700 (PDT) To: linux-riscv@lists.infradead.org From: Darius Rad Subject: [PATCH] irqchip/sifive-plic: add irq_mask and irq_unmask Message-ID: <529ec882-734f-17ae-e4cb-3aeb563ad1d5@bluespec.com> Date: Thu, 12 Sep 2019 17:40:34 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190912_144039_211957_A3DC8293 X-CRM114-Status: GOOD ( 12.65 ) X-Spam-Score: 0.7 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:742 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.7 SPF_NEUTRAL SPF: sender does not match SPF record (neutral) -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Cooper , Marc Zyngier , Palmer Dabbelt , linux-kernel@vger.kernel.org, Paul Walmsley , Thomas Gleixner Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org As per the existing comment, irq_mask and irq_unmask do not need to do anything for the PLIC. However, the functions must exist (the pointers cannot be NULL) as they are not optional, based on the documentation (Documentation/core-api/genericirq.rst) as well as existing usage (e.g., include/linux/irqchip/chained_irq.h). Signed-off-by: Darius Rad Acked-by: Palmer Dabbelt Signed-off-by: Marc Zyngier Reviewed-by: Palmer Dabbelt Tested-by: Palmer Dabbelt (QEMU Boot) Tested-by: Darius Rad Tested-by: Paul Walmsley # HiFive Unleashed --- drivers/irqchip/irq-sifive-plic.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index cf755964f2f8..52d5169f924f 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -111,6 +111,13 @@ static void plic_irq_disable(struct irq_data *d) plic_irq_toggle(cpu_possible_mask, d->hwirq, 0); } +/* + * There is no need to mask/unmask PLIC interrupts. They are "masked" + * by reading claim and "unmasked" when writing it back. + */ +static void plic_irq_mask(struct irq_data *d) { } +static void plic_irq_unmask(struct irq_data *d) { } + #ifdef CONFIG_SMP static int plic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, bool force) @@ -138,12 +145,10 @@ static int plic_set_affinity(struct irq_data *d, static struct irq_chip plic_chip = { .name = "SiFive PLIC", - /* - * There is no need to mask/unmask PLIC interrupts. They are "masked" - * by reading claim and "unmasked" when writing it back. - */ .irq_enable = plic_irq_enable, .irq_disable = plic_irq_disable, + .irq_mask = plic_irq_mask, + .irq_unmask = plic_irq_unmask, #ifdef CONFIG_SMP .irq_set_affinity = plic_set_affinity, #endif