From patchwork Wed Sep 18 08:04:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gareth Williams X-Patchwork-Id: 11149785 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D9AA514DB for ; Wed, 18 Sep 2019 08:05:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C24A120882 for ; Wed, 18 Sep 2019 08:05:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729294AbfIRIFF (ORCPT ); Wed, 18 Sep 2019 04:05:05 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:10399 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726814AbfIRIFD (ORCPT ); Wed, 18 Sep 2019 04:05:03 -0400 X-IronPort-AV: E=Sophos;i="5.64,519,1559487600"; d="scan'208";a="26658094" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 18 Sep 2019 17:05:01 +0900 Received: from renesas-VirtualBox.ree.adwin.renesas.com (unknown [10.226.37.56]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 05B2F41C9BD7; Wed, 18 Sep 2019 17:04:58 +0900 (JST) From: Gareth Williams To: Mark Brown , Rob Herring , Mark Rutland Cc: Phil Edworthy , Geert Uytterhoeven , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gareth Williams Subject: [PATCH v2 1/4] dt: spi: Add Renesas RZ/N1 binding documentation Date: Wed, 18 Sep 2019 09:04:33 +0100 Message-Id: <1568793876-9009-2-git-send-email-gareth.williams.jx@renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568793876-9009-1-git-send-email-gareth.williams.jx@renesas.com> References: <1568793876-9009-1-git-send-email-gareth.williams.jx@renesas.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Phil Edworthy The Renesas RZ/N1 SPI Controller is based on the Synopsys DW SSI, but has additional registers for software CS control and DMA. This patch does not address the changes required for DMA support, it simply adds the compatible string. The CS functionality is not very useful and also not needed as Linux can use gpios for the CS signals. Add a compatible string to handle any unforeseen issues that may arise, and pave the way for DMA support. Signed-off-by: Gareth Williams Signed-off-by: Phil Edworthy Reviewed-by: Rob Herring --- Note: All the other manufacturers detail their compatible strings in snps,dw-apb-ssi.txt. I think it makes sense for rzn1 to be in it's own file due to the changes made to the peripheral for DMA support. v2: - No changes. --- Documentation/devicetree/bindings/spi/renesas,rzn1-spi.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/renesas,rzn1-spi.txt diff --git a/Documentation/devicetree/bindings/spi/renesas,rzn1-spi.txt b/Documentation/devicetree/bindings/spi/renesas,rzn1-spi.txt new file mode 100644 index 0000000..fb1a672 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/renesas,rzn1-spi.txt @@ -0,0 +1,11 @@ +Renesas RZ/N1 SPI Controller + +This controller is based on the Synopsys DW Synchronous Serial Interface and +inherits all properties defined in snps,dw-apb-ssi.txt except for the +compatible property. + +Required properties: +- compatible : The device specific string followed by the generic RZ/N1 string. + Therefore it must be one of: + "renesas,r9a06g032-spi", "renesas,rzn1-spi" + "renesas,r9a06g033-spi", "renesas,rzn1-spi" From patchwork Wed Sep 18 08:04:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gareth Williams X-Patchwork-Id: 11149787 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8ABF814E5 for ; Wed, 18 Sep 2019 08:05:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7392321907 for ; Wed, 18 Sep 2019 08:05:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729356AbfIRIFS (ORCPT ); Wed, 18 Sep 2019 04:05:18 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:27074 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729339AbfIRIFR (ORCPT ); Wed, 18 Sep 2019 04:05:17 -0400 X-IronPort-AV: E=Sophos;i="5.64,519,1559487600"; d="scan'208";a="26658131" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 18 Sep 2019 17:05:16 +0900 Received: from renesas-VirtualBox.ree.adwin.renesas.com (unknown [10.226.37.56]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 2322141CA6B6; Wed, 18 Sep 2019 17:05:13 +0900 (JST) From: Gareth Williams To: Mark Brown , Rob Herring , Mark Rutland Cc: Gareth Williams , Phil Edworthy , Geert Uytterhoeven , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/4] dt-bindings: snps,dw-apb-ssi: Add optional clock domain information Date: Wed, 18 Sep 2019 09:04:34 +0100 Message-Id: <1568793876-9009-3-git-send-email-gareth.williams.jx@renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568793876-9009-1-git-send-email-gareth.williams.jx@renesas.com> References: <1568793876-9009-1-git-send-email-gareth.williams.jx@renesas.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Note in the bindings documentation that pclk should be renamed if a clock domain is used to enable the optional bus clock. Signed-off-by: Gareth Williams --- v2: Introduced this patch. --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index f54c8c3..3ed08ee 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -16,7 +16,8 @@ Required properties: Optional properties: - clock-names : Contains the names of the clocks: "ssi_clk", for the core clock used to generate the external SPI clock. - "pclk", the interface clock, required for register access. + "pclk", the interface clock, required for register access. If a clock domain + used to enable this clock then it should be named "pclk_clkdomain". - cs-gpios : Specifies the gpio pins to be used for chipselects. - num-cs : The number of chipselects. If omitted, this will default to 4. - reg-io-width : The I/O register width (in bytes) implemented by this From patchwork Wed Sep 18 08:04:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gareth Williams X-Patchwork-Id: 11149789 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2351714E5 for ; Wed, 18 Sep 2019 08:05:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0B06D20882 for ; Wed, 18 Sep 2019 08:05:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729381AbfIRIF2 (ORCPT ); Wed, 18 Sep 2019 04:05:28 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:22733 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729339AbfIRIF2 (ORCPT ); Wed, 18 Sep 2019 04:05:28 -0400 X-IronPort-AV: E=Sophos;i="5.64,519,1559487600"; d="scan'208";a="26658158" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 18 Sep 2019 17:05:26 +0900 Received: from renesas-VirtualBox.ree.adwin.renesas.com (unknown [10.226.37.56]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id E139F41CA6B6; Wed, 18 Sep 2019 17:05:24 +0900 (JST) From: Gareth Williams To: Mark Brown Cc: Phil Edworthy , Geert Uytterhoeven , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Gareth Williams Subject: [PATCH v2 3/4] spi: dw: Add basic runtime PM support Date: Wed, 18 Sep 2019 09:04:35 +0100 Message-Id: <1568793876-9009-4-git-send-email-gareth.williams.jx@renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568793876-9009-1-git-send-email-gareth.williams.jx@renesas.com> References: <1568793876-9009-1-git-send-email-gareth.williams.jx@renesas.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Phil Edworthy Enable runtime PM so that the clock used to access the registers in the peripheral is turned on using a clock domain. Signed-off-by: Phil Edworthy Signed-off-by: Gareth Williams --- v2: - set spi_controller.auto_runtime_pm instead of using pm_runtime_get_sync. - Added pm_runtime_disable calls to dw_spi_remove_host and the error condition of dw_spi_add_host. --- drivers/spi/spi-dw.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index 9a49e07..54ed6eb 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -493,10 +494,13 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws) master->dev.of_node = dev->of_node; master->dev.fwnode = dev->fwnode; master->flags = SPI_MASTER_GPIO_SS; + master->auto_runtime_pm = true; if (dws->set_cs) master->set_cs = dws->set_cs; + pm_runtime_enable(dev); + /* Basic HW init */ spi_hw_init(dev, dws); @@ -525,6 +529,7 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws) spi_enable_chip(dws, 0); free_irq(dws->irq, master); err_free_master: + pm_runtime_disable(dev); spi_controller_put(master); return ret; } @@ -539,6 +544,9 @@ void dw_spi_remove_host(struct dw_spi *dws) spi_shutdown_chip(dws); + if (dws->master) + pm_runtime_disable(&dws->master->dev); + free_irq(dws->irq, dws->master); } EXPORT_SYMBOL_GPL(dw_spi_remove_host); From patchwork Wed Sep 18 08:04:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gareth Williams X-Patchwork-Id: 11149791 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6096A14DB for ; Wed, 18 Sep 2019 08:05:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 48EF320882 for ; Wed, 18 Sep 2019 08:05:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728316AbfIRIFj (ORCPT ); Wed, 18 Sep 2019 04:05:39 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:42668 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725298AbfIRIFj (ORCPT ); Wed, 18 Sep 2019 04:05:39 -0400 X-IronPort-AV: E=Sophos;i="5.64,519,1559487600"; d="scan'208";a="26877426" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 18 Sep 2019 17:05:38 +0900 Received: from renesas-VirtualBox.ree.adwin.renesas.com (unknown [10.226.37.56]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id DF00B41CA6D1; Wed, 18 Sep 2019 17:05:36 +0900 (JST) From: Gareth Williams To: Mark Brown Cc: Phil Edworthy , Geert Uytterhoeven , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Gareth Williams Subject: [PATCH v2 4/4] spi: dw: Add compatible string for Renesas RZ/N1 SPI Controller Date: Wed, 18 Sep 2019 09:04:36 +0100 Message-Id: <1568793876-9009-5-git-send-email-gareth.williams.jx@renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568793876-9009-1-git-send-email-gareth.williams.jx@renesas.com> References: <1568793876-9009-1-git-send-email-gareth.williams.jx@renesas.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Phil Edworthy The Renesas RZ/N1 SPI Controller is based on the Synopsys DW SSI, but has additional registers for software CS control and DMA. This patch does not address the changes required for DMA support, it simply adds the compatible string. The CS registers are not needed as Linux can use gpios for the CS signals. Signed-off-by: Gareth Williams Signed-off-by: Phil Edworthy --- v2: no changes --- drivers/spi/spi-dw-mmio.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index edb3cf6..3640b01 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -225,6 +225,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { { .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init}, { .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init}, { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init}, + { .compatible = "renesas,rzn1-spi", }, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);