From patchwork Wed Sep 18 17:31:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 11150927 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0425D16B1 for ; Wed, 18 Sep 2019 17:32:44 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D5A3421920 for ; Wed, 18 Sep 2019 17:32:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="pXDVXDuz"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="OzltOak1" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D5A3421920 Authentication-Results: mail.kernel.org; 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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iAdol-00051v-Ui; Wed, 18 Sep 2019 17:32:40 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iAdoL-0004ed-KK; Wed, 18 Sep 2019 17:32:15 +0000 Received: from localhost.localdomain (unknown [194.230.155.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6680A208C0; Wed, 18 Sep 2019 17:32:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1568827933; bh=1TixgpnrbW74TJpZIMBN4jvpzcDubcE9UumV31l30Nk=; h=From:To:Cc:Subject:Date:From; b=OzltOak1RI4M1f9eGUSNpFq39Ro2X4jHeAfIiXyq0c34FJmpbNaEv7Cjcemb0poM9 uE04q4mDU1LrkMk30mY4EX+LhD7KA8S6J8COMeBcIJZj56YzKZ7ZEf8xMUBTP+sWFK ojyxY9o/4DOqaRfganDMdAi+8phtDnFnChg4e0II= From: Krzysztof Kozlowski To: Rob Herring , Mark Rutland , Thierry Reding , Matt Mackall , Herbert Xu , Wim Van Sebroeck , Guenter Roeck , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-leds@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-crypto@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH v2 1/8] dt-bindings: rng: exynos4-rng: Convert Exynos PRNG bindings to json-schema Date: Wed, 18 Sep 2019 19:31:34 +0200 Message-Id: <20190918173141.4314-1-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190918_103213_708641_8E8EE7B8 X-CRM114-Status: GOOD ( 13.65 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Krzysztof Kozlowski Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Convert Samsung Exynos Pseudo Random Number Generator bindings to DT schema format using json-schema. Signed-off-by: Krzysztof Kozlowski --- Changes since v1: 1. Indent example with four spaces (more readable). --- .../bindings/rng/samsung,exynos4-rng.txt | 19 --------- .../bindings/rng/samsung,exynos4-rng.yaml | 41 +++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 42 insertions(+), 20 deletions(-) delete mode 100644 Documentation/devicetree/bindings/rng/samsung,exynos4-rng.txt create mode 100644 Documentation/devicetree/bindings/rng/samsung,exynos4-rng.yaml diff --git a/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.txt b/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.txt deleted file mode 100644 index a13fbdb4bd88..000000000000 --- a/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.txt +++ /dev/null @@ -1,19 +0,0 @@ -Exynos Pseudo Random Number Generator - -Required properties: - -- compatible : One of: - - "samsung,exynos4-rng" for Exynos4210 and Exynos4412 - - "samsung,exynos5250-prng" for Exynos5250+ -- reg : Specifies base physical address and size of the registers map. -- clocks : Phandle to clock-controller plus clock-specifier pair. -- clock-names : "secss" as a clock name. - -Example: - - rng@10830400 { - compatible = "samsung,exynos4-rng"; - reg = <0x10830400 0x200>; - clocks = <&clock CLK_SSS>; - clock-names = "secss"; - }; diff --git a/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.yaml b/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.yaml new file mode 100644 index 000000000000..2d075d6c87b6 --- /dev/null +++ b/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rng/samsung,exynos4-rng.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC Pseudo Random Number Generator + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + enum: + - samsung,exynos4-rng # for Exynos4210 and Exynos4412 + - samsung,exynos5250-prng # for Exynos5250+ + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: secss + +required: + - compatible + - reg + - clock-names + - clocks + +examples: + - | + rng@10830400 { + compatible = "samsung,exynos4-rng"; + reg = <0x10830400 0x200>; + clocks = <&clock 255>; // CLK_SSS + clock-names = "secss"; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 00969a90f94c..9cec4494b9a8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14181,7 +14181,7 @@ L: linux-crypto@vger.kernel.org L: linux-samsung-soc@vger.kernel.org S: Maintained F: drivers/crypto/exynos-rng.c -F: Documentation/devicetree/bindings/rng/samsung,exynos4-rng.txt +F: Documentation/devicetree/bindings/rng/samsung,exynos4-rng.yaml SAMSUNG EXYNOS TRUE RANDOM NUMBER GENERATOR (TRNG) DRIVER M: Łukasz Stelmach From patchwork Wed Sep 18 17:31:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 11150971 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 397681745 for ; Wed, 18 Sep 2019 17:33:16 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 16343208C0 for ; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1568827939; bh=zjXEIYpD3fE5Zr/V3tvwmlVGzHjthNbt5x4gZC+CdjI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FvR1MjqI294G8TedX7gWzHt3umBVoayRHdF7EOG3JD2wP2uWpCqWQc99LBZQ0Kh3L LDh3tPkQazq+H1Zkj4fi4TBZTgyNr2RAqWjGuznHsqPzewMg7Y8RFelIXYKOF3z4xp SRQvgJUOP+tCnMh2lvxLixwouFiU1b0SyXv+qMn8= From: Krzysztof Kozlowski To: Rob Herring , Mark Rutland , Thierry Reding , Matt Mackall , Herbert Xu , Wim Van Sebroeck , Guenter Roeck , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-leds@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-crypto@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH v2 2/8] dt-bindings: sram: Convert SRAM bindings to json-schema Date: Wed, 18 Sep 2019 19:31:35 +0200 Message-Id: <20190918173141.4314-2-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190918173141.4314-1-krzk@kernel.org> References: <20190918173141.4314-1-krzk@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190918_103219_772760_08FAB82D X-CRM114-Status: GOOD ( 19.83 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Krzysztof Kozlowski MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Convert generic mmio-sram bindings to DT schema format using json-schema. Signed-off-by: Krzysztof Kozlowski --- Changes since v1: 1. Indent example with four spaces (more readable). --- .../devicetree/bindings/sram/sram.txt | 80 ---------- .../devicetree/bindings/sram/sram.yaml | 138 ++++++++++++++++++ 2 files changed, 138 insertions(+), 80 deletions(-) delete mode 100644 Documentation/devicetree/bindings/sram/sram.txt create mode 100644 Documentation/devicetree/bindings/sram/sram.yaml diff --git a/Documentation/devicetree/bindings/sram/sram.txt b/Documentation/devicetree/bindings/sram/sram.txt deleted file mode 100644 index e98908bd4227..000000000000 --- a/Documentation/devicetree/bindings/sram/sram.txt +++ /dev/null @@ -1,80 +0,0 @@ -Generic on-chip SRAM - -Simple IO memory regions to be managed by the genalloc API. - -Required properties: - -- compatible : mmio-sram or atmel,sama5d2-securam - -- reg : SRAM iomem address range - -Reserving sram areas: ---------------------- - -Each child of the sram node specifies a region of reserved memory. Each -child node should use a 'reg' property to specify a specific range of -reserved memory. - -Following the generic-names recommended practice, node names should -reflect the purpose of the node. Unit address (@
) should be -appended to the name. - -Required properties in the sram node: - -- #address-cells, #size-cells : should use the same values as the root node -- ranges : standard definition, should translate from local addresses - within the sram to bus addresses - -Optional properties in the sram node: - -- no-memory-wc : the flag indicating, that SRAM memory region has not to - be remapped as write combining. WC is used by default. - -Required properties in the area nodes: - -- reg : iomem address range, relative to the SRAM range - -Optional properties in the area nodes: - -- compatible : standard definition, should contain a vendor specific string - in the form ,[-] -- pool : indicates that the particular reserved SRAM area is addressable - and in use by another device or devices -- export : indicates that the reserved SRAM area may be accessed outside - of the kernel, e.g. by bootloader or userspace -- protect-exec : Same as 'pool' above but with the additional - constraint that code wil be run from the region and - that the memory is maintained as read-only, executable - during code execution. NOTE: This region must be page - aligned on start and end in order to properly allow - manipulation of the page attributes. -- label : the name for the reserved partition, if omitted, the label - is taken from the node name excluding the unit address. -- clocks : a list of phandle and clock specifier pair that controls the - single SRAM clock. - -Example: - -sram: sram@5c000000 { - compatible = "mmio-sram"; - reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */ - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5c000000 0x40000>; - - smp-sram@100 { - compatible = "socvendor,smp-sram"; - reg = <0x100 0x50>; - }; - - device-sram@1000 { - reg = <0x1000 0x1000>; - pool; - }; - - exported@20000 { - reg = <0x20000 0x20000>; - export; - }; -}; diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml new file mode 100644 index 000000000000..8d9d6ce494b2 --- /dev/null +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sram/sram.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic on-chip SRAM + +maintainers: + - FIXME + +description: |+ + Simple IO memory regions to be managed by the genalloc API. + + Each child of the sram node specifies a region of reserved memory. Each + child node should use a 'reg' property to specify a specific range of + reserved memory. + + Following the generic-names recommended practice, node names should + reflect the purpose of the node. Unit address (@
) should be + appended to the name. + +properties: + $nodename: + pattern: "^sram(@.*)?" + + compatible: + items: + - enum: + - mmio-sram + - atmel,sama5d2-securam + + reg: + maxItems: 1 + + "#address-cells": + description: Should use the same values as the root node. + + "#size-cells": + description: Should use the same values as the root node. + + ranges: + description: + Should translate from local addresses within the sram to bus addresses. + + no-memory-wc: + description: + The flag indicating, that SRAM memory region has not to be remapped + as write combining. WC is used by default. + type: boolean + + # TODO: additionalProperties: false + +patternProperties: + "^([a-z]*-)?sram@[a-f0-9]$": + type: object + description: + Each child of the sram node specifies a region of reserved memory. + properties: + reg: + description: + IO mem address range, relative to the SRAM range. + + compatible: + $ref: /schemas/types.yaml#/definitions/string + description: + Should contain a vendor specific string in the form + ,[-] + + pool: + description: + Indicates that the particular reserved SRAM area is addressable + and in use by another device or devices. + type: boolean + + export: + description: + Indicates that the reserved SRAM area may be accessed outside + of the kernel, e.g. by bootloader or userspace. + type: boolean + + protect-exec: + description: | + Same as 'pool' above but with the additional constraint that code + will be run from the region and that the memory is maintained as + read-only, executable during code execution. NOTE: This region must + be page aligned on start and end in order to properly allow + manipulation of the page attributes. + type: boolean + + label: + $ref: /schemas/types.yaml#/definitions/string + description: + The name for the reserved partition, if omitted, the label is taken + from the node name excluding the unit address. + + clocks: + description: + A list of phandle and clock specifier pair that controls the + single SRAM clock. + + # TODO: additionalProperties: false + + required: + - reg + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +examples: + - | + sram: sram@5c000000 { + compatible = "mmio-sram"; + reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */ + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5c000000 0x40000>; + + smp-sram@100 { + compatible = "socvendor,smp-sram"; + reg = <0x100 0x50>; + }; + + device-sram@1000 { + reg = <0x1000 0x1000>; + pool; + }; + + exported@20000 { + reg = <0x20000 0x20000>; + export; + }; + }; From patchwork Wed Sep 18 17:31:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 11150981 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D392114ED for ; Wed, 18 Sep 2019 17:33:45 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AEA81208C0 for ; Wed, 18 Sep 2019 17:33:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="AMto0O4T"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="urz9lZOd" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AEA81208C0 Authentication-Results: mail.kernel.org; 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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iAdpm-00063X-Ma; Wed, 18 Sep 2019 17:33:42 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iAdoX-0004nT-W2; Wed, 18 Sep 2019 17:32:27 +0000 Received: from localhost.localdomain (unknown [194.230.155.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id C63B821907; Wed, 18 Sep 2019 17:32:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1568827945; bh=PpVGfmbQUMan+CEI3W/iEi0A42O/v6szcQ9dLYD6us0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=urz9lZOdJFxt+2VRjRLmtSMTeQ1d4Jy9u76x7VlvtwoYzmIbeDlEEGw81w8mx/0h4 LF8vtSFKa7DlJuwnsTz3I5nITsyzHmKwB2Tlwz6T7PH/6U/CmGjhnO5eCH4I53nymK BJi93q9qF9RgqdKxkf3GSlDFcoSD9jDwY0RTZqQM= From: Krzysztof Kozlowski To: Rob Herring , Mark Rutland , Thierry Reding , Matt Mackall , Herbert Xu , Wim Van Sebroeck , Guenter Roeck , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-leds@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-crypto@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH v2 3/8] dt-bindings: sram: Convert Samsung Exynos SYSRAM bindings to json-schema Date: Wed, 18 Sep 2019 19:31:36 +0200 Message-Id: <20190918173141.4314-3-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190918173141.4314-1-krzk@kernel.org> References: <20190918173141.4314-1-krzk@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190918_103226_215123_BEF24CD6 X-CRM114-Status: GOOD ( 13.66 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Krzysztof Kozlowski MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Convert Samsung Exynos SYSRAM bindings to DT schema format using json-schema. Signed-off-by: Krzysztof Kozlowski --- TODO: The node naming should be probably fixed (sysram->sram) Changes since v1: 1. Indent example with four spaces (more readable). --- .../devicetree/bindings/sram/samsung-sram.txt | 38 ------------ .../bindings/sram/samsung-sram.yaml | 58 +++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 59 insertions(+), 39 deletions(-) delete mode 100644 Documentation/devicetree/bindings/sram/samsung-sram.txt create mode 100644 Documentation/devicetree/bindings/sram/samsung-sram.yaml diff --git a/Documentation/devicetree/bindings/sram/samsung-sram.txt b/Documentation/devicetree/bindings/sram/samsung-sram.txt deleted file mode 100644 index 61a9bbed303d..000000000000 --- a/Documentation/devicetree/bindings/sram/samsung-sram.txt +++ /dev/null @@ -1,38 +0,0 @@ -Samsung Exynos SYSRAM for SMP bringup: ------------------------------------- - -Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup -of the secondary cores. Once the core gets powered up it executes the -code that is residing at some specific location of the SYSRAM. - -Therefore reserved section sub-nodes have to be added to the mmio-sram -declaration. These nodes are of two types depending upon secure or -non-secure execution environment. - -Required sub-node properties: -- compatible : depending upon boot mode, should be - "samsung,exynos4210-sysram" : for Secure SYSRAM - "samsung,exynos4210-sysram-ns" : for Non-secure SYSRAM - -The rest of the properties should follow the generic mmio-sram discription -found in Documentation/devicetree/bindings/sram/sram.txt - -Example: - - sysram@2020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x54000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x54000>; - - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sysram@53000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x53000 0x1000>; - }; - }; diff --git a/Documentation/devicetree/bindings/sram/samsung-sram.yaml b/Documentation/devicetree/bindings/sram/samsung-sram.yaml new file mode 100644 index 000000000000..f49b3b58eb5c --- /dev/null +++ b/Documentation/devicetree/bindings/sram/samsung-sram.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sram/samsung-sram.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC SYSRAM for SMP bringup + +maintainers: + - Krzysztof Kozlowski + +description: |+ + Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup + of the secondary cores. Once the core gets powered up it executes the + code that is residing at some specific location of the SYSRAM. + + Therefore reserved section sub-nodes have to be added to the mmio-sram + declaration. These nodes are of two types depending upon secure or + non-secure execution environment. + +allOf: + - $ref: "sram.yaml#" + +properties: + $nodename: + pattern: "^sysram(@.*)?" + +patternProperties: + "^([a-z]*-)?sysram@[a-f0-9]$": + type: object + + properties: + compatible: + description: + Depending upon boot mode + enum: + - samsung,exynos4210-sysram # for Secure SYSRAM + - samsung,exynos4210-sysram-ns # for Non-secure SYSRAM + +examples: + - | + sysram@2020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x54000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x54000>; + + smp-sysram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sysram@53000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x53000 0x1000>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 9cec4494b9a8..c49d35dce088 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2225,7 +2225,7 @@ F: drivers/soc/samsung/ F: include/linux/soc/samsung/ F: Documentation/arm/samsung/ F: Documentation/devicetree/bindings/arm/samsung/ -F: Documentation/devicetree/bindings/sram/samsung-sram.txt +F: Documentation/devicetree/bindings/sram/samsung-sram.yaml F: Documentation/devicetree/bindings/power/pd-samsung.txt N: exynos From patchwork Wed Sep 18 17:31:37 2019 Content-Type: text/plain; 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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iAdqC-0006T8-H6; Wed, 18 Sep 2019 17:34:08 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iAdod-0004tF-RD; Wed, 18 Sep 2019 17:32:34 +0000 Received: from localhost.localdomain (unknown [194.230.155.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0D71221927; Wed, 18 Sep 2019 17:32:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1568827951; bh=TBN5rIG3E121IMHkSrsLKM0ttmkZlIGjy8Mb0Alnr2E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fjjw5xql6I5HcW6gX8TfXmC+EZWmaIAAquqmny3vaz+f84Sjkk0yHJy0LE8H7ZUX2 y7Fcw+0k1ciNDrte9YZVLF7tyUnql3LcOve3Ps4wE9XSwAB8H0Ti0vYY7D9uTWDHa/ GK5Xf6mtjT0yzXqCHN6Drr2cFsPOAMLePVUKF0ik= From: Krzysztof Kozlowski To: Rob Herring , Mark Rutland , Thierry Reding , Matt Mackall , Herbert Xu , Wim Van Sebroeck , Guenter Roeck , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-leds@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-crypto@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH v2 4/8] dt-bindings: memory-controllers: Convert Samsung Exynos SROM bindings to json-schema Date: Wed, 18 Sep 2019 19:31:37 +0200 Message-Id: <20190918173141.4314-4-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190918173141.4314-1-krzk@kernel.org> References: <20190918173141.4314-1-krzk@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190918_103232_202720_D6DEB353 X-CRM114-Status: GOOD ( 18.78 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Krzysztof Kozlowski MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Convert Samsung Exynos SROM controller bindings to DT schema format using json-schema. Signed-off-by: Krzysztof Kozlowski --- Changes since v1: 1. Indent example with four spaces (more readable), 2. Split examples into two, 3. Fix pattern for subnode name, 4. Remove checks for #address-cells-ranges-#size-cells, 5. Add "additionalProperties" so the wrongly named subnodes would be matched. --- .../memory-controllers/exynos-srom.txt | 79 ----------- .../memory-controllers/exynos-srom.yaml | 128 ++++++++++++++++++ 2 files changed, 128 insertions(+), 79 deletions(-) delete mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos-srom.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos-srom.txt b/Documentation/devicetree/bindings/memory-controllers/exynos-srom.txt deleted file mode 100644 index f633b5d0f8ca..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/exynos-srom.txt +++ /dev/null @@ -1,79 +0,0 @@ -SAMSUNG Exynos SoCs SROM Controller driver. - -Required properties: -- compatible : Should contain "samsung,exynos4210-srom". - -- reg: offset and length of the register set - -Optional properties: -The SROM controller can be used to attach external peripherals. In this case -extra properties, describing the bus behind it, should be specified as below: - -- #address-cells: Must be set to 2 to allow device address translation. - Address is specified as (bank#, offset). - -- #size-cells: Must be set to 1 to allow device size passing - -- ranges: Must be set up to reflect the memory layout with four integer values - per bank: - 0 - -Sub-nodes: -The actual device nodes should be added as subnodes to the SROMc node. These -subnodes, in addition to regular device specification, should contain the following -properties, describing configuration of the relevant SROM bank: - -Required properties: -- reg: bank number, base address (relative to start of the bank) and size of - the memory mapped for the device. Note that base address will be - typically 0 as this is the start of the bank. - -- samsung,srom-timing : array of 6 integers, specifying bank timings in the - following order: Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs. - Each value is specified in cycles and has the following - meaning and valid range: - Tacp : Page mode access cycle at Page mode (0 - 15) - Tcah : Address holding time after CSn (0 - 15) - Tcoh : Chip selection hold on OEn (0 - 15) - Tacc : Access cycle (0 - 31, the actual time is N + 1) - Tcos : Chip selection set-up before OEn (0 - 15) - Tacs : Address set-up before CSn (0 - 15) - -Optional properties: -- reg-io-width : data width in bytes (1 or 2). If omitted, default of 1 is used. - -- samsung,srom-page-mode : if page mode is set, 4 data page mode will be configured, - else normal (1 data) page mode will be set. - -Example: basic definition, no banks are configured - memory-controller@12570000 { - compatible = "samsung,exynos4210-srom"; - reg = <0x12570000 0x14>; - }; - -Example: SROMc with SMSC911x ethernet chip on bank 3 - memory-controller@12570000 { - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x04000000 0x20000 // Bank0 - 1 0 0x05000000 0x20000 // Bank1 - 2 0 0x06000000 0x20000 // Bank2 - 3 0 0x07000000 0x20000>; // Bank3 - - compatible = "samsung,exynos4210-srom"; - reg = <0x12570000 0x14>; - - ethernet@3,0 { - compatible = "smsc,lan9115"; - reg = <3 0 0x10000>; // Bank 3, offset = 0 - phy-mode = "mii"; - interrupt-parent = <&gpx0>; - interrupts = <5 8>; - reg-io-width = <2>; - smsc,irq-push-pull; - smsc,force-internal-phy; - - samsung,srom-page-mode; - samsung,srom-timing = <9 12 1 9 1 1>; - }; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml b/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml new file mode 100644 index 000000000000..cdfe3f7f0ea9 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC SROM Controller driver + +maintainers: + - Krzysztof Kozlowski + +description: |+ + The SROM controller can be used to attach external peripherals. In this case + extra properties, describing the bus behind it, should be specified. + +properties: + compatible: + items: + - const: samsung,exynos4210-srom + + reg: + maxItems: 1 + + "#address-cells": + const: 2 + + "#size-cells": + const: 1 + + ranges: + description: | + Reflects the memory layout with four integer values per bank. Format: + 0 + Up to four banks are supported. + +patternProperties: + "^.*@[0-3],[a-f0-9]+$": + type: object + description: + The actual device nodes should be added as subnodes to the SROMc node. + These subnodes, in addition to regular device specification, should + contain the following properties, describing configuration + of the relevant SROM bank. + + properties: + reg: + description: + Bank number, base address (relative to start of the bank) and size + of the memory mapped for the device. Note that base address will be + typically 0 as this is the start of the bank. + maxItems: 1 + + reg-io-width: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [1, 2] + description: + Data width in bytes (1 or 2). If omitted, default of 1 is used. + + samsung,srom-page-mode: + description: + If page mode is set, 4 data page mode will be configured, + else normal (1 data) page mode will be set. + type: boolean + + samsung,srom-timing: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - items: + minItems: 6 + maxItems: 6 + description: | + Array of 6 integers, specifying bank timings in the following order: + Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs. + Each value is specified in cycles and has the following meaning + and valid range: + Tacp: Page mode access cycle at Page mode (0 - 15) + Tcah: Address holding time after CSn (0 - 15) + Tcoh: Chip selection hold on OEn (0 - 15) + Tacc: Access cycle (0 - 31, the actual time is N + 1) + Tcos: Chip selection set-up before OEn (0 - 15) + Tacs: Address set-up before CSn (0 - 15) + + required: + - reg + - samsung,srom-timing + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + // Example: basic definition, no banks are configured + memory-controller@12560000 { + compatible = "samsung,exynos4210-srom"; + reg = <0x12560000 0x14>; + }; + + - | + // Example: SROMc with SMSC911x ethernet chip on bank 3 + memory-controller@12570000 { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x04000000 0x20000 // Bank0 + 1 0 0x05000000 0x20000 // Bank1 + 2 0 0x06000000 0x20000 // Bank2 + 3 0 0x07000000 0x20000>; // Bank3 + + compatible = "samsung,exynos4210-srom"; + reg = <0x12570000 0x14>; + + ethernet@3,0 { + compatible = "smsc,lan9115"; + reg = <3 0 0x10000>; // Bank 3, offset = 0 + phy-mode = "mii"; + interrupt-parent = <&gpx0>; + interrupts = <5 8>; + reg-io-width = <2>; + smsc,irq-push-pull; + smsc,force-internal-phy; + + samsung,srom-page-mode; + samsung,srom-timing = <9 12 1 9 1 1>; + }; + }; From patchwork Wed Sep 18 17:31:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 11151001 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1A29676 for ; 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Wed, 18 Sep 2019 17:32:40 +0000 Received: from localhost.localdomain (unknown [194.230.155.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id D79D821928; Wed, 18 Sep 2019 17:32:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1568827958; bh=E9DwEf7R8b/H/w/pY582iNh72DFD9zpZbpy6YjCJtCA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=xHEiwH/r63UQYy4j6Uf8KGGtFbl4pyX4olLMK84c3ybxPXAShOU6AW7FSUIC76wh0 9foNamqzWle3Cgmi0S2/zX1D7GQgiwPMUPGJzBJkTKl0OzQP4UHOYYHcX9YiMaCUCb 5WhDtUwJ68hJrzzVaxE139BLp3UdDCgJMgSlHHEU= From: Krzysztof Kozlowski To: Rob Herring , Mark Rutland , Thierry Reding , Matt Mackall , Herbert Xu , Wim Van Sebroeck , Guenter Roeck , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-leds@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-crypto@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH v2 5/8] dt-bindings: watchdog: Convert Samsung SoC watchdog bindings to json-schema Date: Wed, 18 Sep 2019 19:31:38 +0200 Message-Id: <20190918173141.4314-5-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190918173141.4314-1-krzk@kernel.org> References: <20190918173141.4314-1-krzk@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190918_103238_717065_F5ABA075 X-CRM114-Status: GOOD ( 14.32 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Krzysztof Kozlowski MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Convert Samsung S3C/S5P/Exynos watchdog bindings to DT schema format using json-schema. Signed-off-by: Krzysztof Kozlowski --- Changes since v1: 1. Indent example with four spaces (more readable), 2. Remove unneeded timeout-sec description. --- .../bindings/watchdog/samsung-wdt.txt | 35 ---------- .../bindings/watchdog/samsung-wdt.yaml | 67 +++++++++++++++++++ 2 files changed, 67 insertions(+), 35 deletions(-) delete mode 100644 Documentation/devicetree/bindings/watchdog/samsung-wdt.txt create mode 100644 Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt b/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt deleted file mode 100644 index 46dcb48e75b4..000000000000 --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt +++ /dev/null @@ -1,35 +0,0 @@ -* Samsung's Watchdog Timer Controller - -The Samsung's Watchdog controller is used for resuming system operation -after a preset amount of time during which the WDT reset event has not -occurred. - -Required properties: -- compatible : should be one among the following - - "samsung,s3c2410-wdt" for S3C2410 - - "samsung,s3c6410-wdt" for S3C6410, S5PV210 and Exynos4 - - "samsung,exynos5250-wdt" for Exynos5250 - - "samsung,exynos5420-wdt" for Exynos5420 - - "samsung,exynos7-wdt" for Exynos7 - -- reg : base physical address of the controller and length of memory mapped - region. -- interrupts : interrupt number to the cpu. -- samsung,syscon-phandle : reference to syscon node (This property required only - in case of compatible being "samsung,exynos5250-wdt" or "samsung,exynos5420-wdt". - In case of Exynos5250 and 5420 this property points to syscon node holding the PMU - base address) - -Optional properties: -- timeout-sec : contains the watchdog timeout in seconds. - -Example: - -watchdog@101d0000 { - compatible = "samsung,exynos5250-wdt"; - reg = <0x101D0000 0x100>; - interrupts = <0 42 0>; - clocks = <&clock 336>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_syscon>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml new file mode 100644 index 000000000000..3ea3c9fe8390 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/samsung-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC Watchdog Timer Controller + +maintainers: + - Krzysztof Kozlowski + +description: |+ + The Samsung's Watchdog controller is used for resuming system operation + after a preset amount of time during which the WDT reset event has not + occurred. + +properties: + compatible: + enum: + - samsung,s3c2410-wdt # for S3C2410 + - samsung,s3c6410-wdt # for S3C6410, S5PV210 and Exynos4 + - samsung,exynos5250-wdt # for Exynos5250 + - samsung,exynos5420-wdt # for Exynos5420 + - samsung,exynos7-wdt # for Exynos7 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + samsung,syscon-phandle: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the PMU system controller node (in case of Exynos5250 + and Exynos5420). + + timeout-sec: + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - interrupts + - reg + +allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos5250-wdt + - samsung,exynos5420-wdt + then: + required: + - samsung,syscon-phandle + +examples: + - | + watchdog@101d0000 { + compatible = "samsung,exynos5250-wdt"; + reg = <0x101D0000 0x100>; + interrupts = <0 42 0>; + clocks = <&clock 336>; + clock-names = "watchdog"; + samsung,syscon-phandle = <&pmu_syscon>; + }; From patchwork Wed Sep 18 17:31:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 11151011 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 06D00912 for ; Wed, 18 Sep 2019 17:35:01 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D85E7208C0 for ; Wed, 18 Sep 2019 17:35:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="MFhHIIJr"; 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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iAdqz-0007Jb-TX; Wed, 18 Sep 2019 17:34:57 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iAdoq-00055w-US; Wed, 18 Sep 2019 17:32:46 +0000 Received: from localhost.localdomain (unknown [194.230.155.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 7847C208C0; Wed, 18 Sep 2019 17:32:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1568827964; bh=842m/JSo8zkhqWTjvGIQQMCBzFCNxClDHEXRC5hvQrU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=imfD8ZeFL3JfbWKLBOl0g4IXKqnOv8ebaSBXNzLB3QMI1t3nujlYdNlQj2AOElGSK 0sGzh2M1gdLRgj3EtYl3FCRICCDfqgMC9IAmAXXD6Y8ZDjz66yLkYxctPPVkSNPwwe djNwKk2ojpcu/k/biiusrFHlZ5VLQm3LpFj3nQDI= From: Krzysztof Kozlowski To: Rob Herring , Mark Rutland , Thierry Reding , Matt Mackall , Herbert Xu , Wim Van Sebroeck , Guenter Roeck , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-leds@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-crypto@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH v2 6/8] dt-bindings: watchdog: Add missing clocks requirement in Samsung SoC watchdog Date: Wed, 18 Sep 2019 19:31:39 +0200 Message-Id: <20190918173141.4314-6-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190918173141.4314-1-krzk@kernel.org> References: <20190918173141.4314-1-krzk@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190918_103245_119420_65AEF265 X-CRM114-Status: UNSURE ( 9.88 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Krzysztof Kozlowski MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org The Samsung SoC watchdog driver always required providing a clock (either through platform data or from DT). However when bindings were added in commit 9487a9cc7140 ("watchdog: s3c2410: Add support for device tree based probe"), they missed the requirement of clock. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- Changes since v1: 1. Indent example with four spaces (more readable), 2. Add also missing required entries for clocks. --- .../devicetree/bindings/watchdog/samsung-wdt.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml index 3ea3c9fe8390..311f9dc83fdb 100644 --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml @@ -26,6 +26,13 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 1 + + clock-names: + items: + - const: watchdog + interrupts: maxItems: 1 @@ -40,6 +47,8 @@ properties: required: - compatible + - clocks + - clock-names - interrupts - reg From patchwork Wed Sep 18 17:31:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 11151021 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0B6981747 for ; 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Wed, 18 Sep 2019 17:32:55 +0000 Received: from localhost.localdomain (unknown [194.230.155.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2B0F221920; Wed, 18 Sep 2019 17:32:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1568827970; bh=bzdMlVuxcLV0UyKPiNchuzEiaOKNsJB+A7E9U0LDlpE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=W0yowP3KQjRQm4ccyQnIKqPZwDMosmKn0kWAAfCaNzU4mMgfVj/oSvaAeRvJBplo6 7lUp0Ru9ew9P26KpbZCy5IW15/69X0HR7uZsOBZ2TJQJOf2GKPvFICxvF4J+FOnVFd DOexEOWa3Q0gLWIrIzSZTySWMLhDAo4Siok7PnVo= From: Krzysztof Kozlowski To: Rob Herring , Mark Rutland , Thierry Reding , Matt Mackall , Herbert Xu , Wim Van Sebroeck , Guenter Roeck , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-leds@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-crypto@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH v2 7/8] dt-bindings: pwm: Convert PWM bindings to json-schema Date: Wed, 18 Sep 2019 19:31:40 +0200 Message-Id: <20190918173141.4314-7-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190918173141.4314-1-krzk@kernel.org> References: <20190918173141.4314-1-krzk@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190918_103251_623580_C3A9118A X-CRM114-Status: GOOD ( 18.18 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Krzysztof Kozlowski MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Convert generic PWM bindings to DT schema format using json-schema. The consumer bindings are split to separate file. Signed-off-by: Krzysztof Kozlowski --- Changes since v1: 1. Indent example with four spaces (more readable), 2. Change pattern for pwm nodes, 3. Remove $ref from #cells. --- .../devicetree/bindings/clock/pwm-clock.txt | 2 +- .../bindings/display/bridge/ti,sn65dsi86.txt | 2 +- .../devicetree/bindings/display/ssd1307fb.txt | 2 +- .../bindings/leds/backlight/pwm-backlight.txt | 2 +- .../devicetree/bindings/leds/leds-pwm.txt | 2 +- .../devicetree/bindings/mfd/max77693.txt | 2 +- .../bindings/pwm/atmel-hlcdc-pwm.txt | 2 +- .../devicetree/bindings/pwm/atmel-pwm.txt | 2 +- .../devicetree/bindings/pwm/atmel-tcb-pwm.txt | 2 +- .../bindings/pwm/brcm,bcm7038-pwm.txt | 2 +- .../bindings/pwm/brcm,iproc-pwm.txt | 2 +- .../devicetree/bindings/pwm/brcm,kona-pwm.txt | 2 +- .../devicetree/bindings/pwm/img-pwm.txt | 2 +- .../devicetree/bindings/pwm/imx-pwm.txt | 2 +- .../devicetree/bindings/pwm/imx-tpm-pwm.txt | 2 +- .../bindings/pwm/lpc1850-sct-pwm.txt | 2 +- .../devicetree/bindings/pwm/mxs-pwm.txt | 2 +- .../bindings/pwm/nvidia,tegra20-pwm.txt | 2 +- .../bindings/pwm/nxp,pca9685-pwm.txt | 2 +- .../devicetree/bindings/pwm/pwm-bcm2835.txt | 2 +- .../devicetree/bindings/pwm/pwm-berlin.txt | 2 +- .../bindings/pwm/pwm-consumers.yaml | 76 +++++++++++++++++++ .../devicetree/bindings/pwm/pwm-fsl-ftm.txt | 2 +- .../devicetree/bindings/pwm/pwm-hibvt.txt | 2 +- .../devicetree/bindings/pwm/pwm-lp3943.txt | 2 +- .../devicetree/bindings/pwm/pwm-mediatek.txt | 2 +- .../devicetree/bindings/pwm/pwm-meson.txt | 2 +- .../devicetree/bindings/pwm/pwm-mtk-disp.txt | 2 +- .../bindings/pwm/pwm-omap-dmtimer.txt | 2 +- .../devicetree/bindings/pwm/pwm-rockchip.txt | 2 +- .../devicetree/bindings/pwm/pwm-sifive.txt | 2 +- .../devicetree/bindings/pwm/pwm-stm32-lp.txt | 2 +- .../devicetree/bindings/pwm/pwm-stm32.txt | 2 +- .../devicetree/bindings/pwm/pwm-tiecap.txt | 2 +- .../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 2 +- .../devicetree/bindings/pwm/pwm-zx.txt | 2 +- Documentation/devicetree/bindings/pwm/pwm.txt | 69 ----------------- .../devicetree/bindings/pwm/pwm.yaml | 29 +++++++ .../bindings/pwm/renesas,pwm-rcar.txt | 2 +- .../bindings/pwm/renesas,tpu-pwm.txt | 4 +- .../devicetree/bindings/pwm/spear-pwm.txt | 2 +- .../devicetree/bindings/pwm/st,stmpe-pwm.txt | 2 +- .../devicetree/bindings/pwm/ti,twl-pwm.txt | 2 +- .../devicetree/bindings/pwm/ti,twl-pwmled.txt | 2 +- .../devicetree/bindings/pwm/vt8500-pwm.txt | 2 +- .../bindings/regulator/pwm-regulator.txt | 2 +- .../devicetree/bindings/timer/ingenic,tcu.txt | 2 +- 47 files changed, 150 insertions(+), 114 deletions(-) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-consumers.yaml delete mode 100644 Documentation/devicetree/bindings/pwm/pwm.txt create mode 100644 Documentation/devicetree/bindings/pwm/pwm.yaml diff --git a/Documentation/devicetree/bindings/clock/pwm-clock.txt b/Documentation/devicetree/bindings/clock/pwm-clock.txt index 83db876b3b90..8a791b6d76a9 100644 --- a/Documentation/devicetree/bindings/clock/pwm-clock.txt +++ b/Documentation/devicetree/bindings/clock/pwm-clock.txt @@ -3,7 +3,7 @@ Binding for an external clock signal driven by a PWM pin. This binding uses the common clock binding[1] and the common PWM binding[2]. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/pwm/pwm.txt +[2] Documentation/devicetree/bindings/pwm/pwm-consumers.yaml Required properties: - compatible : shall be "pwm-clock". diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt index 0a3fbb53a16e..8ec4a7f2623a 100644 --- a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt @@ -21,7 +21,7 @@ Optional properties: - #gpio-cells : Should be two. The first cell is the pin number and the second cell is used to specify flags. See ../../gpio/gpio.txt for more information. -- #pwm-cells : Should be one. See ../../pwm/pwm.txt for description of +- #pwm-cells : Should be one. See ../../pwm/pwm.yaml for description of the cell formats. - clock-names: should be "refclk" diff --git a/Documentation/devicetree/bindings/display/ssd1307fb.txt b/Documentation/devicetree/bindings/display/ssd1307fb.txt index 27333b9551b3..da9b28153a3c 100644 --- a/Documentation/devicetree/bindings/display/ssd1307fb.txt +++ b/Documentation/devicetree/bindings/display/ssd1307fb.txt @@ -37,7 +37,7 @@ Optional properties: - solomon,area-color-enable: Display uses color mode - solomon,low-power. Display runs in low power mode -[0]: Documentation/devicetree/bindings/pwm/pwm.txt +[0]: Documentation/devicetree/bindings/pwm/pwm-consumers.yaml Examples: ssd1307: oled@3c { diff --git a/Documentation/devicetree/bindings/leds/backlight/pwm-backlight.txt b/Documentation/devicetree/bindings/leds/backlight/pwm-backlight.txt index 64fa2fbd98c9..8dbbadd3af96 100644 --- a/Documentation/devicetree/bindings/leds/backlight/pwm-backlight.txt +++ b/Documentation/devicetree/bindings/leds/backlight/pwm-backlight.txt @@ -28,7 +28,7 @@ Optional properties: having to list out every possible value in the brightness-level array. -[0]: Documentation/devicetree/bindings/pwm/pwm.txt +[0]: Documentation/devicetree/bindings/pwm/pwm-consumers.yaml [1]: Documentation/devicetree/bindings/gpio/gpio.txt Example: diff --git a/Documentation/devicetree/bindings/leds/leds-pwm.txt b/Documentation/devicetree/bindings/leds/leds-pwm.txt index 6c6583c35f2f..aeaa250668d5 100644 --- a/Documentation/devicetree/bindings/leds/leds-pwm.txt +++ b/Documentation/devicetree/bindings/leds/leds-pwm.txt @@ -11,7 +11,7 @@ LED sub-node properties: specify the period time to be used: <&phandle id period_ns>; - pwm-names : (optional) Name to be used by the PWM subsystem for the PWM device For the pwms and pwm-names property please refer to: - Documentation/devicetree/bindings/pwm/pwm.txt + Documentation/devicetree/bindings/pwm/pwm-consumers.yaml - max-brightness : Maximum brightness possible for the LED - active-low : (optional) For PWMs where the LED is wired to supply rather than ground. diff --git a/Documentation/devicetree/bindings/mfd/max77693.txt b/Documentation/devicetree/bindings/mfd/max77693.txt index a3c60a7a3be1..1e6318695eb2 100644 --- a/Documentation/devicetree/bindings/mfd/max77693.txt +++ b/Documentation/devicetree/bindings/mfd/max77693.txt @@ -38,7 +38,7 @@ Optional properties: PWM properties should be named "pwms". And number of cell is different for each pwm device. To get more information, please refer to documentation. - [*] refer Documentation/devicetree/bindings/pwm/pwm.txt + [*] refer Documentation/devicetree/bindings/pwm/pwm-consumers.yaml - charger : Node configuring the charger driver. If present, required properties: diff --git a/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt index cfda0d57d302..afa501bf7f94 100644 --- a/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt @@ -10,7 +10,7 @@ Required properties: - pinctrl-0: should contain the pinctrl states described by pinctrl default. - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells - bindings defined in pwm.txt in this directory. + bindings defined in pwm.yaml in this directory. Example: diff --git a/Documentation/devicetree/bindings/pwm/atmel-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-pwm.txt index 591ecdd39c7b..fbb5325be1f0 100644 --- a/Documentation/devicetree/bindings/pwm/atmel-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/atmel-pwm.txt @@ -7,7 +7,7 @@ Required properties: - "atmel,sama5d2-pwm" - "microchip,sam9x60-pwm" - reg: physical base address and length of the controller's registers - - #pwm-cells: Should be 3. See pwm.txt in this directory for a + - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of the cells format. Example: diff --git a/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt index 8031148bcf85..985fcc65f8c4 100644 --- a/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt @@ -2,7 +2,7 @@ Atmel TCB PWM controller Required properties: - compatible: should be "atmel,tcb-pwm" -- #pwm-cells: should be 3. See pwm.txt in this directory for a description of +- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of the cells format. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. - tc-block: The Timer Counter block to use as a PWM chip. diff --git a/Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.txt b/Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.txt index d9254a6da5ed..0e662d7f6bd1 100644 --- a/Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.txt @@ -4,7 +4,7 @@ Required properties: - compatible: must be "brcm,bcm7038-pwm" - reg: physical base address and length for this controller -- #pwm-cells: should be 2. See pwm.txt in this directory for a description +- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of the cells format - clocks: a phandle to the reference clock for this block which is fed through its internal variable clock frequency generator diff --git a/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.txt b/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.txt index 21f75bbd6dae..655f6cd4ef46 100644 --- a/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.txt @@ -6,7 +6,7 @@ Required Properties : - compatible: must be "brcm,iproc-pwm" - reg: physical base address and length of the controller's registers - clocks: phandle + clock specifier pair for the external clock -- #pwm-cells: Should be 3. See pwm.txt in this directory for a +- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of the cells format. Refer to clocks/clock-bindings.txt for generic clock consumer properties. diff --git a/Documentation/devicetree/bindings/pwm/brcm,kona-pwm.txt b/Documentation/devicetree/bindings/pwm/brcm,kona-pwm.txt index 8eae9fe7841c..c42eecfc81ed 100644 --- a/Documentation/devicetree/bindings/pwm/brcm,kona-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/brcm,kona-pwm.txt @@ -6,7 +6,7 @@ Required Properties : - compatible: should contain "brcm,kona-pwm" - reg: physical base address and length of the controller's registers - clocks: phandle + clock specifier pair for the external clock -- #pwm-cells: Should be 3. See pwm.txt in this directory for a +- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of the cells format. Refer to clocks/clock-bindings.txt for generic clock consumer properties. diff --git a/Documentation/devicetree/bindings/pwm/img-pwm.txt b/Documentation/devicetree/bindings/pwm/img-pwm.txt index fade5f26fcac..9db6de97317d 100644 --- a/Documentation/devicetree/bindings/pwm/img-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/img-pwm.txt @@ -8,7 +8,7 @@ Required properties: - clock-names: Must include the following entries. - pwm: PWM operating clock. - sys: PWM system interface clock. - - #pwm-cells: Should be 2. See pwm.txt in this directory for the + - #pwm-cells: Should be 2. See pwm.yaml in this directory for the description of the cells format. - img,cr-periph: Must contain a phandle to the peripheral control syscon node which contains PWM control registers. diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt index c61bdf8cd41b..22f1c3d8b773 100644 --- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/imx-pwm.txt @@ -6,7 +6,7 @@ Required properties: - "fsl,imx1-pwm" for PWM compatible with the one integrated on i.MX1 - "fsl,imx27-pwm" for PWM compatible with the one integrated on i.MX27 - reg: physical base address and length of the controller's registers -- #pwm-cells: 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.txt +- #pwm-cells: 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.yaml in this directory for a description of the cells format. - clocks : Clock specifiers for both ipg and per clocks. - clock-names : Clock names should include both "ipg" and "per" diff --git a/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt index 3ba958d764ff..5bf20950a24e 100644 --- a/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt @@ -3,7 +3,7 @@ Freescale i.MX TPM PWM controller Required properties: - compatible : Should be "fsl,imx7ulp-pwm". - reg: Physical base address and length of the controller's registers. -- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of the cells format. +- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of the cells format. - clocks : The clock provided by the SoC to drive the PWM. - interrupts: The interrupt for the PWM controller. diff --git a/Documentation/devicetree/bindings/pwm/lpc1850-sct-pwm.txt b/Documentation/devicetree/bindings/pwm/lpc1850-sct-pwm.txt index 36e49d4325cd..43d9f4f08a2e 100644 --- a/Documentation/devicetree/bindings/pwm/lpc1850-sct-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/lpc1850-sct-pwm.txt @@ -7,7 +7,7 @@ Required properties: See ../clock/clock-bindings.txt for details. - clock-names: Must include the following entries. - pwm: PWM operating clock. - - #pwm-cells: Should be 3. See pwm.txt in this directory for the description + - #pwm-cells: Should be 3. See pwm.yaml in this directory for the description of the cells format. Example: diff --git a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt index 96cdde5f6208..1b06f86a7091 100644 --- a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt @@ -3,7 +3,7 @@ Freescale MXS PWM controller Required properties: - compatible: should be "fsl,imx23-pwm" - reg: physical base address and length of the controller's registers -- #pwm-cells: should be 2. See pwm.txt in this directory for a description of +- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of the cells format. - fsl,pwm-number: the number of PWM devices diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt index c57e11b8d937..0a69eadf44ce 100644 --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt @@ -10,7 +10,7 @@ Required properties: - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210 - "nvidia,tegra186-pwm": for Tegra186 - reg: physical base address and length of the controller's registers -- #pwm-cells: should be 2. See pwm.txt in this directory for a description of +- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of the cells format. - clocks: Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. diff --git a/Documentation/devicetree/bindings/pwm/nxp,pca9685-pwm.txt b/Documentation/devicetree/bindings/pwm/nxp,pca9685-pwm.txt index f84ec9d291ea..f21b55c95738 100644 --- a/Documentation/devicetree/bindings/pwm/nxp,pca9685-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/nxp,pca9685-pwm.txt @@ -3,7 +3,7 @@ NXP PCA9685 16-channel 12-bit PWM LED controller Required properties: - compatible: "nxp,pca9685-pwm" - - #pwm-cells: Should be 2. See pwm.txt in this directory for a description of + - #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of the cells format. The index 16 is the ALLCALL channel, that sets all PWM channels at the same time. diff --git a/Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt b/Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt index 8cf87d1bfca5..f5753b3f79df 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt @@ -6,7 +6,7 @@ Required properties: - clocks: This clock defines the base clock frequency of the PWM hardware system, the period and the duty_cycle of the PWM signal is a multiple of the base period. -- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of +- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of the cells format. Examples: diff --git a/Documentation/devicetree/bindings/pwm/pwm-berlin.txt b/Documentation/devicetree/bindings/pwm/pwm-berlin.txt index 82cbe16fcbbc..f01e993a498a 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-berlin.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-berlin.txt @@ -4,7 +4,7 @@ Required properties: - compatible: should be "marvell,berlin-pwm" - reg: physical base address and length of the controller's registers - clocks: phandle to the input clock -- #pwm-cells: should be 3. See pwm.txt in this directory for a description of +- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of the cells format. Example: diff --git a/Documentation/devicetree/bindings/pwm/pwm-consumers.yaml b/Documentation/devicetree/bindings/pwm/pwm-consumers.yaml new file mode 100644 index 000000000000..39c844fe6338 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-consumers.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/pwm-consumers.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Specifying PWM information for devices + +maintainers: + - Thierry Reding + +description: | + PWM properties should be named "pwms". The exact meaning of each pwms + property must be documented in the device tree binding for each device. + An optional property "pwm-names" may contain a list of strings to label + each of the PWM devices listed in the "pwms" property. If no "pwm-names" + property is given, the name of the user node will be used as fallback. + + Drivers for devices that use more than a single PWM device can use the + "pwm-names" property to map the name of the PWM device requested by the + pwm_get() call to an index into the list given by the "pwms" property. + +properties: + pwms: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + Phandle to PWM controller node and pwm-specifier (controller specific). + pwm-specifier typically encodes the chip-relative PWM number and the PWM + period in nanoseconds. + Optionally, the pwm-specifier can encode a number of flags (defined in + ) in a third cell: + - PWM_POLARITY_INVERTED: invert the PWM signal polarity + + pwm-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: + A list of strings to label each of the PWM devices listed in the "pwms" + property. If no "pwm-names" property is given, the name of the user node + will be used as fallback. + +required: + - pwms + +dependencies: + pwm-names: [ pwms ] + +examples: + - | + // The following example could be used to describe a PWM-based + // backlight device: + + pwm: pwm { + #pwm-cells = <2>; + }; + + bl: backlight { + pwms = <&pwm 0 5000000>; + pwm-names = "backlight"; + }; + + // Note that in the example above, specifying the "pwm-names" is redundant + // because the name "backlight" would be used as fallback anyway. + + - | + // Example with optional PWM specifier for inverse polarity + + #include + + pwm2: pwm { + #pwm-cells = <3>; + }; + + backlight { + pwms = <&pwm2 0 5000000 PWM_POLARITY_INVERTED>; + pwm-names = "backlight"; + }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt index 576ad002bc83..36532cd5ab25 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt @@ -21,7 +21,7 @@ Required properties: - "fsl,vf610-ftm-pwm" for PWM compatible with the one integrated on VF610 - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM - reg: Physical base address and length of the controller's registers -- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of +- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of the cells format. - clock-names: Should include the following module clock source entries: "ftm_sys" (module clock, also can be used as counter clock), diff --git a/Documentation/devicetree/bindings/pwm/pwm-hibvt.txt b/Documentation/devicetree/bindings/pwm/pwm-hibvt.txt index daedfef09bb6..54dbc2a0e648 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-hibvt.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-hibvt.txt @@ -10,7 +10,7 @@ Required properties: - reg: physical base address and length of the controller's registers. - clocks: phandle and clock specifier of the PWM reference clock. - resets: phandle and reset specifier for the PWM controller reset. -- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of +- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of the cells format. Example: diff --git a/Documentation/devicetree/bindings/pwm/pwm-lp3943.txt b/Documentation/devicetree/bindings/pwm/pwm-lp3943.txt index 7bd9d3b12ce1..f214305a8f5e 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-lp3943.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-lp3943.txt @@ -2,7 +2,7 @@ TI/National Semiconductor LP3943 PWM controller Required properties: - compatible: "ti,lp3943-pwm" - - #pwm-cells: Should be 2. See pwm.txt in this directory for a + - #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of the cells format. Note that this hardware limits the period length to the range 6250~1600000. diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt index 991728cb46cb..8caf01d0dd5e 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt @@ -7,7 +7,7 @@ Required properties: - "mediatek,mt7623-pwm": found on mt7623 SoC. - "mediatek,mt7628-pwm": found on mt7628 SoC. - reg: physical base address and length of the controller's registers. - - #pwm-cells: must be 2. See pwm.txt in this directory for a description of + - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of the cell format. - clocks: phandle and clock specifier of the PWM reference clock. - clock-names: must contain the following, except for MT7628 which diff --git a/Documentation/devicetree/bindings/pwm/pwm-meson.txt b/Documentation/devicetree/bindings/pwm/pwm-meson.txt index 891632354065..bd02b0a1496f 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-meson.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-meson.txt @@ -10,7 +10,7 @@ Required properties: or "amlogic,meson-g12a-ee-pwm" or "amlogic,meson-g12a-ao-pwm-ab" or "amlogic,meson-g12a-ao-pwm-cd" -- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of +- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of the cells format. Optional properties: diff --git a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt index 6f8af2bcc7b7..0521957c253f 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt @@ -6,7 +6,7 @@ Required properties: - "mediatek,mt6595-disp-pwm": found on mt6595 SoC. - "mediatek,mt8173-disp-pwm": found on mt8173 SoC. - reg: physical base address and length of the controller's registers. - - #pwm-cells: must be 2. See pwm.txt in this directory for a description of + - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of the cell format. - clocks: phandle and clock specifier of the PWM reference clock. - clock-names: must contain the following: diff --git a/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt b/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt index 5ccfcc82da08..d722ae3be363 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt @@ -4,7 +4,7 @@ Required properties: - compatible: Shall contain "ti,omap-dmtimer-pwm". - ti,timers: phandle to PWM capable OMAP timer. See timer/ti,timer.txt for info about these timers. -- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of +- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of the cells format. Optional properties: diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt index 2c5e52a5bede..f70956dea77b 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt @@ -14,7 +14,7 @@ Required properties: - For newer hardware (rk3328 and future socs): specified by name - "pwm": This is used to derive the functional clock. - "pclk": This is the APB bus clock. - - #pwm-cells: must be 2 (rk2928) or 3 (rk3288). See pwm.txt in this directory + - #pwm-cells: must be 2 (rk2928) or 3 (rk3288). See pwm.yaml in this directory for a description of the cell format. Example: diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt index 36447e3c9378..3d1dd7b06efc 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt @@ -17,7 +17,7 @@ Required properties: Please refer to sifive-blocks-ip-versioning.txt for details. - reg: physical base address and length of the controller's registers - clocks: Should contain a clock identifier for the PWM's parent clock. -- #pwm-cells: Should be 3. See pwm.txt in this directory +- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of the cell format. - interrupts: one interrupt per PWM channel diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt index 6521bc44a74e..4cecb8e456b6 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt @@ -8,7 +8,7 @@ See ../mfd/stm32-lptimer.txt for details about the parent node. Required parameters: - compatible: Must be "st,stm32-pwm-lp". - #pwm-cells: Should be set to 3. This PWM chip uses the default 3 cells - bindings defined in pwm.txt. + bindings defined in pwm.yaml. Optional properties: - pinctrl-names: Set to "default". An additional "sleep" state can be diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt index a8690bfa5e1f..f390a5ba3d3a 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt @@ -9,7 +9,7 @@ Required parameters: - pinctrl-0: List of phandles pointing to pin configuration nodes for PWM module. For Pinctrl properties see ../pinctrl/pinctrl-bindings.txt - #pwm-cells: Should be set to 3. This PWM chip uses the default 3 cells - bindings defined in pwm.txt. + bindings defined in pwm.yaml. Optional parameters: - st,breakinput: One or two to describe break input configurations. diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt index b9a1d7402128..c7c4347a769a 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt @@ -8,7 +8,7 @@ Required properties: for dra746 - compatible = "ti,dra746-ecap", "ti,am3352-ecap"; for 66ak2g - compatible = "ti,k2g-ecap", "ti,am3352-ecap"; for am654 - compatible = "ti,am654-ecap", "ti,am3352-ecap"; -- #pwm-cells: should be 3. See pwm.txt in this directory for a description of +- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of the cells format. The PWM channel index ranges from 0 to 4. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. - reg: physical base address and size of the registers map. diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt index 31c4577157dd..c7e28f6d28be 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt @@ -7,7 +7,7 @@ Required properties: for am654 - compatible = "ti,am654-ehrpwm", "ti-am3352-ehrpwm"; for da850 - compatible = "ti,da850-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm"; for dra746 - compatible = "ti,dra746-ehrpwm", "ti-am3352-ehrpwm"; -- #pwm-cells: should be 3. See pwm.txt in this directory for a description of +- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of the cells format. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. - reg: physical base address and size of the registers map. diff --git a/Documentation/devicetree/bindings/pwm/pwm-zx.txt b/Documentation/devicetree/bindings/pwm/pwm-zx.txt index a6bcc75c9164..3c8fe7aa8269 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-zx.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-zx.txt @@ -7,7 +7,7 @@ Required properties: - clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller. The PCLK is for register access, while WCLK is the reference clock for calculating period and duty cycles. - - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of + - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of the cells format. Example: diff --git a/Documentation/devicetree/bindings/pwm/pwm.txt b/Documentation/devicetree/bindings/pwm/pwm.txt deleted file mode 100644 index 8556263b8502..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm.txt +++ /dev/null @@ -1,69 +0,0 @@ -Specifying PWM information for devices -====================================== - -1) PWM user nodes ------------------ - -PWM users should specify a list of PWM devices that they want to use -with a property containing a 'pwm-list': - - pwm-list ::= [pwm-list] - single-pwm ::= - pwm-phandle : phandle to PWM controller node - pwm-specifier : array of #pwm-cells specifying the given PWM - (controller specific) - -PWM properties should be named "pwms". The exact meaning of each pwms -property must be documented in the device tree binding for each device. -An optional property "pwm-names" may contain a list of strings to label -each of the PWM devices listed in the "pwms" property. If no "pwm-names" -property is given, the name of the user node will be used as fallback. - -Drivers for devices that use more than a single PWM device can use the -"pwm-names" property to map the name of the PWM device requested by the -pwm_get() call to an index into the list given by the "pwms" property. - -The following example could be used to describe a PWM-based backlight -device: - - pwm: pwm { - #pwm-cells = <2>; - }; - - [...] - - bl: backlight { - pwms = <&pwm 0 5000000>; - pwm-names = "backlight"; - }; - -Note that in the example above, specifying the "pwm-names" is redundant -because the name "backlight" would be used as fallback anyway. - -pwm-specifier typically encodes the chip-relative PWM number and the PWM -period in nanoseconds. - -Optionally, the pwm-specifier can encode a number of flags (defined in -) in a third cell: -- PWM_POLARITY_INVERTED: invert the PWM signal polarity - -Example with optional PWM specifier for inverse polarity - - bl: backlight { - pwms = <&pwm 0 5000000 PWM_POLARITY_INVERTED>; - pwm-names = "backlight"; - }; - -2) PWM controller nodes ------------------------ - -PWM controller nodes must specify the number of cells used for the -specifier using the '#pwm-cells' property. - -An example PWM controller might look like this: - - pwm: pwm@7000a000 { - compatible = "nvidia,tegra20-pwm"; - reg = <0x7000a000 0x100>; - #pwm-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/pwm/pwm.yaml b/Documentation/devicetree/bindings/pwm/pwm.yaml new file mode 100644 index 000000000000..aad99d505bb0 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PWM controllers (providers) + +maintainers: + - Thierry Reding + +properties: + $nodename: + pattern: "^pwm(@.*|-[0-9a-f])*$" + + "#pwm-cells": + description: + Number of cells in a PWM specifier. + +required: + - "#pwm-cells" + +examples: + - | + pwm: pwm@7000a000 { + compatible = "nvidia,tegra20-pwm"; + reg = <0x7000a000 0x100>; + #pwm-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt index fbd6a4f943ce..a29137869f7a 100644 --- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt +++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt @@ -20,7 +20,7 @@ Required Properties: - "renesas,pwm-r8a77990": for R-Car E3 - "renesas,pwm-r8a77995": for R-Car D3 - reg: base address and length of the registers block for the PWM. -- #pwm-cells: should be 2. See pwm.txt in this directory for a description of +- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of the cells format. - clocks: clock phandle and specifier pair. - pinctrl-0: phandle, referring to a default pin configuration node. diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt index 848a92b53d81..966994968069 100644 --- a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt @@ -19,11 +19,11 @@ Required Properties: - reg: Base address and length of each memory resource used by the PWM controller hardware module. - - #pwm-cells: should be 3. See pwm.txt in this directory for a description of + - #pwm-cells: should be 3. See pwm.yaml in this directory for a description of the cells format. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. -Please refer to pwm.txt in this directory for details of the common PWM bindings +Please refer to pwm-consumers.yaml in this directory for details of the common PWM bindings used by client devices. Example: R8A7740 (R-Mobile A1) TPU controller node diff --git a/Documentation/devicetree/bindings/pwm/spear-pwm.txt b/Documentation/devicetree/bindings/pwm/spear-pwm.txt index b486de2c3fe3..95894128b62f 100644 --- a/Documentation/devicetree/bindings/pwm/spear-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/spear-pwm.txt @@ -5,7 +5,7 @@ Required properties: - "st,spear320-pwm" - "st,spear1340-pwm" - reg: physical base address and length of the controller's registers -- #pwm-cells: should be 2. See pwm.txt in this directory for a description of +- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of the cells format. Example: diff --git a/Documentation/devicetree/bindings/pwm/st,stmpe-pwm.txt b/Documentation/devicetree/bindings/pwm/st,stmpe-pwm.txt index cb209646bf13..f401316e0248 100644 --- a/Documentation/devicetree/bindings/pwm/st,stmpe-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/st,stmpe-pwm.txt @@ -7,7 +7,7 @@ subdevices of the STMPE MFD device. Required properties: - compatible: should be: - "st,stmpe-pwm" -- #pwm-cells: should be 2. See pwm.txt in this directory for a description of +- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of the cells format. Example: diff --git a/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt b/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt index 4e32bee11201..d97ca1964e94 100644 --- a/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt @@ -6,7 +6,7 @@ On TWL6030 series: PWM0 and PWM1 Required properties: - compatible: "ti,twl4030-pwm" or "ti,twl6030-pwm" -- #pwm-cells: should be 2. See pwm.txt in this directory for a description of +- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of the cells format. Example: diff --git a/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt b/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt index 9f4b46090782..31ca1b032ef0 100644 --- a/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt +++ b/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt @@ -6,7 +6,7 @@ On TWL6030 series: LED PWM (mainly used as charging indicator LED) Required properties: - compatible: "ti,twl4030-pwmled" or "ti,twl6030-pwmled" -- #pwm-cells: should be 2. See pwm.txt in this directory for a description of +- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of the cells format. Example: diff --git a/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt b/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt index a76390e6df2e..4fba93ce1985 100644 --- a/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt @@ -3,7 +3,7 @@ VIA/Wondermedia VT8500/WM8xxx series SoC PWM controller Required properties: - compatible: should be "via,vt8500-pwm" - reg: physical base address and length of the controller's registers -- #pwm-cells: should be 3. See pwm.txt in this directory for a description of +- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of the cells format. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. - clocks: phandle to the PWM source clock diff --git a/Documentation/devicetree/bindings/regulator/pwm-regulator.txt b/Documentation/devicetree/bindings/regulator/pwm-regulator.txt index 3d78d507e29f..252edcc2e381 100644 --- a/Documentation/devicetree/bindings/regulator/pwm-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/pwm-regulator.txt @@ -27,7 +27,7 @@ Required properties: -------------------- - compatible: Should be "pwm-regulator" -- pwms: PWM specification (See: ../pwm/pwm.txt) +- pwms: PWM specification (See: ../pwm/pwm-consumers.yaml) Only required for Voltage Table Mode: - voltage-table: Voltage and Duty-Cycle table consisting of 2 cells diff --git a/Documentation/devicetree/bindings/timer/ingenic,tcu.txt b/Documentation/devicetree/bindings/timer/ingenic,tcu.txt index 5a4b9ddd9470..0c7bd51c19eb 100644 --- a/Documentation/devicetree/bindings/timer/ingenic,tcu.txt +++ b/Documentation/devicetree/bindings/timer/ingenic,tcu.txt @@ -42,7 +42,7 @@ Required properties: - compatible: Must be one of: * ingenic,jz4740-pwm * ingenic,jz4725b-pwm -- #pwm-cells: Should be 3. See ../pwm/pwm.txt for a description of the cell +- #pwm-cells: Should be 3. See ../pwm/pwm.yaml for a description of the cell format. - clocks: List of phandle & clock specifiers for the TCU clocks. - clock-names: List of name strings for the TCU clocks. From patchwork Wed Sep 18 17:31:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 11151031 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6A4B4912 for ; Wed, 18 Sep 2019 17:36:06 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 45B1D20578 for ; Wed, 18 Sep 2019 17:36:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="tS/VVaJS"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="DvkvvauW" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 45B1D20578 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=MiCTK8JnK9YoXVi4mW/wfWs0XLrnAhmw7VMXX7RynBk=; b=tS/VVaJSV6CuFKxpOjhjf+H6eU Bdk2op7HtglVoEqUUq2MMcEt4Qz1R6aVsVmx2vY+83PfNABV0W+Q6Wxj3dKYsRkAGFFgpkOLIyGIu 0c2qTFRgjlPMZi7MR8nPJnnyM5o+hHCraHOXBmSKTw/7VODCaOCZfhupQDXFXdBxMLchmIUtlPrV8 BXiuNAc3J7WhNL4dzaHNRDM2GQDsKYPbXqAJdOrl+etvMO4MEogYqc4vbeWjxM1dyxqGwPty3m7aR OIjFZrENAXHmI+5yf5ffnNoTblrz30GWCQJCJbPaQ0nShzhB3zTF9lP2XyoNjL3W5fbNUk6SXVDof 6GDKSHUw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iAds3-00012a-NN; Wed, 18 Sep 2019 17:36:03 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iAdp3-0005HV-Ew; Wed, 18 Sep 2019 17:32:59 +0000 Received: from localhost.localdomain (unknown [194.230.155.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6F47621925; Wed, 18 Sep 2019 17:32:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1568827977; bh=NfJ9sRleyQQ5tZgP4QFSZEUinJ+3DSTjk/BekNqpBzg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DvkvvauWtTZxYAuzUUBqMADQXEYtupsymGMZ9i8bCRI0eD4uxwy9Mrekx+m7lo608 xXOoC18wwUbAVnB6tbyj6CivJ990xXRyTxbCl/ehV5A+YCwzqW6gWTAS6TYIk27B/m t5v6muzQDp89MsyDGgmfGZt6jDCemAvG/Z7pkoDA= From: Krzysztof Kozlowski To: Rob Herring , Mark Rutland , Thierry Reding , Matt Mackall , Herbert Xu , Wim Van Sebroeck , Guenter Roeck , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-leds@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-crypto@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH v2 8/8] dt-bindings: pwm: Convert Samsung PWM bindings to json-schema Date: Wed, 18 Sep 2019 19:31:41 +0200 Message-Id: <20190918173141.4314-8-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190918173141.4314-1-krzk@kernel.org> References: <20190918173141.4314-1-krzk@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190918_103257_787418_11573839 X-CRM114-Status: GOOD ( 14.44 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Krzysztof Kozlowski MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Convert Samsung PWM (S3C, S5P and Exynos SoCs) bindings to DT schema format using json-schema. Signed-off-by: Krzysztof Kozlowski --- Changes since v1: 1. Indent example with four spaces (more readable), 2. Fix samsung,pwm-outputs after review, 3. Remove double-quotes from clock names. --- .../devicetree/bindings/pwm/pwm-samsung.txt | 51 --------- .../devicetree/bindings/pwm/pwm-samsung.yaml | 107 ++++++++++++++++++ 2 files changed, 107 insertions(+), 51 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-samsung.txt create mode 100644 Documentation/devicetree/bindings/pwm/pwm-samsung.yaml diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt deleted file mode 100644 index 5538de9c2007..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt +++ /dev/null @@ -1,51 +0,0 @@ -* Samsung PWM timers - -Samsung SoCs contain PWM timer blocks which can be used for system clock source -and clock event timers, as well as to drive SoC outputs with PWM signal. Each -PWM timer block provides 5 PWM channels (not all of them can drive physical -outputs - see SoC and board manual). - -Be aware that the clocksource driver supports only uniprocessor systems. - -Required properties: -- compatible : should be one of following: - samsung,s3c2410-pwm - for 16-bit timers present on S3C24xx SoCs - samsung,s3c6400-pwm - for 32-bit timers present on S3C64xx SoCs - samsung,s5p6440-pwm - for 32-bit timers present on S5P64x0 SoCs - samsung,s5pc100-pwm - for 32-bit timers present on S5PC100, S5PV210, - Exynos4210 rev0 SoCs - samsung,exynos4210-pwm - for 32-bit timers present on Exynos4210, - Exynos4x12, Exynos5250 and Exynos5420 SoCs -- reg: base address and size of register area -- interrupts: list of timer interrupts (one interrupt per timer, starting at - timer 0) -- clock-names: should contain all following required clock names: - - "timers" - PWM base clock used to generate PWM signals, - and any subset of following optional clock names: - - "pwm-tclk0" - first external PWM clock source, - - "pwm-tclk1" - second external PWM clock source. - Note that not all IP variants allow using all external clock sources. - Refer to SoC documentation to learn which clock source configurations - are available. -- clocks: should contain clock specifiers of all clocks, which input names - have been specified in clock-names property, in same order. -- #pwm-cells: should be 3. See pwm.txt in this directory for a description of - the cells format. The only third cell flag supported by this binding is - PWM_POLARITY_INVERTED. - -Optional properties: -- samsung,pwm-outputs: list of PWM channels used as PWM outputs on particular - platform - an array of up to 5 elements being indices of PWM channels - (from 0 to 4), the order does not matter. - -Example: - pwm@7f006000 { - compatible = "samsung,s3c6400-pwm"; - reg = <0x7f006000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <23>, <24>, <25>, <27>, <28>; - clocks = <&clock 67>; - clock-names = "timers"; - samsung,pwm-outputs = <0>, <1>; - #pwm-cells = <3>; - } diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml new file mode 100644 index 000000000000..06d11faabff6 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC PWM timers + +maintainers: + - Thierry Reding + - Krzysztof Kozlowski + +description: |+ + Samsung SoCs contain PWM timer blocks which can be used for system clock source + and clock event timers, as well as to drive SoC outputs with PWM signal. Each + PWM timer block provides 5 PWM channels (not all of them can drive physical + outputs - see SoC and board manual). + + Be aware that the clocksource driver supports only uniprocessor systems. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - samsung,s3c2410-pwm # 16-bit, S3C24xx + - samsung,s3c6400-pwm # 32-bit, S3C64xx + - samsung,s5p6440-pwm # 32-bit, S5P64x0 + - samsung,s5pc100-pwm # 32-bit, S5PC100, S5PV210, Exynos4210 rev0 SoCs + - samsung,exynos4210-pwm # 32-bit, Exynos + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + description: | + Should contain all following required clock names: + - "timers" - PWM base clock used to generate PWM signals, + and any subset of following optional clock names: + - "pwm-tclk0" - first external PWM clock source, + - "pwm-tclk1" - second external PWM clock source. + Note that not all IP variants allow using all external clock sources. + Refer to SoC documentation to learn which clock source configurations + are available. + oneOf: + - items: + - const: timers + - items: + - const: timers + - const: pwm-tclk0 + - items: + - const: timers + - const: pwm-tclk1 + - items: + - const: timers + - const: pwm-tclk0 + - const: pwm-tclk1 + + interrupts: + description: + One interrupt per timer, starting at timer 0. + minItems: 1 + maxItems: 5 + + "#pwm-cells": + description: + The only third cell flag supported by this binding + is PWM_POLARITY_INVERTED. + const: 3 + + samsung,pwm-outputs: + description: + A list of PWM channels used as PWM outputs on particular platform. + It is an array of up to 5 elements being indices of PWM channels + (from 0 to 4), the order does not matter. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - uniqueItems: true + - items: + minimum: 0 + maximum: 4 + +required: + - clocks + - clock-names + - compatible + - interrupts + - "#pwm-cells" + - reg + +examples: + - | + pwm@7f006000 { + compatible = "samsung,s3c6400-pwm"; + reg = <0x7f006000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <23>, <24>, <25>, <27>, <28>; + clocks = <&clock 67>; + clock-names = "timers"; + samsung,pwm-outputs = <0>, <1>; + #pwm-cells = <3>; + };