From patchwork Sat Sep 21 15:12:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11155531 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1CD84112B for ; Sat, 21 Sep 2019 15:13:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F03BB21835 for ; Sat, 21 Sep 2019 15:13:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="OVKi08S5" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2438053AbfIUPMs (ORCPT ); Sat, 21 Sep 2019 11:12:48 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:39095 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2438034AbfIUPMr (ORCPT ); Sat, 21 Sep 2019 11:12:47 -0400 Received: by mail-wr1-f66.google.com with SMTP id r3so9604766wrj.6; Sat, 21 Sep 2019 08:12:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WfQ1e9LFDFE1Z5maZrDyEq/WutECQBCS0m0ceOAIqa0=; b=OVKi08S50hGEiRw9dBzGluGTGgtg+pKlp3xygMsU4spmhQ51+dAU5e6bPO31NbjcRR q0OHBrM3S3waNNWWw51OjK4uchrcrc/TFylItNLLqgi75Q2j3h1n/b9QPljojXbD1kFP NevFD8TLX1GtPO4cyMTxRaMDfy6etU+ilLKB75FaAUt2Pvbf3IS5Bdzhjx2BfgpEjLh8 CeF5cq5Jf6S2DvnGXC8y7wlDNsHaWtg8KZpJubtEYTSE5VvPEh8fDbR+zaInW3CuqHfY Upb+8JbbcoYmzMttXpMdnx3SU2WOmZ3YFxH9/HGGMzlC2MdmHep1XsWA7hrJI9S4SH21 inHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WfQ1e9LFDFE1Z5maZrDyEq/WutECQBCS0m0ceOAIqa0=; b=PzmZ0Ij7dmEGXzcBnGJBn7D7zeb3B9jyAFAXpsKY91oOVvUCURrTFpsVfxiH557RC0 7pR2meHCtvHfaodchgfy9+alJuRo8yr//K0E3c0szkEit4/bqRi3+xfrnE9qWLzaOISX e24FGqwD+3oUKyxRe2WPbPkPvCIBh8msm2NGld3SL6NC9VuDX1lphUQbvwjPVq0yovxG 9JGU+AZ8tClPbISBbNCzrHW9jLZi0NBxgFa6pED6yPUm8GaA7cuRJMPAuEUbbBQrdg63 GdChDEytvLbVfS31SPNoneRbbTHkFCETs7g9NmcMdWLzPtIUubEIjmBeuzxNtqtdfBTF 2X0Q== X-Gm-Message-State: APjAAAX/+MWMHcS55+TbM+8scic8WJyDgjrZT1ve3/drkQlRctzRq1m8 LEX36B3LLCO4+Rc6GD959CI= X-Google-Smtp-Source: APXvYqz97gwP1YJzwvQCqfcq+Gp85bKA2r8M6d+E7PYadTAilKiby2e0S8TKyZPdPmgnhDeAvWVe6A== X-Received: by 2002:a5d:40d2:: with SMTP id b18mr15977793wrq.4.1569078765019; Sat, 21 Sep 2019 08:12:45 -0700 (PDT) Received: from blackbox.darklights.net (p200300F133CE0B0028BAA8C744A6F562.dip0.t-ipconnect.de. [2003:f1:33ce:b00:28ba:a8c7:44a6:f562]) by smtp.googlemail.com with ESMTPSA id y186sm10712491wmb.41.2019.09.21.08.12.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Sep 2019 08:12:44 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, khilman@baylibre.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 1/5] dt-bindings: clock: meson8b: add the clock inputs Date: Sat, 21 Sep 2019 17:12:19 +0200 Message-Id: <20190921151223.768842-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190921151223.768842-1-martin.blumenstingl@googlemail.com> References: <20190921151223.768842-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The clock controller on Meson8/Meson8b/Meson8m2 has three (known) inputs: - "xtal": the main 24MHz crystal - "ddr_pll": some of the audio clocks use the output of the DDR PLL as input - "clk_32k": an optional clock signal which can be connected to GPIOAO_6 (which then has to be switched to the CLK_32K_IN function) Add the inputs to the documentation so we can wire up these inputs in a follow-up patch. Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring --- .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt index 4d94091c1d2d..cc51e4746b3b 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt @@ -11,6 +11,11 @@ Required Properties: - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs - #clock-cells: should be 1. - #reset-cells: should be 1. +- clocks: list of clock phandles, one for each entry in clock-names +- clock-names: should contain the following: + * "xtal": the 24MHz system oscillator + * "ddr_pll": the DDR PLL clock + * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN) Parent node should have the following properties : - compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon" From patchwork Sat Sep 21 15:12:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11155523 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 99428112B for ; Sat, 21 Sep 2019 15:13:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 73F36217F5 for ; Sat, 21 Sep 2019 15:13:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="tyKJBdOM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2438074AbfIUPMu (ORCPT ); Sat, 21 Sep 2019 11:12:50 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:37774 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2438044AbfIUPMs (ORCPT ); Sat, 21 Sep 2019 11:12:48 -0400 Received: by mail-wr1-f67.google.com with SMTP id i1so9599659wro.4; Sat, 21 Sep 2019 08:12:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CPQNzivuVZNWDtPwgDvWYp9o/YTaW3TY1ny0gNcTyh8=; b=tyKJBdOMcUtbyFEEuDYriQySbMRUnzXuTDnHyk5sSVY9vIyXw98fB0hQyP6qVFJ819 DfquyskfRywLFLSYTc4YKTG24fIDU9iNeW3oT3mQyd4k/jSF63Gc80ivqn1BpQzJ8NDC Cm6xzIST6MSIpYsoLgu6bkosOUGBDKvWKf5IX7aX6bljDyWXSMafPMACH/PZIZeC9Bjz yW18+/FdXg4beschyz7151ft/qab39sCKXnygfB7RmGcCLjddnDATjrI3w7hiqsTboo9 dRcPgHweDogzdhcO2WbGaTDqIGsedGomszlBQYyR8RQd+fa4D1NzjHWhYU/0+2LY8+Qa FNrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CPQNzivuVZNWDtPwgDvWYp9o/YTaW3TY1ny0gNcTyh8=; b=oZPNFRj7nXKr4pCO2t8h8RQcQsFH+2fOJqtUNgrVJq153SEI7+Df5lwjGTAhD14jSg w3bqmM3OhN8YT0MvptHxx9P5wX0PVd5xcxjuvdlskH/ouAOCfWr4I+b3dwrTpXc+GdLH BNY2OabNVPAjytKkfhE5Sykt67rWvH3IZ1qQngUumKubzD7675I1D57guiCQxzZF/K+k AqXV0pEy5YxmCMP+P8+H07Q3KXAm73Tarn0KUlOa+zOV8DzdRzHWyXGpcxO6ZNxg9yOB AiHtQX6WEMkM9jgnrMPfsi2Gcd3biicPn34wNaALVUy1QGlt9fCdfHIzVPYcjRyutAb1 pWUQ== X-Gm-Message-State: APjAAAVy+HR2l9uRr/+amvTtZnAFJ0rhBQy7lqQY19PsYPRFeY7j9NfY ezT578lhpgBjFhaNRMGKUjU= X-Google-Smtp-Source: APXvYqwnd+5qIx487C1bZirqZ9rqerQUlrUb7EkYpyDE0y3bXL3OIoYGID3wBEp9e0T8xvje4DoNEQ== X-Received: by 2002:a5d:5592:: with SMTP id i18mr15044038wrv.316.1569078766284; Sat, 21 Sep 2019 08:12:46 -0700 (PDT) Received: from blackbox.darklights.net (p200300F133CE0B0028BAA8C744A6F562.dip0.t-ipconnect.de. [2003:f1:33ce:b00:28ba:a8c7:44a6:f562]) by smtp.googlemail.com with ESMTPSA id y186sm10712491wmb.41.2019.09.21.08.12.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Sep 2019 08:12:45 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, khilman@baylibre.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 2/5] clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier Date: Sat, 21 Sep 2019 17:12:20 +0200 Message-Id: <20190921151223.768842-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190921151223.768842-1-martin.blumenstingl@googlemail.com> References: <20190921151223.768842-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Switch from clk_set_parent() to clk_hw_set_parent() now that we have a way to configure a mux clock based on clk_hw pointers. This simplifies the meson8b_cpu_clk_notifier_cb logic. No functional changes. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 67e6691e080c..d376f80e806d 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -3585,7 +3585,7 @@ static const struct reset_control_ops meson8b_clk_reset_ops = { struct meson8b_nb_data { struct notifier_block nb; - struct clk_hw_onecell_data *onecell_data; + struct clk_hw *cpu_clk; }; static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb, @@ -3593,30 +3593,25 @@ static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb, { struct meson8b_nb_data *nb_data = container_of(nb, struct meson8b_nb_data, nb); - struct clk_hw **hws = nb_data->onecell_data->hws; - struct clk_hw *cpu_clk_hw, *parent_clk_hw; - struct clk *cpu_clk, *parent_clk; + struct clk_hw *parent_clk; int ret; switch (event) { case PRE_RATE_CHANGE: - parent_clk_hw = hws[CLKID_XTAL]; + /* xtal */ + parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 0); break; case POST_RATE_CHANGE: - parent_clk_hw = hws[CLKID_CPU_SCALE_OUT_SEL]; + /* cpu_scale_out_sel */ + parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 1); break; default: return NOTIFY_DONE; } - cpu_clk_hw = hws[CLKID_CPUCLK]; - cpu_clk = __clk_lookup(clk_hw_get_name(cpu_clk_hw)); - - parent_clk = __clk_lookup(clk_hw_get_name(parent_clk_hw)); - - ret = clk_set_parent(cpu_clk, parent_clk); + ret = clk_hw_set_parent(nb_data->cpu_clk, parent_clk); if (ret) return notifier_from_errno(ret); @@ -3695,7 +3690,7 @@ static void __init meson8b_clkc_init_common(struct device_node *np, return; } - meson8b_cpu_nb_data.onecell_data = clk_hw_onecell_data; + meson8b_cpu_nb_data.cpu_clk = clk_hw_onecell_data->hws[CLKID_CPUCLK]; /* * FIXME we shouldn't program the muxes in notifier handlers. The From patchwork Sat Sep 21 15:12:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11155529 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 781371747 for ; Sat, 21 Sep 2019 15:13:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4D83221882 for ; Sat, 21 Sep 2019 15:13:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="tSf36BVW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2438141AbfIUPNF (ORCPT ); Sat, 21 Sep 2019 11:13:05 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:33145 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2438061AbfIUPMu (ORCPT ); Sat, 21 Sep 2019 11:12:50 -0400 Received: by mail-wr1-f67.google.com with SMTP id b9so9642010wrs.0; Sat, 21 Sep 2019 08:12:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+ELKKDirjp0oZPBJ44VpnYEwyvsV3MSi9kYfRjT4vis=; b=tSf36BVWvtXx+VPiJbvevWv9xlJ1MUcJK4nZLS1qWGYNLxNoHdV/7xgWGIod4J18ne 9bpfamIpQ6rlDAewCfWEch+b3DIMg12XG5ZiLs5/C2Cx4Z4YXWyux/iDi3msAT3US/ry Pko0MtDG5LmeNd2zARa2loDVGhCAdgexNmZIFqU/PEPNVQoAX3MRPpvpkC28NZvuzL4c kXztKPpRiaAru9syL6RcQ0CwNAiCFbJsDJw0PD9/k3hWR9kV34MPf2RssSYirgiJeucn TGFOqWe5OeaVg9FWH83tY5HoV0MCZYvjWWXH6jLnsZbeeTEcrI6HCBFonKgTt96aczaY T4Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+ELKKDirjp0oZPBJ44VpnYEwyvsV3MSi9kYfRjT4vis=; b=kQ7tOER15cvrpQpUHTS5XbBnOFzjp91uGjPE1qkmJR28fue4avOngDHXisov5fCWD4 d7Sx/XCXmfafvARu13bR1bYZIiYiazh947pvkV08RCUMlzKCk3Mw90ej1GGiXT+oTyka m1UvlN+oWyBEDrA16Gub2b8hVi+sBhElS2vw/wa7SPeS1J8aD9N+RyuaRObYoLlC0UMh ZCMS2xoxZkjibwxIFABqf+NZ0Gbm8akzS1qWoUAHi8oDsqSzA7GkF34C0hubYWGyiW4S 5YQfBcazXzNv/xV8v0LqKcgZgKH7S75jXN5lH1GPbYjhXFwuRVQc1HZqRyPUPg8ZTto7 YQMQ== X-Gm-Message-State: APjAAAUGPtAtAge7kQIqqbkyonHb99GXMDGYScAz3mpGCFQoBS8vlnqi yacBIszEqxbz5Fhk2eOliqo= X-Google-Smtp-Source: APXvYqwx45owz2FGuyA/qiPoL6+BJkR2g+Q1oinww/HO5IBtLhd+znAWfPtMJt/w4Y6dclBVZlf0Og== X-Received: by 2002:a5d:5403:: with SMTP id g3mr15302198wrv.338.1569078767754; Sat, 21 Sep 2019 08:12:47 -0700 (PDT) Received: from blackbox.darklights.net (p200300F133CE0B0028BAA8C744A6F562.dip0.t-ipconnect.de. [2003:f1:33ce:b00:28ba:a8c7:44a6:f562]) by smtp.googlemail.com with ESMTPSA id y186sm10712491wmb.41.2019.09.21.08.12.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Sep 2019 08:12:46 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, khilman@baylibre.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 3/5] clk: meson: meson8b: change references to the XTAL clock to use the name Date: Sat, 21 Sep 2019 17:12:21 +0200 Message-Id: <20190921151223.768842-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190921151223.768842-1-martin.blumenstingl@googlemail.com> References: <20190921151223.768842-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The XTAL clock is an actual crystal which is mounted on the PCB. Thus the meson8b clock controller driver should not provide the XTAL clock. The meson8b clock controller driver must not use references to the meson8b_xtal clock anymore before we can provide the XTAL clock via OF. Replace the references to the meson8b_xtal.hw by using clk_parent_data.name = "xtal" (along with index = -1) because this works regardless how the XTAL clock is registered (either as fixed-clock in the .dtb or - if missing - when registered in the meson8b clock controller driver). Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 73 ++++++++++++++++++++----------------- 1 file changed, 39 insertions(+), 34 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index d376f80e806d..b785b67baf2b 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -97,8 +97,9 @@ static struct clk_regmap meson8b_fixed_pll_dco = { .hw.init = &(struct clk_init_data){ .name = "fixed_pll_dco", .ops = &meson_clk_pll_ro_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw + .parent_data = &(const struct clk_parent_data) { + .name = "xtal", + .index = -1, }, .num_parents = 1, }, @@ -162,8 +163,9 @@ static struct clk_regmap meson8b_hdmi_pll_dco = { /* sometimes also called "HPLL" or "HPLL PLL" */ .name = "hdmi_pll_dco", .ops = &meson_clk_pll_ro_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw + .parent_data = &(const struct clk_parent_data) { + .name = "xtal", + .index = -1, }, .num_parents = 1, }, @@ -237,8 +239,9 @@ static struct clk_regmap meson8b_sys_pll_dco = { .hw.init = &(struct clk_init_data){ .name = "sys_pll_dco", .ops = &meson_clk_pll_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw + .parent_data = &(const struct clk_parent_data) { + .name = "xtal", + .index = -1, }, .num_parents = 1, }, @@ -631,9 +634,9 @@ static struct clk_regmap meson8b_cpu_in_sel = { .hw.init = &(struct clk_init_data){ .name = "cpu_in_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw, - &meson8b_sys_pll.hw, + .parent_data = (const struct clk_parent_data[]) { + { .name = "xtal", .index = -1, }, + { .hw = &meson8b_sys_pll.hw, }, }, .num_parents = 2, .flags = (CLK_SET_RATE_PARENT | @@ -736,9 +739,9 @@ static struct clk_regmap meson8b_cpu_clk = { .hw.init = &(struct clk_init_data){ .name = "cpu_clk", .ops = &clk_regmap_mux_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw, - &meson8b_cpu_scale_out_sel.hw, + .parent_data = (const struct clk_parent_data[]) { + { .name = "xtal", .index = -1, }, + { .hw = &meson8b_cpu_scale_out_sel.hw, }, }, .num_parents = 2, .flags = (CLK_SET_RATE_PARENT | @@ -758,12 +761,12 @@ static struct clk_regmap meson8b_nand_clk_sel = { .name = "nand_clk_sel", .ops = &clk_regmap_mux_ops, /* FIXME all other parents are unknown: */ - .parent_hws = (const struct clk_hw *[]) { - &meson8b_fclk_div4.hw, - &meson8b_fclk_div3.hw, - &meson8b_fclk_div5.hw, - &meson8b_fclk_div7.hw, - &meson8b_xtal.hw, + .parent_data = (const struct clk_parent_data[]) { + { .hw = &meson8b_fclk_div4.hw, }, + { .hw = &meson8b_fclk_div3.hw, }, + { .hw = &meson8b_fclk_div5.hw, }, + { .hw = &meson8b_fclk_div7.hw, }, + { .name = "xtal", .index = -1, }, }, .num_parents = 5, .flags = CLK_SET_RATE_PARENT, @@ -1721,8 +1724,9 @@ static struct clk_regmap meson8b_hdmi_sys_sel = { .name = "hdmi_sys_sel", .ops = &clk_regmap_mux_ro_ops, /* FIXME: all other parents are unknown */ - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw + .parent_data = &(const struct clk_parent_data) { + .name = "xtal", + .index = -1, }, .num_parents = 1, .flags = CLK_SET_RATE_NO_REPARENT, @@ -1767,14 +1771,14 @@ static struct clk_regmap meson8b_hdmi_sys = { * muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only * has mali_0 and no glitch-free mux. */ -static const struct clk_hw *meson8b_mali_0_1_parent_hws[] = { - &meson8b_xtal.hw, - &meson8b_mpll2.hw, - &meson8b_mpll1.hw, - &meson8b_fclk_div7.hw, - &meson8b_fclk_div4.hw, - &meson8b_fclk_div3.hw, - &meson8b_fclk_div5.hw, +static const struct clk_parent_data meson8b_mali_0_1_parent_data[] = { + { .name = "xtal", .index = -1, }, + { .hw = &meson8b_mpll2.hw, }, + { .hw = &meson8b_mpll1.hw, }, + { .hw = &meson8b_fclk_div7.hw, }, + { .hw = &meson8b_fclk_div4.hw, }, + { .hw = &meson8b_fclk_div3.hw, }, + { .hw = &meson8b_fclk_div5.hw, }, }; static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 }; @@ -1789,8 +1793,8 @@ static struct clk_regmap meson8b_mali_0_sel = { .hw.init = &(struct clk_init_data){ .name = "mali_0_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_mali_0_1_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_hws), + .parent_data = meson8b_mali_0_1_parent_data, + .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data), /* * Don't propagate rate changes up because the only changeable * parents are mpll1 and mpll2 but we need those for audio and @@ -1844,8 +1848,8 @@ static struct clk_regmap meson8b_mali_1_sel = { .hw.init = &(struct clk_init_data){ .name = "mali_1_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_mali_0_1_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_hws), + .parent_data = meson8b_mali_0_1_parent_data, + .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data), /* * Don't propagate rate changes up because the only changeable * parents are mpll1 and mpll2 but we need those for audio and @@ -1944,8 +1948,9 @@ static struct clk_regmap meson8m2_gp_pll_dco = { .hw.init = &(struct clk_init_data){ .name = "gp_pll_dco", .ops = &meson_clk_pll_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw + .parent_data = &(const struct clk_parent_data) { + .name = "xtal", + .index = -1, }, .num_parents = 1, }, From patchwork Sat Sep 21 15:12:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11155521 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A4601112B for ; Sat, 21 Sep 2019 15:13:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8356621907 for ; Sat, 21 Sep 2019 15:13:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="b0kfoR7H" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2438095AbfIUPMw (ORCPT ); Sat, 21 Sep 2019 11:12:52 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:53520 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2438034AbfIUPMv (ORCPT ); Sat, 21 Sep 2019 11:12:51 -0400 Received: by mail-wm1-f65.google.com with SMTP id i16so5380998wmd.3; Sat, 21 Sep 2019 08:12:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g3g3V03D6DkRYbYZABMPMLQMCrNMpOQBXxgsvwVk66Y=; b=b0kfoR7HMIpmuiYPIzNdtQLx3b8uneVrYYQ+dwHeZiDpi5mt5Spb2BSDtFU3KWKmCx +u1uR/rfNujS2PO/A7PdN+r11lDxBjnESvNNS/dmarQN/UssD/3LVpv+Zu9gIMvAVK/q kZbRPxGwZvNQAQXQ+twwkL48AU9/uucjb95D+t6jxIpWaaXo4ye0zqMEcbv3dzFUgnS9 vc9/vEbudhmHO3DOO0tBvjih385+ZFtD3FNE356fvdFXkge7WPluqmIKDEFYE1w0RGXf g48+nPKSQhGJKWpCYBCWWr3YFT8kctrGp0e8gNqV6haE7dGgBEushMGaShSexyqtirIo ucfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g3g3V03D6DkRYbYZABMPMLQMCrNMpOQBXxgsvwVk66Y=; b=CT/Pg9+V2YHUI62FEw4we+QjTraL9C1WijmG7GwsEW/8a9zPsu8P52iwGgDR8W5uER qQwT1SjscKCFn7L3wID3RhbsxC6A4HeUx/ymOCCy0xvWpuIWgOwUtjs9L77qt0yypoQR DK07HBfJn+QOJMihV+1EilK6MG5IQDcswHFR8CfTpPIag4VFJAbS0bhprKc/5H5/gb/8 sj2qNf90RZTTgg5S5E32d47uwWqK+kJAHFaQwypQtcT02/dM3Io8cPOy8qqT6WT5+bEC Tuz8pIKCiWLVgV35y6Z7UVpC6WRqSCcWEPdmh0hADvWKRmxvSCvNVJzgX+tBkHFkYhxz x0Ww== X-Gm-Message-State: APjAAAWEDrss8Rf1RZyChzIm5XDgpvt6suFzz1HFBXlntjKXOc5ASPH3 1z2NOQdgcBWJcCasp/LOz/g= X-Google-Smtp-Source: APXvYqz6hlOksjMhBKLSwZPGPxQ6oqEOuX/QaQonH+2wP07T3D3DBw9L4AZNYrqyscJFSb74nmb3Xg== X-Received: by 2002:a05:600c:389:: with SMTP id w9mr7047507wmd.139.1569078769146; Sat, 21 Sep 2019 08:12:49 -0700 (PDT) Received: from blackbox.darklights.net (p200300F133CE0B0028BAA8C744A6F562.dip0.t-ipconnect.de. [2003:f1:33ce:b00:28ba:a8c7:44a6:f562]) by smtp.googlemail.com with ESMTPSA id y186sm10712491wmb.41.2019.09.21.08.12.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Sep 2019 08:12:48 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, khilman@baylibre.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 4/5] clk: meson: meson8b: don't register the XTAL clock when provided via OF Date: Sat, 21 Sep 2019 17:12:22 +0200 Message-Id: <20190921151223.768842-5-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190921151223.768842-1-martin.blumenstingl@googlemail.com> References: <20190921151223.768842-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The XTAL clock is an actual crystal on the PCB. Thus the meson8b clock driver should not register the XTAL clock - instead it should be provided via .dts and then passed to the clock controller. Skip the registration of the XTAL clock if a parent clock is provided via OF. Fall back to registering the XTAL clock if this is not the case to keep support for old .dtbs. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index b785b67baf2b..15ec14fde2a0 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -3682,10 +3682,16 @@ static void __init meson8b_clkc_init_common(struct device_node *np, meson8b_clk_regmaps[i]->map = map; /* - * register all clks - * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1 + * always skip CLKID_UNUSED and also skip XTAL if the .dtb provides the + * XTAL clock as input. */ - for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) { + if (of_clk_get_parent_count(np)) + i = CLKID_PLL_FIXED; + else + i = CLKID_XTAL; + + /* register all clks */ + for (; i < CLK_NR_CLKS; i++) { /* array might be sparse */ if (!clk_hw_onecell_data->hws[i]) continue; From patchwork Sat Sep 21 15:12:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11155519 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 47EE8112B for ; Sat, 21 Sep 2019 15:13:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1C49621835 for ; Sat, 21 Sep 2019 15:13:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="jljvR6u4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2438034AbfIUPM7 (ORCPT ); Sat, 21 Sep 2019 11:12:59 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:50837 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2438081AbfIUPMx (ORCPT ); Sat, 21 Sep 2019 11:12:53 -0400 Received: by mail-wm1-f65.google.com with SMTP id 5so5397609wmg.0; Sat, 21 Sep 2019 08:12:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FLfO/KxjQrMiblT1/Pl6tSGizwnToQmABBG15vNjp4k=; b=jljvR6u41lhZC97d2nOVlCbfA7sN8ysHuicakSGltcm1A/jN6XBxvO6B5GkgHODJKA yXAX31bnNYB8VtlG4K9eb4Mws3TF0IGpNDp25bcs2O9rd+7JPXqkL1C++vpQRzjqb+zK Bme5zHxKn8yzbyf2jRdUgr07bYQVFhxLYiEAH+HgRLI5hRVPIl84qiIRWHkUH5tTIc5M g/AtumzOFJKBBx+2eushGZGzuGGoi9tPcP6qZEnv7XKR5kECRTMFZANwWvIzQJbSNSE3 NyAA2ga1zp72/vEvNpL0lfDQ8jxIzTN5HsCkdIIxyM9D/r5BQtUKiun82/Fd6x7tUBcf FwCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FLfO/KxjQrMiblT1/Pl6tSGizwnToQmABBG15vNjp4k=; b=FNXNz/fG4JzQrQMjTUMiTr3TPhr87zT9hQng0FN6GXQGymnnMomTnWPzaJXboOhi8W 7PpFhTEcg07Pfl3KiHt+8/+xTPQbfh08FVOOxy9GwyEurvB/3DxKBlUYcpJHV/MqKOEC 1OPk+yVF85TuOTcb1qSB7g+qQNSXqXmGGyDqWGGX5BqoGYz5SnTMf7mICi/4draN+ROU C0Ze1Y6Wg9BEcGyaHRbNGqEzT5C7tNij3iqaeCbZEF6I2e+tQ5rPr4Nax3AbQjZCJKm7 gwL8yt9ReYcr1Ke+4eoUofE7u7Kyq+kdooiF/7fOOiB2aycOmvqvHNhGQ2Gf04Pd7Ma0 Xi+w== X-Gm-Message-State: APjAAAW+QSKY7SM2OYNsbPOJaYsSx7o7j1/3Zsadlym/cZMLFG23QL4t NfdbnBleuSZQjQs0nQDGh8fYO1k3 X-Google-Smtp-Source: APXvYqwGCh09uYfuqvcZSmO+ibjdhqjWpzqPVLsWsMzl+s68SPOO6wbK8vMNCkEcHCNrmx4ZVEv9bA== X-Received: by 2002:a1c:4946:: with SMTP id w67mr7291151wma.131.1569078770337; Sat, 21 Sep 2019 08:12:50 -0700 (PDT) Received: from blackbox.darklights.net (p200300F133CE0B0028BAA8C744A6F562.dip0.t-ipconnect.de. [2003:f1:33ce:b00:28ba:a8c7:44a6:f562]) by smtp.googlemail.com with ESMTPSA id y186sm10712491wmb.41.2019.09.21.08.12.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Sep 2019 08:12:49 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, khilman@baylibre.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 5/5] ARM: dts: meson: provide the XTAL clock using a fixed-clock Date: Sat, 21 Sep 2019 17:12:23 +0200 Message-Id: <20190921151223.768842-6-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190921151223.768842-1-martin.blumenstingl@googlemail.com> References: <20190921151223.768842-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The clock controller driver has provided the XTAL clock so far. This does not match how the hardware actually works because the XTAL clock is an actual crystal which is mounted on the PCB. Add the "xtal" clock to meson.dtsi and replace all references to the clock controller's CLKID_XTAL with the new xtal clock node. Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson.dtsi | 7 +++++++ arch/arm/boot/dts/meson6.dtsi | 7 ------- arch/arm/boot/dts/meson8.dtsi | 15 ++++++++------- arch/arm/boot/dts/meson8b-ec100.dts | 2 +- arch/arm/boot/dts/meson8b-mxq.dts | 2 +- arch/arm/boot/dts/meson8b-odroidc1.dts | 2 +- arch/arm/boot/dts/meson8b.dtsi | 15 ++++++++------- 7 files changed, 26 insertions(+), 24 deletions(-) diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index c4447f6c8b2c..5d198309058a 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -282,4 +282,11 @@ }; }; }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; }; /* end of / */ diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi index 2d31b7ce3f8c..4716030a48d0 100644 --- a/arch/arm/boot/dts/meson6.dtsi +++ b/arch/arm/boot/dts/meson6.dtsi @@ -36,13 +36,6 @@ ranges = <0x0 0xd0000000 0x40000>; }; - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; - clk81: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 5a7e3e5caebe..4f59a4c8f036 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -455,6 +455,8 @@ &hhi { clkc: clock-controller { compatible = "amlogic,meson8-clkc"; + clocks = <&xtal>; + clock-names = "xtal"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -529,8 +531,7 @@ &saradc { compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; - clocks = <&clkc CLKID_XTAL>, - <&clkc CLKID_SAR_ADC>; + clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; clock-names = "clkin", "core"; amlogic,hhi-sysctrl = <&hhi>; nvmem-cells = <&temperature_calib>; @@ -548,31 +549,31 @@ }; &timer_abcde { - clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; + clocks = <&xtal>, <&clkc CLKID_CLK81>; clock-names = "xtal", "pclk"; }; &uart_AO { compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>; clock-names = "baud", "xtal", "pclk"; }; &uart_A { compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>; clock-names = "baud", "xtal", "pclk"; }; &uart_B { compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>; clock-names = "baud", "xtal", "pclk"; }; &uart_C { compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>; clock-names = "baud", "xtal", "pclk"; }; diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index bed1dfef1985..163a200d5a7b 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -377,7 +377,7 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>; + clocks = <&xtal>, <&xtal>; clock-names = "clkin0", "clkin1"; }; diff --git a/arch/arm/boot/dts/meson8b-mxq.dts b/arch/arm/boot/dts/meson8b-mxq.dts index 6e39ad52e42d..33037ef62d0a 100644 --- a/arch/arm/boot/dts/meson8b-mxq.dts +++ b/arch/arm/boot/dts/meson8b-mxq.dts @@ -165,7 +165,7 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>; + clocks = <&xtal>, <&xtal>; clock-names = "clkin0", "clkin1"; }; diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index a24eccc354b9..a2a47804fc4a 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -340,7 +340,7 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>; + clocks = <&xtal>, <&xtal>; clock-names = "clkin0", "clkin1"; }; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 099bf8e711c9..1934666ff60f 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -434,6 +434,8 @@ &hhi { clkc: clock-controller { compatible = "amlogic,meson8-clkc"; + clocks = <&xtal>; + clock-names = "xtal"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -508,8 +510,7 @@ &saradc { compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc"; - clocks = <&clkc CLKID_XTAL>, - <&clkc CLKID_SAR_ADC>; + clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; clock-names = "clkin", "core"; amlogic,hhi-sysctrl = <&hhi>; nvmem-cells = <&temperature_calib>; @@ -523,31 +524,31 @@ }; &timer_abcde { - clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; + clocks = <&xtal>, <&clkc CLKID_CLK81>; clock-names = "xtal", "pclk"; }; &uart_AO { compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>; clock-names = "baud", "xtal", "pclk"; }; &uart_A { compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>; clock-names = "baud", "xtal", "pclk"; }; &uart_B { compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>; clock-names = "baud", "xtal", "pclk"; }; &uart_C { compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>; clock-names = "baud", "xtal", "pclk"; };