From patchwork Sat Sep 21 15:18:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11155567 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6BFAD16B1 for ; Sat, 21 Sep 2019 15:19:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4A97F21928 for ; Sat, 21 Sep 2019 15:19:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="AwdZfkWa" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2394284AbfIUPSv (ORCPT ); Sat, 21 Sep 2019 11:18:51 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:40395 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2392043AbfIUPSu (ORCPT ); Sat, 21 Sep 2019 11:18:50 -0400 Received: by mail-wr1-f65.google.com with SMTP id l3so9591654wru.7; Sat, 21 Sep 2019 08:18:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0VvVyYbylhhn27lwnpj3kEDmecswF/DtGt6I7xL1THE=; b=AwdZfkWa2Zgunj0RMms1Csk0t/Bg4v/uFPqVU7GERZOhx5a+rh7P2KefE2ys3mgPqu 8sp95P0w1G334sr3PxEdxmIvH2QCvBrTN8aHPLl2ln2VNjMp6QF5U41qAzgt07Vt3jNK etQuibrNO5D+4kjr6tb1quq6zE7UmuiM+whDQ0Pt/ca8TCmboJA/I8j3/SW2Rd1eHr5v Bt+60xkXfqkCmntTrq5oeWVgY5ZLULnV9aLK4uBFGEQAh9bMJLtL+wlSnXiPM1WCpoU/ JDdwt0avJHJ+mwWhE5P5hFn29PnNssxuJtf25y/JaSPcy2boWyrnXBP8saOOd30Vdqz+ NHWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0VvVyYbylhhn27lwnpj3kEDmecswF/DtGt6I7xL1THE=; b=Q4Ei4hDgrQluqeCKdGK/ey8uA0hLUurNL6Zy4kAkpFUWoIOaKDvh7vsTiLKkLe+uYX FSnaiMh045EQBs3fAiIAukUfKNDHJtKSZRhIoTMeK1jsJjvaop3fT3s/JqV+3XzT3emP jbyncNQl3dTOvZsnBZro1zZLJuriC0DxUINGCwl0ZlT0Tj9UhvXIT012+br8C7IW+/Zc KivgCN7ZPbrF3QvG1cgoMXZpDZ/4CX/EbPLp4L49zo4baPoleg9IL8QItKzZXa2kWEGb jSeZqVVXvcbNrU5PvXsBEq+ZfpX9oLn+fV8LMGn1ClNgI90CxKJ9/w4IWfv5xm16EIx3 /evg== X-Gm-Message-State: APjAAAX8UPF4Dx0AkWNTv5Sn+5i06RX2A3D2hciWyU1DRdr8OvrdckGc 3NEPiBW5zoaXrNderoxkkbo= X-Google-Smtp-Source: APXvYqzjLsxL6Hb5gWpypNfZmMuuKIqU6e8iKaQeFtNzeVg/UC9EEacsUopb1O4+mKK7gli1ftsl7g== X-Received: by 2002:a5d:6885:: with SMTP id h5mr16181417wru.92.1569079128474; Sat, 21 Sep 2019 08:18:48 -0700 (PDT) Received: from blackbox.darklights.net (p200300F133CE0B0028BAA8C744A6F562.dip0.t-ipconnect.de. [2003:f1:33ce:b00:28ba:a8c7:44a6:f562]) by smtp.googlemail.com with ESMTPSA id c6sm6003120wrb.60.2019.09.21.08.18.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Sep 2019 08:18:47 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, khilman@baylibre.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 1/6] dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding Date: Sat, 21 Sep 2019 17:18:30 +0200 Message-Id: <20190921151835.770263-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190921151835.770263-1-martin.blumenstingl@googlemail.com> References: <20190921151835.770263-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Amlogic Meson8, Meson8b and Meson8m2 SoCs have a DDR clock controller in the MMCBUS registers. There is no public documentation on this, but the GPL u-boot sources from the Amlogic BSP show that: - it uses the same XTAL input as the main clock controller - it contains a PLL which seems to be implemented just like the other PLLs in this SoC - there is a power-of-two PLL post-divider Add the documentation and header file for this DDR clock controller. Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring --- .../clock/amlogic,meson8-ddr-clkc.yaml | 50 +++++++++++++++++++ include/dt-bindings/clock/meson8-ddr-clkc.h | 4 ++ 2 files changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml create mode 100644 include/dt-bindings/clock/meson8-ddr-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml new file mode 100644 index 000000000000..bf3ca5888485 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic DDR Clock Controller Device Tree Bindings + +maintainers: + - Martin Blumenstingl + +properties: + compatible: + enum: + - amlogic,meson8-ddr-clkc + - amlogic,meson8b-ddr-clkc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: xtal + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + ddr_clkc: clock-controller@400 { + compatible = "amlogic,meson8-ddr-clkc"; + reg = <0x400 0x20>; + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/meson8-ddr-clkc.h b/include/dt-bindings/clock/meson8-ddr-clkc.h new file mode 100644 index 000000000000..a8e0fa2987ab --- /dev/null +++ b/include/dt-bindings/clock/meson8-ddr-clkc.h @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#define DDR_CLKID_DDR_PLL_DCO 0 +#define DDR_CLKID_DDR_PLL 1 From patchwork Sat Sep 21 15:18:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11155565 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7AFB016B1 for ; Sat, 21 Sep 2019 15:19:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4EE2C2190F for ; Sat, 21 Sep 2019 15:19:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="E2NvMrxJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2438098AbfIUPSx (ORCPT ); Sat, 21 Sep 2019 11:18:53 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:38171 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389472AbfIUPSw (ORCPT ); Sat, 21 Sep 2019 11:18:52 -0400 Received: by mail-wr1-f65.google.com with SMTP id l11so9606734wrx.5; Sat, 21 Sep 2019 08:18:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tL9H2pw8VcVH+/HrGAKtJB8z0yBrLzroNdJ39zlPsf4=; b=E2NvMrxJwSJxDTHoMuEVvpjk5eoEdywakfkz3KI/elTbseQesn7NRfAf+J7nh+CuoX xckU3BUNGb+wvWirb6Ew+me7AR5ygjNMH8FkvpiqBRBzciZ5mys67+1u3y/a3rrBMcY8 e7Et+4g23Rualkpxz6oJO0VphLBV+d6Omyj5KQ+umIna6XI7spwO0+1oT2vu/RrCUj0k 2huU7C8thkD/bGYP4U+wW2Fn/rsKM8lncqNW4r9cxpHWFoJZtGlgraGFxz9EogFZrdfv cVYOk4lQMTbozxPXEYxzsmnopEblu26mkFSeAKcH7a7peVmSX2HM+c+4yFu4oPvyIbaC mKKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tL9H2pw8VcVH+/HrGAKtJB8z0yBrLzroNdJ39zlPsf4=; b=cv4K+bbyxG720J6HU54iODVLzSvIdODaghGZHf9zr21XwD8TJgDamQJXZW2IRSAXHv ZzOeQoifDRnwZnUXbGnOc9HQokBZan9hE4znB8urY1Jud7VJiUF9gNaK+WbzyJxaCvSP dlcXQEQEBkdItYoy3G1Supcm9qS6ujLqOx11/3sOJ5yTonn7HTdhb+pig4JHVDFGBLy2 /JstAdjSg5kH7WCFWISSJAm7s+WOEMp7ClhiAgWczpBB0Ld7vk64sp1ZBvJy1dM8pwmS O0Rh1p0OF3iW5JDLww4Oym+kk/1WjkZMLThg3StTfdX8QMzJ05odE/bVWwOAAMzkz7j4 9d/w== X-Gm-Message-State: APjAAAVxmwaMFiPKnn0HmRbq7137ozi+sE+LmZc82YD6cIm4NqBT/YjX qBhdkLrNgIE0TWr+BMqHOus= X-Google-Smtp-Source: APXvYqzFIz37+RJLiSRJg6Togsnn6KnEGn+RMKSBinwFDfuqF0wDYCcbcEWm1MA9Goj5aB/ivwIIUQ== X-Received: by 2002:a5d:4307:: with SMTP id h7mr3178723wrq.393.1569079129875; Sat, 21 Sep 2019 08:18:49 -0700 (PDT) Received: from blackbox.darklights.net (p200300F133CE0B0028BAA8C744A6F562.dip0.t-ipconnect.de. [2003:f1:33ce:b00:28ba:a8c7:44a6:f562]) by smtp.googlemail.com with ESMTPSA id c6sm6003120wrb.60.2019.09.21.08.18.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Sep 2019 08:18:49 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, khilman@baylibre.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 2/6] clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller Date: Sat, 21 Sep 2019 17:18:31 +0200 Message-Id: <20190921151835.770263-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190921151835.770263-1-martin.blumenstingl@googlemail.com> References: <20190921151835.770263-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The Meson8/Meson8b/Meson8m2 SoCs embed a DDR clock controller in the MMCBUS registers. There is no public documentation, but the u-boot GPL sources from the Amlogic BSP show that the DDR clock controller is identical on all three SoCs: #define CFG_DDR_CLK 792 #define CFG_PLL_M (((CFG_DDR_CLK/12)*12)/24) #define CFG_PLL_N 1 #define CFG_PLL_OD 1 // from set_ddr_clock: t_ddr_pll_cntl= (CFG_PLL_OD << 16)|(CFG_PLL_N<<9)|(CFG_PLL_M<<0) writel(timing_reg->t_ddr_pll_cntl|(1<<29),AM_DDR_PLL_CNTL); writel(readl(AM_DDR_PLL_CNTL) & (~(1<<29)),AM_DDR_PLL_CNTL); // from hx_ddr_power_down_enter: shut down DDR PLL writel(readl(AM_DDR_PLL_CNTL)|(1<<30),AM_DDR_PLL_CNTL); do { ... } while((readl(AM_DDR_PLL_CNTL)&(1<<31))==0) This translates to: - AM_DDR_PLL_CNTL[29] is the reset bit - AM_DDR_PLL_CNTL[30] is the enable bit - AM_DDR_PLL_CNTL[31] is the lock bit - AM_DDR_PLL_CNTL[8:0] is the m value (assuming the width is 9 bits based on the start of the n value) - AM_DDR_PLL_CNTL[13:9] is the n value (assuming the width is 5 bits based on the start of the od) - AM_DDR_PLL_CNTL[17:16] is the od (assuming the width is 2 bits based on other PLLs on this SoC) Add a driver for this PLL setup because it's used as one of the inputs of the audio clocks. There may be more clocks inside that clock controller - those can be added in subsequent patches. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/Makefile | 2 +- drivers/clk/meson/meson8-ddr.c | 153 +++++++++++++++++++++++++++++++++ 2 files changed, 154 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/meson/meson8-ddr.c diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 3939f218587a..6eca2a406ee3 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -18,4 +18,4 @@ obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o -obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o +obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o diff --git a/drivers/clk/meson/meson8-ddr.c b/drivers/clk/meson/meson8-ddr.c new file mode 100644 index 000000000000..64ab4c27cce0 --- /dev/null +++ b/drivers/clk/meson/meson8-ddr.c @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Amlogic Meson8 DDR clock controller + * + * Copyright (C) 2019 Martin Blumenstingl + */ + +#include + +#include +#include +#include +#include + +#include "clk-regmap.h" +#include "clk-pll.h" + +#define AM_DDR_PLL_CNTL 0x00 +#define AM_DDR_PLL_CNTL1 0x04 +#define AM_DDR_PLL_CNTL2 0x08 +#define AM_DDR_PLL_CNTL3 0x0c +#define AM_DDR_PLL_CNTL4 0x10 +#define AM_DDR_PLL_STS 0x14 +#define DDR_CLK_CNTL 0x18 +#define DDR_CLK_STS 0x1c + +static struct clk_regmap meson8_ddr_pll_dco = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = AM_DDR_PLL_CNTL, + .shift = 30, + .width = 1, + }, + .m = { + .reg_off = AM_DDR_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = AM_DDR_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .l = { + .reg_off = AM_DDR_PLL_CNTL, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = AM_DDR_PLL_CNTL, + .shift = 29, + .width = 1, + }, + }, + .hw.init = &(struct clk_init_data){ + .name = "ddr_pll_dco", + .ops = &meson_clk_pll_ro_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap meson8_ddr_pll = { + .data = &(struct clk_regmap_div_data){ + .offset = AM_DDR_PLL_CNTL, + .shift = 16, + .width = 2, + .flags = CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init = &(struct clk_init_data){ + .name = "ddr_pll", + .ops = &clk_regmap_divider_ro_ops, + .parent_hws = (const struct clk_hw *[]) { + &meson8_ddr_pll_dco.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_hw_onecell_data meson8_ddr_clk_hw_onecell_data = { + .hws = { + [DDR_CLKID_DDR_PLL_DCO] = &meson8_ddr_pll_dco.hw, + [DDR_CLKID_DDR_PLL] = &meson8_ddr_pll.hw, + }, + .num = 2, +}; + +static struct clk_regmap *const meson8_ddr_clk_regmaps[] = { + &meson8_ddr_pll_dco, + &meson8_ddr_pll, +}; + +static const struct regmap_config meson8_ddr_clkc_regmap_config = { + .reg_bits = 8, + .val_bits = 32, + .reg_stride = 4, + .fast_io = true, +}; + +static int meson8_ddr_clkc_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + struct resource *res; + void __iomem *base; + struct clk_hw *hw; + int ret, i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(&pdev->dev, base, + &meson8_ddr_clkc_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* Populate regmap */ + for (i = 0; i < ARRAY_SIZE(meson8_ddr_clk_regmaps); i++) + meson8_ddr_clk_regmaps[i]->map = regmap; + + /* Register all clks */ + for (i = 0; i < meson8_ddr_clk_hw_onecell_data.num; i++) { + hw = meson8_ddr_clk_hw_onecell_data.hws[i]; + + ret = devm_clk_hw_register(&pdev->dev, hw); + if (ret) { + dev_err(&pdev->dev, "Clock registration failed\n"); + return ret; + } + } + + return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, + &meson8_ddr_clk_hw_onecell_data); +} + +static const struct of_device_id meson8_ddr_clkc_match_table[] = { + { .compatible = "amlogic,meson8-ddr-clkc" }, + { .compatible = "amlogic,meson8b-ddr-clkc" }, + { /* sentinel */ }, +}; + +static struct platform_driver meson8_ddr_clkc_driver = { + .probe = meson8_ddr_clkc_probe, + .driver = { + .name = "meson8-ddr-clkc", + .of_match_table = meson8_ddr_clkc_match_table, + }, +}; + +builtin_platform_driver(meson8_ddr_clkc_driver); From patchwork Sat Sep 21 15:18:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11155551 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F0BE216B1 for ; Sat, 21 Sep 2019 15:18:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CDE4D208C0 for ; Sat, 21 Sep 2019 15:18:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="CcvR8pSU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2394295AbfIUPSx (ORCPT ); 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[2003:f1:33ce:b00:28ba:a8c7:44a6:f562]) by smtp.googlemail.com with ESMTPSA id c6sm6003120wrb.60.2019.09.21.08.18.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Sep 2019 08:18:50 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, khilman@baylibre.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 3/6] clk: meson: meson8b: use of_clk_hw_register to register the clocks Date: Sat, 21 Sep 2019 17:18:32 +0200 Message-Id: <20190921151835.770263-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190921151835.770263-1-martin.blumenstingl@googlemail.com> References: <20190921151835.770263-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Switch from clk_hw_register to of_clk_hw_register so we can use clk_parent_data.fw_name. This will be used to get the "xtal", "ddr_pll" and possibly others from the .dtb. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 15ec14fde2a0..fefb4b7185d0 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -3696,7 +3696,7 @@ static void __init meson8b_clkc_init_common(struct device_node *np, if (!clk_hw_onecell_data->hws[i]) continue; - ret = clk_hw_register(NULL, clk_hw_onecell_data->hws[i]); + ret = of_clk_hw_register(np, clk_hw_onecell_data->hws[i]); if (ret) return; } From patchwork Sat Sep 21 15:18:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11155561 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 45D5514DB for ; Sat, 21 Sep 2019 15:19:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 24460218AE for ; Sat, 21 Sep 2019 15:19:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="cH05sPvR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2438178AbfIUPSz (ORCPT ); Sat, 21 Sep 2019 11:18:55 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:39601 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2392043AbfIUPSy (ORCPT ); Sat, 21 Sep 2019 11:18:54 -0400 Received: by mail-wr1-f65.google.com with SMTP id r3so9614381wrj.6; Sat, 21 Sep 2019 08:18:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MgeOWr52J0AbeRdfS/blsOSLs4diI31K6bmRntAvmGc=; b=cH05sPvRnyjjP4kqZ62tz5buGh4I6wiRdSZ73thccq3BH6hMZ/efZjpv/k0ukN1j6o I7ZPU9kRKbOMbsE3D6vjGOKpngSxeRVR8P+HTYqmPZXOIQO4Yfl95X3gNhQk7hvYghRY 0YG09bEXuXWi4js1VASxO8rD+1pHiB7L4da3a56wWljAt0HIpN00+zwF2zg+YSTq8r+U IjmZZs6AcM5nQ8IS4k1D/ZvwCObfssmRcIgxSmNPTcn28/WxpNQBe0/mlluLGd10wXrF 41YzrSpx6DKRfthRXUurdMqNtq+g9wzy2rgIVSnjyrkV2S3fh8BudveJtu5+9jce4TO3 akpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MgeOWr52J0AbeRdfS/blsOSLs4diI31K6bmRntAvmGc=; b=eC6aOuX+V3D7Q54Z41RkcpzPWK2ZeSJaLK7Qya4IvF9SFhjhhJwuXOt9SYBElmUWlS 505IOmcRt1Ch4x9DZrSLoaeAbvO8oXwLM+n9v56oXS0z4PZWIT1cWiZpYO/x3huu5Pkj HhdxaVSFl9HwOez1NMWx5LKekwwMvf6rHDUDRUzRBxDg9JyEvDOcMc5vPj57hDX1fzdx AuIN15EiMF+7Y2ku3LgKtLLhCgx8amyraeBbjI9ssfZUWUGitsK0yNvE+CL7uaolYQ6l drjoefoQGQFBnzfIMI3g+U+Bfv6Akpp1pNJ6Yo1h8DgQuCvmJIYSqQPjVltWFFx1UgUL udlA== X-Gm-Message-State: APjAAAV/L52eYfiUlbMHMEyLX0O7TM6BXKsNaKpOIYK0eIVw406O+A8b vO+lbG5tQUEYlSrDqGPG3d8= X-Google-Smtp-Source: APXvYqzFKXhBjZTODvaRaYjnssgMU/qh93dWuwrlF1daSaR72oohtXpNNgFalCsExTd4cIdV4rv50A== X-Received: by 2002:adf:f44e:: with SMTP id f14mr15047963wrp.290.1569079132443; Sat, 21 Sep 2019 08:18:52 -0700 (PDT) Received: from blackbox.darklights.net (p200300F133CE0B0028BAA8C744A6F562.dip0.t-ipconnect.de. [2003:f1:33ce:b00:28ba:a8c7:44a6:f562]) by smtp.googlemail.com with ESMTPSA id c6sm6003120wrb.60.2019.09.21.08.18.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Sep 2019 08:18:51 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, khilman@baylibre.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 4/6] clk: meson: meson8b: add the ddr_pll input for the audio clocks Date: Sat, 21 Sep 2019 17:18:33 +0200 Message-Id: <20190921151835.770263-5-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190921151835.770263-1-martin.blumenstingl@googlemail.com> References: <20190921151835.770263-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The two audio muxes cts_amclk_sel and cts_mclk_i958_sel use ddr_pll as input at index 0. Update the muxes to use clk_parent_data and add "ddr_pll" as input using clk_parent_data.fw_name because the DDR clock controller is actually separate from the main clock controller. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 34 ++++++++++++++-------------------- 1 file changed, 14 insertions(+), 20 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index fefb4b7185d0..3987f4ea7378 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -2429,28 +2429,25 @@ static struct clk_regmap meson8b_vdec_hevc = { }, }; -/* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */ -static const struct clk_hw *meson8b_cts_amclk_parent_hws[] = { - &meson8b_mpll0.hw, - &meson8b_mpll1.hw, - &meson8b_mpll2.hw +static const struct clk_parent_data meson8b_cts_amclk_parent_data[] = { + { .fw_name = "ddr_pll", }, + { .hw = &meson8b_mpll0.hw, }, + { .hw = &meson8b_mpll1.hw, }, + { .hw = &meson8b_mpll2.hw, }, }; -static u32 meson8b_cts_amclk_mux_table[] = { 1, 2, 3 }; - static struct clk_regmap meson8b_cts_amclk_sel = { .data = &(struct clk_regmap_mux_data){ .offset = HHI_AUD_CLK_CNTL, .mask = 0x3, .shift = 9, - .table = meson8b_cts_amclk_mux_table, .flags = CLK_MUX_ROUND_CLOSEST, }, .hw.init = &(struct clk_init_data){ .name = "cts_amclk_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_cts_amclk_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_hws), + .parent_data = meson8b_cts_amclk_parent_data, + .num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_data), }, }; @@ -2488,28 +2485,25 @@ static struct clk_regmap meson8b_cts_amclk = { }, }; -/* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */ -static const struct clk_hw *meson8b_cts_mclk_i958_parent_hws[] = { - &meson8b_mpll0.hw, - &meson8b_mpll1.hw, - &meson8b_mpll2.hw +static const struct clk_parent_data meson8b_cts_mclk_i958_parent_data[] = { + { .fw_name = "ddr_pll", }, + { .hw = &meson8b_mpll0.hw, }, + { .hw = &meson8b_mpll1.hw, }, + { .hw = &meson8b_mpll2.hw, }, }; -static u32 meson8b_cts_mclk_i958_mux_table[] = { 1, 2, 3 }; - static struct clk_regmap meson8b_cts_mclk_i958_sel = { .data = &(struct clk_regmap_mux_data){ .offset = HHI_AUD_CLK_CNTL2, .mask = 0x3, .shift = 25, - .table = meson8b_cts_mclk_i958_mux_table, .flags = CLK_MUX_ROUND_CLOSEST, }, .hw.init = &(struct clk_init_data) { .name = "cts_mclk_i958_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_cts_mclk_i958_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_hws), + .parent_data = meson8b_cts_mclk_i958_parent_data, + .num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_data), }, }; From patchwork Sat Sep 21 15:18:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11155563 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 65BAA14DB for ; Sat, 21 Sep 2019 15:19:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4455F21A4C for ; Sat, 21 Sep 2019 15:19:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="KWRSBJVs" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2438225AbfIUPTF (ORCPT ); Sat, 21 Sep 2019 11:19:05 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:37997 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2438147AbfIUPSz (ORCPT ); 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[2003:f1:33ce:b00:28ba:a8c7:44a6:f562]) by smtp.googlemail.com with ESMTPSA id c6sm6003120wrb.60.2019.09.21.08.18.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Sep 2019 08:18:53 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, khilman@baylibre.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 5/6] ARM: dts: meson8: add the DDR clock controller Date: Sat, 21 Sep 2019 17:18:34 +0200 Message-Id: <20190921151835.770263-6-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190921151835.770263-1-martin.blumenstingl@googlemail.com> References: <20190921151835.770263-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main (HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the inputs for the audio clock muxes. Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson8.dtsi | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 4f59a4c8f036..257c1364864c 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -3,6 +3,7 @@ * Copyright 2014 Carlo Caione */ +#include #include #include #include @@ -195,6 +196,14 @@ #size-cells = <1>; ranges = <0x0 0xc8000000 0x8000>; + ddr_clkc: clock-controller@400 { + compatible = "amlogic,meson8-ddr-clkc"; + reg = <0x400 0x20>; + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + dmcbus: bus@6000 { compatible = "simple-bus"; reg = <0x6000 0x400>; @@ -455,8 +464,8 @@ &hhi { clkc: clock-controller { compatible = "amlogic,meson8-clkc"; - clocks = <&xtal>; - clock-names = "xtal"; + clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; + clock-names = "xtal", "ddr_pll"; #clock-cells = <1>; #reset-cells = <1>; }; From patchwork Sat Sep 21 15:18:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11155559 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9FC7916B1 for ; Sat, 21 Sep 2019 15:19:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7DA6F217F5 for ; Sat, 21 Sep 2019 15:19:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="jbSHNaXE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2438199AbfIUPS5 (ORCPT ); Sat, 21 Sep 2019 11:18:57 -0400 Received: from mail-wm1-f66.google.com ([209.85.128.66]:33621 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2438182AbfIUPS5 (ORCPT ); Sat, 21 Sep 2019 11:18:57 -0400 Received: by mail-wm1-f66.google.com with SMTP id r17so11623708wme.0; Sat, 21 Sep 2019 08:18:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ryY1C6V/Fnndw45BEkZbgWqU1CO6K4z5Y17d3HMNBz4=; b=jbSHNaXEeYn6hTwnob4r0cFK1tawMR7cK74NLvuSDg9K1Q+i9UN9MDMzyPNum1rg3u 3+Zlha3bTktCHxytNPYwWn53kVqaCHTgDo1L0cjl3wRSBAjIgHQkbY/BPedgCdfd+m9m JA6TQEeNuoNw7bN0LVMoBnGgKOo5DmAPmrUPyP62jHCdLV+yumcWomD7WbfFLICNTIMl wOB/n0k8in4sKU/Ftefui+uGHNdWEvAMHFdPXAUmYacmj0L6jE0PslD3GpFqk++rcNG6 8ykti5lqNIIgp4jx0YLk0usYFU/nzwdGlTbqK72AnwmeBGV/FbdcGgiN58hjVeP3yfjM XSnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ryY1C6V/Fnndw45BEkZbgWqU1CO6K4z5Y17d3HMNBz4=; b=o2dAXi0lZ2SbqSq9U5qnP3uRVuFwPHMmjHL43wzVfpNrnGe4NIqZod1FY6FH/v/kPh /zzGpxwokbe+boXQfzIfr099Y+sHvQ6HjzF9Bc/kZgVPbPaeYdT/5cv2nloQ8w5s5h/p +9Ql+PGAcbaHpuCW+rFandoZO470g7phaUbMvHm8nMW2nqYNPEV/2C19woyG1wAcv7gO gt+7TVkAb8HX3u8r/us72MgdwE/FA/NhWD95aajOfA6IdOPdDb4PDpfGNbab1tFSxCtb OR3F7BMqw4P5zr2slwZTeQ8aelUzG/96GpHvVFtwHzpKl3ty0+nNnPLfCywZulQQIbdl CmLw== X-Gm-Message-State: APjAAAUuXXZkQCzNIstXrQf2Gnl3wEBQWqmmELW8iyiX9Sp9VCmi9bLE Auznc1RkMZ/vgfQMn49DkZM= X-Google-Smtp-Source: APXvYqzBWlO/a1o7buEzHL4fJp72XmAnFcohUCZlv806SiF/cVfQ3RUOZrNiEOVvXdyUtLEN+b6d2A== X-Received: by 2002:a05:600c:217:: with SMTP id 23mr7868145wmi.76.1569079134900; Sat, 21 Sep 2019 08:18:54 -0700 (PDT) Received: from blackbox.darklights.net (p200300F133CE0B0028BAA8C744A6F562.dip0.t-ipconnect.de. [2003:f1:33ce:b00:28ba:a8c7:44a6:f562]) by smtp.googlemail.com with ESMTPSA id c6sm6003120wrb.60.2019.09.21.08.18.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Sep 2019 08:18:54 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, khilman@baylibre.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 6/6] ARM: dts: meson8b: add the DDR clock controller Date: Sat, 21 Sep 2019 17:18:35 +0200 Message-Id: <20190921151835.770263-7-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190921151835.770263-1-martin.blumenstingl@googlemail.com> References: <20190921151835.770263-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main (HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the inputs for the audio clock muxes. Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson8b.dtsi | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 1934666ff60f..8ac8bdfaf58f 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -4,6 +4,7 @@ * Author: Carlo Caione */ +#include #include #include #include @@ -172,6 +173,14 @@ #size-cells = <1>; ranges = <0x0 0xc8000000 0x8000>; + ddr_clkc: clock-controller@400 { + compatible = "amlogic,meson8b-ddr-clkc"; + reg = <0x400 0x20>; + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + dmcbus: bus@6000 { compatible = "simple-bus"; reg = <0x6000 0x400>; @@ -434,8 +443,8 @@ &hhi { clkc: clock-controller { compatible = "amlogic,meson8-clkc"; - clocks = <&xtal>; - clock-names = "xtal"; + clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; + clock-names = "xtal", "ddr_pll"; #clock-cells = <1>; #reset-cells = <1>; };