From patchwork Wed Oct 2 06:04:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11170393 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 029AA16B1 for ; Wed, 2 Oct 2019 06:05:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C891B21783 for ; Wed, 2 Oct 2019 06:05:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="IeouzOu8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727381AbfJBGFH (ORCPT ); Wed, 2 Oct 2019 02:05:07 -0400 Received: from mailout1.w1.samsung.com ([210.118.77.11]:45464 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727111AbfJBGFH (ORCPT ); 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Wed, 2 Oct 2019 06:05:03 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, robh+dt@kernel.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v3 1/4] dt-bindings: memory-controllers: Add Exynos5422 DMC interrupts description Date: Wed, 2 Oct 2019 08:04:52 +0200 Message-Id: <20191002060455.3834-2-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191002060455.3834-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSa0hTYRjHe3d2tjNzdjZFX8ySJkIaalbQm4oV+GEggoF9MSRXHlRyTnfU tAtNKyuvpaYiXrFQ1so1h5dpUs60sjYlvKCJMgPzNiLNLt7a8Uz69nv+z/95/g8vL4GJdbg7 kZicRimTZUkSngO3rf+PyY8MLYs5OrkehF5WtuBobHUOR3V9JhwVzy5iyGzW8tGnnCU+mlB5 IN3sKI4+G6p5aKWwD6BKcw8HPe+b4qOnY8McNJndzEN3X/XxkXHpHo7W3lnAGZFUU6sB0s6q Kb5Up37Ak7Y+uSV9Y+3mSIv0aiBd0R2M5Ec7hMRRSYkZlDIgNNYhwazdBCmPhZk/5r/gKlCw Nw8ICEiegOtrZsCwmGwGsPWFnOVVANeGwvOAg41XAOxq78Z2B7Y+ZnPZRhOAGvVfwBa2iZrl SVtBEDzSH3aoU5kBF7LRtskYzXgwso0DZ9RrOONxJuNghVbGeLikN9zM6eIyLCRDoX5ilMuG ecJn2tc7wQLyNLROj2PMHkia+HBmJJvPmsKgpbYFZ9kZLgzo7boH3O6s47BMQ1VhA2D5Bpwt rrF7gqFxYHjnHoz0gS2GAFY+CzsXRzFGhqQTHF8WMTJmw5K2CrsshPdzxaz7MNQXDNmDXGGT pty+XAq3cmo57OuUAFhXr8IeAs+q/2H1AKiBG5VOy+Mp+ngyddWflsnp9OR4/8sKuQ7YftLg 1sDPDtCzcakXkASQOArHo0pjxLgsg86S9wJIYBIXYchGSYxYGCfLukYpFReV6UkU3Qv2E1yJ m/D6npkLYjJelkZdoagUSrnb5RACdxWINM63lsUKsI6wNNdHXjedqlwHR879PlkWgb0nKXFU 2rE7fop8b5NvWPt319QFUbmo4YhiJGN+wfqhwOz1Ldd4PtbCKWssnYvoCvfJ91pJsvhgC/uU KtGpiWaB1q0l+ICh4au12EKP/Uq8jZky6zVtHY791YHTh0xBRX7bbw0SLp0gC/TFlLTsHyyz o/NFAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprOIsWRmVeSWpSXmKPExsVy+t/xe7oCdlNiDWZMVLDYOGM9q8X1L89Z LeYfOcdq0f/4NbPF+fMb2C3ONr1ht7jVIGOx6fE1VovLu+awWXzuPcJoMeP8PiaLtUfuslss vX6RyeJ24wo2i9a9R9gtDr9pZ7X4duIRo4Ogx5p5axg9ds66y+6xaVUnm8fmJfUeB9/tYfLo 27KK0ePzJrkA9ig9m6L80pJUhYz84hJbpWhDCyM9Q0sLPSMTSz1DY/NYKyNTJX07m5TUnMyy 1CJ9uwS9jPMb/jIWTOWt+PTyDmsDYw93FyMnh4SAicS/M40sXYxcHEICSxklGvf+Z4NIiElM 2redHcIWlvhzrYsNougTo0TfouWsXYwcHGwCehI7VhWCxEUEljNKHFv1lhnEYRY4wiRxdPU1 RpBuYYEkiVkrj7GC2CwCqhJ/m3azgNi8AnYSW25dY4HYIC+xesMBZhCbU8Be4t39G8wgC4SA av6fqZzAyLeAkWEVo0hqaXFuem6xoV5xYm5xaV66XnJ+7iZGYKRsO/Zz8w7GSxuDDzEKcDAq 8fA2BE2OFWJNLCuuzD3EKMHBrCTCa/NnUqwQb0piZVVqUX58UWlOavEhRlOgmyYyS4km5wOj OK8k3tDU0NzC0tDc2NzYzEJJnLdD4GCMkEB6YklqdmpqQWoRTB8TB6dUA2NsaKRo8ib9+66S X/b07TM7/6Hh641H69efeB2aa5v2fkbyrqY3jwwWaqUGBoYcbjvUKsZ29CWPFIe+d9h9Ga70 v62fhLWr7Tw337p8yu7VWY7HjsZpHAdZlvC9Xb6cK3bPlbIVjUqty47e+Kz/v6/wyct/F87a dacodC+75muf3hG1gN057L0SS3FGoqEWc1FxIgDSu1YsqgIAAA== X-CMS-MailID: 20191002060504eucas1p2f023677bb85a7f6a1efebf891e8d81df X-Msg-Generator: CA X-RootMTR: 20191002060504eucas1p2f023677bb85a7f6a1efebf891e8d81df X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20191002060504eucas1p2f023677bb85a7f6a1efebf891e8d81df References: <20191002060455.3834-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add description for optional interrupt lines. It provides a new operation mode, which uses internal performance counters interrupt when overflow. This is more reliable than using default polling mode implemented in devfreq. Signed-off-by: Lukasz Luba --- .../bindings/memory-controllers/exynos5422-dmc.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt index 02aeb3b5a820..e2434cac4858 100644 --- a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt @@ -31,6 +31,14 @@ Required properties for DMC device for Exynos5422: The register offsets are in the driver code and specyfic for this SoC type. +Optional properties for DMC device for Exynos5422: +- interrupt-parent : The parent interrupt controller. +- interrupts : Contains the IRQ line numbers for the DMC internal performance + event counters in DREX0 and DREX1 channels. Align with specification of the + interrupt line(s) in the interrupt-parent controller. +- interrupt-names : IRQ names "drex_0" and "drex_1", the order should be the + same as in the 'interrupts' list above. + Example: ppmu_dmc0_0: ppmu@10d00000 { @@ -70,4 +78,7 @@ Example: device-handle = <&samsung_K3QF2F20DB>; vdd-supply = <&buck1_reg>; samsung,syscon-clk = <&clock>; + interrupt-parent = <&combiner>; + interrupts = <16 0>, <16 1>; + interrupt-names = "drex_0", "drex_1"; }; From patchwork Wed Oct 2 06:04:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11170399 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CADA216B1 for ; Wed, 2 Oct 2019 06:05:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A917D21906 for ; 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Wed, 2 Oct 2019 06:05:05 +0000 (GMT) X-AuditID: cbfec7f5-4ddff70000001116-a2-5d943e110fc0 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id FE.14.04166.11E349D5; Wed, 2 Oct 2019 07:05:05 +0100 (BST) Received: from AMDC3778.digital.local (unknown [106.120.51.20]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20191002060504eusmtip22e10129d7ab4a3a21f1dcfc74dff71c9~Jv1If9uHN3226032260eusmtip2f; Wed, 2 Oct 2019 06:05:04 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, robh+dt@kernel.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v3 2/4] ARM: dts: exynos: Add interrupt to DMC controller in Exynos5422 Date: Wed, 2 Oct 2019 08:04:53 +0200 Message-Id: <20191002060455.3834-3-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191002060455.3834-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSfUhTYRTGe3d3d6/m4jojD6UJo8CCNLHiDXUVCY0IKrA/UlbOvE3JTdtV 0wqafarlB/Zly7Qw0eZCm8Om+dVcTjFboqQUUWmYlBoxXYitcl6t/57znN95n8PhpQlJPbma Ttaks1qNMkUq8hY2ds06NklkNxSb9fvwk9I6Eg9NfyFxhe0ViYtGvxHY4aincN/5CQq/1QVg 0+gbEg80l4mws8CGcKmjTYAf295TuGqoX4Df5dSI8KVWG4U7J66Q2NU9gnb6yo3lRiRv0r+n 5CZDnkje8PCc/PlUi0BeaDYgudO09gAV6x2ZyKYkZ7LaUFm8d9Ll9glRmovKqq3ooXSoR5SP vGhgtkBNlY3KR960hKlB0Np1l+SLaQSzOWVCvnAi6Cl1oKWRIptRxDeqETjqB4X/Rp4a7UQ+ omkREwIWw0nPwEqmEoGrM9bDEEyjAD4aXKSH8WMOQ3GXzCOFzHoo7KU8UszIwD0YxkcFQW19 B+HRXswOmPowTHheAcZKgb7tGsFD0eA2Dyzu5gdf7WaK1wHwp6lCwGsOdAUPFpmzMFp0b5GJ gE57/8I2BLMB6ppDeXsXjJUPL9jArIDhSV+PTczLksbbBG+LIfeyhKeDwXzt9WLQKqg23qJ4 RA6TN8P505QgGH/RTRSjIP3/rPsIGZA/m8GpVSwXrmFPhXBKNZehUYUcS1Wb0Pw/6v1tn7Gg tl8JVsTQSOojHo65rpCQykwuW21FQBPSleLIXyUKiThRmX2a1aYe1WaksJwVraGFUn/xmWUf 4ySMSpnOnmDZNFa71BXQXqt1iP4cY8Fn9B2zCbRTMWcy9oxYrmqOfB/Xpgfun0skfI7T96Xr VC+tyO6OeqTdFmF/tn3H3rzczJGauIvxdYa5zGb3aLilZffZnPzAPsXBnyZcEtX4bS5i8E5W 0Lr1/YdapyUNJ4J1ipn4jrGtldC9XLGHaA/8cSGaEjgV0Y5PUiGXpAzbSGg55V8/NAtnQwMA AA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprKIsWRmVeSWpSXmKPExsVy+t/xe7qCdlNiDSa/E7fYOGM9q8X1L89Z LeYfOcdq0f/4NbPF+fMb2C3ONr1ht7jVIGOx6fE1VovLu+awWXzuPcJoMeP8PiaLtUfuslss vX6RyeJ24wo2i9a9R9gtDr9pZ7X4duIRo4Ogx5p5axg9ds66y+6xaVUnm8fmJfUeB9/tYfLo 27KK0ePzJrkA9ig9m6L80pJUhYz84hJbpWhDCyM9Q0sLPSMTSz1DY/NYKyNTJX07m5TUnMyy 1CJ9uwS9jLb9b9gKvrFXrJ5/kr2B8SRbFyMnh4SAiUT/kTVANheHkMBSRolTJ74yQiTEJCbt 284OYQtL/LnWBVX0iVHi788bQAkODjYBPYkdqwpB4iICyxkljq16ywziMAscYZI4uvoa2CRh gXCJS3vbmEEaWARUJfpOg/XyCthJ/L1iCDFfXmL1hgPMIDangL3Eu/s3wKqFgEr+n6mcwMi3 gJFhFaNIamlxbnpusaFecWJucWleul5yfu4mRmCUbDv2c/MOxksbgw8xCnAwKvHwNgRNjhVi TSwrrsw9xCjBwawkwmvzZ1KsEG9KYmVValF+fFFpTmrxIUZToIsmMkuJJucDIzivJN7Q1NDc wtLQ3Njc2MxCSZy3Q+BgjJBAemJJanZqakFqEUwfEwenVANjp966Ta9DDvvtcmRVsWd9ckVC dc1ZUT3Xjz/+yTyUnKG37JJW8+/VXz5EF3AssRY5Ge1oaX70Wfja+b/NTh2PPTwziCXxYvid W+YPbm5/xNr+h81nya5ne0zZrwksnXmdzVQ47qhnc0WFihRn0NNTTgwNj7Q0j/ae1yk/mrZY I6xqXsXa1qnySizFGYmGWsxFxYkA3EL4bKgCAAA= X-CMS-MailID: 20191002060505eucas1p2efd80ccde8c728973df8d932580cd58b X-Msg-Generator: CA X-RootMTR: 20191002060505eucas1p2efd80ccde8c728973df8d932580cd58b X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20191002060505eucas1p2efd80ccde8c728973df8d932580cd58b References: <20191002060455.3834-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add interrupt to Dynamic Memory Controller in Exynos5422 and Odroid XU3-family boards. It will be used instead of devfreq polling mode governor. The interrupt is connected to performance counters private for DMC, which might track utilisation of the memory channels. Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5420.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 92c5e0d8a824..98f6c71f57d8 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -240,6 +240,9 @@ dmc: memory-controller@10c20000 { compatible = "samsung,exynos5422-dmc"; reg = <0x10c20000 0x100>, <0x10c30000 0x100>; + interrupt-parent = <&combiner>; + interrupts = <16 0>, <16 1>; + interrupt-names = "drex_0", "drex_1"; clocks = <&clock CLK_FOUT_SPLL>, <&clock CLK_MOUT_SCLK_SPLL>, <&clock CLK_FF_DOUT_SPLL2>, From patchwork Wed Oct 2 06:04:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11170387 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F3DC617EE for ; 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Wed, 2 Oct 2019 06:05:06 +0000 (GMT) X-AuditID: cbfec7f4-afbff700000010d5-60-5d943e126bc1 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 60.24.04166.21E349D5; Wed, 2 Oct 2019 07:05:06 +0100 (BST) Received: from AMDC3778.digital.local (unknown [106.120.51.20]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20191002060505eusmtip2fac233f17aa68714e6d59812cf48e561~Jv1JTt1rw0033000330eusmtip2D; Wed, 2 Oct 2019 06:05:05 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, robh+dt@kernel.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v3 3/4] ARM: dts: exynos: map 0x10000 SFR instead of 0x100 in DMC Exynos5422 Date: Wed, 2 Oct 2019 08:04:54 +0200 Message-Id: <20191002060455.3834-4-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191002060455.3834-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTYRju29m5aE6OU/RzWeIgqTCtVPpKMwOLBUIRQWBorTyoeN9xliU0 Q8tJanhJkUxNTZuGtnTeo+ZISdSGoJKJtx+B99S85LB22rH+Pe9zeZ+Xj4/CxM24hIqKS2IU cfIYKWEt1H3aGjgqDigIPaZa8UBvixtwNLL2HUdlhgEc5c7MYWhwsJFE/Q/nSfRV5YK0M8M4 Gmp/TqDVbANAxYPvBeiNYZxE1SNGARpLqyVQRpeBRN3zj3G03jsNAu1k9S/qgaytZJyUaTVq Qvau6oHs42KnQJbTpAGyVe2By2SItX84ExOVzCi8Am5aRy4vpYOEafLuq8KXhAp0EFnAioK0 DzROVZixNSWmawHsn1ELLMMagNOZOcAyrJoVU7pgN7Ixm867agDc2NaDf5FldatZoSiC9oSt mkQu4EBXArjeHcJ5MFongJOadZwT7OkwmPGr6+8hQvogzBidEHJYRAfAXpNJaGlzhXWNHzAO W9Fn4eLEKMYtgvRnElY3bwOLKQiub47wAXs429NEWrAL/N1Wxp/NQlV2Be9PhTO5pbzHD3b3 GHHuaIw+DBvavSz0OWjoXMY4GtK2cHTBjqMxM8zTFfG0CGY+Elvch2DTky98kSOsqX/GL5fB qpYS/q3yAOwdLwBPgWvJ/7JyADTAiVGysREMeyKOuePJymNZZVyE5+34WC0wf6a+nZ61VtBu uqUHNAWkNiLVlfxQMS5PZlNi9QBSmNRB5G/KCxWLwuUp9xhF/A2FMoZh9WAfJZQ6ie7vmbwu piPkSUw0wyQwil1VQFlJVEAZovFounjB9/VydN+Wd6Bv3cCUW4X+p6MkJssQpM1vWEgpLAr4 Id3xVbc0EO6baZSR6Kg0OQ+X0rZGZfeKtzu2oPZ1XOr7VpOTOLd36FLQ+ZMFY7pKKu/qmVSv 0hzJ6fnyoWD9QovfoI9XsMkpNHpKnKQANqfcnPfLr4UZaqVCNlJ+/AimYOV/AER5huVIAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprOIsWRmVeSWpSXmKPExsVy+t/xe7pCdlNiDVb85rfYOGM9q8X1L89Z LeYfOcdq0f/4NbPF+fMb2C3ONr1ht7jVIGOx6fE1VovLu+awWXzuPcJoMeP8PiaLtUfuslss vX6RyeJ24wo2i9a9R9gtDr9pZ7X4duIRo4Ogx5p5axg9ds66y+6xaVUnm8fmJfUeB9/tYfLo 27KK0ePzJrkA9ig9m6L80pJUhYz84hJbpWhDCyM9Q0sLPSMTSz1DY/NYKyNTJX07m5TUnMyy 1CJ9uwS9jA/vWxgLHrFXLJu6iK2BcTdbFyMnh4SAicT3Vy1MXYxcHEICSxklJv39zgyREJOY tG87O4QtLPHnWhcbRNEnRomdP1+zdDFycLAJ6EnsWFUIEhcRWM4ocWzVW2YQh1ngCJPE0dXX GEG6hQViJJb8/gm2jkVAVaL1xn0WEJtXwE7ixJ8/LBAb5CVWbzgAtplTwF7i3f0bzCALhIBq /p+pnMDIt4CRYRWjSGppcW56brGhXnFibnFpXrpecn7uJkZgpGw79nPzDsZLG4MPMQpwMCrx 8DYETY4VYk0sK67MPcQowcGsJMJr82dSrBBvSmJlVWpRfnxRaU5q8SFGU6CbJjJLiSbnA6M4 ryTe0NTQ3MLS0NzY3NjMQkmct0PgYIyQQHpiSWp2ampBahFMHxMHp1QDo6igfm/kRsUAR9vi /301pryb/t2Jq9j/fdUBgZqpre8ZBJ+2p+7p9ahWDXoySeBv0pNkka1u58MsVrdK9HZ9/P5y q4GhoEQ/Z2yD43+Nfp1FPxnsUj3Wlr99Ov38lYLnkg4PVm3iWl8hu+xOvcSTmLDmLuOeHet+ M3o1qLgeFG24NGmb9Ku/SizFGYmGWsxFxYkAP+hTaKoCAAA= X-CMS-MailID: 20191002060506eucas1p28c9670128f5adfb628d7e84ce55c6e60 X-Msg-Generator: CA X-RootMTR: 20191002060506eucas1p28c9670128f5adfb628d7e84ce55c6e60 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20191002060506eucas1p28c9670128f5adfb628d7e84ce55c6e60 References: <20191002060455.3834-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org There is a need to access registers at address offset near 0x10000. These registers are private DMC performance counters, which might be used as interrupt trigger when overflow. Potential usage is to skip polling in devfreq framework and switch to interrupt managed bandwidth control. Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5420.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 98f6c71f57d8..c829bbdc5711 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -239,7 +239,7 @@ dmc: memory-controller@10c20000 { compatible = "samsung,exynos5422-dmc"; - reg = <0x10c20000 0x100>, <0x10c30000 0x100>; + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; interrupt-parent = <&combiner>; interrupts = <16 0>, <16 1>; interrupt-names = "drex_0", "drex_1"; From patchwork Wed Oct 2 06:04:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11170389 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1BE1017EE for ; Wed, 2 Oct 2019 06:05:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DC0CA2190F for ; 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Wed, 2 Oct 2019 06:05:07 +0000 (GMT) X-AuditID: cbfec7f4-ae1ff700000010d5-65-5d943e1321d6 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id AD.EB.04117.31E349D5; Wed, 2 Oct 2019 07:05:07 +0100 (BST) Received: from AMDC3778.digital.local (unknown [106.120.51.20]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20191002060506eusmtip29e375027648baa6b08fd56e4986441be~Jv1KHo0he2638126381eusmtip28; Wed, 2 Oct 2019 06:05:06 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, robh+dt@kernel.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v3 4/4] memory: samsung: exynos5422-dmc: Add support for interrupt from performance counters Date: Wed, 2 Oct 2019 08:04:55 +0200 Message-Id: <20191002060455.3834-5-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191002060455.3834-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrCKsWRmVeSWpSXmKPExsWy7djP87rCdlNiDX58kbPYOGM9q8X1L89Z LeYfOcdq0f/4NbPF+fMb2C3ONr1ht7jVIGOx6fE1VovLu+awWXzuPcJoMeP8PiaLtUfuslss vX6RyeJ24wo2i9a9R9gtDr9pZ7X4duIRo4Ogx5p5axg9ds66y+6xaVUnm8fmJfUeB9/tYfLo 27KK0ePzJrkA9igum5TUnMyy1CJ9uwSujCcb1jMXXC6p6Pn8mrGBcX58FyMnh4SAicS1pfOY uhi5OIQEVjBKLJ21jB3C+cIo8XzLLqjMZ0aJ2ft2sMC0PHxxmg0isZxRYvutpyxwLRMPLgdy ODjYBPQkdqwqBGkQEVjMKPHtcBRIDbPANiaJB6u+sYIkhAXyJPbufAFmswioSsw9fZMRxOYV sJNYfPEuG8Q2eYnVGw4wg9icAvYS7+7fYIaIn2KX2PDYBMJ2kXjT/IoVwhaWeHV8CzuELSNx enIP1NXFEg29Cxkh7BqJx/1zoWqsJQ4fv8gKcjOzgKbE+l36EGFHiWf7usBekRDgk7jxVhAk zAxkTto2nRkizCvR0SYEUa0hsaXnAhOELSaxfM00qOEeEv/ftDJDQmcSo8TpXd/ZJjDKz0JY toCRcRWjeGppcW56arFRXmq5XnFibnFpXrpecn7uJkZgWjr97/iXHYy7/iQdYhTgYFTi4W0I mhwrxJpYVlyZe4hRgoNZSYTX5s+kWCHelMTKqtSi/Pii0pzU4kOM0hwsSuK81QwPooUE0hNL UrNTUwtSi2CyTBycUg2MDBX/OplSlt0UyX75YPld5YVVXhM/PJjGwzT7yvlFC2JPKF/4OGnO ha3udy4JOWupbVDn+vVg+lXv71lhJwtm+wtN7UrcvlNLf1WItMgTBwfNR0XHhVr3LvKUXTKR 5dzdnyEG09qKOqKPrDfeIK+5s6LqwVn9KXzMMp8tN83p6O58sfK0N4dhohJLcUaioRZzUXEi AEuVMRxHAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprGIsWRmVeSWpSXmKPExsVy+t/xe7rCdlNiDeZsYLXYOGM9q8X1L89Z LeYfOcdq0f/4NbPF+fMb2C3ONr1ht7jVIGOx6fE1VovLu+awWXzuPcJoMeP8PiaLtUfuslss vX6RyeJ24wo2i9a9R9gtDr9pZ7X4duIRo4Ogx5p5axg9ds66y+6xaVUnm8fmJfUeB9/tYfLo 27KK0ePzJrkA9ig9m6L80pJUhYz84hJbpWhDCyM9Q0sLPSMTSz1DY/NYKyNTJX07m5TUnMyy 1CJ9uwS9jCcb1jMXXC6p6Pn8mrGBcX58FyMnh4SAicTDF6fZuhi5OIQEljJKrP68kQkiISYx ad92dghbWOLPtS6ook+MEs8n/wdyODjYBPQkdqwqBImLCCxnlDi26i0ziMMscIRJ4ujqa4wg RcICORLTG4xABrEIqErMPX2TEcTmFbCTWHzxLhvEAnmJ1RsOMIPYnAL2Eu/u32AGaRUCqvl/ pnICI98CRoZVjCKppcW56bnFRnrFibnFpXnpesn5uZsYgXGy7djPLTsYu94FH2IU4GBU4uFt CJocK8SaWFZcmXuIUYKDWUmE1+bPpFgh3pTEyqrUovz4otKc1OJDjKZAN01klhJNzgfGcF5J vKGpobmFpaG5sbmxmYWSOG+HwMEYIYH0xJLU7NTUgtQimD4mDk6pBkZ1vmccx+ZrW+RartdI Vjk996LSw4SqoGzz4x/N3C9/mvA0LDNjxev+76/v3vs23bbHKSGSu1V9puYjhXkJjL/2X3Pc vd7a5bKkU0hxu+Sp4z7ny5OC9VN6TG/r3LA4NvH9/erTLJw75u/fKPAqnEvDg7Hh6Ref+ruP T60Tfc6iJvWqf9aLi6JKLMUZiYZazEXFiQDpFegrqQIAAA== X-CMS-MailID: 20191002060507eucas1p169394dec59f010e112eb38d83e3fb8ba X-Msg-Generator: CA X-RootMTR: 20191002060507eucas1p169394dec59f010e112eb38d83e3fb8ba X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20191002060507eucas1p169394dec59f010e112eb38d83e3fb8ba References: <20191002060455.3834-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce a new interrupt driven mechanism for managing speed of the memory controller. The interrupts are generated due to performance counters overflow. The performance counters might track memory reads, writes, transfers, page misses, etc. In the basic algorithm tracking read transfers and calculating memory pressure should be enough to skip polling mode in devfreq. Signed-off-by: Lukasz Luba --- drivers/memory/samsung/exynos5422-dmc.c | 345 ++++++++++++++++++++++-- 1 file changed, 320 insertions(+), 25 deletions(-) diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c index 0fe5f2186139..47dbf6d1789f 100644 --- a/drivers/memory/samsung/exynos5422-dmc.c +++ b/drivers/memory/samsung/exynos5422-dmc.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -35,6 +36,61 @@ #define USE_BPLL_TIMINGS (0) #define EXYNOS5_AREF_NORMAL (0x2e) +#define DREX_PPCCLKCON (0x0130) +#define DREX_PEREV2CONFIG (0x013c) +#define DREX_PMNC_PPC (0xE000) +#define DREX_CNTENS_PPC (0xE010) +#define DREX_CNTENC_PPC (0xE020) +#define DREX_INTENS_PPC (0xE030) +#define DREX_INTENC_PPC (0xE040) +#define DREX_FLAG_PPC (0xE050) +#define DREX_PMCNT2_PPC (0xE130) + +/* + * A value for register DREX_PMNC_PPC which should be written to reset + * the cycle counter CCNT (a reference wall clock). It sets zero to the + * CCNT counter. + */ +#define CC_RESET BIT(2) + +/* + * A value for register DREX_PMNC_PPC which does the reset of all performance + * counters to zero. + */ +#define PPC_COUNTER_RESET BIT(1) + +/* + * Enables all configured counters (including cycle counter). The value should + * be written to the register DREX_PMNC_PPC. + */ +#define PPC_ENABLE BIT(0) + +/* A value for register DREX_PPCCLKCON which enables performance events clock. + * Must be written before first access to the performance counters register + * set, otherwise it could crash. + */ +#define PEREV_CLK_EN BIT(0) + +/* + * Values which are used to enable counters, interrupts or configure flags of + * the performance counters. They configure counter 2 and cycle counter. + */ +#define PERF_CNT2 BIT(2) +#define PERF_CCNT BIT(31) + +/* + * Performance event types which are used for setting the preferred event + * to track in the counters. + * There is a set of different types, the values are from range 0 to 0x6f. + * These settings should be written to the configuration register which manages + * the type of the event (register DREX_PEREV2CONFIG). + */ +#define READ_TRANSFER_CH0 (0x6d) +#define READ_TRANSFER_CH1 (0x6f) + +#define PERF_COUNTER_START_VALUE 0xff000000 +#define PERF_EVENT_UP_DOWN_THRESHOLD 900000000ULL + /** * struct dmc_opp_table - Operating level desciption * @@ -85,6 +141,10 @@ struct exynos5_dmc { struct clk *mout_mx_mspll_ccore_phy; struct devfreq_event_dev **counter; int num_counters; + u64 last_overflow_ts[2]; + unsigned long load; + unsigned long total; + bool in_irq_mode; }; #define TIMING_FIELD(t_name, t_bit_beg, t_bit_end) \ @@ -653,6 +713,173 @@ static int exynos5_counters_get(struct exynos5_dmc *dmc, return 0; } +/** + * exynos5_dmc_start_perf_events() - Setup and start performance event counters + * @dmc: device for which the counters are going to be checked + * @beg_value: initial value for the counter + * + * Function which enables needed counters, interrupts and sets initial values + * then starts the counters. + */ +static void exynos5_dmc_start_perf_events(struct exynos5_dmc *dmc, + u32 beg_value) +{ + /* Enable interrupts for counter 2 */ + writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENS_PPC); + writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENS_PPC); + + /* Enable counter 2 and CCNT */ + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENS_PPC); + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENS_PPC); + + /* Clear overflow flag for all counters */ + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC); + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC); + + /* Reset all counters */ + writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi0 + DREX_PMNC_PPC); + writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi1 + DREX_PMNC_PPC); + + /* + * Set start value for the counters, the number of samples that + * will be gathered is calculated as: 0xffffffff - beg_value + */ + writel(beg_value, dmc->base_drexi0 + DREX_PMCNT2_PPC); + writel(beg_value, dmc->base_drexi1 + DREX_PMCNT2_PPC); + + /* Start all counters */ + writel(PPC_ENABLE, dmc->base_drexi0 + DREX_PMNC_PPC); + writel(PPC_ENABLE, dmc->base_drexi1 + DREX_PMNC_PPC); +} + +/** + * exynos5_dmc_perf_events_calc() - Calculate utilization + * @dmc: device for which the counters are going to be checked + * @diff_ts: time between last interrupt and current one + * + * Function which calculates needed utilization for the devfreq governor. + * It prepares values for 'busy_time' and 'total_time' based on elapsed time + * between interrupts, which approximates utilization. + */ +static void exynos5_dmc_perf_events_calc(struct exynos5_dmc *dmc, u64 diff_ts) +{ + /* + * This is a simple algorithm for managing traffic on DMC. + * When there is almost no load the counters overflow every 4s, + * no mater the DMC frequency. + * The high load might be approximated using linear function. + * Knowing that, simple calculation can provide 'busy_time' and + * 'total_time' to the devfreq governor which picks up target + * frequency. + * We want a fast ramp up and slow decay in frequency change function. + */ + if (diff_ts < PERF_EVENT_UP_DOWN_THRESHOLD) { + /* + * Set higher utilization for the simple_ondemand governor. + * The governor should increase the frequency of the DMC. + */ + dmc->load = 70; + dmc->total = 100; + } else { + /* + * Set low utilization for the simple_ondemand governor. + * The governor should decrease the frequency of the DMC. + */ + dmc->load = 35; + dmc->total = 100; + } + + dev_dbg(dmc->dev, "diff_ts=%llu\n", diff_ts); +} + +/** + * exynos5_dmc_perf_events_check() - Checks the status of the counters + * @dmc: device for which the counters are going to be checked + * + * Function which is called from threaded IRQ to check the counters state + * and to call approximation for the needed utilization. + */ +static void exynos5_dmc_perf_events_check(struct exynos5_dmc *dmc) +{ + u32 val; + u64 diff_ts, ts; + + ts = ktime_get_ns(); + + /* Stop all counters */ + writel(0, dmc->base_drexi0 + DREX_PMNC_PPC); + writel(0, dmc->base_drexi1 + DREX_PMNC_PPC); + + /* Check the source in interrupt flag registers (which channel) */ + val = readl(dmc->base_drexi0 + DREX_FLAG_PPC); + if (val) { + diff_ts = ts - dmc->last_overflow_ts[0]; + dmc->last_overflow_ts[0] = ts; + dev_dbg(dmc->dev, "drex0 0xE050 val= 0x%08x\n", val); + } else { + val = readl(dmc->base_drexi1 + DREX_FLAG_PPC); + diff_ts = ts - dmc->last_overflow_ts[1]; + dmc->last_overflow_ts[1] = ts; + dev_dbg(dmc->dev, "drex1 0xE050 val= 0x%08x\n", val); + } + + exynos5_dmc_perf_events_calc(dmc, diff_ts); + + exynos5_dmc_start_perf_events(dmc, PERF_COUNTER_START_VALUE); +} + +/** + * exynos5_dmc_enable_perf_events() - Enable performance events + * @dmc: device for which the counters are going to be checked + * + * Function which is setup needed environment and enables counters. + */ +static void exynos5_dmc_enable_perf_events(struct exynos5_dmc *dmc) +{ + u64 ts; + + /* Enable Performance Event Clock */ + writel(PEREV_CLK_EN, dmc->base_drexi0 + DREX_PPCCLKCON); + writel(PEREV_CLK_EN, dmc->base_drexi1 + DREX_PPCCLKCON); + + /* Select read transfers as performance event2 */ + writel(READ_TRANSFER_CH0, dmc->base_drexi0 + DREX_PEREV2CONFIG); + writel(READ_TRANSFER_CH1, dmc->base_drexi1 + DREX_PEREV2CONFIG); + + ts = ktime_get_ns(); + dmc->last_overflow_ts[0] = ts; + dmc->last_overflow_ts[1] = ts; + + /* Devfreq shouldn't be faster than initialization, play safe though. */ + dmc->load = 99; + dmc->total = 100; +} + +/** + * exynos5_dmc_disable_perf_events() - Disable performance events + * @dmc: device for which the counters are going to be checked + * + * Function which stops, disables performance event counters and interrupts. + */ +static void exynos5_dmc_disable_perf_events(struct exynos5_dmc *dmc) +{ + /* Stop all counters */ + writel(0, dmc->base_drexi0 + DREX_PMNC_PPC); + writel(0, dmc->base_drexi1 + DREX_PMNC_PPC); + + /* Disable interrupts for counter 2 */ + writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENC_PPC); + writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENC_PPC); + + /* Disable counter 2 and CCNT */ + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENC_PPC); + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENC_PPC); + + /* Clear overflow flag for all counters */ + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC); + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC); +} + /** * exynos5_dmc_get_status() - Read current DMC performance statistics. * @dev: device for which the statistics are requested @@ -669,18 +896,24 @@ static int exynos5_dmc_get_status(struct device *dev, unsigned long load, total; int ret; - ret = exynos5_counters_get(dmc, &load, &total); - if (ret < 0) - return -EINVAL; + if (dmc->in_irq_mode) { + stat->current_frequency = dmc->curr_rate; + stat->busy_time = dmc->load; + stat->total_time = dmc->total; + } else { + ret = exynos5_counters_get(dmc, &load, &total); + if (ret < 0) + return -EINVAL; - /* To protect from overflow in calculation ratios, divide by 1024 */ - stat->busy_time = load >> 10; - stat->total_time = total >> 10; + /* To protect from overflow, divide by 1024 */ + stat->busy_time = load >> 10; + stat->total_time = total >> 10; - ret = exynos5_counters_set_event(dmc); - if (ret < 0) { - dev_err(dev, "could not set event counter\n"); - return ret; + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dev, "could not set event counter\n"); + return ret; + } } return 0; @@ -712,7 +945,6 @@ static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq) * It provides to the devfreq framework needed functions and polling period. */ static struct devfreq_dev_profile exynos5_dmc_df_profile = { - .polling_ms = 500, .target = exynos5_dmc_target, .get_dev_status = exynos5_dmc_get_status, .get_cur_freq = exynos5_dmc_get_cur_freq, @@ -1108,6 +1340,24 @@ static inline int exynos5_dmc_set_pause_on_switching(struct exynos5_dmc *dmc) return 0; } +static irqreturn_t dmc_irq_thread(int irq, void *priv) +{ + int res; + struct exynos5_dmc *dmc = priv; + + mutex_lock(&dmc->df->lock); + + exynos5_dmc_perf_events_check(dmc); + + res = update_devfreq(dmc->df); + if (res) + dev_warn(dmc->dev, "devfreq failed with %d\n", res); + + mutex_unlock(&dmc->df->lock); + + return IRQ_HANDLED; +} + /** * exynos5_dmc_probe() - Probe function for the DMC driver * @pdev: platform device for which the driver is going to be initialized @@ -1125,6 +1375,7 @@ static int exynos5_dmc_probe(struct platform_device *pdev) struct device_node *np = dev->of_node; struct exynos5_dmc *dmc; struct resource *res; + int irq[2]; dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL); if (!dmc) @@ -1172,24 +1423,59 @@ static int exynos5_dmc_probe(struct platform_device *pdev) goto remove_clocks; } - ret = exynos5_performance_counters_init(dmc); + ret = exynos5_dmc_set_pause_on_switching(dmc); if (ret) { - dev_warn(dev, "couldn't probe performance counters\n"); + dev_warn(dev, "couldn't get access to PAUSE register\n"); goto remove_clocks; } - ret = exynos5_dmc_set_pause_on_switching(dmc); - if (ret) { - dev_warn(dev, "couldn't get access to PAUSE register\n"); - goto err_devfreq_add; + /* There is two modes in which the driver works: polling or IRQ */ + irq[0] = platform_get_irq_byname(pdev, "drex_0"); + irq[1] = platform_get_irq_byname(pdev, "drex_1"); + if (irq[0] > 0 && irq[1] > 0) { + ret = devm_request_threaded_irq(dev, irq[0], NULL, + dmc_irq_thread, IRQF_ONESHOT, + dev_name(dev), dmc); + if (ret) { + dev_err(dev, "couldn't grab IRQ\n"); + goto remove_clocks; + } + + ret = devm_request_threaded_irq(dev, irq[1], NULL, + dmc_irq_thread, IRQF_ONESHOT, + dev_name(dev), dmc); + if (ret) { + dev_err(dev, "couldn't grab IRQ\n"); + goto remove_clocks; + } + + /* + * Setup default thresholds for the devfreq governor. + * The values are chosen based on experiments. + */ + dmc->gov_data.upthreshold = 55; + dmc->gov_data.downdifferential = 5; + + exynos5_dmc_enable_perf_events(dmc); + + dmc->in_irq_mode = 1; + } else { + ret = exynos5_performance_counters_init(dmc); + if (ret) { + dev_warn(dev, "couldn't probe performance counters\n"); + goto remove_clocks; + } + + /* + * Setup default thresholds for the devfreq governor. + * The values are chosen based on experiments. + */ + dmc->gov_data.upthreshold = 30; + dmc->gov_data.downdifferential = 5; + + exynos5_dmc_df_profile.polling_ms = 500; } - /* - * Setup default thresholds for the devfreq governor. - * The values are chosen based on experiments. - */ - dmc->gov_data.upthreshold = 30; - dmc->gov_data.downdifferential = 5; dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile, DEVFREQ_GOV_SIMPLE_ONDEMAND, @@ -1200,12 +1486,18 @@ static int exynos5_dmc_probe(struct platform_device *pdev) goto err_devfreq_add; } + if (dmc->in_irq_mode) + exynos5_dmc_start_perf_events(dmc, PERF_COUNTER_START_VALUE); + dev_info(dev, "DMC initialized\n"); return 0; err_devfreq_add: - exynos5_counters_disable_edev(dmc); + if (dmc->in_irq_mode) + exynos5_dmc_disable_perf_events(dmc); + else + exynos5_counters_disable_edev(dmc); remove_clocks: clk_disable_unprepare(dmc->mout_bpll); clk_disable_unprepare(dmc->fout_bpll); @@ -1225,7 +1517,10 @@ static int exynos5_dmc_remove(struct platform_device *pdev) { struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev); - exynos5_counters_disable_edev(dmc); + if (dmc->in_irq_mode) + exynos5_dmc_disable_perf_events(dmc); + else + exynos5_counters_disable_edev(dmc); clk_disable_unprepare(dmc->mout_bpll); clk_disable_unprepare(dmc->fout_bpll);