From patchwork Thu Oct 3 20:18:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 11173259 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 921B81709 for ; Thu, 3 Oct 2019 20:18:52 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 69C6D20862 for ; Thu, 3 Oct 2019 20:18:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ucuy2RXZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 69C6D20862 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=wwwdotorg.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=XobfFdZtgfEgBI0tfEYErcqlgTjiBMQZ7iSK2Jk57j4=; b=ucuy2RXZXsdF44 1it4AKasdyegYONkigd9uMYhIE/egw0QPm2kJFkiSwTGxsbDReHK6BdhGnLi3iFT8M6bGQXOSm4Zk 7f2cynVppN1NltVmyTuVFADn9++SPGrUlLBsbHkaQ58QvQVwDC8h3c1ewVXN/bWXnA0ff5rZf25a5 o7zjBoRT+1RrWFJL8tZfBitsJ9R2kBLCaYNzJAA7PEstaQNQrtb2rq7qGHKo/er0pJz/n+Z7ApRSw JevPBSdR2qmodCC/Us+IuPAGypgMDyBlHlqUjfGGuSQNPtQJq9pp7mNBSgFDxoHI8G3aiDzDOayXH pkKnyBp4Gp/b9df0GbzQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iG7Yo-0000EG-P0; Thu, 03 Oct 2019 20:18:50 +0000 Received: from avon.wwwdotorg.org ([104.237.132.123]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iG7Yj-00009J-Ng for linux-arm-kernel@lists.infradead.org; Thu, 03 Oct 2019 20:18:47 +0000 Received: from swarren-lx1.nvidia.com (unknown [216.228.112.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPSA id DD6FB1C0728; Thu, 3 Oct 2019 14:18:43 -0600 (MDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.100.3 at avon.wwwdotorg.org From: Stephen Warren To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad Subject: [PATCH V2 1/4] clk: tegra: mark fuse clock as critical Date: Thu, 3 Oct 2019 14:18:34 -0600 Message-Id: <20191003201837.86824-1-swarren@wwwdotorg.org> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 X-NVConfidentiality: public X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191003_131845_818266_4F6F5FE0 X-CRM114-Status: GOOD ( 10.71 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-tegra@vger.kernel.org, Michael Turquette , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Stephen Warren For a little over a year, U-Boot on Tegra124 has configured the flow controller to perform automatic RAM re-repair on off->on power transitions of the CPU rail1]. This is mandatory for correct operation of Tegra124. However, RAM re-repair relies on certain clocks, which the kernel must enable and leave running. The fuse clock is one of those clocks. Mark this clock as critical so that LP1 power mode (system suspend) operates correctly. [1] 3cc7942a4ae5 ARM: tegra: implement RAM repair Reported-by: Jonathan Hunter Cc: stable@vger.kernel.org Signed-off-by: Stephen Warren --- v2: Set CRITICAL flag on the clock, rather than enabling it in tegra124_init_table[]. --- drivers/clk/tegra/clk-tegra-periph.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index 1ed85f120a1b..76dd91eebd13 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -785,7 +785,7 @@ static struct tegra_periph_init_data gate_clks[] = { GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0), GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0), GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0), - GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0), + GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, CLK_IS_CRITICAL), GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0), GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0), GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0), From patchwork Thu Oct 3 20:18:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 11173263 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5BE3B1599 for ; Thu, 3 Oct 2019 20:19:18 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3A5B22133F for ; Thu, 3 Oct 2019 20:19:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="s4a70dpj" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3A5B22133F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=wwwdotorg.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1GH+DyVWPVi6ul/ZsvT3xuDh0h56GuCg0hSd6AAMCuo=; b=s4a70dpjTapvT4 PtThXsdcBC/CAPHtLUn91mtrz8CUMmQBxZmj0eRHpMmuGIl1J8cwY88QpN6nsvZsmGsrvZwrj20+v vEG+JuBa8nr8LO5Y5fjF7bgEucFvQT9R938aOWR4DQZFGLqj2fxNmoZJSug91SATCBQMEswAM7cg/ 0cslK+f9ihTD64QKSHsww+ZRA6C3htN+wwil43zieTHSnE8/P7G384bi+OOVbEL/QvmXpSjNfJkr9 DV/4QGDEGkVfbL/kBz2i5gWSC207LCXFDotS38CGmEnMIXPLSf8colcFcJmqvQ9fsrp7SFIW8lk3h eU43om8qXMFrzsvo30mg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iG7ZC-0000ed-Tm; Thu, 03 Oct 2019 20:19:14 +0000 Received: from avon.wwwdotorg.org ([104.237.132.123]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iG7Yk-0000AP-63 for linux-arm-kernel@lists.infradead.org; Thu, 03 Oct 2019 20:18:49 +0000 Received: from swarren-lx1.nvidia.com (unknown [216.228.112.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPSA id E66E91C0C16; Thu, 3 Oct 2019 14:18:44 -0600 (MDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.100.3 at avon.wwwdotorg.org From: Stephen Warren To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad Subject: [PATCH V2 2/4] ARM: tegra: Enable PLLP bypass during Tegra124 LP1 Date: Thu, 3 Oct 2019 14:18:35 -0600 Message-Id: <20191003201837.86824-2-swarren@wwwdotorg.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191003201837.86824-1-swarren@wwwdotorg.org> References: <20191003201837.86824-1-swarren@wwwdotorg.org> MIME-Version: 1.0 X-NVConfidentiality: public X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191003_131846_268567_5D4315A0 X-CRM114-Status: GOOD ( 11.74 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-tegra@vger.kernel.org, Michael Turquette , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Stephen Warren For a little over a year, U-Boot has configured the flow controller to perform automatic RAM re-repair on off->on power transitions of the CPU rail1]. This is mandatory for correct operation of Tegra124. However, RAM re-repair relies on certain clocks, which the kernel must enable and leave running. PLLP is one of those clocks. This clock is shut down during LP1 in order to save power. Enable bypass (which I believe routes osc_div_clk, essentially the crystal clock, to the PLL output) so that this clock signal toggles even though the PLL is not active. This is required so that LP1 power mode (system suspend) operates correctly. The bypass configuration must then be undone when resuming from LP1, so that all peripheral clocks run at the expected rate. Without this, many peripherals won't work correctly; for example, the UART baud rate would be incorrect. NVIDIA's downstream kernel code only does this if not compiled for Tegra30, so the added code is made conditional upon the chip ID. NVIDIA's downstream code makes this change conditional upon the active CPU cluster. The upstream kernel currently doesn't support cluster switching, so this patch doesn't test the active CPU cluster ID. [1] 3cc7942a4ae5 ARM: tegra: implement RAM repair Reported-by: Jonathan Hunter Cc: stable@vger.kernel.org Signed-off-by: Stephen Warren --- v2: No change. --- arch/arm/mach-tegra/sleep-tegra30.S | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index b408fa56eb89..6922dd8d3e2d 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -370,6 +370,14 @@ _pll_m_c_x_done: pll_locked r1, r0, CLK_RESET_PLLC_BASE pll_locked r1, r0, CLK_RESET_PLLX_BASE + tegra_get_soc_id TEGRA_APB_MISC_BASE, r1 + cmp r1, #TEGRA30 + beq 1f + ldr r1, [r0, #CLK_RESET_PLLP_BASE] + bic r1, r1, #(1<<31) @ disable PllP bypass + str r1, [r0, #CLK_RESET_PLLP_BASE] +1: + mov32 r7, TEGRA_TMRUS_BASE ldr r1, [r7] add r1, r1, #LOCK_DELAY @@ -630,7 +638,10 @@ tegra30_switch_cpu_to_clk32k: str r0, [r4, #PMC_PLLP_WB0_OVERRIDE] /* disable PLLP, PLLA, PLLC and PLLX */ + tegra_get_soc_id TEGRA_APB_MISC_BASE, r1 + cmp r1, #TEGRA30 ldr r0, [r5, #CLK_RESET_PLLP_BASE] + orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster bic r0, r0, #(1 << 30) str r0, [r5, #CLK_RESET_PLLP_BASE] ldr r0, [r5, #CLK_RESET_PLLA_BASE] From patchwork Thu Oct 3 20:18:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 11173261 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 13C321709 for ; Thu, 3 Oct 2019 20:19:08 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E5B79215EA for ; Thu, 3 Oct 2019 20:19:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="HCAI/pMy" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E5B79215EA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=wwwdotorg.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Oj7W7kmkIBYlYB8FampK95W63UZ36s4eDmdvE5rMEwQ=; b=HCAI/pMyYncQH6 g05RJnxO7L6ERk3/hxB/TJggdPsyaQKGU0ApjQyrqxN75oVtke8Z+P0rUMRSYVUNr0CLYlL416E1q S6qeXt337wNqjMprtlnRtbBNdcvByIew5qlqfC6JCNxHmxXLxSfWVbFj9VfNxgkiiWH/wQOFRZKWY YUveGFqMcCZPDR1B4y+WdqNkRzzeIUp1P3t+/ZOPmxqUWJ0Rkh8jKQnFec5DK4XxrbaAX8UIkrIKh 1b9lRHVCBfix4XyeKmLHdIf0yLpe8dnqvt4xZ7KNErKDTZVraBpj8r1ycaa2jpj5y7lTskSJVGX5O bwzp2l53RbTYG2S2jlbw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iG7Z2-0000Rb-SF; Thu, 03 Oct 2019 20:19:04 +0000 Received: from avon.wwwdotorg.org ([104.237.132.123]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iG7Yl-0000CB-RK for linux-arm-kernel@lists.infradead.org; Thu, 03 Oct 2019 20:18:50 +0000 Received: from swarren-lx1.nvidia.com (unknown [216.228.112.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPSA id F37A91C0CB9; Thu, 3 Oct 2019 14:18:45 -0600 (MDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.100.3 at avon.wwwdotorg.org From: Stephen Warren To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad Subject: [PATCH V2 3/4] ARM: tegra: modify reshift divider during LP1 Date: Thu, 3 Oct 2019 14:18:36 -0600 Message-Id: <20191003201837.86824-3-swarren@wwwdotorg.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191003201837.86824-1-swarren@wwwdotorg.org> References: <20191003201837.86824-1-swarren@wwwdotorg.org> MIME-Version: 1.0 X-NVConfidentiality: public X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191003_131847_977150_5F6275AB X-CRM114-Status: UNSURE ( 9.37 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-tegra@vger.kernel.org, Michael Turquette , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Stephen Warren The reshift hardware module implements the RAM re-repair process. This module uses PLLP as an input clock during LP1 resume. The input divider for this clock is typically set for PLLP's normal rate. During LP1 resume, PLLP is bypassed and so runs at the crystal rate, which is much slower. Consequently, decrease the divider so that the reshift module runs at a reasonable rate during LP1 resume. NVIDIA's downstream kernel code only does this if not compiled for Tegra30, so the added code is made conditional upon the chip ID. Signed-off-by: Stephen Warren --- v2: No change. --- arch/arm/mach-tegra/sleep-tegra30.S | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 6922dd8d3e2d..6191f9456288 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -59,6 +59,9 @@ #define CLK_RESET_PLLX_MISC3_IDDQ 3 #define CLK_RESET_PLLM_MISC_IDDQ 5 #define CLK_RESET_PLLC_MISC_IDDQ 26 +#define CLK_RESET_PLLP_RESHIFT 0x528 +#define CLK_RESET_PLLP_RESHIFT_DEFAULT 0x3b +#define CLK_RESET_PLLP_RESHIFT_ENABLE 0x3 #define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4 @@ -373,9 +376,13 @@ _pll_m_c_x_done: tegra_get_soc_id TEGRA_APB_MISC_BASE, r1 cmp r1, #TEGRA30 beq 1f + ldr r1, [r0, #CLK_RESET_PLLP_BASE] bic r1, r1, #(1<<31) @ disable PllP bypass str r1, [r0, #CLK_RESET_PLLP_BASE] + + mov r1, #CLK_RESET_PLLP_RESHIFT_DEFAULT + str r1, [r0, #CLK_RESET_PLLP_RESHIFT] 1: mov32 r7, TEGRA_TMRUS_BASE @@ -644,6 +651,10 @@ tegra30_switch_cpu_to_clk32k: orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster bic r0, r0, #(1 << 30) str r0, [r5, #CLK_RESET_PLLP_BASE] + beq 1f + mov r0, #CLK_RESET_PLLP_RESHIFT_ENABLE + str r0, [r5, #CLK_RESET_PLLP_RESHIFT] +1: ldr r0, [r5, #CLK_RESET_PLLA_BASE] bic r0, r0, #(1 << 30) str r0, [r5, #CLK_RESET_PLLA_BASE] From patchwork Thu Oct 3 20:18:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 11173265 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C12971709 for ; Thu, 3 Oct 2019 20:19:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9FC6E20862 for ; Thu, 3 Oct 2019 20:19:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="rMq7PKFO" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9FC6E20862 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=wwwdotorg.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=93fL/C+JQpQwpoMNyfnY+uTZ5o1MkBVJIrOZUTFvt2A=; b=rMq7PKFOuYJqdI pjJg2dQK2OsSiHB2zhRYDDhypNJr3TUjhuVVsO+z4zj5y1Yw3sZnvT5LEO30wRz75CFDE73/gyPai qei7rMetYpzWSil6pbfIhgylJjaV3uepzYaTSsbSXzTowzONw0OyNkCjV2e6vOeWzJS1IQpByssSW mYQhFKSGntpqWSnr0muA2GIu2RxstzeC7EQVeA3l6viDAbMG7BGuEMHU0jtdn1fh0FW809ojQ8hM3 yBq4ua7fAiB7XhSDXvIWZNHjPNtWAoy3TsKHh6iEaNB1ct+FEQRuPJ1+6LpRozT4eKoe659w7myM4 JR2VePLHJGnuAoM4kcOg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iG7ZT-0000vZ-2f; Thu, 03 Oct 2019 20:19:31 +0000 Received: from avon.wwwdotorg.org ([104.237.132.123]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iG7Ym-0000DG-Sg for linux-arm-kernel@lists.infradead.org; Thu, 03 Oct 2019 20:18:52 +0000 Received: from swarren-lx1.nvidia.com (unknown [216.228.112.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPSA id 571981C0728; Thu, 3 Oct 2019 14:18:47 -0600 (MDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.100.3 at avon.wwwdotorg.org From: Stephen Warren To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad Subject: [PATCH V2 4/4] ARM: tegra: use clk_m CPU on Tegra124 LP1 resume Date: Thu, 3 Oct 2019 14:18:37 -0600 Message-Id: <20191003201837.86824-4-swarren@wwwdotorg.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191003201837.86824-1-swarren@wwwdotorg.org> References: <20191003201837.86824-1-swarren@wwwdotorg.org> MIME-Version: 1.0 X-NVConfidentiality: public X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191003_131848_988372_C172C1C4 X-CRM114-Status: GOOD ( 11.94 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-tegra@vger.kernel.org, Michael Turquette , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Stephen Warren Configure the clock controller to set an alternate clock for the CPU when it receives an IRQ during LP1 (system suspend). Specifically, use clk_m (the crystal) rather than clk_s (a 32KHz clock). Such an IRQ will be the LP1 wake event. This reduces the amount of time taken to resume from LP1. NVIDIA's downstream kernel executes this code on both Tegra30 and Tegra124, so it appears OK to make this change unconditionally. Signed-off-by: Stephen Warren --- v2: No change. --- arch/arm/mach-tegra/sleep-tegra30.S | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 6191f9456288..ba5e9c07d1b6 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -670,8 +670,12 @@ tegra30_switch_cpu_to_clk32k: pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ _no_pll_in_iddq: - /* switch to CLKS */ - mov r0, #0 /* brust policy = 32KHz */ + /* + * Switch to clk_s (32KHz); bits 28:31=0 + * Enable burst on CPU IRQ; bit 24=1 + * Set IRQ burst clock source to clk_m; bits 10:8=0 + */ + mov r0, #(1 << 24) str r0, [r5, #CLK_RESET_SCLK_BURST] ret lr