From patchwork Fri Oct 11 19:40:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aaron Lewis X-Patchwork-Id: 11186311 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CA12815AB for ; Fri, 11 Oct 2019 19:41:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AB368218AC for ; Fri, 11 Oct 2019 19:41:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="nrQWGXsc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729023AbfJKTlB (ORCPT ); Fri, 11 Oct 2019 15:41:01 -0400 Received: from mail-pf1-f202.google.com ([209.85.210.202]:55832 "EHLO mail-pf1-f202.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728889AbfJKTlB (ORCPT ); Fri, 11 Oct 2019 15:41:01 -0400 Received: by mail-pf1-f202.google.com with SMTP id u21so5360778pfm.22 for ; Fri, 11 Oct 2019 12:40:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=tFjCmwHNkWY/vtXdDAhqblK0COAto8NjIyTqKF2VaKg=; b=nrQWGXscB36hvzb/+9K7jjA9//3BNp4/XJGUu1wTuOMnB7lrh4qC+jT+4ACc6E3HEw PpIpv5zEFkKw4aPtu41WtWD/MRlfLLGzspdERee1zFBGNT00N6BtPHfi89d4Q20AGPBg Tg9OOzbzAWd1TLmnYMcnsh9omH7dlSa5FA8Uv/p3WCt1Izo26VR2tpdxJSxK/so+9wbF /Wf8HARNhZk+go8Q0D3UA4szvNF8rNMUCzz6C4n008782d+DAzaLKe8og1B1SLJHgB+q 8guZgwBKuW0MRzZmc1qotHwsUk/qQFVAmH+oFs8x2goep8wkeigl6tq/XNokyJw8dvBF CkDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=tFjCmwHNkWY/vtXdDAhqblK0COAto8NjIyTqKF2VaKg=; b=hs+o5XUmmJMc6qEg8JUTcLTdWoVG8unUrlAVbD7sl4PiDspmF8or221CeESrTxwPHJ 7CgonJvspLp2KqUJSmXXW8dBKBP9ECx2FopueCClPqcUITTu9zf/uPTI2mdWfhgAvhzT d7sBuOyRic4ro1et6xWZefiCLW9zMijgGENHYrNcl59VpPFy8ToFQIsmnhcQNnRmztUW lR7ZtB4G1R/XeT+HIlyf1E0oHgjGPOM5s6CZDytgW+39t+bPEAQuj4r37idwKbn5NLLK b36M49P2nhjcDWDNZno5olmszG/zxEaG42wEsEkj7aZsgk8Vv8K97wEqcxFE3puHu9Fa vJiw== X-Gm-Message-State: APjAAAXzhkLlC2sgRTZr316BeOsTpGIyTZXHKF8yK1ab1FYZnVauFWkt sdAlK52WVFDsMLt8z4aSMJ7vsvrplTw9ysMV X-Google-Smtp-Source: APXvYqxbt6TWtw0vLChkx71/BWcvtD1Nqihu/gC69YYt5qoaXWdLbuWCfCe7D+OUsa/4juRCdj35oFZzX5PoNRSi X-Received: by 2002:a65:450c:: with SMTP id n12mr13571848pgq.394.1570822859060; Fri, 11 Oct 2019 12:40:59 -0700 (PDT) Date: Fri, 11 Oct 2019 12:40:28 -0700 In-Reply-To: <20191011194032.240572-1-aaronlewis@google.com> Message-Id: <20191011194032.240572-2-aaronlewis@google.com> Mime-Version: 1.0 References: <20191011194032.240572-1-aaronlewis@google.com> X-Mailer: git-send-email 2.23.0.700.g56cf767bdb-goog Subject: [PATCH v2 1/5] KVM: VMX: Remove unneeded check for X86_FEATURE_XSAVE From: Aaron Lewis To: Babu Moger , Yang Weijiang , Sebastian Andrzej Siewior , kvm@vger.kernel.org Cc: Paolo Bonzini , Jim Mattson , Aaron Lewis Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Volume 4 of the SDM says that IA32_XSS is supported "If(CPUID.(0DH, 1):EAX.[3] = 1", so only the X86_FEATURE_XSAVES check is necessary. Fixes: 4d763b168e9c5 ("KVM: VMX: check CPUID before allowing read/write of IA32_XSS") Reviewed-by: Jim Mattson Signed-off-by: Aaron Lewis --- arch/x86/kvm/vmx/vmx.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index e7970a2e8eae..409e9a7323f1 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -1823,8 +1823,7 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_IA32_XSS: if (!vmx_xsaves_supported() || (!msr_info->host_initiated && - !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && - guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)))) + !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))) return 1; msr_info->data = vcpu->arch.ia32_xss; break; @@ -2066,8 +2065,7 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_IA32_XSS: if (!vmx_xsaves_supported() || (!msr_info->host_initiated && - !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && - guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)))) + !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))) return 1; /* * The only supported bit as of Skylake is bit 8, but From patchwork Fri Oct 11 19:40:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aaron Lewis X-Patchwork-Id: 11186313 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3D91714ED for ; Fri, 11 Oct 2019 19:41:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 14ED52084C for ; Fri, 11 Oct 2019 19:41:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="YsNz8AkL" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729050AbfJKTlF (ORCPT ); Fri, 11 Oct 2019 15:41:05 -0400 Received: from mail-pl1-f202.google.com ([209.85.214.202]:55460 "EHLO mail-pl1-f202.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728889AbfJKTlE (ORCPT ); Fri, 11 Oct 2019 15:41:04 -0400 Received: by mail-pl1-f202.google.com with SMTP id g11so6628785plm.22 for ; Fri, 11 Oct 2019 12:41:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=a2OnAlUknYYYhqmTtsWzMoB6MeANxh1WTSsk/O3pEpc=; b=YsNz8AkLaJTQgxGg+QXyX7+VAOL658TEwLUVIt2UyEElxsB9w9xx7Kv9SNZ99ASNpL 7wA1UC0SuVgts76d+xOlhthD22u7ZNz8czQrbPLL0qncZqfoqoBcnmJEGB+QVk9+PFZJ NLONgR2T+ONKOz8J4r1OQdtf0ICxHLoV7I5MG80koaqghzr5knRs+JuaZVcWnx5z9kvD +par5b+WwGc0gRJ39JaWzJou/mId036IkIE/tlf9MOcR8l07OmZzBG82tYBVCpfVdps/ Z/JGv+iFv+aT/zVihfXWzQhWqiSTaWeSbfaOu6OFselIaR2m6G13X0lsIFRv7DS0K9qZ O2fA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=a2OnAlUknYYYhqmTtsWzMoB6MeANxh1WTSsk/O3pEpc=; b=fPrpSOumuRdSCR8szp8FS9xMT8SRBKkGmUuRH/IGy/g+mfsMmf6F+nolF4RUiVL5K5 W6urerCnFyXRuaaF94SaU7FDNip50fJ5DT6/SMvkySGSBNHhnYQGnqqJz1Pbtcyl1EyI Xc2DpRhitKFhse+szM4i6N/2uPEJkSih6Jky8Q93MhYsyyatJM8RQT8GGVqOZ5P9JFN9 E1bt0uiIGzG5m4jBMiOY/IaIsw6Um1cyhs/rt2EkV9Y0sg54wmYSE/6k6Jt9ljmrv8/n 2oHFUbFTi708325ocRj5sWmgyAIXcyKppdPq0YfQctHA0xZjK8BkWPwPZDO2h3+AH6EZ 9L/A== X-Gm-Message-State: APjAAAWeX4SWUqWssElzBGvzOOxA8VH8VwjjMGsjcK3d6SHJTP7FKCvv T5Mt4J2kuoLMC2zmBxBN61y1HiQVVtF/AFrX X-Google-Smtp-Source: APXvYqw7l85FkDQ6L1kWK3acvPoCbEuO9qcCzjOECbGAivNKspaTi8oq8A/5LLOx8FISDEpbu3TuOWN5Re4jtbky X-Received: by 2002:a63:f40e:: with SMTP id g14mr6300583pgi.62.1570822863853; Fri, 11 Oct 2019 12:41:03 -0700 (PDT) Date: Fri, 11 Oct 2019 12:40:29 -0700 In-Reply-To: <20191011194032.240572-1-aaronlewis@google.com> Message-Id: <20191011194032.240572-3-aaronlewis@google.com> Mime-Version: 1.0 References: <20191011194032.240572-1-aaronlewis@google.com> X-Mailer: git-send-email 2.23.0.700.g56cf767bdb-goog Subject: [PATCH v2 2/5] KVM: VMX: Use wrmsr for switching between guest and host IA32_XSS From: Aaron Lewis To: Babu Moger , Yang Weijiang , Sebastian Andrzej Siewior , kvm@vger.kernel.org Cc: Paolo Bonzini , Jim Mattson , Aaron Lewis Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Set IA32_XSS for the guest and host during VM Enter and VM Exit transitions rather than by using the MSR-load areas. By moving away from using the MSR-load area we can have a unified solution for both AMD and Intel. Reviewed-by: Jim Mattson Signed-off-by: Aaron Lewis --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/svm.c | 7 +++++-- arch/x86/kvm/vmx/vmx.c | 22 ++++++++++------------ arch/x86/kvm/x86.c | 23 +++++++++++++++++++---- arch/x86/kvm/x86.h | 4 ++-- 5 files changed, 37 insertions(+), 20 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 50eb430b0ad8..634c2598e389 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -562,6 +562,7 @@ struct kvm_vcpu_arch { u64 smbase; u64 smi_count; bool tpr_access_reporting; + bool xsaves_enabled; u64 ia32_xss; u64 microcode_version; u64 arch_capabilities; diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index f8ecb6df5106..da69e95beb4d 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -5628,7 +5628,7 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu) svm->vmcb->save.cr2 = vcpu->arch.cr2; clgi(); - kvm_load_guest_xcr0(vcpu); + kvm_load_guest_xsave_controls(vcpu); if (lapic_in_kernel(vcpu) && vcpu->arch.apic->lapic_timer.timer_advance_ns) @@ -5778,7 +5778,7 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu) if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) kvm_before_interrupt(&svm->vcpu); - kvm_put_guest_xcr0(vcpu); + kvm_load_host_xsave_controls(vcpu); stgi(); /* Any pending NMI will happen here */ @@ -5887,6 +5887,9 @@ static void svm_cpuid_update(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm = to_svm(vcpu); + vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && + boot_cpu_has(X86_FEATURE_XSAVES); + /* Update nrips enabled cache */ svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS); diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 409e9a7323f1..ce3020914c69 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -106,8 +106,6 @@ module_param(enable_apicv, bool, S_IRUGO); static bool __read_mostly nested = 1; module_param(nested, bool, S_IRUGO); -static u64 __read_mostly host_xss; - bool __read_mostly enable_pml = 1; module_param_named(pml, enable_pml, bool, S_IRUGO); @@ -2074,11 +2072,6 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) if (data != 0) return 1; vcpu->arch.ia32_xss = data; - if (vcpu->arch.ia32_xss != host_xss) - add_atomic_switch_msr(vmx, MSR_IA32_XSS, - vcpu->arch.ia32_xss, host_xss, false); - else - clear_atomic_switch_msr(vmx, MSR_IA32_XSS); break; case MSR_IA32_RTIT_CTL: if ((pt_mode != PT_MODE_HOST_GUEST) || @@ -4038,6 +4031,8 @@ static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); + vcpu->arch.xsaves_enabled = xsaves_enabled; + if (!xsaves_enabled) exec_control &= ~SECONDARY_EXEC_XSAVES; @@ -6540,7 +6535,7 @@ static void vmx_vcpu_run(struct kvm_vcpu *vcpu) if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) vmx_set_interrupt_shadow(vcpu, 0); - kvm_load_guest_xcr0(vcpu); + kvm_load_guest_xsave_controls(vcpu); if (static_cpu_has(X86_FEATURE_PKU) && kvm_read_cr4_bits(vcpu, X86_CR4_PKE) && @@ -6647,7 +6642,7 @@ static void vmx_vcpu_run(struct kvm_vcpu *vcpu) __write_pkru(vmx->host_pkru); } - kvm_put_guest_xcr0(vcpu); + kvm_load_host_xsave_controls(vcpu); vmx->nested.nested_run_pending = 0; vmx->idt_vectoring_info = 0; @@ -7091,6 +7086,12 @@ static void vmx_cpuid_update(struct kvm_vcpu *vcpu) { struct vcpu_vmx *vmx = to_vmx(vcpu); + /* + * This will be set back to true in vmx_compute_secondary_exec_control() + * if it should be true, so setting it to false here is okay. + */ + vcpu->arch.xsaves_enabled = false; + if (cpu_has_secondary_exec_ctrls()) { vmx_compute_secondary_exec_control(vmx); vmcs_set_secondary_exec_control(vmx); @@ -7599,9 +7600,6 @@ static __init int hardware_setup(void) WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost"); } - if (boot_cpu_has(X86_FEATURE_XSAVES)) - rdmsrl(MSR_IA32_XSS, host_xss); - if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) enable_vpid = 0; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 661e2bf38526..a61570d7034b 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -176,6 +176,8 @@ struct kvm_shared_msrs { static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; static struct kvm_shared_msrs __percpu *shared_msrs; +static u64 __read_mostly host_xss; + struct kvm_stats_debugfs_item debugfs_entries[] = { { "pf_fixed", VCPU_STAT(pf_fixed) }, { "pf_guest", VCPU_STAT(pf_guest) }, @@ -812,27 +814,37 @@ void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) } EXPORT_SYMBOL_GPL(kvm_lmsw); -void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) +void kvm_load_guest_xsave_controls(struct kvm_vcpu *vcpu) { if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && !vcpu->guest_xcr0_loaded) { /* kvm_set_xcr() also depends on this */ if (vcpu->arch.xcr0 != host_xcr0) xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); + + if (vcpu->arch.xsaves_enabled && + vcpu->arch.ia32_xss != host_xss) + wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); + vcpu->guest_xcr0_loaded = 1; } } -EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0); +EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_controls); -void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) +void kvm_load_host_xsave_controls(struct kvm_vcpu *vcpu) { if (vcpu->guest_xcr0_loaded) { if (vcpu->arch.xcr0 != host_xcr0) xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); + + if (vcpu->arch.xsaves_enabled && + vcpu->arch.ia32_xss != host_xss) + wrmsrl(MSR_IA32_XSS, host_xss); + vcpu->guest_xcr0_loaded = 0; } } -EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0); +EXPORT_SYMBOL_GPL(kvm_load_host_xsave_controls); static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) { @@ -9293,6 +9305,9 @@ int kvm_arch_hardware_setup(void) kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; } + if (boot_cpu_has(X86_FEATURE_XSAVES)) + rdmsrl(MSR_IA32_XSS, host_xss); + kvm_init_msr_list(); return 0; } diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index dbf7442a822b..0d04e865665b 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -366,7 +366,7 @@ static inline bool kvm_pat_valid(u64 data) return (data | ((data & 0x0202020202020202ull) << 1)) == data; } -void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu); -void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu); +void kvm_load_guest_xsave_controls(struct kvm_vcpu *vcpu); +void kvm_load_host_xsave_controls(struct kvm_vcpu *vcpu); #endif From patchwork Fri Oct 11 19:40:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aaron Lewis X-Patchwork-Id: 11186315 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6547C15AB for ; Fri, 11 Oct 2019 19:41:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4711621835 for ; Fri, 11 Oct 2019 19:41:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="QbSuIu//" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729052AbfJKTlK (ORCPT ); Fri, 11 Oct 2019 15:41:10 -0400 Received: from mail-vk1-f202.google.com ([209.85.221.202]:56314 "EHLO mail-vk1-f202.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729014AbfJKTlK (ORCPT ); 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Fri, 11 Oct 2019 12:41:07 -0700 (PDT) Date: Fri, 11 Oct 2019 12:40:30 -0700 In-Reply-To: <20191011194032.240572-1-aaronlewis@google.com> Message-Id: <20191011194032.240572-4-aaronlewis@google.com> Mime-Version: 1.0 References: <20191011194032.240572-1-aaronlewis@google.com> X-Mailer: git-send-email 2.23.0.700.g56cf767bdb-goog Subject: [PATCH v2 3/5] kvm: svm: Add support for XSAVES on AMD From: Aaron Lewis To: Babu Moger , Yang Weijiang , Sebastian Andrzej Siewior , kvm@vger.kernel.org Cc: Paolo Bonzini , Jim Mattson , Aaron Lewis Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Hoist support for RDMSR/WRMSR of IA32_XSS from vmx into common code so that it can be used for AMD as well. AMD has no equivalent of Intel's "Enable XSAVES/XRSTORS" VM-execution control. Instead, XSAVES is always available to the guest when supported on the host. Unfortunately, right now, kvm only allows the guest IA32_XSS to be zero, so the guest's usage of XSAVES will be exactly the same as XSAVEC. Reviewed-by: Jim Mattson Signed-off-by: Aaron Lewis --- arch/x86/kvm/svm.c | 2 +- arch/x86/kvm/vmx/vmx.c | 20 -------------------- arch/x86/kvm/x86.c | 22 ++++++++++++++++++++++ 3 files changed, 23 insertions(+), 21 deletions(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index da69e95beb4d..1953898e37ce 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -5965,7 +5965,7 @@ static bool svm_mpx_supported(void) static bool svm_xsaves_supported(void) { - return false; + return boot_cpu_has(X86_FEATURE_XSAVES); } static bool svm_umip_emulated(void) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index ce3020914c69..18bea844fffc 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -1818,13 +1818,6 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) return 1; return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index, &msr_info->data); - case MSR_IA32_XSS: - if (!vmx_xsaves_supported() || - (!msr_info->host_initiated && - !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))) - return 1; - msr_info->data = vcpu->arch.ia32_xss; - break; case MSR_IA32_RTIT_CTL: if (pt_mode != PT_MODE_HOST_GUEST) return 1; @@ -2060,19 +2053,6 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) if (!nested_vmx_allowed(vcpu)) return 1; return vmx_set_vmx_msr(vcpu, msr_index, data); - case MSR_IA32_XSS: - if (!vmx_xsaves_supported() || - (!msr_info->host_initiated && - !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))) - return 1; - /* - * The only supported bit as of Skylake is bit 8, but - * it is not supported on KVM. - */ - if (data != 0) - return 1; - vcpu->arch.ia32_xss = data; - break; case MSR_IA32_RTIT_CTL: if ((pt_mode != PT_MODE_HOST_GUEST) || vmx_rtit_ctl_check(vcpu, data) || diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index a61570d7034b..2104e21855fc 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -2700,6 +2700,21 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_IA32_TSC: kvm_write_tsc(vcpu, msr_info); break; + case MSR_IA32_XSS: + if (!kvm_x86_ops->xsaves_supported() || + (!msr_info->host_initiated && + !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))) + return 1; + /* + * We do support PT if kvm_x86_ops->pt_supported(), but we do + * not support IA32_XSS[bit 8]. Guests will have to use + * RDMSR/WRMSR rather than XSAVES/XRSTORS to save/restore PT + * MSRs. + */ + if (data != 0) + return 1; + vcpu->arch.ia32_xss = data; + break; case MSR_SMI_COUNT: if (!msr_info->host_initiated) return 1; @@ -3030,6 +3045,13 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: return get_msr_mce(vcpu, msr_info->index, &msr_info->data, msr_info->host_initiated); + case MSR_IA32_XSS: + if (!kvm_x86_ops->xsaves_supported() || + (!msr_info->host_initiated && + !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))) + return 1; + msr_info->data = vcpu->arch.ia32_xss; + break; case MSR_K7_CLK_CTL: /* * Provide expected ramp-up count for K7. All other From patchwork Fri Oct 11 19:40:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aaron Lewis X-Patchwork-Id: 11186317 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7CB7315AB for ; Fri, 11 Oct 2019 19:41:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5D37A2084C for ; Fri, 11 Oct 2019 19:41:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="nLsiobK7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729055AbfJKTlL (ORCPT ); Fri, 11 Oct 2019 15:41:11 -0400 Received: from mail-pg1-f202.google.com ([209.85.215.202]:35699 "EHLO mail-pg1-f202.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729014AbfJKTlL (ORCPT ); Fri, 11 Oct 2019 15:41:11 -0400 Received: by mail-pg1-f202.google.com with SMTP id s1so7667041pgm.2 for ; Fri, 11 Oct 2019 12:41:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=WBZQuUCDQHNl1l1bGWNs/9RUHosUT5fVUoCeqs6NXeU=; b=nLsiobK7toiL0tMAZXKCM1qFRtLPxSTfoj/qE/UTRLVQRuWan3v8eGF73Sgx58Jphl WOEs1kOjviwRoZFhV7kX2k4QrzuyoZqK13v0TSlZqTKu/FN64Gh2xiT5u68HNP9K6ydM thU551rToDNNg9sJxgbynIuPQCI0w8qFx/DbAhZxlAxzK4MLp6QPSgpWM/FYauPZu1ev vbyNTQql6/J+VE/aQEQQAAM77ENhfd2JAJAl9+IA9DZIXOHUmXP8/CEDjAE/roiP05nu Bn6sqy9XKPG80Gjg1LVWlq7aRcMLZyCn6M45v7Yg/XLrWE+LNExFQCWbveJ+65t+BHHW my/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=WBZQuUCDQHNl1l1bGWNs/9RUHosUT5fVUoCeqs6NXeU=; b=rAwdQSeHBnnuZJNCHniafw/N04G/lMNagl2GsClva37bZpua+JWRE9GjRCf6ugR9JI 2A1U7gSjPuS5YPRc8mFApWPeGWfqza3aw0eGStwxdntjdGkIfj6WWTBdLLL//HSlYTTb mGvlhs8PBTGQbpBRg82eO9bf2sJ+znx9Q0vfVR/FDBvCfut7qLdkCbySSgnEpAAdeoPU NpxmWkxSTGqyqsbp39Y2jzkGcYp82PLXu3Lr1ruVHIgKpnEdPFDCogWvOscxb+LYtCO1 INkmhx+PjElcZNhaPjqu1a9n24ofzjpAjERJkTaYMYyfDP0UrDr/Go+oJ8GmxI8pfPHP xjWw== X-Gm-Message-State: APjAAAVrNaD3SZU8MskxtyQkAjD/3u2SF33AGDWW4kbZbopE6pITGkZa j3xbZnj/5neQUuhg/xtFR9o0LGXQMPguYSfL X-Google-Smtp-Source: APXvYqzePMsEtzf0mOV1afpqsOBDPe2zZKsh3WkM5xBc7EgmtzQ6pZkFJ66dkvg2MfmQqfhPAN/k+HTNXANDm31T X-Received: by 2002:a65:66d1:: with SMTP id c17mr18364033pgw.169.1570822870397; Fri, 11 Oct 2019 12:41:10 -0700 (PDT) Date: Fri, 11 Oct 2019 12:40:31 -0700 In-Reply-To: <20191011194032.240572-1-aaronlewis@google.com> Message-Id: <20191011194032.240572-5-aaronlewis@google.com> Mime-Version: 1.0 References: <20191011194032.240572-1-aaronlewis@google.com> X-Mailer: git-send-email 2.23.0.700.g56cf767bdb-goog Subject: [PATCH v2 4/5] kvm: x86: Add IA32_XSS to the emulated_msrs list From: Aaron Lewis To: Babu Moger , Yang Weijiang , Sebastian Andrzej Siewior , kvm@vger.kernel.org Cc: Paolo Bonzini , Jim Mattson , Aaron Lewis Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add IA32_XSS to the list of emulated MSRs if it is supported in the guest. At the moment, the guest IA32_XSS must be zero, but this change prepares for expanded support in the future. Reviewed-by: Jim Mattson Signed-off-by: Aaron Lewis --- arch/x86/kvm/svm.c | 12 +++++++----- arch/x86/kvm/vmx/vmx.c | 2 ++ arch/x86/kvm/x86.c | 1 + 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 1953898e37ce..e23a5013c812 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -498,6 +498,11 @@ static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu) return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); } +static bool svm_xsaves_supported(void) +{ + return boot_cpu_has(X86_FEATURE_XSAVES); +} + static void recalc_intercepts(struct vcpu_svm *svm) { struct vmcb_control_area *c, *h; @@ -5871,6 +5876,8 @@ static bool svm_has_emulated_msr(int index) case MSR_IA32_MCG_EXT_CTL: case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: return false; + case MSR_IA32_XSS: + return svm_xsaves_supported(); default: break; } @@ -5963,11 +5970,6 @@ static bool svm_mpx_supported(void) return false; } -static bool svm_xsaves_supported(void) -{ - return boot_cpu_has(X86_FEATURE_XSAVES); -} - static bool svm_umip_emulated(void) { return false; diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 18bea844fffc..4ba62ebd8703 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -6272,6 +6272,8 @@ static bool vmx_has_emulated_msr(int index) case MSR_AMD64_VIRT_SPEC_CTRL: /* This is AMD only. */ return false; + case MSR_IA32_XSS: + return vmx_xsaves_supported(); default: return true; } diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 2104e21855fc..e3b7dbb8be8f 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1227,6 +1227,7 @@ static u32 emulated_msrs[] = { MSR_MISC_FEATURES_ENABLES, MSR_AMD64_VIRT_SPEC_CTRL, MSR_IA32_POWER_CTL, + MSR_IA32_XSS, /* * The following list leaves out MSRs whose values are determined From patchwork Fri Oct 11 19:40:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aaron Lewis X-Patchwork-Id: 11186319 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE40614ED for ; Fri, 11 Oct 2019 19:41:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B83E52190F for ; Fri, 11 Oct 2019 19:41:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="spE3SI/t" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729060AbfJKTlQ (ORCPT ); Fri, 11 Oct 2019 15:41:16 -0400 Received: from mail-pl1-f202.google.com ([209.85.214.202]:35436 "EHLO mail-pl1-f202.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728985AbfJKTlQ (ORCPT ); Fri, 11 Oct 2019 15:41:16 -0400 Received: by mail-pl1-f202.google.com with SMTP id o12so6652798pll.2 for ; Fri, 11 Oct 2019 12:41:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=uigccOC75UQVYGcTvnAyLucq/FZ2h1PCnP1UNKyHaxs=; b=spE3SI/tGJXcTgjoJJxWOj/KdkWX0410GrN0KcOwG4VW9rZYSS/wuVhc82WkTWDuo7 aXLJ+16OZRQAiZoRtH6JD81rsKHkXjk9thEvAq/vlxTCXpfXeifqABYSFGLK6L2higcK tWDA/rvHFtPFwzQNvblwJ2PL0nKDmFbR/B8C5wy1xUC24hZKtUx3mSQRWtSbYQFoxz2s Nu9g8MZ/nSBfTdGAXkIvhmjIzfKWuHGGMAVvXf95+PfPvlZUQHQzj+2XWrB8K60VQzhr cdh0bcTFkAdNuWObxSUiGO3RR43qN2IKIgj386ZGkuZLxV3oCnvOrv7Pv9Q1wQdCj+z1 xubw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=uigccOC75UQVYGcTvnAyLucq/FZ2h1PCnP1UNKyHaxs=; b=Y0jdcw5GmJc87L63gmu9rhSwVw9Tlj8s2RWZjNDlf9BvcmPM8avl9yp/o13LuFiOPt d5kbISSgBCj6jY9oxQLhe8VVWpmP9rexjGaYWjfN/XynKwf0Wk450i/SOHih3Ue8SYw0 MsRGsO3tCdXRGw4xVbv1lV+ehbzbCDOnW+GIdM4Buiwfz+v9qUEi6Zbet9Gb+g4SFVop BTriOL+YOFewj9/pI7zmYtyHvUMNBQGoCGDIqv8v/qoZFIUWmaIk73gaKEM743KCiCrq kiX2dkAAvcARZfW7bTUMGdfdR3vevvYvJYq3/92fTW5ZJ5uK+9HW2X7mJis59/u8IBS6 cX0g== X-Gm-Message-State: APjAAAWr6IufDYjuGDYUBf8L0v6pXRn/V26NAP7Z6p78E+r0oCSqMfAl IX7i5e0jPvbHtBwIoINFXamBjx0KMxDxanOG X-Google-Smtp-Source: APXvYqzhYsMJnMSrzhwSujmHuTAOVj0OLASdf47quEOEGjwuXvyT01Gvfpa1Rn1yK7XLdGLnZYYEyOL+jhO5vpXm X-Received: by 2002:a63:e156:: with SMTP id h22mr18232130pgk.266.1570822874169; Fri, 11 Oct 2019 12:41:14 -0700 (PDT) Date: Fri, 11 Oct 2019 12:40:32 -0700 In-Reply-To: <20191011194032.240572-1-aaronlewis@google.com> Message-Id: <20191011194032.240572-6-aaronlewis@google.com> Mime-Version: 1.0 References: <20191011194032.240572-1-aaronlewis@google.com> X-Mailer: git-send-email 2.23.0.700.g56cf767bdb-goog Subject: [PATCH v2 5/5] kvm: tests: Add test to verify MSR_IA32_XSS From: Aaron Lewis To: Babu Moger , Yang Weijiang , Sebastian Andrzej Siewior , kvm@vger.kernel.org Cc: Paolo Bonzini , Jim Mattson , Aaron Lewis Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Verify that calling get and set for MSR_IA32_XSS returns expected results. Reviewed-by: Jim Mattson Signed-off-by: Aaron Lewis --- tools/testing/selftests/kvm/.gitignore | 1 + tools/testing/selftests/kvm/Makefile | 1 + .../selftests/kvm/include/x86_64/processor.h | 7 +- .../selftests/kvm/lib/x86_64/processor.c | 72 ++++++++++++++++--- .../selftests/kvm/x86_64/xss_msr_test.c | 70 ++++++++++++++++++ 5 files changed, 141 insertions(+), 10 deletions(-) create mode 100644 tools/testing/selftests/kvm/x86_64/xss_msr_test.c diff --git a/tools/testing/selftests/kvm/.gitignore b/tools/testing/selftests/kvm/.gitignore index b35da375530a..6e9ec34f8124 100644 --- a/tools/testing/selftests/kvm/.gitignore +++ b/tools/testing/selftests/kvm/.gitignore @@ -11,6 +11,7 @@ /x86_64/vmx_close_while_nested_test /x86_64/vmx_set_nested_state_test /x86_64/vmx_tsc_adjust_test +/x86_64/xss_msr_test /clear_dirty_log_test /dirty_log_test /kvm_create_max_vcpus diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile index c5ec868fa1e5..3138a916574a 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -25,6 +25,7 @@ TEST_GEN_PROGS_x86_64 += x86_64/vmx_close_while_nested_test TEST_GEN_PROGS_x86_64 += x86_64/vmx_dirty_log_test TEST_GEN_PROGS_x86_64 += x86_64/vmx_set_nested_state_test TEST_GEN_PROGS_x86_64 += x86_64/vmx_tsc_adjust_test +TEST_GEN_PROGS_x86_64 += x86_64/xss_msr_test TEST_GEN_PROGS_x86_64 += clear_dirty_log_test TEST_GEN_PROGS_x86_64 += dirty_log_test TEST_GEN_PROGS_x86_64 += kvm_create_max_vcpus diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools/testing/selftests/kvm/include/x86_64/processor.h index ff234018219c..635ee6c33ad2 100644 --- a/tools/testing/selftests/kvm/include/x86_64/processor.h +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h @@ -308,6 +308,8 @@ struct kvm_x86_state *vcpu_save_state(struct kvm_vm *vm, uint32_t vcpuid); void vcpu_load_state(struct kvm_vm *vm, uint32_t vcpuid, struct kvm_x86_state *state); +struct kvm_msr_list *kvm_get_msr_index_list(void); + struct kvm_cpuid2 *kvm_get_supported_cpuid(void); void vcpu_set_cpuid(struct kvm_vm *vm, uint32_t vcpuid, struct kvm_cpuid2 *cpuid); @@ -322,10 +324,13 @@ kvm_get_supported_cpuid_entry(uint32_t function) } uint64_t vcpu_get_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index); +int _vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index, + uint64_t msr_value); void vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index, uint64_t msr_value); -uint32_t kvm_get_cpuid_max(void); +uint32_t kvm_get_cpuid_max_basic(void); +uint32_t kvm_get_cpuid_max_extended(void); void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits); /* diff --git a/tools/testing/selftests/kvm/lib/x86_64/processor.c b/tools/testing/selftests/kvm/lib/x86_64/processor.c index 6698cb741e10..683d3bdb8f6a 100644 --- a/tools/testing/selftests/kvm/lib/x86_64/processor.c +++ b/tools/testing/selftests/kvm/lib/x86_64/processor.c @@ -869,7 +869,7 @@ uint64_t vcpu_get_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index) return buffer.entry.data; } -/* VCPU Set MSR +/* _VCPU Set MSR * * Input Args: * vm - Virtual Machine @@ -879,12 +879,12 @@ uint64_t vcpu_get_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index) * * Output Args: None * - * Return: On success, nothing. On failure a TEST_ASSERT is produced. + * Return: The result of KVM_SET_MSRS. * - * Set value of MSR for VCPU. + * Sets the value of an MSR for the given VCPU. */ -void vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index, - uint64_t msr_value) +int _vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index, + uint64_t msr_value) { struct vcpu *vcpu = vcpu_find(vm, vcpuid); struct { @@ -899,6 +899,29 @@ void vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index, buffer.entry.index = msr_index; buffer.entry.data = msr_value; r = ioctl(vcpu->fd, KVM_SET_MSRS, &buffer.header); + return r; +} + +/* VCPU Set MSR + * + * Input Args: + * vm - Virtual Machine + * vcpuid - VCPU ID + * msr_index - Index of MSR + * msr_value - New value of MSR + * + * Output Args: None + * + * Return: On success, nothing. On failure a TEST_ASSERT is produced. + * + * Set value of MSR for VCPU. + */ +void vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index, + uint64_t msr_value) +{ + int r; + + r = _vcpu_set_msr(vm, vcpuid, msr_index, msr_value); TEST_ASSERT(r == 1, "KVM_SET_MSRS IOCTL failed,\n" " rc: %i errno: %i", r, errno); } @@ -1000,19 +1023,45 @@ struct kvm_x86_state { struct kvm_msrs msrs; }; -static int kvm_get_num_msrs(struct kvm_vm *vm) +static int kvm_get_num_msrs_fd(int kvm_fd) { struct kvm_msr_list nmsrs; int r; nmsrs.nmsrs = 0; - r = ioctl(vm->kvm_fd, KVM_GET_MSR_INDEX_LIST, &nmsrs); + r = ioctl(kvm_fd, KVM_GET_MSR_INDEX_LIST, &nmsrs); TEST_ASSERT(r == -1 && errno == E2BIG, "Unexpected result from KVM_GET_MSR_INDEX_LIST probe, r: %i", r); return nmsrs.nmsrs; } +static int kvm_get_num_msrs(struct kvm_vm *vm) +{ + return kvm_get_num_msrs_fd(vm->kvm_fd); +} + +struct kvm_msr_list *kvm_get_msr_index_list(void) +{ + struct kvm_msr_list *list; + int nmsrs, r, kvm_fd; + + kvm_fd = open(KVM_DEV_PATH, O_RDONLY); + if (kvm_fd < 0) + exit(KSFT_SKIP); + + nmsrs = kvm_get_num_msrs_fd(kvm_fd); + list = malloc(sizeof(*list) + nmsrs * sizeof(list->indices[0])); + list->nmsrs = nmsrs; + r = ioctl(kvm_fd, KVM_GET_MSR_INDEX_LIST, list); + close(kvm_fd); + + TEST_ASSERT(r == 0, "Unexpected result from KVM_GET_MSR_INDEX_LIST, r: %i", + r); + + return list; +} + struct kvm_x86_state *vcpu_save_state(struct kvm_vm *vm, uint32_t vcpuid) { struct vcpu *vcpu = vcpu_find(vm, vcpuid); @@ -1158,7 +1207,12 @@ bool is_intel_cpu(void) return (ebx == chunk[0] && edx == chunk[1] && ecx == chunk[2]); } -uint32_t kvm_get_cpuid_max(void) +uint32_t kvm_get_cpuid_max_basic(void) +{ + return kvm_get_supported_cpuid_entry(0)->eax; +} + +uint32_t kvm_get_cpuid_max_extended(void) { return kvm_get_supported_cpuid_entry(0x80000000)->eax; } @@ -1169,7 +1223,7 @@ void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits) bool pae; /* SDM 4.1.4 */ - if (kvm_get_cpuid_max() < 0x80000008) { + if (kvm_get_cpuid_max_extended() < 0x80000008) { pae = kvm_get_supported_cpuid_entry(1)->edx & (1 << 6); *pa_bits = pae ? 36 : 32; *va_bits = 32; diff --git a/tools/testing/selftests/kvm/x86_64/xss_msr_test.c b/tools/testing/selftests/kvm/x86_64/xss_msr_test.c new file mode 100644 index 000000000000..17db23336673 --- /dev/null +++ b/tools/testing/selftests/kvm/x86_64/xss_msr_test.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019, Google LLC. + * + * Tests for the IA32_XSS MSR. + */ + +#define _GNU_SOURCE /* for program_invocation_short_name */ +#include + +#include "test_util.h" +#include "kvm_util.h" +#include "vmx.h" + +#define VCPU_ID 1 + +#define X86_FEATURE_XSAVES (1<<3) + +int main(int argc, char *argv[]) +{ + struct kvm_cpuid_entry2 *entry; + struct kvm_msr_list *list; + bool found_xss = false; + struct kvm_vm *vm; + uint64_t xss_val; + int i, r; + + /* Create VM */ + vm = vm_create_default(VCPU_ID, 0, 0); + + list = kvm_get_msr_index_list(); + for (i = 0; i < list->nmsrs; ++i) { + if (list->indices[i] == MSR_IA32_XSS) { + found_xss = true; + break; + } + } + + if (kvm_get_cpuid_max_basic() < 0xd) { + printf("XSAVES is not supported by the CPU.\n"); + exit(KSFT_SKIP); + } + + entry = kvm_get_supported_cpuid_index(0xd, 1); + TEST_ASSERT(found_xss == !!(entry->eax & X86_FEATURE_XSAVES), + "Support for IA32_XSS and support for XSAVES do not match."); + + if (!found_xss) { + printf("IA32_XSS and XSAVES are not supported. Skipping test.\n"); + exit(KSFT_SKIP); + } + + xss_val = vcpu_get_msr(vm, VCPU_ID, MSR_IA32_XSS); + TEST_ASSERT(xss_val == 0, "MSR_IA32_XSS should always be zero\n"); + + vcpu_set_msr(vm, VCPU_ID, MSR_IA32_XSS, xss_val); + /* + * At present, KVM only supports a guest IA32_XSS value of 0. Verify + * that trying to set the guest IA32_XSS to an unsupported value fails. + * + * Using '1' which is an illegal value since bit 0 is x87 state, which + * is covered by XCR0. + */ + r = _vcpu_set_msr(vm, VCPU_ID, MSR_IA32_XSS, 1); + TEST_ASSERT(r == 0, + "KVM_SET_MSRS IOCTL failed,\n rc: %i errno: %i", r, errno); + + free(list); + kvm_vm_free(vm); +}