From patchwork Tue Oct 15 10:10:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11191127 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5A4DB912 for ; Tue, 15 Oct 2019 16:38:59 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 42C5320650 for ; Tue, 15 Oct 2019 16:38:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 42C5320650 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B0BF46E85C; Tue, 15 Oct 2019 16:38:30 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1F5738958E; Tue, 15 Oct 2019 10:11:04 +0000 (UTC) Received: by mail-wm1-x341.google.com with SMTP id v17so19614478wml.4; Tue, 15 Oct 2019 03:11:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WvSHBpX9lS7H/7h03OBUZGWizg4wyuzQ6h+W62egxjQ=; b=c2aUzdHTd0PbEx/ykX7CNoCHYMvTXp94pldGORUy/wSRNwFlwadyjh8wxdlAKX1b5k KCPM1DWI/+6g5j3MNziA2UJfYSpdbJRfBbNoNDX7+hz8W0CXRZ9AVfNxCZYBoqACp9ww KknVLTj3mZhUZjQDte7eI1TD5Io7VUy/kUzMU9js1g0QIogE/4bB2rjQZsnWXYZVfNeu wRizztxu+1lONDCjXmgZjsA0EVNdbBlAKubojS7vb3vCD7X3j2Zkhja3RxFJKDe3iDI6 O0ugyx3IjlvU9kNjjnJU01geAY8JySu5xfXL8d+qIj3Aasx+wppRzpS3AxOnTP4mW7jx eA4g== X-Gm-Message-State: APjAAAWH465pnTxA00P20R+o0yVDo7vdp3uCeo8teL3fENKAGs1Cmb7e dlFY6ipP6e6wQPmSQHD8y4Q= X-Google-Smtp-Source: APXvYqwaRv8ZYQC8dAYjJc6iVKtoY8zuWRF0nJk+OnWTd2Ku/I5N1E6aLiEh9IxXvvzNWM2HsNdcGw== X-Received: by 2002:a7b:c413:: with SMTP id k19mr19955698wmi.175.1571134262527; Tue, 15 Oct 2019 03:11:02 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([93.51.16.173]) by smtp.gmail.com with ESMTPSA id y186sm42778837wmd.26.2019.10.15.03.11.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 Oct 2019 03:11:02 -0700 (PDT) From: kholk11@gmail.com To: linux-arm-msm@vger.kernel.org Subject: [PATCH v3 1/7] drm/msm/mdp5: Add optional TBU and TBU_RT clocks Date: Tue, 15 Oct 2019 12:10:52 +0200 Message-Id: <20191015101058.37157-2-kholk11@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191015101058.37157-1-kholk11@gmail.com> References: <20191015101058.37157-1-kholk11@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 15 Oct 2019 16:38:12 +0000 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WvSHBpX9lS7H/7h03OBUZGWizg4wyuzQ6h+W62egxjQ=; b=eyWWTg+jLxtt84nZoM5D4rcr+PH8MheESX0TLZRqE997hzCQdhz8dLvGO1VIIvIR7k MYDiERgsu9eEtbsu+2xlQ0ddekGD3+1i2qdFjDIg+NsDWJj0Ov3CWAJMGIZiEBdqhVt8 vDFRVm7pRnp85QftR8jftnJWImEweu+8K8Fca9lRFVtjugbvev3io6jZz1Bk/6Sv58oG pMVLkwOShw0uczWIyZmjNOdasg+kdkbz+NQbdzlQdG2eEnPvhRrQuZMg/v4/I4baEQBy BLrFyqJJ0ICw4XY+aAA57VJcDR3u1u9h4ywlyUqRs9pV8tixLkUnuAYH0QIh9WgdQmbq XGRg== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, freedreno@lists.freedesktop.org, marijns95@gmail.com, jonathan@marek.ca, airlied@linux.ie, gregkh@linuxfoundation.org, dri-devel@lists.freedesktop.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, tglx@linutronix.de, kholk11@gmail.com, sean@poorly.run, georgi.djakov@linaro.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: AngeloGioacchino Del Regno Some SoCs, like MSM8956/8976 (and APQ variants), do feature these clocks and we need to enable them in order to get both of the hw (mdp5/rot) Translation Buffer Units (TBUs) to properly work. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 10 ++++++++++ drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c index 5476892a335f..e43ecd4be10a 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c @@ -309,6 +309,10 @@ int mdp5_disable(struct mdp5_kms *mdp5_kms) mdp5_kms->enable_count--; WARN_ON(mdp5_kms->enable_count < 0); + if (mdp5_kms->tbu_rt_clk) + clk_disable_unprepare(mdp5_kms->tbu_rt_clk); + if (mdp5_kms->tbu_clk) + clk_disable_unprepare(mdp5_kms->tbu_clk); clk_disable_unprepare(mdp5_kms->ahb_clk); clk_disable_unprepare(mdp5_kms->axi_clk); clk_disable_unprepare(mdp5_kms->core_clk); @@ -329,6 +333,10 @@ int mdp5_enable(struct mdp5_kms *mdp5_kms) clk_prepare_enable(mdp5_kms->core_clk); if (mdp5_kms->lut_clk) clk_prepare_enable(mdp5_kms->lut_clk); + if (mdp5_kms->tbu_clk) + clk_prepare_enable(mdp5_kms->tbu_clk); + if (mdp5_kms->tbu_rt_clk) + clk_prepare_enable(mdp5_kms->tbu_rt_clk); return 0; } @@ -965,6 +973,8 @@ static int mdp5_init(struct platform_device *pdev, struct drm_device *dev) /* optional clocks: */ get_clk(pdev, &mdp5_kms->lut_clk, "lut", false); + get_clk(pdev, &mdp5_kms->tbu_clk, "tbu", false); + get_clk(pdev, &mdp5_kms->tbu_rt_clk, "tbu_rt", false); /* we need to set a default rate before enabling. Set a safe * rate first, then figure out hw revision, and then set a diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h index d1bf4fdfc815..128866742593 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h @@ -53,6 +53,8 @@ struct mdp5_kms { struct clk *ahb_clk; struct clk *core_clk; struct clk *lut_clk; + struct clk *tbu_clk; + struct clk *tbu_rt_clk; struct clk *vsync_clk; /* From patchwork Tue Oct 15 10:10:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11191101 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E39501390 for ; Tue, 15 Oct 2019 16:38:29 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C9FE920650 for ; Tue, 15 Oct 2019 16:38:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C9FE920650 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F3B426E84D; Tue, 15 Oct 2019 16:38:13 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3B0BD6E150; Tue, 15 Oct 2019 10:11:05 +0000 (UTC) Received: by mail-wm1-x342.google.com with SMTP id 7so20204564wme.1; Tue, 15 Oct 2019 03:11:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ekKfkWDCfgvdYFBqJ7b5n66skD2pbjEj/Fafy9wVYoE=; b=n01VZqttZy5Nrd9wNVfOIJGSQ/UMQL7x3LUqqOyPe/zjDfd9p0aoMe5Xf7CX5mEpwK PzArVvLGj6XKVBKv/zLizFSRO61sJaVEuzfTBWUrx2WufJGIXQBOV4+wjtSbeQLBwE47 hRIeeHK62YSpenom3Fe0QNjrlmM/bPL/ITi164NGBIpD0MdIzkPDPDeCe1QlsnvznaoW 0/M3v5Xvm0pZgeiG7qFKu4YXhBcTPP/ChaJLnA0Zm53uhC3iLpo1od09mdvdYvzESqHw V5FXdHsDDFuXtemNP7ZAT3alLOImv1CQYepKVstvSyF9uQSgfuiQA9+FzHngjar793LY UHmw== X-Gm-Message-State: APjAAAXqB2TgWEPXb8MpkxCD3+eivdaMlaqCWZLySYor7XtRXekWoVAI Hx0zkEDKIIMzOt7K8o33n1s= X-Google-Smtp-Source: APXvYqyPVLnjDiYl87POHRW8VN0tUihEAxvO/+0++G1lbLs4ypFF2T1OQn38A+5OS4GmxLtWwsmxdQ== X-Received: by 2002:a7b:caea:: with SMTP id t10mr15633501wml.38.1571134263669; Tue, 15 Oct 2019 03:11:03 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([93.51.16.173]) by smtp.gmail.com with ESMTPSA id y186sm42778837wmd.26.2019.10.15.03.11.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 Oct 2019 03:11:03 -0700 (PDT) From: kholk11@gmail.com To: linux-arm-msm@vger.kernel.org Subject: [PATCH v3 2/7] dt-bindings: msm/mdp5: Document optional TBU and TBU_RT clocks Date: Tue, 15 Oct 2019 12:10:53 +0200 Message-Id: <20191015101058.37157-3-kholk11@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191015101058.37157-1-kholk11@gmail.com> References: <20191015101058.37157-1-kholk11@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 15 Oct 2019 16:38:12 +0000 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ekKfkWDCfgvdYFBqJ7b5n66skD2pbjEj/Fafy9wVYoE=; b=vGMW97MJ6WdyPk02rAJYW5hBe109q7xTv+F9Pm2vjuApqi+XlsgeMuCb+B4BmrL4zg 8AlHifAmBgeR844Yp8XFZMS/NpBbhFvIM0gq/6PDxYYEE+DAU1NaRGwmQT1VxOLioYVL X/qKOx+WpVZpXZlIwvtp1bobfoeuVz1X0GtW9vy3MSKSXY+QvTLMsqIFPbj2TGFPrMjE AdF7tP9j4YSi4IL95oeg/UHYvoOsR6MtPqZXmJmgOw4KdYwwvpZ2ZSt41N678XK0Y4yQ 4FC1YqpdurRJQKS0KqlZcQSYCu4RCi8tZjJ4yVyRQJiGNy95+YGY6wMQm4bySqFDzFAm S62Q== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, freedreno@lists.freedesktop.org, marijns95@gmail.com, jonathan@marek.ca, airlied@linux.ie, gregkh@linuxfoundation.org, dri-devel@lists.freedesktop.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, tglx@linutronix.de, kholk11@gmail.com, sean@poorly.run, georgi.djakov@linaro.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: AngeloGioacchino Del Regno These two clocks aren't present in all versions of the MDP5 HW: where present, they are needed to enable the Translation Buffer Unit(s). Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/display/msm/mdp5.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/mdp5.txt b/Documentation/devicetree/bindings/display/msm/mdp5.txt index 4e11338548aa..43d11279c925 100644 --- a/Documentation/devicetree/bindings/display/msm/mdp5.txt +++ b/Documentation/devicetree/bindings/display/msm/mdp5.txt @@ -76,6 +76,8 @@ Required properties: Optional properties: - clock-names: the following clocks are optional: * "lut" + * "tbu" + * "tbu_rt" Example: From patchwork Tue Oct 15 10:10:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11191135 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C9E691390 for ; Tue, 15 Oct 2019 16:39:08 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B22BB20872 for ; Tue, 15 Oct 2019 16:39:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B22BB20872 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7EBF06E861; Tue, 15 Oct 2019 16:38:31 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by gabe.freedesktop.org (Postfix) with ESMTPS id 26A176E2D3; Tue, 15 Oct 2019 10:11:06 +0000 (UTC) Received: by mail-wr1-x444.google.com with SMTP id n14so23058062wrw.9; Tue, 15 Oct 2019 03:11:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NM0ZQ0YqLj9AAkiTqqi3iRVNKR68xa3LpemkjK2oJlo=; b=mZTEqNUj9c+uQS+5I4AYpUAAJUfWFBSDuySXgreUiNk0ZyTwmZQ9/uA2ifK+iXQN24 X4iAVBjMCoX7qasLLuh0YDoby3ilxlFH29Pbt5WXhD5Clbx8xZtCPIERCdrJY2sKfkeZ v0YIPZmnrVHpy6kNrhlGzivf/a/CCQ0GGkSKFwx/KNK/hNQY4nYt7PDNM8eKB5ag3IlK yHsVN5elP1eOYCUWNuUf7TKgKxpfbzYF/DX5AdMu95S2mOLx6Wahg152qbrrdChpkIpo 1ORrq2A/ZdhHBQA2Gi+bWVNf4GCQXdOBfh9Z+ReicDdGSE0MT2Y0V1hiNZ8MAKiufrci Vb8g== X-Gm-Message-State: APjAAAVL5Brro5sM99yIEvQ66VNvxJajd55NQ/vVIltHbewhsaFg18xr PZIKPMGAVKsHwEHn0MyueOw= X-Google-Smtp-Source: APXvYqzOdcC7RRLBjTc2K334M0Fr5ZEwG3WffQCqGTmKWtSovwVaphVJ6E4lNlM5CeQMkcNcCKu5tQ== X-Received: by 2002:adf:e542:: with SMTP id z2mr12482426wrm.338.1571134264591; Tue, 15 Oct 2019 03:11:04 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([93.51.16.173]) by smtp.gmail.com with ESMTPSA id y186sm42778837wmd.26.2019.10.15.03.11.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 Oct 2019 03:11:04 -0700 (PDT) From: kholk11@gmail.com To: linux-arm-msm@vger.kernel.org Subject: [PATCH v3 3/7] drm/msm/mdp5: Add configuration for msm8x76 Date: Tue, 15 Oct 2019 12:10:54 +0200 Message-Id: <20191015101058.37157-4-kholk11@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191015101058.37157-1-kholk11@gmail.com> References: <20191015101058.37157-1-kholk11@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 15 Oct 2019 16:38:12 +0000 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NM0ZQ0YqLj9AAkiTqqi3iRVNKR68xa3LpemkjK2oJlo=; b=cCi+p6beTsj9Yuz4bUkH9Vw5ZE6UE4ZhmyLPBEfR1p4bn6Ncll7Ic7/qG0UWV2ZHkE PDoWqmtjoYMp/AVgyW7PTFDrlFMVgdxl+nBaE7KAH6UHgYPATIh3FajubajMTOR85VpB aQn/ewD+3sNG/lTpPGukWGhkfmC8fX9mX1yZDwoCITtYZKm17RcCumKpZCUqWm43ZyiB 29SsLnqxfL4h+bAxvTwdS66sLC4PoT6fz0wM8+TmB/ydBbtVs7y2Toxs/bfqBZOp11vJ SebFLxUyt3NYqNeBAj9/vBTTf93HQxwfh2yg1Jpxk3BYSQmAv54oV3wDZgB6+JPYnJWc Mvzg== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, freedreno@lists.freedesktop.org, marijns95@gmail.com, jonathan@marek.ca, airlied@linux.ie, gregkh@linuxfoundation.org, dri-devel@lists.freedesktop.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, tglx@linutronix.de, kholk11@gmail.com, sean@poorly.run, georgi.djakov@linaro.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: AngeloGioacchino Del Regno Add the configuration entries for the MDP5 v1.11, found on MSM8956, MSM8976 and APQ variants. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 98 ++++++++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c index 7c9c1ddae821..1f48f64539a2 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c @@ -545,6 +545,103 @@ static const struct mdp5_cfg_hw msm8x96_config = { .max_clk = 412500000, }; +const struct mdp5_cfg_hw msm8x76_config = { + .name = "msm8x76", + .mdp = { + .count = 1, + .caps = MDP_CAP_SMP | + MDP_CAP_DSC | + MDP_CAP_SRC_SPLIT | + 0, + }, + .ctl = { + .count = 3, + .base = { 0x01000, 0x01200, 0x01400 }, + .flush_hw_mask = 0xffffffff, + }, + .smp = { + .mmb_count = 10, + .mmb_size = 10240, + .clients = { + [SSPP_VIG0] = 1, [SSPP_VIG1] = 9, + [SSPP_DMA0] = 4, + [SSPP_RGB0] = 7, [SSPP_RGB1] = 8, + }, + }, + .pipe_vig = { + .count = 2, + .base = { 0x04000, 0x06000 }, + .caps = MDP_PIPE_CAP_HFLIP | + MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_SCALE | + MDP_PIPE_CAP_CSC | + MDP_PIPE_CAP_DECIMATION | + MDP_PIPE_CAP_SW_PIX_EXT | + 0, + }, + .pipe_rgb = { + .count = 2, + .base = { 0x14000, 0x16000 }, + .caps = MDP_PIPE_CAP_HFLIP | + MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_DECIMATION | + MDP_PIPE_CAP_SW_PIX_EXT | + 0, + }, + .pipe_dma = { + .count = 1, + .base = { 0x24000 }, + .caps = MDP_PIPE_CAP_HFLIP | + MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_SW_PIX_EXT | + 0, + }, + .pipe_cursor = { + .count = 1, + .base = { 0x440DC }, + .caps = MDP_PIPE_CAP_HFLIP | + MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_SW_PIX_EXT | + MDP_PIPE_CAP_CURSOR | + 0, + }, + .lm = { + .count = 2, + .base = { 0x44000, 0x45000 }, + .instances = { + { .id = 0, .pp = 0, .dspp = 0, + .caps = MDP_LM_CAP_DISPLAY, }, + { .id = 1, .pp = -1, .dspp = -1, + .caps = MDP_LM_CAP_WB }, + }, + .nb_stages = 8, + .max_width = 2560, + .max_height = 0xFFFF, + }, + .dspp = { + .count = 1, + .base = { 0x54000 }, + + }, + .pp = { + .count = 3, + .base = { 0x70000, 0x70800, 0x72000 }, + }, + .dsc = { + .count = 2, + .base = { 0x80000, 0x80400 }, + }, + .intf = { + .base = { 0x6a000, 0x6a800, 0x6b000 }, + .connect = { + [0] = INTF_DISABLED, + [1] = INTF_DSI, + [2] = INTF_DSI, + }, + }, + .max_clk = 360000000, +}; + static const struct mdp5_cfg_hw msm8917_config = { .name = "msm8917", .mdp = { @@ -745,6 +842,7 @@ static const struct mdp5_cfg_handler cfg_handlers_v1[] = { { .revision = 6, .config = { .hw = &msm8x16_config } }, { .revision = 9, .config = { .hw = &msm8x94_config } }, { .revision = 7, .config = { .hw = &msm8x96_config } }, + { .revision = 11, .config = { .hw = &msm8x76_config } }, { .revision = 15, .config = { .hw = &msm8917_config } }, }; From patchwork Tue Oct 15 10:10:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11191133 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE0F5912 for ; Tue, 15 Oct 2019 16:39:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C683A20650 for ; Tue, 15 Oct 2019 16:39:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C683A20650 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 53D5B6E860; Tue, 15 Oct 2019 16:38:31 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by gabe.freedesktop.org (Postfix) with ESMTPS id 41B096E2D3; Tue, 15 Oct 2019 10:11:07 +0000 (UTC) Received: by mail-wr1-x442.google.com with SMTP id j11so23126906wrp.1; Tue, 15 Oct 2019 03:11:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yTcxngXEkdeT6TmpQoj373zyfLdTNEDntvuleghb3z0=; b=LXzO29c6J1Fsr2gycH05tePZdjxBFlf685JycVDJvS+U4V9shl7q9lIoTP//DV+Iam 25iYQSQwIILAZ9io3GKDua9DHG4/BgmvxFdf9WGs08EHoBjueDmoA4HctZgxLb7VHtAA chJDORGj9U0jrmcZ+y6j58mOxwWimKx2r1fuN8npj81alnrxNKisZ+pZ46RSLEVNzrta YSgO3KcUpBV2y0miMlOjunr0JO9m3RhLrOMnatJz3v8qxxcXvVSRSuQCXy/l6i5c+r8r a61y3f3lRaVWJ/Pieia339hsKy9zmBfe/UkLEf49MmNwFRQIUWE5qJVxT7ve3Uv4b/ul DJQw== X-Gm-Message-State: APjAAAXHhDAp48k3JAixTsNJOh7rG6BeWGggyyFIAhzWckJHVBOqAPni oA4GuW4uuJVBL4oWIP2thQA= X-Google-Smtp-Source: APXvYqx432gjFnXZKeEVX6PE1pt4uYSzdjJ9xDnwcnNJxxi74raOf/9SMD8lTM3ejiLUqunU0pwGkA== X-Received: by 2002:adf:f511:: with SMTP id q17mr1444270wro.3.1571134265626; Tue, 15 Oct 2019 03:11:05 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([93.51.16.173]) by smtp.gmail.com with ESMTPSA id y186sm42778837wmd.26.2019.10.15.03.11.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 Oct 2019 03:11:05 -0700 (PDT) From: kholk11@gmail.com To: linux-arm-msm@vger.kernel.org Subject: [PATCH v3 4/7] drm/msm/dsi: Add configuration for 28nm PLL on family B Date: Tue, 15 Oct 2019 12:10:55 +0200 Message-Id: <20191015101058.37157-5-kholk11@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191015101058.37157-1-kholk11@gmail.com> References: <20191015101058.37157-1-kholk11@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 15 Oct 2019 16:38:12 +0000 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yTcxngXEkdeT6TmpQoj373zyfLdTNEDntvuleghb3z0=; b=Tk3U4INVvMhn3XuqivdMRKYFmy1lMLS1ACVuZo/76VgXTjomtOlZ9OqUlracsv33Vq xFRM90kKKiMBBX2Ye8yIe2AWio4DmGOfvK5e4FCxQkKGwiajFBGfMYSrMFidAo0JZqt6 sqYkVftgtyc21x4VFhS+jB1QojVVwJSYMIR2Z5Q3r/PL97TAb8HnkzZSTa1YdE7o4UtC kTdMD3UDPaRixQN4c+ux/5arVaXw77pxXkwEQAN4WwhuvZ1nwrH/6bTQ6H+XfJU0NNH6 zIblq1TUfLvRJo3U16cbRxDaSlq06we2oGa/E3UW2RxmRX6fJiHbl/wtLhzm4NuxMHEG QuEw== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, freedreno@lists.freedesktop.org, marijns95@gmail.com, jonathan@marek.ca, airlied@linux.ie, gregkh@linuxfoundation.org, dri-devel@lists.freedesktop.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, tglx@linutronix.de, kholk11@gmail.com, sean@poorly.run, georgi.djakov@linaro.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: AngeloGioacchino Del Regno The 28nm PLL has a different iospace on MSM/APQ family B SoCs: add a new configuration and use it when the DT reports the "qcom,dsi-phy-28nm-hpm-fam-b" compatible. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 18 ++++++++++++++++++ 3 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index aa22c3ae5230..b0cfa67d2a57 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -483,6 +483,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { #ifdef CONFIG_DRM_MSM_DSI_28NM_PHY { .compatible = "qcom,dsi-phy-28nm-hpm", .data = &dsi_phy_28nm_hpm_cfgs }, + { .compatible = "qcom,dsi-phy-28nm-hpm-fam-b", + .data = &dsi_phy_28nm_hpm_famb_cfgs }, { .compatible = "qcom,dsi-phy-28nm-lp", .data = &dsi_phy_28nm_lp_cfgs }, #endif diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index c4069ce6afe6..24b294ed3059 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -40,6 +40,7 @@ struct msm_dsi_phy_cfg { }; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index b3f678f6c2aa..3b9300545e16 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -142,6 +142,24 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { .num_dsi_phy = 2, }; +const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { + .type = MSM_DSI_PHY_28NM_HPM, + .src_pll_truthtable = { {true, true}, {false, true} }, + .reg_cfg = { + .num = 1, + .regs = { + {"vddio", 100000, 100}, + }, + }, + .ops = { + .enable = dsi_28nm_phy_enable, + .disable = dsi_28nm_phy_disable, + .init = msm_dsi_phy_init_common, + }, + .io_start = { 0x1a94400, 0x1a94800 }, + .num_dsi_phy = 2, +}; + const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { .type = MSM_DSI_PHY_28NM_LP, .src_pll_truthtable = { {true, true}, {true, true} }, From patchwork Tue Oct 15 10:10:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11191123 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 00E5814ED for ; Tue, 15 Oct 2019 16:38:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D9F48217F9 for ; Tue, 15 Oct 2019 16:38:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D9F48217F9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1141A6E858; Tue, 15 Oct 2019 16:38:16 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) by gabe.freedesktop.org (Postfix) with ESMTPS id 417CE6E7AF; Tue, 15 Oct 2019 10:11:08 +0000 (UTC) Received: by mail-wm1-x343.google.com with SMTP id 5so20207317wmg.0; Tue, 15 Oct 2019 03:11:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A61m3u12oKMYzHTcbcOV5T5oBURDYn0JpKjZ9AFEq8Q=; b=FUk8wvXFaAY2Vv7HvFEKRdVyYo5FQ/MfUFP3banm8mISB34lz3u/6EM8YCSUAe8dAz Xlo9CzKpdMjZZNqGXCoPo8CDfVIs9huOxUJGF22mDkCuGqmb70se4+VxA3ezoKlBHlAw pGnXBV5O5sO+ynaieVRt0cF94ieJm2y282nxsXb36FR7y9ZvsWZpiWSDPqgrKI+AEA1K 9LQNlJhcBlPsyrbqg4g/Qd7C6k1MZI/UcaTfSI1ULAlAFjQSG26ClGJF3ZTLYGscTxkP 8BA9KAjmHkGYIHGnOnjZZ1qPPGIIrjwIdzwahapy0qLpO0ym4B0iTicd7MLV216JMqoh cthQ== X-Gm-Message-State: APjAAAWA9oqyD5LeCEB7/3L6H4ojDrYsqttB+/EiAMbnerK7lGbO1shG Np3/mE9dg7GfTpM8p4a4mII= X-Google-Smtp-Source: APXvYqwaT28ROh8W7H79jlgiIgSfuIxdnPW47q5u676fq4bJzk89FhRhR06TPi4ewvwrxDk1OGt4wA== X-Received: by 2002:a1c:4e15:: with SMTP id g21mr17440290wmh.148.1571134266579; Tue, 15 Oct 2019 03:11:06 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([93.51.16.173]) by smtp.gmail.com with ESMTPSA id y186sm42778837wmd.26.2019.10.15.03.11.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 Oct 2019 03:11:06 -0700 (PDT) From: kholk11@gmail.com To: linux-arm-msm@vger.kernel.org Subject: [PATCH v3 5/7] dt-bindings: msm/dsi: Add 28nm PLL for family B compatible Date: Tue, 15 Oct 2019 12:10:56 +0200 Message-Id: <20191015101058.37157-6-kholk11@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191015101058.37157-1-kholk11@gmail.com> References: <20191015101058.37157-1-kholk11@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 15 Oct 2019 16:38:12 +0000 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A61m3u12oKMYzHTcbcOV5T5oBURDYn0JpKjZ9AFEq8Q=; b=qSTQcxLV7utjjgxWnjpUDSKrGcqHyirT803FXxRmFjRBpo3nJvYYRZSoKowE2vU6Eb cVNVFjOYn/oRpsN6CRXydjBAYxYMVYXwufIggaWs0K8JiAtMDFxeIsIXBi9waJwla6T5 Cc4T3MvsIp9DdBEk7BxcCiJAAp6Jd576yiJjuYU6EBwcv+3ehvpshZX3kf4XpFpGQVuU NzA1UgWgosF6sEdm8+xss2QDWvrUzBqs0oj5duZ+F3OBCZvSqf2QiOF3TNk9nsZOvwNa NtH1acXumxrh3d8NaYA9Tdrrkplf5l0OAKUDz8RYVgryukn7FLQhZ4MP/PKP4erpWbnO b5ng== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, freedreno@lists.freedesktop.org, marijns95@gmail.com, jonathan@marek.ca, airlied@linux.ie, gregkh@linuxfoundation.org, dri-devel@lists.freedesktop.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, tglx@linutronix.de, kholk11@gmail.com, sean@poorly.run, georgi.djakov@linaro.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: AngeloGioacchino Del Regno On family B SoCs, the 28nm PLL has a different iospace address and that required a new compatible in the driver. Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/display/msm/dsi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index af95586c898f..d3ba9ee22f38 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -83,6 +83,7 @@ DSI PHY: Required properties: - compatible: Could be the following * "qcom,dsi-phy-28nm-hpm" + * "qcom,dsi-phy-28nm-hpm-fam-b" * "qcom,dsi-phy-28nm-lp" * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" From patchwork Tue Oct 15 10:10:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11191107 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A0938912 for ; Tue, 15 Oct 2019 16:38:37 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 88C5420650 for ; Tue, 15 Oct 2019 16:38:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 88C5420650 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D5BDB6E849; Tue, 15 Oct 2019 16:38:13 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2C8CC6E7AF; Tue, 15 Oct 2019 10:11:09 +0000 (UTC) Received: by mail-wr1-x443.google.com with SMTP id r3so23114805wrj.6; Tue, 15 Oct 2019 03:11:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sejk2YL89CpJ4d32oSXQDgSXo7RkFLMYz8ZMaclYygI=; b=S6gdssyEqwRBa/VmxPq07WKi2tHsnBf298V8lZiQMbVz1QgxUWgDFB0U/EITqwKlGO 7lS1igRdd2hsr3w78JPngj/lWJFdjLo/1WJwhHKyILi9KtAL+xKiQlaj1gCJqTB7u0NJ o636/xZAAs8SHjRLPtBN33XPDp/62hzmJ7ODtC1lcDGl3mpji+KdM4EoBCL0JJOIQFxZ MDmegcEzcSN8cbvrdKee+P0g3gcro2+8PI/i+p1xUSAhomzOytX15XD6oERbOqcFkrU3 en7DqJ8ZXvODMbow8G3boVnZXM6XlageONNouRIzTojYHzcViYt1O4RoA9r0Ppr7+Nca Is+A== X-Gm-Message-State: APjAAAWRAVl4z3NI1LA/f6co+HvUImR3FBBAXfsrrZzoW57LIBapwWTo ZIgyiW8+6S471S2A/ok0ySw= X-Google-Smtp-Source: APXvYqzh6ikhkAJIxT1JM2CyTFo8oYKiPl5pxfYWLXs0MtiFztOCEJ9XFRTRIUT8A9Ah3RBu5rJkWg== X-Received: by 2002:adf:e78c:: with SMTP id n12mr7287863wrm.351.1571134267656; Tue, 15 Oct 2019 03:11:07 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([93.51.16.173]) by smtp.gmail.com with ESMTPSA id y186sm42778837wmd.26.2019.10.15.03.11.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 Oct 2019 03:11:07 -0700 (PDT) From: kholk11@gmail.com To: linux-arm-msm@vger.kernel.org Subject: [PATCH v3 6/7] drm/msm/dsi: Add configuration for 8x76 Date: Tue, 15 Oct 2019 12:10:57 +0200 Message-Id: <20191015101058.37157-7-kholk11@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191015101058.37157-1-kholk11@gmail.com> References: <20191015101058.37157-1-kholk11@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 15 Oct 2019 16:38:12 +0000 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sejk2YL89CpJ4d32oSXQDgSXo7RkFLMYz8ZMaclYygI=; b=B+SgmOVhnzWDeXUA1P8zwLGAoRtUEyIp+HEVXLWOPieJYMxyG1a0Bx70L/QJXyGE9i +sETZCc6wUutYHXvZFmjDLgnMlzi5Y68riDfpGJlvnjbQH3BR0k5HiCJF8TNKAT3J/Uc MxaCL0nGuYADWtT9RgY4qmxKI++JEqHMUl7HNZpwGh8ROxHAoRO0Xijej2FM5sF7zJg1 gKIvibt2mIwmsTFKLulHIATbXxF/iKOtd24RYNkJzQ6LxSUqwOzdwS1nBJp7jU61ukbO 5WMjEIxs3wZtrxAoFebWSmUXfsashy0tUNpOJNfkC40K323my2wModg+yncwM8CE99mu 2PbA== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, freedreno@lists.freedesktop.org, marijns95@gmail.com, jonathan@marek.ca, airlied@linux.ie, gregkh@linuxfoundation.org, dri-devel@lists.freedesktop.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, tglx@linutronix.de, kholk11@gmail.com, sean@poorly.run, georgi.djakov@linaro.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: AngeloGioacchino Del Regno MSM8976, MSM8976 and APQ variants have DSI version 3:10040002 (DSI 6G V1.4.2), featuring two DSIs. They need three clocks (mdp_core, iface, bus), one GDSC and two vregs, VDDA at 1.2V and VDDIO at 1.8V. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + 2 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c index e74dc8cc904b..8364c2dc3f37 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -66,6 +66,26 @@ static const struct msm_dsi_config msm8916_dsi_cfg = { .num_dsi = 1, }; +static const char * const dsi_8976_bus_clk_names[] = { + "mdp_core", "iface", "bus", +}; + +static const struct msm_dsi_config msm8976_dsi_cfg = { + .io_offset = DSI_6G_REG_SHIFT, + .reg_cfg = { + .num = 3, + .regs = { + {"gdsc", -1, -1}, + {"vdda", 100000, 100}, /* 1.2 V */ + {"vddio", 100000, 100}, /* 1.8 V */ + }, + }, + .bus_clk_names = dsi_8976_bus_clk_names, + .num_bus_clks = ARRAY_SIZE(dsi_8976_bus_clk_names), + .io_start = { 0x1a94000, 0x1a96000 }, + .num_dsi = 2, +}; + static const struct msm_dsi_config msm8994_dsi_cfg = { .io_offset = DSI_6G_REG_SHIFT, .reg_cfg = { @@ -197,6 +217,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { &msm8916_dsi_cfg, &msm_dsi_6g_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_1, &msm8996_dsi_cfg, &msm_dsi_6g_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_2, + &msm8976_dsi_cfg, &msm_dsi_6g_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_0, &msm8998_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1, diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h index e2b7a7dfbe49..50a37ceb6a25 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -17,6 +17,7 @@ #define MSM_DSI_6G_VER_MINOR_V1_3 0x10030000 #define MSM_DSI_6G_VER_MINOR_V1_3_1 0x10030001 #define MSM_DSI_6G_VER_MINOR_V1_4_1 0x10040001 +#define MSM_DSI_6G_VER_MINOR_V1_4_2 0x10040002 #define MSM_DSI_6G_VER_MINOR_V2_2_0 0x20000000 #define MSM_DSI_6G_VER_MINOR_V2_2_1 0x20020001 From patchwork Tue Oct 15 10:10:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11191115 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E759A1390 for ; Tue, 15 Oct 2019 16:38:47 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CF85020650 for ; Tue, 15 Oct 2019 16:38:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CF85020650 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 990476E856; Tue, 15 Oct 2019 16:38:15 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5981D6E7B5; Tue, 15 Oct 2019 10:11:10 +0000 (UTC) Received: by mail-wr1-x443.google.com with SMTP id y19so23125504wrd.3; Tue, 15 Oct 2019 03:11:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M60UiEhUmmNWU8RgBGE4zx++F2XO1/RbSWEAXRbbk3s=; b=OLGSBj2JmuIdbmLCsrsNfq2wc4R12eF7qc+vnGQbRYt7KbNsQIs9heN1u5JKc8CGEi hABUSNGwH6ePSH3ufJNWzUO14A6hqG+E4k4x8DdWD5JEUElLhbqcIJZG4MClzjZ+rzuD yHqUz9H1m+nodsCPVtroT2hHzqTqkRIyM/X7DnBGlWuDK2uiqVukhs2wy3wgrWaHIW62 vXWNaRq4nLypsP7627Q07Jx1F1wDZpi+H7XHQpWFH3trp2Tt8UvucD0p8GJ22+FhMn5w l+oW9d627XBNc2qvo4NYilFMvum5QM4rO/+DWwmMhU0J3XpNPMhtjyfyHDeHGjzQCgth jFfg== X-Gm-Message-State: APjAAAUWBYEHyva0p3Tb2G8CdnG6iCAyC5gEhgKj0f2ki/BgIV0qpcLG QXXfs3HXKuWPfSxYjfORcFA= X-Google-Smtp-Source: APXvYqw4aZ2PYKCFamRjTt5WiSAtYexVCAcId2104Z1BtAOMPZyoYFmZgK+KR+ZwZImFuiKhpuwBKQ== X-Received: by 2002:a5d:5271:: with SMTP id l17mr30527096wrc.19.1571134268683; Tue, 15 Oct 2019 03:11:08 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([93.51.16.173]) by smtp.gmail.com with ESMTPSA id y186sm42778837wmd.26.2019.10.15.03.11.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 Oct 2019 03:11:08 -0700 (PDT) From: kholk11@gmail.com To: linux-arm-msm@vger.kernel.org Subject: [PATCH v3 7/7] drm/msm/adreno: Add support for Adreno 510 GPU Date: Tue, 15 Oct 2019 12:10:58 +0200 Message-Id: <20191015101058.37157-8-kholk11@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191015101058.37157-1-kholk11@gmail.com> References: <20191015101058.37157-1-kholk11@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 15 Oct 2019 16:38:12 +0000 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M60UiEhUmmNWU8RgBGE4zx++F2XO1/RbSWEAXRbbk3s=; b=GyIabOmOECxYleSCLas13t7q4NBINOq68jhNKOoYJAI2z7TTqLGG6au47mvQgJ6C4K PZuZ7ls9fsikhws6RC+Q1vVKzTQPW2XDDHyHR92umUam6iBbD8XxreU3/5yQzBvRgk57 glFYL0bZHUAHkwcIH95Ky/5t/2cGkyq8VTWeNcP7Wln6uO34aSveAIdpgejF/ODvlKIm Lt23hb0rdVInkwkzyETBq9zKkBMHG8j94zG3iYtqpV7jCoIeeNO6PT48WnB9SIw8HNzL GtibtEtecKckzZ0m3E1vuQFmqZkeglwIUgcPX7bIaJfJsKl3eC6PYl3XBFv7MrbDtclK g7+g== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, freedreno@lists.freedesktop.org, marijns95@gmail.com, jonathan@marek.ca, airlied@linux.ie, gregkh@linuxfoundation.org, dri-devel@lists.freedesktop.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, tglx@linutronix.de, kholk11@gmail.com, sean@poorly.run, georgi.djakov@linaro.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: AngeloGioacchino Del Regno The Adreno 510 GPU is a stripped version of the Adreno 5xx, found in low-end SoCs like 8x56 and 8x76, which has 256K of GMEM, with no GPMU nor ZAP. Also, since the Adreno 5xx part of this driver seems to be developed with high-end Adreno GPUs in mind, and since this is a lower end one, add a comment making clear which GPUs which support is not implemented yet is not using the GPMU related hw init code, so that future developers will not go crazy with that. By the way, the lower end Adreno GPUs with no GPMU are: A505/A506/A510 (usually no ZAP firmware) A508/A509/A512 (usually with ZAP firmware) Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 73 +++++++++++++++++----- drivers/gpu/drm/msm/adreno/a5xx_power.c | 7 +++ drivers/gpu/drm/msm/adreno/adreno_device.c | 15 +++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 ++ 4 files changed, 86 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 7fdc9e2bcaac..b02e2042547f 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -353,6 +353,9 @@ static int a5xx_me_init(struct msm_gpu *gpu) * 2D mode 3 draw */ OUT_RING(ring, 0x0000000B); + } else if (adreno_is_a510(adreno_gpu)) { + /* Workaround for token and syncs */ + OUT_RING(ring, 0x00000001); } else { /* No workarounds enabled */ OUT_RING(ring, 0x00000000); @@ -568,15 +571,24 @@ static int a5xx_hw_init(struct msm_gpu *gpu) 0x00100000 + adreno_gpu->gmem - 1); gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000); - gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x40); - if (adreno_is_a530(adreno_gpu)) - gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x40); - if (adreno_is_a540(adreno_gpu)) - gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400); - gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x80000060); - gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16); - - gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, (0x400 << 11 | 0x300 << 22)); + if (adreno_is_a510(adreno_gpu)) { + gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x20); + gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20); + gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x40000030); + gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x20100D0A); + gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, + (0x200 << 11 | 0x200 << 22)); + } else { + gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x40); + if (adreno_is_a530(adreno_gpu)) + gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x40); + if (adreno_is_a540(adreno_gpu)) + gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400); + gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x80000060); + gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16); + gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, + (0x400 << 11 | 0x300 << 22)); + } if (adreno_gpu->info->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI) gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8)); @@ -589,6 +601,19 @@ static int a5xx_hw_init(struct msm_gpu *gpu) /* Enable ME/PFP split notification */ gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL1, 0xA6FFFFFF); + /* + * In A5x, CCU can send context_done event of a particular context to + * UCHE which ultimately reaches CP even when there is valid + * transaction of that context inside CCU. This can let CP to program + * config registers, which will make the "valid transaction" inside + * CCU to be interpreted differently. This can cause gpu fault. This + * bug is fixed in latest A510 revision. To enable this bug fix - + * bit[11] of RB_DBG_ECO_CNTL need to be set to 0, default is 1 + * (disable). For older A510 version this bit is unused. + */ + if (adreno_is_a510(adreno_gpu)) + gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, (1 << 11), 0); + /* Enable HWCG */ a5xx_set_hwcg(gpu, true); @@ -635,7 +660,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu) /* UCHE */ gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16)); - if (adreno_is_a530(adreno_gpu)) + if (adreno_is_a530(adreno_gpu) || adreno_is_a510(adreno_gpu)) gpu_write(gpu, REG_A5XX_CP_PROTECT(17), ADRENO_PROTECT_RW(0x10000, 0x8000)); @@ -679,7 +704,8 @@ static int a5xx_hw_init(struct msm_gpu *gpu) a5xx_preempt_hw_init(gpu); - a5xx_gpmu_ucode_init(gpu); + if (!adreno_is_a510(adreno_gpu)) + a5xx_gpmu_ucode_init(gpu); ret = a5xx_ucode_init(gpu); if (ret) @@ -712,7 +738,8 @@ static int a5xx_hw_init(struct msm_gpu *gpu) } /* - * Try to load a zap shader into the secure world. If successful + * If the chip that we are using does support loading one, then + * try to load a zap shader into the secure world. If successful * we can use the CP to switch out of secure mode. If not then we * have no resource but to try to switch ourselves out manually. If we * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will @@ -1066,6 +1093,7 @@ static void a5xx_dump(struct msm_gpu *gpu) static int a5xx_pm_resume(struct msm_gpu *gpu) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); int ret; /* Turn on the core power */ @@ -1073,6 +1101,15 @@ static int a5xx_pm_resume(struct msm_gpu *gpu) if (ret) return ret; + if (adreno_is_a510(adreno_gpu)) { + /* Halt the sp_input_clk at HM level */ + gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, 0x00000055); + a5xx_set_hwcg(gpu, true); + /* Turn on sp_input_clk at HM level */ + gpu_rmw(gpu, REG_A5XX_RBBM_CLOCK_CNTL, 0xff, 0); + return 0; + } + /* Turn the RBCCU domain first to limit the chances of voltage droop */ gpu_write(gpu, REG_A5XX_GPMU_RBCCU_POWER_CNTL, 0x778000); @@ -1101,9 +1138,17 @@ static int a5xx_pm_resume(struct msm_gpu *gpu) static int a5xx_pm_suspend(struct msm_gpu *gpu) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + u32 mask = 0xf; + + /* A510 has 3 XIN ports in VBIF */ + if (adreno_is_a510(adreno_gpu)) + mask = 0x7; + /* Clear the VBIF pipe before shutting down */ - gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0xF); - spin_until((gpu_read(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL1) & 0xF) == 0xF); + gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, mask); + spin_until((gpu_read(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL1) & + mask) == mask); gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0); diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c b/drivers/gpu/drm/msm/adreno/a5xx_power.c index a3a06db675ba..321a8061fd32 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_power.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c @@ -297,6 +297,10 @@ int a5xx_power_init(struct msm_gpu *gpu) struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); int ret; + /* Not all A5xx chips have a GPMU */ + if (adreno_is_a510(adreno_gpu)) + return 0; + /* Set up the limits management */ if (adreno_is_a530(adreno_gpu)) a530_lm_setup(gpu); @@ -326,6 +330,9 @@ void a5xx_gpmu_ucode_init(struct msm_gpu *gpu) unsigned int *data, *ptr, *cmds; unsigned int cmds_size; + if (adreno_is_a510(adreno_gpu)) + return; + if (a5xx_gpu->gpmu_bo) return; diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 0888e0df660d..fbbdf86504f5 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -114,6 +114,21 @@ static const struct adreno_info gpulist[] = { .gmem = (SZ_1M + SZ_512K), .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a4xx_gpu_init, + }, { + .rev = ADRENO_REV(5, 1, 0, ANY_ID), + .revn = 510, + .name = "A510", + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + }, + .gmem = SZ_256K, + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .init = a5xx_gpu_init, }, { .rev = ADRENO_REV(5, 3, 0, 2), .revn = 530, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index d225a8a92e58..e71a7570ef72 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -212,6 +212,11 @@ static inline int adreno_is_a430(struct adreno_gpu *gpu) return gpu->revn == 430; } +static inline int adreno_is_a510(struct adreno_gpu *gpu) +{ + return gpu->revn == 510; +} + static inline int adreno_is_a530(struct adreno_gpu *gpu) { return gpu->revn == 530;