From patchwork Tue Oct 15 21:19:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11191747 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 621BE139A for ; Tue, 15 Oct 2019 21:21:21 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 125E620872 for ; Tue, 15 Oct 2019 21:21:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="GCW+eNnJ"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="rcPC9SKw" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 125E620872 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=lc4s6tnQbMy/eoBVBJdTpOhGuKzTQsVlERsOkmlpJrM=; b=GCW+eNnJJz4PQgrwm6HW/72goo PEP5FBosoJ3AS/ST//HjMSO00uXCCM7XnRa/bdHpKKGzym9BQwhKKiX+Oe2zxKx31udBe2c6shKJC dyW3V0Gt3JA6p68sNzeBxKreoKRWygSEnkgAOP4fEMsrPW9zH14SBsbQ7xW3tBvdiM1x3Gn33WwKZ +yvvB7BiZlqR6fzVekLvYuirpiCWv+aecBzjzTRJCNDN0L9hIexBUxc15nTIEK5HZGA6F/GsGNTkf Z7A7l3CaE/sjG8LuWhKWMN1Xfs+eENKNmvTP43XHwxJwgNiiL4Xr1lZnOQG8NqHbAbbChl2RaSuti O/KlOCgw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUFj-0003FU-0C; Tue, 15 Oct 2019 21:21:11 +0000 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUFS-00030a-T7 for linux-arm-kernel@lists.infradead.org; Tue, 15 Oct 2019 21:20:56 +0000 Received: by mail-wr1-x443.google.com with SMTP id p14so25525438wro.4 for ; Tue, 15 Oct 2019 14:20:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JRO3tClUzpMi9acjR3thqehN+ENGTOGjbtCc0AW0Fs8=; b=rcPC9SKwb8Zv8jq74ZzC+zkAEzX+eMOYIP5T/0XiMyNrcuSYsh4SIcU/6o9bnjL1B+ TzpFvCTfZaD+y977GS9kvLl75WuuTM1qvG19NrjV+oUNG/UrUZKOPDL9SR+66fN9bpVM bJLIw+9aSsGhsb4jP9JopFUY2DzhGthEsuSOgpPyTCpF45etZbIRIGH2DtDltc+bGb1L rb1kCBIt/xrg9XmmmuNaGks7oFcRre64qhh3f7LG0IlAt8Wn+hDd3bsKmz9GelL9jfXm q32DkCdgOzj2L/1urJXzztiEZZWPlJPmW5Vn6kDKL9M+ICyIqPbp9mKY/ia1Z8GLTL4l adOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JRO3tClUzpMi9acjR3thqehN+ENGTOGjbtCc0AW0Fs8=; b=gJnXCgbd6SGnAFGJaWlMldARLAMdafUiw/3xq0dfh2V1Ht8B+1m1cLwxISyJd42+x3 hTZEvWkuDLOLuM8f+svAd8U1C8Pmzr97loz2cbNVT5hlLPc6VlJaNW2euVTdIS8CJUAI Efyp8cNUZ4TjC+yWa9jgiqFmhmrmHlIq7AZt9fcs4yRNIDiNhj4iapUqbT1InDbgjkK7 F6aL8LsZByItutk/cIk6/8KkrLBhAxKu699S0FeLYy/q/zgja7oEuedNgq1d9iutbWTS euszsYuPd9wve6K5oTv55YevrXJRX+ZFUCwVKXyLcLtq1OkrDmKG2/yNeUe7xAZaZwLU PdyA== X-Gm-Message-State: APjAAAW5J9XlqO2tCuea0Smfkds6ntLqQ3j9vHtvYJj3OT6LOK3cm+EV QZQR4qd+DI6GrKuUFNczO0V/UQ== X-Google-Smtp-Source: APXvYqyY9s+if0u6fzoBhmY8qkQfL9fhhKAiFpjfY2QjZPxZhtz8OI3u5kWOiie5uvm9+0pTsueXhQ== X-Received: by 2002:a05:6000:1c7:: with SMTP id t7mr2595316wrx.198.1571174451413; Tue, 15 Oct 2019 14:20:51 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6815:3901:39d2:21a2:678a:9501]) by smtp.gmail.com with ESMTPSA id g185sm517649wme.10.2019.10.15.14.20.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 14:20:50 -0700 (PDT) From: Mike Leach To: mike.leach@linaro.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org Subject: [PATCH v3 01/11] coresight: etm4x: Fixes for ETM v4.4 architecture updates. Date: Tue, 15 Oct 2019 22:19:54 +0100 Message-Id: <20191015212004.24748-2-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191015212004.24748-1-mike.leach@linaro.org> References: <20191015212004.24748-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191015_142054_944353_523E4738 X-CRM114-Status: GOOD ( 13.73 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:443 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gregkh@linuxfoundation.org, suzuki.poulose@arm.com, mathieu.poirier@linaro.org, corbet@lwn.net MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org ETMv4.4 adds in support for tracing secure EL2 (per arch 8.x updates). Patch accounts for this new capability. Reviewed-by: Leo Yan Signed-off-by: Mike Leach --- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 12 ++++++------ drivers/hwtracing/coresight/coresight-etm4x.c | 5 ++++- drivers/hwtracing/coresight/coresight-etm4x.h | 15 +++++++++++---- 3 files changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 219c10eb752c..b6984be0c515 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -738,7 +738,7 @@ static ssize_t s_exlevel_vinst_show(struct device *dev, struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etmv4_config *config = &drvdata->config; - val = BMVAL(config->vinst_ctrl, 16, 19); + val = (config->vinst_ctrl & ETM_EXLEVEL_S_VICTLR_MASK) >> 16; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } @@ -754,8 +754,8 @@ static ssize_t s_exlevel_vinst_store(struct device *dev, return -EINVAL; spin_lock(&drvdata->spinlock); - /* clear all EXLEVEL_S bits (bit[18] is never implemented) */ - config->vinst_ctrl &= ~(BIT(16) | BIT(17) | BIT(19)); + /* clear all EXLEVEL_S bits */ + config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK); /* enable instruction tracing for corresponding exception level */ val &= drvdata->s_ex_level; config->vinst_ctrl |= (val << 16); @@ -773,7 +773,7 @@ static ssize_t ns_exlevel_vinst_show(struct device *dev, struct etmv4_config *config = &drvdata->config; /* EXLEVEL_NS, bits[23:20] */ - val = BMVAL(config->vinst_ctrl, 20, 23); + val = (config->vinst_ctrl & ETM_EXLEVEL_NS_VICTLR_MASK) >> 20; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } @@ -789,8 +789,8 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev, return -EINVAL; spin_lock(&drvdata->spinlock); - /* clear EXLEVEL_NS bits (bit[23] is never implemented */ - config->vinst_ctrl &= ~(BIT(20) | BIT(21) | BIT(22)); + /* clear EXLEVEL_NS bits */ + config->vinst_ctrl &= ~(ETM_EXLEVEL_NS_VICTLR_MASK); /* enable instruction tracing for corresponding exception level */ val &= drvdata->ns_ex_level; config->vinst_ctrl |= (val << 20); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 8f98701cadc5..efe120925f9d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -648,6 +648,7 @@ static void etm4_init_arch_data(void *info) * TRCARCHMAJ, bits[11:8] architecture major versin number */ drvdata->arch = BMVAL(etmidr1, 4, 11); + drvdata->config.arch = drvdata->arch; /* maximum size of resources */ etmidr2 = readl_relaxed(drvdata->base + TRCIDR2); @@ -799,6 +800,7 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config) static u64 etm4_get_access_type(struct etmv4_config *config) { u64 access_type = etm4_get_ns_access_type(config); + u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0; /* * EXLEVEL_S, bits[11:8], don't trace anything happening @@ -806,7 +808,8 @@ static u64 etm4_get_access_type(struct etmv4_config *config) */ access_type |= (ETM_EXLEVEL_S_APP | ETM_EXLEVEL_S_OS | - ETM_EXLEVEL_S_HYP); + s_hyp | + ETM_EXLEVEL_S_MON); return access_type; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 546d790cb01b..b873df38e7d8 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -181,17 +181,22 @@ /* PowerDown Control Register bits */ #define TRCPDCR_PU BIT(3) -/* secure state access levels */ +/* secure state access levels - TRCACATRn */ #define ETM_EXLEVEL_S_APP BIT(8) #define ETM_EXLEVEL_S_OS BIT(9) -#define ETM_EXLEVEL_S_NA BIT(10) -#define ETM_EXLEVEL_S_HYP BIT(11) -/* non-secure state access levels */ +#define ETM_EXLEVEL_S_HYP BIT(10) +#define ETM_EXLEVEL_S_MON BIT(11) +/* non-secure state access levels - TRCACATRn */ #define ETM_EXLEVEL_NS_APP BIT(12) #define ETM_EXLEVEL_NS_OS BIT(13) #define ETM_EXLEVEL_NS_HYP BIT(14) #define ETM_EXLEVEL_NS_NA BIT(15) +/* secure / non secure masks - TRCVICTLR, IDR3 */ +#define ETM_EXLEVEL_S_VICTLR_MASK GENMASK(19, 16) +/* NS MON (EL3) mode never implemented */ +#define ETM_EXLEVEL_NS_VICTLR_MASK GENMASK(22, 20) + /** * struct etmv4_config - configuration information related to an ETMv4 * @mode: Controls various modes supported by this ETM. @@ -238,6 +243,7 @@ * @vmid_mask0: VM ID comparator mask for comparator 0-3. * @vmid_mask1: VM ID comparator mask for comparator 4-7. * @ext_inp: External input selection. + * @arch: ETM architecture version (for arch dependent config). */ struct etmv4_config { u32 mode; @@ -280,6 +286,7 @@ struct etmv4_config { u32 vmid_mask0; u32 vmid_mask1; u32 ext_inp; + u8 arch; }; /** From patchwork Tue Oct 15 21:19:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11191745 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D71A814DB for ; Tue, 15 Oct 2019 21:20:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B481520873 for ; Tue, 15 Oct 2019 21:20:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="re7pyv7a"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="TaLFgxGU" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B481520873 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=ixkVZwGNhPa1tnTETkvQr8sH8SMYy9FMBHLPYJ8xvEM=; b=re7pyv7a10OFYsMQhjJIfN53Dt FErEKHUQVKoFOvdxXMg7TO3DZzg02mmVL3efANE4vFUrM4uhUM1AUQz62p4Ch085qwNhpLxP1db1I hBgw+fFt5TBpyTi1EQSsDaIRPUoW/MDb8Ur6ial746hNW/lRzHQ8U+TXA+7EZ2YLqyaI0Az2RQ6if fPtrHbYHHz0klziOhWXKo6YMrkAouxoceR5lX59KVO83heGGb++qSJEsKm1obAi6e5kiwZVToDErQ My3pei0rqcIN/UR7DOlGm7Tqg2nQr8Oz+6VvQHgUTuy7wm8ZXy2428L7oxpBbyxxaAb5kIyaSGGU9 6dNnoaZw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUFW-000333-3v; Tue, 15 Oct 2019 21:20:58 +0000 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUFS-00030b-Nx for linux-arm-kernel@lists.infradead.org; Tue, 15 Oct 2019 21:20:56 +0000 Received: by mail-wm1-x343.google.com with SMTP id y21so535583wmi.0 for ; Tue, 15 Oct 2019 14:20:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1/nDamY0vcX3mI7xTMQncxC0g153aasRB+pWD3LOkGg=; b=TaLFgxGU6jVMwelP5mURDjGBxzXtchTb23/HSjCJYtTlzeBmJ+juEnP00kaLhqirfA /a7Q6LMlt1AEKDjB4/wEw1kfV0tdz8YbXqkdB6whLnkpAod6YOvz64ceYZfYzCUnaUtJ jaWvDqW+We1YUnji8YRrVLyO4cdXdYn9hLtWNy8Qdbe3F5mH6TFzfu3I2DrEoBBFrXce CP0JU310tM7d4b3R/3FGd09iWc5Q93Cdr/qaKS2wXA6U8wWxe5iK5cDw9N48G2rjRK03 r/dU+RYCgxG3GnMmiT2d+RkXF4+qVl8yZAqgrHQcF9rMrMkBmtiOolPHyxgyrLgGV47D YIHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1/nDamY0vcX3mI7xTMQncxC0g153aasRB+pWD3LOkGg=; b=b8NddHEEdv2GIZpqZon4+TG+cp51BV6GkhM+szUmB7f03loOTHx2aNiVnQa8IL+vFT dYQPGtxrZAaG6s3+Yo6SjTCtPHBnEdvdQpLHfEM0wW/8wPomTAntk/CavAjFC+z3YwKU FSBlIx2/I28QJaM4HhbiylmOsFqQ9hJA7ywabrlQT4SaF5CcgBhieeA+OLUDlUP3+xiU /RtHhCAgSjFM2fNAgccKYOTC8XCI5ZiYL4fnfMuaBWYxP9JctSa4bbgkpjRTqxjYVO8K oliDbMy5dis4YcZX3HOUWXp3ZBv2Hidk5H4MstO7b/5sUE0YHC91tehRaMouhSv517pa H6eA== X-Gm-Message-State: APjAAAXSxUiki1h3HiOsTPdaL9IHUCcXkS/bmeFctZizfMhbT2P8RjZt 9zggsECuewdcncZ7UCb/m9RnBB1IMto= X-Google-Smtp-Source: APXvYqwEUxH5hHScjclAUc0I0+HFns+TpSn6XeAN1cUcRGj342cZJkUiCCw3wYm6utihcH46SCGX7Q== X-Received: by 2002:a1c:7c13:: with SMTP id x19mr388646wmc.80.1571174452543; Tue, 15 Oct 2019 14:20:52 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6815:3901:39d2:21a2:678a:9501]) by smtp.gmail.com with ESMTPSA id g185sm517649wme.10.2019.10.15.14.20.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 14:20:52 -0700 (PDT) From: Mike Leach To: mike.leach@linaro.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org Subject: [PATCH v3 02/11] coresight: etm4x: Fix input validation for sysfs. Date: Tue, 15 Oct 2019 22:19:55 +0100 Message-Id: <20191015212004.24748-3-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191015212004.24748-1-mike.leach@linaro.org> References: <20191015212004.24748-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191015_142054_780696_A44D4303 X-CRM114-Status: GOOD ( 12.44 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:343 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gregkh@linuxfoundation.org, suzuki.poulose@arm.com, stable , mathieu.poirier@linaro.org, corbet@lwn.net MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org A number of issues are fixed relating to sysfs input validation:- 1) bb_ctrl_store() - incorrect compare of bit select field to absolute value. Reworked per ETMv4 specification. 2) seq_event_store() - incorrect mask value - register has two event values. 3) cyc_threshold_store() - must mask with max before checking min otherwise wrapped values can set illegal value below min. 4) res_ctrl_store() - update to mask off all res0 bits. Reviewed-by: Leo Yan Reviewed-by: Mathieu Poirier Signed-off-by: Mike Leach Fixes: a77de2637c9eb ("coresight: etm4x: moving sysFS entries to a dedicated file") Cc: stable # 4.9+ --- .../coresight/coresight-etm4x-sysfs.c | 21 ++++++++++++------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index b6984be0c515..cc8156318018 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -652,10 +652,13 @@ static ssize_t cyc_threshold_store(struct device *dev, if (kstrtoul(buf, 16, &val)) return -EINVAL; + + /* mask off max threshold before checking min value */ + val &= ETM_CYC_THRESHOLD_MASK; if (val < drvdata->ccitmin) return -EINVAL; - config->ccctlr = val & ETM_CYC_THRESHOLD_MASK; + config->ccctlr = val; return size; } static DEVICE_ATTR_RW(cyc_threshold); @@ -686,14 +689,16 @@ static ssize_t bb_ctrl_store(struct device *dev, return -EINVAL; if (!drvdata->nr_addr_cmp) return -EINVAL; + /* - * Bit[7:0] selects which address range comparator is used for - * branch broadcast control. + * Bit[8] controls include(1) / exclude(0), bits[0-7] select + * individual range comparators. If include then at least 1 + * range must be selected. */ - if (BMVAL(val, 0, 7) > drvdata->nr_addr_cmp) + if ((val & BIT(8)) && (BMVAL(val, 0, 7) == 0)) return -EINVAL; - config->bb_ctrl = val; + config->bb_ctrl = val & GENMASK(8, 0); return size; } static DEVICE_ATTR_RW(bb_ctrl); @@ -1324,8 +1329,8 @@ static ssize_t seq_event_store(struct device *dev, spin_lock(&drvdata->spinlock); idx = config->seq_idx; - /* RST, bits[7:0] */ - config->seq_ctrl[idx] = val & 0xFF; + /* Seq control has two masks B[15:8] F[7:0] */ + config->seq_ctrl[idx] = val & 0xFFFF; spin_unlock(&drvdata->spinlock); return size; } @@ -1580,7 +1585,7 @@ static ssize_t res_ctrl_store(struct device *dev, if (idx % 2 != 0) /* PAIRINV, bit[21] */ val &= ~BIT(21); - config->res_ctrl[idx] = val; + config->res_ctrl[idx] = val & GENMASK(21, 0); spin_unlock(&drvdata->spinlock); return size; } From patchwork Tue Oct 15 21:19:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11191751 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2897E139A for ; Tue, 15 Oct 2019 21:21:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0424920663 for ; Tue, 15 Oct 2019 21:21:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="es2WUq77"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="xcD5Ld1H" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0424920663 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=cZDLiBd5AcPmOa8GFfXrZNC0nEb12QSgRN2dPc/MmIw=; b=es2WUq77zx9tAedIH3iCjiSRGi 4x15bg8Jv+Gqd31rfHtarAap/Vjeb1RRRK57DQtOD7o/d7Ua5G9y3lteVqktDWicwILKFYdHJERK2 47ZRRfDPXesGUm2z0+aEXKHwjlfcS9fFQ9p7R5tOWKmDeY14BUYvdBHzLjg4o2loN7g0bhuwrAuHx iybiSOKcGMuUowCQ2I3WrgmrSXwn58fn92ciC2B0xrugJ2B3CBUFEO3UufDYCYpWwf/zj1v3ahGBh E6xcdXKvy5CIGXSmgPCUGVxeUJRYDMFGtRkjMfDKLeK7OjCUd2CfN286zBTIRi8SDnuhSuNyihj+x zqaiMUmA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUGO-0003lN-U8; Tue, 15 Oct 2019 21:21:52 +0000 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUFT-00030e-Vu for linux-arm-kernel@lists.infradead.org; Tue, 15 Oct 2019 21:20:58 +0000 Received: by mail-wr1-x442.google.com with SMTP id z9so25523807wrl.11 for ; Tue, 15 Oct 2019 14:20:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=S3UAHvYOfzaEuKOyFm5bIC6hR9X0XbyeBd523nH5LjI=; b=xcD5Ld1HPwUSEVIVpOpCpXkrJCxGgE0dzmg8piQwSelX0dhdTPrJmP9RPfDEKFHtOZ DxaSlUo2Uf5MnFv3cq1KcjYEQts+YXvhsyn1sZMD8ijkfC+t2EhF7Ha/xSJ6FinS9Nfj NqaduGkLueoeY2dbeTcNl/M/usynHnzlPxo2fRrZOqHC+lCI2i+Kq+CAUpKeERK8r0Sh lRluCKn4Wm9aRv+1QpYKaG9o+sx1RB34xNh0AGMnzeDvqWyqFRRhrxuTHvzNqVPhopkD km5zbIiICHfL5yCQJU9MpJLj64IJVTXpywzRcZzkS0aovrAKBx/ZxLXK90KQR96SZGL+ ZGUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=S3UAHvYOfzaEuKOyFm5bIC6hR9X0XbyeBd523nH5LjI=; b=mCaE0YCYdoVdA6CCdgFrQMjwXIdrdS5nfzQCOzHpm1yBHf8t9py1eRNlxORzLFvqov eOfYeuYwUzCBiH26tTMPjiGk+0PBXRGzksYGZGuzLuiMcLWer3rbO6l5lMyE+N7pqiTl Ubl/dBwNfGYu+KWSgUl7Cln3+lw92PWs3AJHHalJEHZQ9KlhHaz3br5Onzm+7dLHrfl0 yDmJkcD4S87Zr3HKKq/t3wLfxNyrn5eNHZCuQokNJdAu9xEtPj8w+HCMB2kVLQqEjitn xRItAdVJA+S9RZujphfZ/LUTe4vOQRKAx+8TxHMD4denXCs+/iYc0RFZqbuXi7tLMj2r cPKg== X-Gm-Message-State: APjAAAX0RE/2fEDmxse+pguWUSirve2j+VEa6qCInVXCZ3gwQrAyKyM8 tPG9B3wSv4ly75gPz3to+dSBig== X-Google-Smtp-Source: APXvYqyzczWIc0NWBtEJtC3oudlkwG9WnR9D8/zcSa7AAMvPP2xM3ZOa49CggmwNX4G9OF3hlwisiQ== X-Received: by 2002:a5d:5386:: with SMTP id d6mr31586944wrv.155.1571174453471; Tue, 15 Oct 2019 14:20:53 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6815:3901:39d2:21a2:678a:9501]) by smtp.gmail.com with ESMTPSA id g185sm517649wme.10.2019.10.15.14.20.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 14:20:53 -0700 (PDT) From: Mike Leach To: mike.leach@linaro.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org Subject: [PATCH v3 03/11] coresight: etm4x: Add missing API to set EL match on address filters Date: Tue, 15 Oct 2019 22:19:56 +0100 Message-Id: <20191015212004.24748-4-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191015212004.24748-1-mike.leach@linaro.org> References: <20191015212004.24748-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191015_142056_021365_5FF5A783 X-CRM114-Status: GOOD ( 11.15 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:442 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gregkh@linuxfoundation.org, suzuki.poulose@arm.com, mathieu.poirier@linaro.org, corbet@lwn.net MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org TRCACATRn registers have match bits for secure and non-secure exception levels which are not accessible by the sysfs API. This adds a new sysfs parameter to enable this - addr_exlevel_s_ns. Reviewed-by: Suzuki K Poulose Signed-off-by: Mike Leach --- .../coresight/coresight-etm4x-sysfs.c | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index cc8156318018..45fa7743eea4 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1233,6 +1233,47 @@ static ssize_t addr_context_store(struct device *dev, } static DEVICE_ATTR_RW(addr_context); +static ssize_t addr_exlevel_s_ns_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + spin_lock(&drvdata->spinlock); + idx = config->addr_idx; + val = BMVAL(config->addr_acc[idx], 14, 8); + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t addr_exlevel_s_ns_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + if (val & ~((GENMASK(14, 8) >> 8)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = config->addr_idx; + /* clear Exlevel_ns & Exlevel_s bits[14:12, 11:8], bit[15] is res0 */ + config->addr_acc[idx] &= ~(GENMASK(14, 8)); + config->addr_acc[idx] |= (val << 8); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_exlevel_s_ns); + static ssize_t seq_idx_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -2038,6 +2079,7 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_addr_stop.attr, &dev_attr_addr_ctxtype.attr, &dev_attr_addr_context.attr, + &dev_attr_addr_exlevel_s_ns.attr, &dev_attr_seq_idx.attr, &dev_attr_seq_state.attr, &dev_attr_seq_event.attr, From patchwork Tue Oct 15 21:19:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11191749 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 67059139A for ; Tue, 15 Oct 2019 21:21:35 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3AE9920663 for ; Tue, 15 Oct 2019 21:21:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="PXljEDlh"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="txHkyKEH" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3AE9920663 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=9Z4SVfK1DmrRidBislJiHGNPbDjH4VuxZFaX1KSzaWI=; b=PXljEDlhvNbyY62G9PrXuzgy0A RqVeSjeQ7Of/zDgLBfvwUHonFO/WgU2dwWgkiGvFL+ur6Ybv6Ot0D6K9iMyakmPvA6Y2Z6hsoi6iB sGBKMJE8t4a0GGuMN44Jo6EMOmdMZiFY63n8nfUmTY5IDktLT9k6ux6fjd693YHLSgHfPzHXG+4EW uLqPiH2Fd6VmTkXukuQzHKlH1sRqwJuVNcnz/xvMP+OjVuXp+rJsoJ342JTF27GVI6mM5ZXudbNm7 JyPEMFSX47K6OBIhRX1Q5IMICPTxQBxV2bpMXldUy+JzhwQOfxLE0yRZE7Y3CKpggqxJxQ8NgCyrv PPGQ4/DQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUG6-0003Ww-BU; Tue, 15 Oct 2019 21:21:34 +0000 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUFT-00031C-L4 for linux-arm-kernel@lists.infradead.org; Tue, 15 Oct 2019 21:20:58 +0000 Received: by mail-wr1-x442.google.com with SMTP id j11so25558658wrp.1 for ; Tue, 15 Oct 2019 14:20:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JOcTLOqG6/8JBYdUtCKUjnzDdNgGAk3Lo1/s5SPM2vQ=; b=txHkyKEHnouHy5st53YylZ9aOwOE/Nv5QboOO2n6gYm2emk+vDvLPN0A5ycD1abeHA 8lk8l3WlyW/uy7wkh3zX6aYjwjKKVxEJps+ArOvRlLy2sxDr4604CEOf2nEFA9J9Rlf1 ZsMyYMssCf5h6eztKHJ+mdRsc7XR3pkSQ6rdf6sgnnz/IW4E8nnjoJyXomJyWhUEMpFR kKwTT6NDoVN8a45nKrMhL+4jjfOFai1phnO2fs2HYWD+zWXPSXOGcDPlGOpVwUVGTdNT Z0VArCUgeiI9MKrjxYPnHmtH+pxgfLIDE9Fl5rCU4bqX/2gI3mHxwGGLLBySw7CtzQRa cdLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JOcTLOqG6/8JBYdUtCKUjnzDdNgGAk3Lo1/s5SPM2vQ=; b=c+gVCvbp7U0hnVkShIkLE4dJsRJfoqS3TGWwcqnOE6zy2A799+g6BFdLXollpWyDGH 9DPy7avonRMPjmdVBmNwlf+xkGIBEsIExFWSTkCgjspfm0Ktm6ZXb+ibRBEbh3bZMyz0 zoCwFxTyPLF+jClZKwJrzr9xtHrqnRPSDCUTWnbB9Y1FfjbyZAGuo9VZ5TtJdE0QXuOt Qhd4iRqPmO7gLLk3dPXbsKisq+7d4jX3awjeFFVDRsySeWK71UmQEaDpmnJ5HmxEqT66 hYL2OvT/2HfoAjoasyD79ibBAdLY8wtA8HmM1Xhz3kzobMzCtSuWf+sSNUpqVYSP6MWa o/UQ== X-Gm-Message-State: APjAAAVv0StpdsZscu75Vpe8x6LTv8n9XqzPgXyVuQ2GjEzPwD9BTIO7 WEOoLUHqWgWCRUy7ozSUH3bbjg== X-Google-Smtp-Source: APXvYqz4Jr5RkrAR2YTxHroI0VVN3aiOOOy7zJSyn5Vbz8lAOydfpR7X29BrEx4tNDJ7mtRmQepUcQ== X-Received: by 2002:a5d:4a81:: with SMTP id o1mr31198630wrq.291.1571174454488; Tue, 15 Oct 2019 14:20:54 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6815:3901:39d2:21a2:678a:9501]) by smtp.gmail.com with ESMTPSA id g185sm517649wme.10.2019.10.15.14.20.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 14:20:54 -0700 (PDT) From: Mike Leach To: mike.leach@linaro.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org Subject: [PATCH v3 04/11] coresight: etm4x: Fix issues with start-stop logic. Date: Tue, 15 Oct 2019 22:19:57 +0100 Message-Id: <20191015212004.24748-5-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191015212004.24748-1-mike.leach@linaro.org> References: <20191015212004.24748-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191015_142055_688536_A06E95D9 X-CRM114-Status: GOOD ( 15.63 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:442 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gregkh@linuxfoundation.org, suzuki.poulose@arm.com, mathieu.poirier@linaro.org, corbet@lwn.net MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Fixes the following issues when using the ETMv4 start-stop logic. 1) Setting a start or a stop address should not automatically set the start-stop status to 'on'. The value set by the user in 'mode' must be respected or start instances could be missed. 2) Missing API for controlling TRCVIPCSSCTLR - start stop control by PE comparators. 3) Default ETM configuration sets a trace all range, and correctly sets the start-stop status bit. This was not being correctly reflected in the 'mode' parameter. Signed-off-by: Mike Leach --- .../coresight/coresight-etm4x-sysfs.c | 39 +++++++++++++++++-- drivers/hwtracing/coresight/coresight-etm4x.c | 1 + 2 files changed, 36 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 45fa7743eea4..2dbad7162557 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -217,6 +217,7 @@ static ssize_t reset_store(struct device *dev, /* No start-stop filtering for ViewInst */ config->vissctlr = 0x0; + config->vipcssctlr = 0x0; /* Disable seq events */ for (i = 0; i < drvdata->nrseqstate-1; i++) @@ -1059,8 +1060,6 @@ static ssize_t addr_start_store(struct device *dev, config->addr_val[idx] = (u64)val; config->addr_type[idx] = ETM_ADDR_TYPE_START; config->vissctlr |= BIT(idx); - /* SSSTATUS, bit[9] - turn on start/stop logic */ - config->vinst_ctrl |= BIT(9); spin_unlock(&drvdata->spinlock); return size; } @@ -1116,8 +1115,6 @@ static ssize_t addr_stop_store(struct device *dev, config->addr_val[idx] = (u64)val; config->addr_type[idx] = ETM_ADDR_TYPE_STOP; config->vissctlr |= BIT(idx + 16); - /* SSSTATUS, bit[9] - turn on start/stop logic */ - config->vinst_ctrl |= BIT(9); spin_unlock(&drvdata->spinlock); return size; } @@ -1274,6 +1271,39 @@ static ssize_t addr_exlevel_s_ns_store(struct device *dev, } static DEVICE_ATTR_RW(addr_exlevel_s_ns); +static ssize_t vinst_pe_cmp_start_stop_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (!drvdata->nr_pe_cmp) + return -EINVAL; + val = config->vipcssctlr; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static ssize_t vinst_pe_cmp_start_stop_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (!drvdata->nr_pe_cmp) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + config->vipcssctlr = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(vinst_pe_cmp_start_stop); + static ssize_t seq_idx_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -2080,6 +2110,7 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_addr_ctxtype.attr, &dev_attr_addr_context.attr, &dev_attr_addr_exlevel_s_ns.attr, + &dev_attr_vinst_pe_cmp_start_stop.attr, &dev_attr_seq_idx.attr, &dev_attr_seq_state.attr, &dev_attr_seq_event.attr, diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index efe120925f9d..d5148afdbe80 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -887,6 +887,7 @@ static void etm4_set_default_filter(struct etmv4_config *config) * in the started state */ config->vinst_ctrl |= BIT(9); + config->mode |= ETM_MODE_VIEWINST_STARTSTOP; /* No start-stop filtering for ViewInst */ config->vissctlr = 0x0; From patchwork Tue Oct 15 21:19:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11191753 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 29CC6139A for ; Tue, 15 Oct 2019 21:22:14 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EF75F20872 for ; Tue, 15 Oct 2019 21:22:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="lV0zuVpm"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="saIqH2d+" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EF75F20872 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=1KsxtlMChpa2YUZpvEZneI96zPuaEtMW2Piie18bX+0=; b=lV0zuVpmfcsvcPraneOsZGAFSI 3o2X1wgUt8Hqt9K9iLkZ0U6i3t3AiI7aZkUPWEBV+G9R9URldIkfc/8G7QiyvIEwNlbZ+0SdUA0An ypRggJU1kI9uAldJilj7H+ZL405a1LqfTrbJFg6poKb2CxcjoFFHJQ56YzqrpYx9LP9X6/tsaohPx WvtsNZcZdXxs9guJ4WLov2c8Kb5yT4AHA4r8v2C8BpMY/ueIUp7dvsmqWx6K3AB+ZepmSagUJWHKi ey0Ld0iXYwY45nBNqN4hFQyJeCMsgAJzkQtf9N7KVDbN9HI1DSqkqlgei62MkeS6ih+fOvSgz5zHq gIiM5b4w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUGb-0003xg-PL; Tue, 15 Oct 2019 21:22:05 +0000 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUFU-00031l-OZ for linux-arm-kernel@lists.infradead.org; Tue, 15 Oct 2019 21:20:58 +0000 Received: by mail-wm1-x342.google.com with SMTP id 3so517261wmi.3 for ; Tue, 15 Oct 2019 14:20:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rDuhlvBwT6uhRxkYGcIkKsWqjq/99jBo0tsPSyIyS1M=; b=saIqH2d+hiYz0leLDWU+UOsYxldo9oKXimdPq0hgyllb9sRTvKMMiWYCIKMvNjTvx0 UuD6Mlko6ETxXOXHxJeKVu8sk7V051KVJtQCEvY7mmD56ZxQX+XV3Ec2Bi+296aEe4NZ T/bbut1dKnKc0bTqMoV7Ky0CZW1RTMXdTgW6A8MsyynCt+LTBmD+1LsSX2WEtVGt/8LZ GuO591E35WtjZxvJRSqmRpxvAGi2ea/GLf8qV7Tvx0x6+hXpJIkxoci7vJYY+jKRkfPg xzzibw8S51kFex9fzjjjG1F/ofnYkbYlIvAtEPVNLfoJ6Jg863nVaoXx0nhaFBIF8x4m LX5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rDuhlvBwT6uhRxkYGcIkKsWqjq/99jBo0tsPSyIyS1M=; b=CKj1x63l28asCnuj82/tQrMN2k+c5//BQnuBo/ivm4KusolxHeV5STFSuF6dpx4Wax vbLjUmWzSNjV/bYcDCID38Gh5B6qTjO+r4r6IpkCfPgvwTDQR15iDjVggnl1ucH86f8Y pxV+m7gLR3lB7/IRPVhvmV2szSks6Md7Tr2+odR86pwOFlTBG8uyOznw2oVXCahuYU/2 q0WKsVpYTIRuhJcRJJ2Dezl9jnGiBw+24lXKPeBe8d+2q2YVLs2vO9xB7mrE1IWT+pQl nR+mt4N5s4rSv5sEkQutVi2pbIbj+E4JMZP2CyyDRrqy37w1zr+5ze0GjIccNNXpz86W ig2Q== X-Gm-Message-State: APjAAAUuKRW+snqJyrAtRxtrphDn4Xum4x/kWv8xsCxJIw9Tkj79+ChE xf7HQaFrom0VMWzFEH/Y673B9A== X-Google-Smtp-Source: APXvYqzsG0Havf3lVAWtlB+9gFIRq1BAC5ZnbgJMgm9uWjQ7BLw/fiVfBDesO7cFSGEAMf1/LcxEzQ== X-Received: by 2002:a05:600c:21da:: with SMTP id x26mr381977wmj.152.1571174455434; Tue, 15 Oct 2019 14:20:55 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6815:3901:39d2:21a2:678a:9501]) by smtp.gmail.com with ESMTPSA id g185sm517649wme.10.2019.10.15.14.20.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 14:20:55 -0700 (PDT) From: Mike Leach To: mike.leach@linaro.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org Subject: [PATCH v3 05/11] coresight: etm4x: Improve usability of sysfs - include/exclude addr. Date: Tue, 15 Oct 2019 22:19:58 +0100 Message-Id: <20191015212004.24748-6-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191015212004.24748-1-mike.leach@linaro.org> References: <20191015212004.24748-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191015_142056_807602_9465E116 X-CRM114-Status: GOOD ( 14.94 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:342 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gregkh@linuxfoundation.org, suzuki.poulose@arm.com, mathieu.poirier@linaro.org, corbet@lwn.net MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Setting include / exclude on a range had to be done by setting the bit in 'mode' before setting the range. However, setting this bit also had the effect of altering the current range as well. Changed to only set include / exclude setting of a range at the point of setting that range. Either use a 3rd input parameter as the include exclude value, or if not present use the current value of 'mode'. Do not change current range when 'mode' changes. Reviewed-by: Mathieu Poirier Signed-off-by: Mike Leach --- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 2dbad7162557..d772765dcd29 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -297,8 +297,6 @@ static ssize_t mode_store(struct device *dev, spin_lock(&drvdata->spinlock); config->mode = val & ETMv4_MODE_ALL; - etm4_set_mode_exclude(drvdata, - config->mode & ETM_MODE_EXCLUDE ? true : false); if (drvdata->instrp0 == true) { /* start by clearing instruction P0 field */ @@ -972,8 +970,12 @@ static ssize_t addr_range_store(struct device *dev, unsigned long val1, val2; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etmv4_config *config = &drvdata->config; + int elements, exclude; - if (sscanf(buf, "%lx %lx", &val1, &val2) != 2) + elements = sscanf(buf, "%lx %lx %x", &val1, &val2, &exclude); + + /* exclude is optional, but need at least two parameter */ + if (elements < 2) return -EINVAL; /* lower address comparator cannot have a higher address value */ if (val1 > val2) @@ -1001,9 +1003,11 @@ static ssize_t addr_range_store(struct device *dev, /* * Program include or exclude control bits for vinst or vdata * whenever we change addr comparators to ETM_ADDR_TYPE_RANGE + * use supplied value, or default to bit set in 'mode' */ - etm4_set_mode_exclude(drvdata, - config->mode & ETM_MODE_EXCLUDE ? true : false); + if (elements != 3) + exclude = config->mode & ETM_MODE_EXCLUDE; + etm4_set_mode_exclude(drvdata, exclude ? true : false); spin_unlock(&drvdata->spinlock); return size; From patchwork Tue Oct 15 21:19:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11191759 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7480B139A for ; Tue, 15 Oct 2019 21:22:57 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4CF9620663 for ; Tue, 15 Oct 2019 21:22:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Cbd/I0Ll"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="UAVuIDOU" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4CF9620663 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=4g6iu4AjeoQTyMIHNjMo8VKEx2IpDtZFWTgoA+4wPjw=; b=Cbd/I0LlM5Sv4TCFkYHQQCyYj7 DO0iJLO0oIt89NH4l3kFXpIDp14/2JykaLDuXC2KzXGGWTOfbYgmjuRewdJh3WM9SvS0jQP7ZWzda IfmO627hO7Cv+k0p2AbqeaYOslK8ImNxItyScH85nu8/9IxI237WQxCtSqQf9aCXoMBEMtwWkVztq gQUS4eflWf4tJxYNNa7rofGng7XEBACDp6VqITk/BKf+1IZhvLQRAGfRqfxSV8X6+XNmLCbTOUrIL igvUqtNayteCVbr1NjHCZC7ZGGudJXNKHaGP/v71KqNd7dc4/UDlA/g67Oz+Y+O0+Hc0BGOEXyRYR h6FfIxXQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUHL-0004if-1b; Tue, 15 Oct 2019 21:22:51 +0000 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUFW-00032u-Pv for linux-arm-kernel@lists.infradead.org; Tue, 15 Oct 2019 21:21:00 +0000 Received: by mail-wm1-x344.google.com with SMTP id y135so3201583wmc.1 for ; Tue, 15 Oct 2019 14:20:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DCrRB45TPzffk/SG7GSckRQdVqj6ZXw8oOiajo6TgQI=; b=UAVuIDOUvZZyV9kO0gvn+x6GUYOnygxkODoUfALvIsMaw6iKXTdPjrTQ1/2tAq/O+V 1gI0fI2ihrg8U0u8VsqX9bK7m++OeZO+pOB4s8FbkLSkgh5GetHpRKSuEnkcYvoO6vRv QZLjyukx3tERcSOtM/HXqRD1WPjjaSkRE4pKDGKxpLkNftixSK+CeITcMNnCZWHKP/sR J25T4HwG8yZeq/mXdvFlXV0aQt/TIeNhid+EFeQXv+3PhmV2hdOGaCJ/ymUvDXk+OmgG p2Wx3iSa82S9gQCS5xVVCQl/pjBO3YH1S9Mcch1qDEDGpthT5JAAyg4VPMOmYKvU0tRY //Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DCrRB45TPzffk/SG7GSckRQdVqj6ZXw8oOiajo6TgQI=; b=oVushefkOhSgQ7ek4RFYT8KInjMI4KXeiOv/4AFUxqMEsHyR3o3X1motOz5v4yCY/c 7orup5YJORh625SiLhDgEqqe8tBMVTEJFwXaSNIaXWgIKwV1bSH+FdjRJNQ5OH7NBSEz uF+43HHVw13WjmF0vioZ5VRkYAIZrbVno+XGKRfUj4sBtT43GeASlckPlxXd2Ry0RUDR FsA+O8lYjUrRzTzfXX7d4r73tpm2gNQFXJ7mg8iyGtfiLCkAab8vK3FlsDXR42S/f7oq 0fPcpK8OTLMLdyDRvubNqgfLefbHiI+zp1rwZ9LxkWoDwiCkwHTCnZKmPLYRbHgAcEZb AkHg== X-Gm-Message-State: APjAAAUbed1orqLyrQF9fKVMrIZz+dWMVfDi59XpuoGmkL56jxH3yME4 TDG9ztisMTD055O/SYWq+3X6mw== X-Google-Smtp-Source: APXvYqy4BIPufvC95A9MJQDTfCl0bC0PyKdCFW22iNvtafhJog5HkDLu3m0vixfc3Ae+wpStOmoTnA== X-Received: by 2002:a7b:cb95:: with SMTP id m21mr432615wmi.36.1571174456914; Tue, 15 Oct 2019 14:20:56 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6815:3901:39d2:21a2:678a:9501]) by smtp.gmail.com with ESMTPSA id g185sm517649wme.10.2019.10.15.14.20.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 14:20:56 -0700 (PDT) From: Mike Leach To: mike.leach@linaro.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org Subject: [PATCH v3 06/11] coresight: etm4x: Improve usability of sysfs - CID and VMID masks. Date: Tue, 15 Oct 2019 22:19:59 +0100 Message-Id: <20191015212004.24748-7-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191015212004.24748-1-mike.leach@linaro.org> References: <20191015212004.24748-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191015_142058_902811_B7DB6883 X-CRM114-Status: GOOD ( 14.22 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:344 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gregkh@linuxfoundation.org, suzuki.poulose@arm.com, mathieu.poirier@linaro.org, corbet@lwn.net MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Context ID and VM ID masks required 2 value inputs, even when the second value is ignored as insufficient CID / VMID comparators are implemented. Permit a single value to be used if that is sufficient to cover all implemented comparators. Reviewed-by: Mathieu Poirier Signed-off-by: Mike Leach --- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index d772765dcd29..d6fcb9fee97a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1794,6 +1794,7 @@ static ssize_t ctxid_masks_store(struct device *dev, unsigned long val1, val2, mask; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etmv4_config *config = &drvdata->config; + int nr_inputs; /* * Don't use contextID tracing if coming from a PID namespace. See @@ -1809,7 +1810,9 @@ static ssize_t ctxid_masks_store(struct device *dev, */ if (!drvdata->ctxid_size || !drvdata->numcidc) return -EINVAL; - if (sscanf(buf, "%lx %lx", &val1, &val2) != 2) + /* one mask if <= 4 comparators, two for up to 8 */ + nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2); + if ((drvdata->numcidc > 4) && (nr_inputs != 2)) return -EINVAL; spin_lock(&drvdata->spinlock); @@ -1983,6 +1986,7 @@ static ssize_t vmid_masks_store(struct device *dev, unsigned long val1, val2, mask; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etmv4_config *config = &drvdata->config; + int nr_inputs; /* * only implemented when vmid tracing is enabled, i.e. at least one @@ -1990,7 +1994,9 @@ static ssize_t vmid_masks_store(struct device *dev, */ if (!drvdata->vmid_size || !drvdata->numvmidc) return -EINVAL; - if (sscanf(buf, "%lx %lx", &val1, &val2) != 2) + /* one mask if <= 4 comparators, two for up to 8 */ + nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2); + if ((drvdata->numvmidc > 4) && (nr_inputs != 2)) return -EINVAL; spin_lock(&drvdata->spinlock); From patchwork Tue Oct 15 21:20:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11191757 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 56826139A for ; Tue, 15 Oct 2019 21:22:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3481120663 for ; Tue, 15 Oct 2019 21:22:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="jxQaeRFn"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Il5KPxhs" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3481120663 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=noJlcT7E17qvgD/qV75k1cYGlwkWaVGdKHl2m2YQLdc=; b=jxQaeRFn7fw3loVO/8oF12sIxq nslUqGZc+wDuBHw9uiwzw80+ubTL22MslvT3Q9Qkr84Gk/HfME6sa2y8S/m7f80FFWuK8AL2vpHbT 8kd56VVoW1azcvwQSE037+0NHTLpXhoNIoK1YNAiyhF7nWE/8NGe1Q/WEDSu7W1Ygt/gPC9piQd7Y +03JUsoZwhwI3MTc1LDsebtJV5qt7PnlK2g1uXh4KHmK48UhxoO0hjSiJfTL0B83a0Gs6A6g0LqJy +93FGFT9oGRFGNZZ+upzvZ1XkpE1sDyjnojzP0MgKAmTYjBR6vw0jc1v9WXvmTwwpHv9Gqs05ppUv rjHq7AaA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUH2-0004QK-Lh; Tue, 15 Oct 2019 21:22:32 +0000 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUFX-00033W-FN for linux-arm-kernel@lists.infradead.org; Tue, 15 Oct 2019 21:21:01 +0000 Received: by mail-wr1-x443.google.com with SMTP id y18so16088791wrn.5 for ; Tue, 15 Oct 2019 14:20:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=alLGJNyVbZt7KtVg3svRAQohavR/n2a/uHVAjbCo+ys=; b=Il5KPxhsnxm+Ix6dhPSpK8HRTsKtqHrGi6vQ9B32L+KB5lI2iQM7q2rX5lNgxBZOAj sTxK+FQXLWS8NNlBwBSn2RemW7KmzzP1SIi23IUKkgFUD4Vz5NFVSXqfM40bHG9ywp5L 1UdLhA1cG/g+DPMwAKB1ZdZiCkVE9ijj5PhrTvqxwIFwENPVwLWdyyyDopnzsG+7FAPC 8ncZ4P27r9qnPSa7VKYt8jgJAt7qsd9kZ3j4cffLY4gOhhMKB0K+26uuZdq75L2mRUfZ 0HKO3jeMkq0nV0bMOSB2oj7T3jVoZAtLIFeM4gsp6lGEuMBX4zChruTqJykbO6VtrV/Q zvmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=alLGJNyVbZt7KtVg3svRAQohavR/n2a/uHVAjbCo+ys=; b=AGxXAlYFbxQ3fq/a5zXxfoQ5xTZ0JEPCetrk2JuQeL4yN3+2YEN9eZjh44lUa46uab oPPy8Uvf5pAD1UeILE1YIkTX+AMkh8+293N4iLzVIRaFwK08luE0VwhRCX6VRs4S43js Ft1ZYwPGjICscFliedGQbXto9qj4bEwfqfO9fEm6WjxXqIxr9/VF5D7sjoweb8DoQJXv sydLrOG7FIXsvPQVq7jXmMqZJIYDNwqC6UqKCwGdOuDWPlFnCexubkaatXUBpuPVSVhX ikhe/PdsDtroV4ThokJtACPiUW5XIN1Dzb+IogVgvCTLy2hfgMkjbEK31d3FUxc0PbOu RXug== X-Gm-Message-State: APjAAAXqDNUZKWcJkvhPZOWFLOLOFTF1QD/DxxgrLsXzhsRozF1JG6J8 0M4Hh+SwFuzyIjwyCpf7WLFDPg== X-Google-Smtp-Source: APXvYqzkHH8ZWehVkIFHGRN8tgNXwkkU2U/LLCNdx5ni4mo3xTpD80O35029jqeWSB380+7UDX4RGw== X-Received: by 2002:a05:6000:1252:: with SMTP id j18mr3244847wrx.23.1571174457936; Tue, 15 Oct 2019 14:20:57 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6815:3901:39d2:21a2:678a:9501]) by smtp.gmail.com with ESMTPSA id g185sm517649wme.10.2019.10.15.14.20.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 14:20:57 -0700 (PDT) From: Mike Leach To: mike.leach@linaro.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org Subject: [PATCH v3 07/11] coresight: etm4x: Add view comparator settings API to sysfs. Date: Tue, 15 Oct 2019 22:20:00 +0100 Message-Id: <20191015212004.24748-8-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191015212004.24748-1-mike.leach@linaro.org> References: <20191015212004.24748-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191015_142059_539939_C72A6A26 X-CRM114-Status: GOOD ( 15.46 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:443 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gregkh@linuxfoundation.org, suzuki.poulose@arm.com, mathieu.poirier@linaro.org, corbet@lwn.net MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Currently it is not possible to view the current settings of a given address comparator without knowing what type it is set to. For example, if a comparator is set as an addr_start comparator, attempting to read addr_stop for the same index will result in an error. addr_cmp_view is added to allow the user to see the current settings of the indexed address comparator without resorting to trial and error when the set type is not known. Reviewed-by: Mathieu Poirier Reviewed-by: Leo Yan Signed-off-by: Mike Leach --- .../coresight/coresight-etm4x-sysfs.c | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index d6fcb9fee97a..ca1a54411225 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1275,6 +1275,57 @@ static ssize_t addr_exlevel_s_ns_store(struct device *dev, } static DEVICE_ATTR_RW(addr_exlevel_s_ns); +static const char * const addr_type_names[] = { + "unused", + "single", + "range", + "start", + "stop" +}; + +static ssize_t addr_cmp_view_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u8 idx, addr_type; + unsigned long addr_v, addr_v2, addr_ctrl; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + int size = 0; + bool exclude = false; + + spin_lock(&drvdata->spinlock); + idx = config->addr_idx; + addr_v = config->addr_val[idx]; + addr_ctrl = config->addr_acc[idx]; + addr_type = config->addr_type[idx]; + if (addr_type == ETM_ADDR_TYPE_RANGE) { + if (idx & 0x1) { + idx -= 1; + addr_v2 = addr_v; + addr_v = config->addr_val[idx]; + } else { + addr_v2 = config->addr_val[idx + 1]; + } + exclude = config->viiectlr & BIT(idx / 2 + 16); + } + spin_unlock(&drvdata->spinlock); + if (addr_type) { + size = scnprintf(buf, PAGE_SIZE, "addr_cmp[%i] %s %#lx", idx, + addr_type_names[addr_type], addr_v); + if (addr_type == ETM_ADDR_TYPE_RANGE) { + size += scnprintf(buf + size, PAGE_SIZE - size, + " %#lx %s", addr_v2, + exclude ? "exclude" : "include"); + } + size += scnprintf(buf + size, PAGE_SIZE - size, + " ctrl(%#lx)\n", addr_ctrl); + } else { + size = scnprintf(buf, PAGE_SIZE, "addr_cmp[%i] unused\n", idx); + } + return size; +} +static DEVICE_ATTR_RO(addr_cmp_view); + static ssize_t vinst_pe_cmp_start_stop_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -2120,6 +2171,7 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_addr_ctxtype.attr, &dev_attr_addr_context.attr, &dev_attr_addr_exlevel_s_ns.attr, + &dev_attr_addr_cmp_view.attr, &dev_attr_vinst_pe_cmp_start_stop.attr, &dev_attr_seq_idx.attr, &dev_attr_seq_state.attr, From patchwork Tue Oct 15 21:20:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11191761 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E4BB614DB for ; Tue, 15 Oct 2019 21:23:05 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A2C8720663 for ; Tue, 15 Oct 2019 21:23:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="RzngCFAY"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="b2vQVEAa" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A2C8720663 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=YaeM1YaWq+ugjUQgR96LiPpSkl/yerw8OO0NhDIQlCM=; b=RzngCFAYKZNprZLIrsaPzNyJIl InZfsz5QkBLE4HAvyVOSxUU/elhEXQoSIf8PwPW6jgUMny1QxHC9yMxDTqGi84TIOKrdh8B6dhmN3 WJVOYHXHvV/9Kl8xmIW3FH1j4UlrTQAUll8Q6hBwc3kgfyOlcS431Agaz3lNKAHV6uq7FiSm6pyDo Cd4IsALrKZyWu+pYeEJ4IMJaC0JD48aplOIsyX4jfJTus+yihw2eeDfx0nw+VlCveqCs+FBz5hZLA O6CsAJCrsKFtxvcvdEAWaua+mZVm5sTiK7IVTVNB6o03jpS4XjYYtJAueTSw+D9aKY1qN+Uahzpcg lXJmfSow==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUHY-0004vI-Oe; Tue, 15 Oct 2019 21:23:04 +0000 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUFY-000357-Le for linux-arm-kernel@lists.infradead.org; Tue, 15 Oct 2019 21:21:02 +0000 Received: by mail-wm1-x342.google.com with SMTP id y135so3201651wmc.1 for ; Tue, 15 Oct 2019 14:21:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9CcXkND/loPHwB/0IZNErSLM2EUjzrpfm9HiXP45pXY=; b=b2vQVEAaEbr7dtIjqS634fBexGd6fJsvn38Qq+x6YBwgw+FnV1xNQ+q1NawAr3lrGp 6EPI4J40sfzk6lM4BAnI4BiPQDpbPW075bx3J1dir9Unw32cw7tuhvklkXaA9XNYoukb 4oX2i7ItlhAmCFPNMIuF8VQrwrz4rCfjS5jXhnQp7xf0AqeyqqPvHINM4rGfkLpabVyx fROFV5m1jocu7afgkJAqDT8VocPMtg2ZB8C460/7zz4rkGUAxPjZsKsEygz4o/bfcPkS R+fiyauxnk5rk+WLF/TmM372a3AMUW6jpKcItbhawSi1F1JrV2Gt4gx6cmYGV+yKRs9M W1Kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9CcXkND/loPHwB/0IZNErSLM2EUjzrpfm9HiXP45pXY=; b=gznXzEx/+/em8HjhM/OWNpeoPTEs4lzW6sbMoHSARJtmKXJ3UCnrd34XCIkIzJStv4 w8EyzOKTd3T/sfM2XyoOUus0/3BXohVftXvAB+u4OgudJKNSStcAbd2daOz/SpxePn2c zcM0dgx0vEzGtfa3Fg8CqmD/huZUx926j8vecgAO+W/85bM1UHUl8pVWxxkrbabG8oI8 /lOJBTZkR4O2+MX9ZP68lrbKXyoxaVb62lRE56GitHwXifN6j1q374uC5Z7ENnJy/YOu OLpxZUMTFcQaGwZFzyaMO8Zb5IR6EcXiU30jr7SJ/d2AlCRlMGSApAPsZE8PhaeRhvmS BdUA== X-Gm-Message-State: APjAAAU12hyajOH4YHlTLOe83oVKXPN5QEQZ+bzBBnWkLMROtMBEMnTU TVPnB875IkSEhGFYMiblOKJBVw== X-Google-Smtp-Source: APXvYqwEoEg6Td0hp924Qe5H3qf/s1UqPbK7OY4uRMBUJN8+TLbAC7gpR320jOm1B6Eah76TdshzFA== X-Received: by 2002:a1c:7401:: with SMTP id p1mr430900wmc.144.1571174459118; Tue, 15 Oct 2019 14:20:59 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6815:3901:39d2:21a2:678a:9501]) by smtp.gmail.com with ESMTPSA id g185sm517649wme.10.2019.10.15.14.20.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 14:20:58 -0700 (PDT) From: Mike Leach To: mike.leach@linaro.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org Subject: [PATCH v3 08/11] coresight: etm4x: Add missing single-shot control API to sysfs Date: Tue, 15 Oct 2019 22:20:01 +0100 Message-Id: <20191015212004.24748-9-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191015212004.24748-1-mike.leach@linaro.org> References: <20191015212004.24748-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191015_142100_732226_372CEF8E X-CRM114-Status: GOOD ( 16.58 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:342 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gregkh@linuxfoundation.org, suzuki.poulose@arm.com, mathieu.poirier@linaro.org, corbet@lwn.net MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org An API to control single-shot comparator operation was missing from sysfs. This adds the parameters to sysfs to allow programming of this feature. Signed-off-by: Mike Leach --- .../coresight/coresight-etm4x-sysfs.c | 122 ++++++++++++++++++ drivers/hwtracing/coresight/coresight-etm4x.c | 26 +++- drivers/hwtracing/coresight/coresight-etm4x.h | 2 + 3 files changed, 149 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index ca1a54411225..43b3f0976034 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -239,6 +239,7 @@ static ssize_t reset_store(struct device *dev, for (i = 0; i < drvdata->nr_resource; i++) config->res_ctrl[i] = 0x0; + config->ss_idx = 0x0; for (i = 0; i < drvdata->nr_ss_cmp; i++) { config->ss_ctrl[i] = 0x0; config->ss_pe_cmp[i] = 0x0; @@ -1717,6 +1718,123 @@ static ssize_t res_ctrl_store(struct device *dev, } static DEVICE_ATTR_RW(res_ctrl); +static ssize_t sshot_idx_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + val = config->ss_idx; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t sshot_idx_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val >= drvdata->nr_ss_cmp) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + config->ss_idx = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(sshot_idx); + +static ssize_t sshot_ctrl_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + spin_lock(&drvdata->spinlock); + val = config->ss_ctrl[config->ss_idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t sshot_ctrl_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = config->ss_idx; + config->ss_ctrl[idx] = val & GENMASK(24, 0); + /* must clear bit 31 in related status register on programming */ + config->ss_status[idx] &= ~BIT(31); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(sshot_ctrl); + +static ssize_t sshot_status_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + spin_lock(&drvdata->spinlock); + val = config->ss_status[config->ss_idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(sshot_status); + +static ssize_t sshot_pe_ctrl_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + spin_lock(&drvdata->spinlock); + val = config->ss_pe_cmp[config->ss_idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t sshot_pe_ctrl_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = config->ss_idx; + config->ss_pe_cmp[idx] = val & GENMASK(7, 0); + /* must clear bit 31 in related status register on programming */ + config->ss_status[idx] &= ~BIT(31); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(sshot_pe_ctrl); + static ssize_t ctxid_idx_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -2173,6 +2291,10 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_addr_exlevel_s_ns.attr, &dev_attr_addr_cmp_view.attr, &dev_attr_vinst_pe_cmp_start_stop.attr, + &dev_attr_sshot_idx.attr, + &dev_attr_sshot_ctrl.attr, + &dev_attr_sshot_pe_ctrl.attr, + &dev_attr_sshot_status.attr, &dev_attr_seq_idx.attr, &dev_attr_seq_state.attr, &dev_attr_seq_event.attr, diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index d5148afdbe80..dc3f507e7562 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -168,6 +168,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) drvdata->base + TRCRSCTLRn(i)); for (i = 0; i < drvdata->nr_ss_cmp; i++) { + /* always clear status bit on restart if using single-shot */ + if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) + config->ss_status[i] &= ~BIT(31); writel_relaxed(config->ss_ctrl[i], drvdata->base + TRCSSCCRn(i)); writel_relaxed(config->ss_status[i], @@ -467,6 +470,9 @@ static void etm4_disable_hw(void *info) { u32 control; struct etmv4_drvdata *drvdata = info; + struct etmv4_config *config = &drvdata->config; + struct device *etm_dev = &drvdata->csdev->dev; + int i; CS_UNLOCK(drvdata->base); @@ -489,6 +495,18 @@ static void etm4_disable_hw(void *info) isb(); writel_relaxed(control, drvdata->base + TRCPRGCTLR); + /* wait for TRCSTATR.PMSTABLE to go to '1' */ + if (coresight_timeout(drvdata->base, TRCSTATR, + TRCSTATR_PMSTABLE_BIT, 1)) + dev_err(etm_dev, + "timeout while waiting for PM stable Trace Status\n"); + + /* read the status of the single shot comparators */ + for (i = 0; i < drvdata->nr_ss_cmp; i++) { + config->ss_status[i] = + readl_relaxed(drvdata->base + TRCSSCSRn(i)); + } + coresight_disclaim_device_unlocked(drvdata->base); CS_LOCK(drvdata->base); @@ -595,6 +613,7 @@ static void etm4_init_arch_data(void *info) u32 etmidr4; u32 etmidr5; struct etmv4_drvdata *drvdata = info; + int i; /* Make sure all registers are accessible */ etm4_os_unlock(drvdata); @@ -718,9 +737,14 @@ static void etm4_init_arch_data(void *info) drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1; /* * NUMSSCC, bits[23:20] the number of single-shot - * comparator control for tracing + * comparator control for tracing. Read any status regs as these + * also contain RO capability data. */ drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23); + for (i = 0; i < drvdata->nr_ss_cmp; i++) { + drvdata->config.ss_status[i] = + readl_relaxed(drvdata->base + TRCSSCSRn(i)); + } /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ drvdata->numcidc = BMVAL(etmidr4, 24, 27); /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */ diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index b873df38e7d8..4a695bf90582 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -227,6 +227,7 @@ * @cntr_val: Sets or returns the value for a counter. * @res_idx: Resource index selector. * @res_ctrl: Controls the selection of the resources in the trace unit. + * @ss_idx: Single-shot index selector. * @ss_ctrl: Controls the corresponding single-shot comparator resource. * @ss_status: The status of the corresponding single-shot comparator. * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control. @@ -270,6 +271,7 @@ struct etmv4_config { u32 cntr_val[ETMv4_MAX_CNTR]; u8 res_idx; u32 res_ctrl[ETM_MAX_RES_SEL]; + u8 ss_idx; u32 ss_ctrl[ETM_MAX_SS_CMP]; u32 ss_status[ETM_MAX_SS_CMP]; u32 ss_pe_cmp[ETM_MAX_SS_CMP]; From patchwork Tue Oct 15 21:20:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11191765 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 72DE315AB for ; Tue, 15 Oct 2019 21:23:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4C4F920663 for ; Tue, 15 Oct 2019 21:23:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="TVR9JSxB"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="LWjuGCKf" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4C4F920663 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=xFJDVZl5utY9o3X49+1Vtss7ECZIi5jmBRudtbaIdDY=; b=TVR9JSxB26OEvxvX/SQz5p/5RP GY4HZOU2cXciaLb1YqXaUnyUkqWDG2BjmM7ugHy0tj02Qb/LKt3ifGx/X7NUdX3FBop5734CQIJk/ 0cHMINySzHxAiZZywayq/dBrXK3jR/Ai31WWev2YD/KbcqEhfsFHLCHsB/OmTpgk38EMlfvQVIKgb DwPS4Atr6HiT68sF1QEaj+2CgPu5hDT8hzPMFyzuQMf6dsWmW7/d4Df1KtqG1mla035kTBz4kzO4A 8Lp2wXP9dBU6NjKYie+uwW90x5sYYfW0K7wLt0RC/GsmkSwHJFyEWH1gILFuw+AnknTcoGsZkPUX/ UQuDG7aw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUI0-0005NV-9C; Tue, 15 Oct 2019 21:23:32 +0000 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUFa-00036Z-Nd for linux-arm-kernel@lists.infradead.org; Tue, 15 Oct 2019 21:21:06 +0000 Received: by mail-wm1-x335.google.com with SMTP id 3so517402wmi.3 for ; Tue, 15 Oct 2019 14:21:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wJrfM+erqbGZASYxkhw8vbuvL6PkIa9iln3+ec3N9wo=; b=LWjuGCKfW9diNGm4JYo23DK+YbLH/X87i9ONc12hz6IbyBZQjjoZe4OR8Oi7j54lR9 nsfHW/SiNS0mgNjhxXNZ/XSUja2LEZkuSLSBRXrIulkq1BzleR0MUgcebkMv1Mac7SJL NMQw48crws7wTnhNRjnGZteV0Vg+71BuO4luvbwlo3btcj51sLt3VNj17GGOUWD6ibw+ aOhJSoyvyLYLNyNH4Szhq5T2daflt9L7csUwg/e8oJMtmkVrOiUozr563/mpZ7XypeyV r36DdnldDiC+AEo7kCrPesPvQzThaCURgM51+ZQodr/7paVIK6y59t7DAUlzKV6hWr/H LOUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wJrfM+erqbGZASYxkhw8vbuvL6PkIa9iln3+ec3N9wo=; b=oTFtWiUf2V7zM9+GBE1mocFP0AAEY3Ul2wK795PK/pPrZXJIP6FeTDu60wm3tS7HHn UAYVSCHvG/DQqdAXC0n+ZrbrB63lpfmWepC4SFAXlsFbkn+/Fym5SN8T2/2FFTDOXuPL MvyRCh/UtByFGt2gN07nyWRya/5foZvPI1vHGfQR+bRe4FEWlrJyUVi+jRdKkM4j5V4y URoWk54fsTo2y8VVryKPE+LJx8qpo4Ic92UoV9Q2uTRb1c9/g2rgOFSC77sv37oeXr+F xq33kVBjXygU1PvrC14/cqS8tMfRQI3P8LI+iJJ5h0A6CAorFRFOJ+/Yp3ig74u4B7hT Gfzw== X-Gm-Message-State: APjAAAWDARbtOHljBoIe+xJCf8jiZrl7ujARl4nmxQo6+VsmjgGF6qNR co5qbNrwKuG7pn3z8XgWrdKHsQ== X-Google-Smtp-Source: APXvYqxOYdOO6PGURamAzLw1pZMYE9LRScselQjpInZEHU89/6EL910l2OFeHxOhRMgr2txCTOLwGw== X-Received: by 2002:a7b:c74a:: with SMTP id w10mr464543wmk.30.1571174460085; Tue, 15 Oct 2019 14:21:00 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6815:3901:39d2:21a2:678a:9501]) by smtp.gmail.com with ESMTPSA id g185sm517649wme.10.2019.10.15.14.20.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 14:20:59 -0700 (PDT) From: Mike Leach To: mike.leach@linaro.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org Subject: [PATCH v3 09/11] coresight: etm4x: docs: Update ABI doc for sysfs features added. Date: Tue, 15 Oct 2019 22:20:02 +0100 Message-Id: <20191015212004.24748-10-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191015212004.24748-1-mike.leach@linaro.org> References: <20191015212004.24748-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191015_142102_887810_57F0A859 X-CRM114-Status: GOOD ( 12.16 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:335 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gregkh@linuxfoundation.org, suzuki.poulose@arm.com, mathieu.poirier@linaro.org, corbet@lwn.net MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Update document to include the new sysfs features added during this patchset. Updated to reflect the new sysfs component nameing schema. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- .../testing/sysfs-bus-coresight-devices-etm4x | 183 +++++++++++------- 1 file changed, 115 insertions(+), 68 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 36258bc1b473..112c50ae9986 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -1,4 +1,4 @@ -What: /sys/bus/coresight/devices/.etm/enable_source +What: /sys/bus/coresight/devices/etm/enable_source Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier @@ -8,82 +8,82 @@ Description: (RW) Enable/disable tracing on this specific trace entiry. of coresight components linking the source to the sink is configured and managed automatically by the coresight framework. -What: /sys/bus/coresight/devices/.etm/cpu +What: /sys/bus/coresight/devices/etm/cpu Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) The CPU this tracing entity is associated with. -What: /sys/bus/coresight/devices/.etm/nr_pe_cmp +What: /sys/bus/coresight/devices/etm/nr_pe_cmp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of PE comparator inputs that are available for tracing. -What: /sys/bus/coresight/devices/.etm/nr_addr_cmp +What: /sys/bus/coresight/devices/etm/nr_addr_cmp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of address comparator pairs that are available for tracing. -What: /sys/bus/coresight/devices/.etm/nr_cntr +What: /sys/bus/coresight/devices/etm/nr_cntr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of counters that are available for tracing. -What: /sys/bus/coresight/devices/.etm/nr_ext_inp +What: /sys/bus/coresight/devices/etm/nr_ext_inp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates how many external inputs are implemented. -What: /sys/bus/coresight/devices/.etm/numcidc +What: /sys/bus/coresight/devices/etm/numcidc Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of Context ID comparators that are available for tracing. -What: /sys/bus/coresight/devices/.etm/numvmidc +What: /sys/bus/coresight/devices/etm/numvmidc Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of VMID comparators that are available for tracing. -What: /sys/bus/coresight/devices/.etm/nrseqstate +What: /sys/bus/coresight/devices/etm/nrseqstate Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of sequencer states that are implemented. -What: /sys/bus/coresight/devices/.etm/nr_resource +What: /sys/bus/coresight/devices/etm/nr_resource Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of resource selection pairs that are available for tracing. -What: /sys/bus/coresight/devices/.etm/nr_ss_cmp +What: /sys/bus/coresight/devices/etm/nr_ss_cmp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of single-shot comparator controls that are available for tracing. -What: /sys/bus/coresight/devices/.etm/reset +What: /sys/bus/coresight/devices/etm/reset Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (W) Cancels all configuration on a trace unit and set it back to its boot configuration. -What: /sys/bus/coresight/devices/.etm/mode +What: /sys/bus/coresight/devices/etm/mode Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier @@ -91,302 +91,349 @@ Description: (RW) Controls various modes supported by this ETM, for example P0 instruction tracing, branch broadcast, cycle counting and context ID tracing. -What: /sys/bus/coresight/devices/.etm/pe +What: /sys/bus/coresight/devices/etm/pe Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls which PE to trace. -What: /sys/bus/coresight/devices/.etm/event +What: /sys/bus/coresight/devices/etm/event Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3. -What: /sys/bus/coresight/devices/.etm/event_instren +What: /sys/bus/coresight/devices/etm/event_instren Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls the behavior of the events in bank 0 to 3. -What: /sys/bus/coresight/devices/.etm/event_ts +What: /sys/bus/coresight/devices/etm/event_ts Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls the insertion of global timestamps in the trace streams. -What: /sys/bus/coresight/devices/.etm/syncfreq +What: /sys/bus/coresight/devices/etm/syncfreq Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls how often trace synchronization requests occur. -What: /sys/bus/coresight/devices/.etm/cyc_threshold +What: /sys/bus/coresight/devices/etm/cyc_threshold Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Sets the threshold value for cycle counting. -What: /sys/bus/coresight/devices/.etm/bb_ctrl +What: /sys/bus/coresight/devices/etm/bb_ctrl Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls which regions in the memory map are enabled to use branch broadcasting. -What: /sys/bus/coresight/devices/.etm/event_vinst +What: /sys/bus/coresight/devices/etm/event_vinst Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls instruction trace filtering. -What: /sys/bus/coresight/devices/.etm/s_exlevel_vinst +What: /sys/bus/coresight/devices/etm/s_exlevel_vinst Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level. -What: /sys/bus/coresight/devices/.etm/ns_exlevel_vinst +What: /sys/bus/coresight/devices/etm/ns_exlevel_vinst Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) In non-secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level. -What: /sys/bus/coresight/devices/.etm/addr_idx +What: /sys/bus/coresight/devices/etm/addr_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Select which address comparator or pair (of comparators) to work with. -What: /sys/bus/coresight/devices/.etm/addr_instdatatype +What: /sys/bus/coresight/devices/etm/addr_instdatatype Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls what type of comparison the trace unit performs. -What: /sys/bus/coresight/devices/.etm/addr_single +What: /sys/bus/coresight/devices/etm/addr_single Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Used to setup single address comparator values. -What: /sys/bus/coresight/devices/.etm/addr_range +What: /sys/bus/coresight/devices/etm/addr_range Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Used to setup address range comparator values. -What: /sys/bus/coresight/devices/.etm/seq_idx +What: /sys/bus/coresight/devices/etm/seq_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Select which sequensor. -What: /sys/bus/coresight/devices/.etm/seq_state +What: /sys/bus/coresight/devices/etm/seq_state Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Use this to set, or read, the sequencer state. -What: /sys/bus/coresight/devices/.etm/seq_event +What: /sys/bus/coresight/devices/etm/seq_event Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Moves the sequencer state to a specific state. -What: /sys/bus/coresight/devices/.etm/seq_reset_event +What: /sys/bus/coresight/devices/etm/seq_reset_event Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Moves the sequencer to state 0 when a programmed event occurs. -What: /sys/bus/coresight/devices/.etm/cntr_idx +What: /sys/bus/coresight/devices/etm/cntr_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Select which counter unit to work with. -What: /sys/bus/coresight/devices/.etm/cntrldvr +What: /sys/bus/coresight/devices/etm/cntrldvr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) This sets or returns the reload count value of the specific counter. -What: /sys/bus/coresight/devices/.etm/cntr_val +What: /sys/bus/coresight/devices/etm/cntr_val Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) This sets or returns the current count value of the specific counter. -What: /sys/bus/coresight/devices/.etm/cntr_ctrl +What: /sys/bus/coresight/devices/etm/cntr_ctrl Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls the operation of the selected counter. -What: /sys/bus/coresight/devices/.etm/res_idx +What: /sys/bus/coresight/devices/etm/res_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Select which resource selection unit to work with. -What: /sys/bus/coresight/devices/.etm/res_ctrl +What: /sys/bus/coresight/devices/etm/res_ctrl Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls the selection of the resources in the trace unit. -What: /sys/bus/coresight/devices/.etm/ctxid_idx +What: /sys/bus/coresight/devices/etm/ctxid_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Select which context ID comparator to work with. -What: /sys/bus/coresight/devices/.etm/ctxid_pid +What: /sys/bus/coresight/devices/etm/ctxid_pid Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Get/Set the context ID comparator value to trigger on. -What: /sys/bus/coresight/devices/.etm/ctxid_masks +What: /sys/bus/coresight/devices/etm/ctxid_masks Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Mask for all 8 context ID comparator value registers (if implemented). -What: /sys/bus/coresight/devices/.etm/vmid_idx +What: /sys/bus/coresight/devices/etm/vmid_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Select which virtual machine ID comparator to work with. -What: /sys/bus/coresight/devices/.etm/vmid_val +What: /sys/bus/coresight/devices/etm/vmid_val Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Get/Set the virtual machine ID comparator value to trigger on. -What: /sys/bus/coresight/devices/.etm/vmid_masks +What: /sys/bus/coresight/devices/etm/vmid_masks Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Mask for all 8 virtual machine ID comparator value registers (if implemented). -What: /sys/bus/coresight/devices/.etm/mgmt/trcoslsr +What: /sys/bus/coresight/devices/etm/addr_exlevel_s_ns +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier +Description: (RW) Set the Exception Level matching bits for secure and + non-secure exception levels. + +What: /sys/bus/coresight/devices/etm/vinst_pe_cmp_start_stop +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier +Description: (RW) Access the start stop control register for PE input + comparators. + +What: /sys/bus/coresight/devices/etm/addr_cmp_view +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier +Description: (R) Print the current settings for the selected address + comparator. + +What: /sys/bus/coresight/devices/etm/sshot_idx +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier +Description: (RW) Select the single shot control register to access. + +What: /sys/bus/coresight/devices/etm/sshot_ctrl +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier +Description: (RW) Access the selected single shot control register. + +What: /sys/bus/coresight/devices/etm/sshot_status +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier +Description: (R) Print the current value of the selected single shot + status register. + +What: /sys/bus/coresight/devices/etm/sshot_pe_ctrl +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier +Description: (RW) Access the selected single show PE comparator control + register. + +What: /sys/bus/coresight/devices/etm/mgmt/trcoslsr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the OS Lock Status Register (0x304). The value it taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcpdcr +What: /sys/bus/coresight/devices/etm/mgmt/trcpdcr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Power Down Control Register (0x310). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcpdsr +What: /sys/bus/coresight/devices/etm/mgmt/trcpdsr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Power Down Status Register (0x314). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trclsr +What: /sys/bus/coresight/devices/etm/mgmt/trclsr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the SW Lock Status Register (0xFB4). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcauthstatus +What: /sys/bus/coresight/devices/etm/mgmt/trcauthstatus Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Authentication Status Register (0xFB8). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcdevid +What: /sys/bus/coresight/devices/etm/mgmt/trcdevid Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Device ID Register (0xFC8). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcdevtype +What: /sys/bus/coresight/devices/etm/mgmt/trcdevtype Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Device Type Register (0xFCC). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcpidr0 +What: /sys/bus/coresight/devices/etm/mgmt/trcpidr0 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Peripheral ID0 Register (0xFE0). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcpidr1 +What: /sys/bus/coresight/devices/etm/mgmt/trcpidr1 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Peripheral ID1 Register (0xFE4). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcpidr2 +What: /sys/bus/coresight/devices/etm/mgmt/trcpidr2 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Peripheral ID2 Register (0xFE8). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcpidr3 +What: /sys/bus/coresight/devices/etm/mgmt/trcpidr3 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Peripheral ID3 Register (0xFEC). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcconfig +What: /sys/bus/coresight/devices/etm/mgmt/trcconfig Date: February 2016 KernelVersion: 4.07 Contact: Mathieu Poirier Description: (R) Print the content of the trace configuration register (0x010) as currently set by SW. -What: /sys/bus/coresight/devices/.etm/mgmt/trctraceid +What: /sys/bus/coresight/devices/etm/mgmt/trctraceid Date: February 2016 KernelVersion: 4.07 Contact: Mathieu Poirier Description: (R) Print the content of the trace ID register (0x040). -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr0 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr0 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns the tracing capabilities of the trace unit (0x1E0). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr1 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr1 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns the tracing capabilities of the trace unit (0x1E4). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr2 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr2 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier @@ -394,7 +441,7 @@ Description: (R) Returns the maximum size of the data value, data address, VMID, context ID and instuction address in the trace unit (0x1E8). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr3 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr3 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier @@ -403,42 +450,42 @@ Description: (R) Returns the value associated with various resources architecture specification for more details (0x1E8). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr4 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr4 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns how many resources the trace unit supports (0x1F0). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr5 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr5 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns how many resources the trace unit supports (0x1F4). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr8 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr8 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns the maximum speculation depth of the instruction trace stream. (0x180). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr9 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr9 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns the number of P0 right-hand keys that the trace unit can use (0x184). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr10 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr10 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns the number of P1 right-hand keys that the trace unit can use (0x188). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr11 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr11 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier @@ -446,7 +493,7 @@ Description: (R) Returns the number of special P1 right-hand keys that the trace unit can use (0x18C). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr12 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr12 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier @@ -454,7 +501,7 @@ Description: (R) Returns the number of conditional P1 right-hand keys that the trace unit can use (0x190). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr13 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr13 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier From patchwork Tue Oct 15 21:20:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11191763 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 80B9114DB for ; Tue, 15 Oct 2019 21:23:19 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4D45420663 for ; Tue, 15 Oct 2019 21:23:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="bE+cUlp1"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="rOJJ11N5" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4D45420663 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=bCxyDh3lngsZJ7bZDpth9/l56BRKahqXZlFj/jznOu4=; b=bE+cUlp1u87eXhzGcRpGeOWnUB uIjxNltv0uGvWlEI/WfDL4ChujRbYLKkH/Mcst5LG56Qul9a5gibWKY6i6cnJOX0PpEdYUikTyadA wWFegwQou3ZlLuRuYG2bp0zjOE/i3r0BKvT35ZsRhnqDq2b6Ir+jxBmyiQ5myz66EJ4qz3OIAZMHb PiP2vcPo9/FaotLcN4WxIC2e3LAybu3XXBPDUqIHehzmZ74MwMYfwyu+es8X7atVgdgBd8FDWMXlX f1Hd5MVEsm2JF3ojoNe0SB0CfOlTkVvlUZnWuefFll9961Q/qTekki0/t2mIDBiuBBMuthHwrcSEk cS7jTL0A==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUHm-00058Z-CI; Tue, 15 Oct 2019 21:23:18 +0000 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUFb-00036t-4s for linux-arm-kernel@lists.infradead.org; Tue, 15 Oct 2019 21:21:05 +0000 Received: by mail-wr1-x441.google.com with SMTP id y19so25555720wrd.3 for ; Tue, 15 Oct 2019 14:21:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Dq3rU4Lby8dKxd9LSbXA1tMIoZsiALr+ULF/WaB9EEo=; b=rOJJ11N59/RJiU4wFpp62lXcXEbgZ4axYNakFv179BHGhRWL9GNXKVbTPkyVAZC/6/ AwBR8OJMJtUpuSOfjvNecgf7gBV4onK7sh/y43H9+iW893VPTFPm3r2XGCrR7M39QhyE afo7BVhydlM6Ygqbcs1Dq7rnBGKP5f7kJ4h6WYuQVCJzfatTd3kaifGttBqPjeuyrdiA 5R2BbbH+emp7gkSRh0KNAQzoEGABFnrh+vqPtnGYTvsbqzrXEXdY2GCZGXLpCEvnjc4z LK1pp/30BafCCoCjSDCZYmB3ksOb4sjySOr8VkGGsUt7T2rmvG8Suzl1ByFrDhbpH6GZ T37A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Dq3rU4Lby8dKxd9LSbXA1tMIoZsiALr+ULF/WaB9EEo=; b=giisfui+tp+6sn7mw6oOXROYLXgHY5b43YS4BU5CkylZT+TPpyITPi+rZRefBrehj1 aJeOpODu1D2+2pOICxiKIYhQoN0sMaQaIVJJtZs6Qz7UnNRDCZOCuQFei33xVIIZZ/r7 qzGiwGoHx4GuL0sOQ0hLvwzeQ1ESbhPrJwmfLiRk+GcoK2YEzsjL4SLh+WluxeyShO+G dVYrcZaQX57zWLxKTaIqCs5HfoShjoVacax0nLISXhm49vz/h6vT0urrV+bOlN1k2CL+ QPxnJD4L3RHwxbsX4GOC5+AcpvAbm50sl1W4c6V9gL2GTu/nZRipI7xgU0yVydyqAldJ vjqA== X-Gm-Message-State: APjAAAWvok73Z3XywL/0LFogacrkZgEafLTKN3lHqJyVSIyonqiH5eDG qRdhS2qfuYxjbsbImjOaG+bAPezmUag= X-Google-Smtp-Source: APXvYqxLphcf7uqpOFSJsUgKXrjRXhyaHe51oiz20Gcv9OdCzKx3ZseZi3quOnQtgeq+bBSGnyv1rg== X-Received: by 2002:a5d:6942:: with SMTP id r2mr30992500wrw.363.1571174461023; Tue, 15 Oct 2019 14:21:01 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6815:3901:39d2:21a2:678a:9501]) by smtp.gmail.com with ESMTPSA id g185sm517649wme.10.2019.10.15.14.21.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 14:21:00 -0700 (PDT) From: Mike Leach To: mike.leach@linaro.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org Subject: [PATCH v3 10/11] coresight: docs: Create common sub-directory for coresight trace. Date: Tue, 15 Oct 2019 22:20:03 +0100 Message-Id: <20191015212004.24748-11-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191015212004.24748-1-mike.leach@linaro.org> References: <20191015212004.24748-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191015_142103_223507_076B52FF X-CRM114-Status: GOOD ( 11.31 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:441 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gregkh@linuxfoundation.org, suzuki.poulose@arm.com, mathieu.poirier@linaro.org, corbet@lwn.net MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org There are two files in the Documentation/trace directory relating to coresight, with more to follow, so create a Documentation/trace/coresight directory and move existing files there. Update MAINTAINERS to reference this sub-directory rather than the individual files. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- Documentation/trace/{ => coresight}/coresight-cpu-debug.rst | 0 Documentation/trace/{ => coresight}/coresight.rst | 2 +- Documentation/trace/{ => coresight}/stm.rst | 0 MAINTAINERS | 3 +-- 4 files changed, 2 insertions(+), 3 deletions(-) rename Documentation/trace/{ => coresight}/coresight-cpu-debug.rst (100%) rename Documentation/trace/{ => coresight}/coresight.rst (99%) rename Documentation/trace/{ => coresight}/stm.rst (100%) diff --git a/Documentation/trace/coresight-cpu-debug.rst b/Documentation/trace/coresight/coresight-cpu-debug.rst similarity index 100% rename from Documentation/trace/coresight-cpu-debug.rst rename to Documentation/trace/coresight/coresight-cpu-debug.rst diff --git a/Documentation/trace/coresight.rst b/Documentation/trace/coresight/coresight.rst similarity index 99% rename from Documentation/trace/coresight.rst rename to Documentation/trace/coresight/coresight.rst index 72f4b7ef1bad..835e8aa0bf8c 100644 --- a/Documentation/trace/coresight.rst +++ b/Documentation/trace/coresight/coresight.rst @@ -493,6 +493,6 @@ Details on how to use the generic STM API can be found here [#second]_. .. [#first] Documentation/ABI/testing/sysfs-bus-coresight-devices-stm -.. [#second] Documentation/trace/stm.rst +.. [#second] Documentation/trace/coresight/stm.rst .. [#third] https://github.com/Linaro/perf-opencsd diff --git a/Documentation/trace/stm.rst b/Documentation/trace/coresight/stm.rst similarity index 100% rename from Documentation/trace/stm.rst rename to Documentation/trace/coresight/stm.rst diff --git a/MAINTAINERS b/MAINTAINERS index 296de2b51c83..f903160b507c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1608,8 +1608,7 @@ R: Suzuki K Poulose L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/hwtracing/coresight/* -F: Documentation/trace/coresight.rst -F: Documentation/trace/coresight-cpu-debug.rst +F: Documentation/trace/coresight/* F: Documentation/devicetree/bindings/arm/coresight.txt F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* From patchwork Tue Oct 15 21:20:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11191767 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C1B9D14DB for ; Tue, 15 Oct 2019 21:24:06 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 98C7B20663 for ; Tue, 15 Oct 2019 21:24:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="c/Fjqf9P"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="WvgPES9A" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 98C7B20663 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=iWp03NQ+evoVKlPEIzV6lSn487piwVr9qci2ShgIs3Q=; b=c/Fjqf9PmlpYeY nl9mCEt3cvJLnb4nxU/lrOdp3aeVzb63dXVBLs4Iqs5+tN9qKGukvgiH/1QD5K7ht8BhbcUHOfGt5 D/aASNLxfTpydA3CDm/CGKV2mJfUAmejdm+awxjz5ydUZZiMELE9POJu2sUx+q28AXA2CgrhbIGWo nvQHXxzd+tiu4dYg+wgf+Hu1Pue8SVmkB/sg7nJlGCIpAvG2+iLP2mDUF0pfswMs6VIQHe67Ol95w IQ9hljGAAuLYh4bgNzNHTgBbOxLXdVr9yewwFiQm82trbCckVZ1UReCtANO19Z2TIO9dXncm+tr0P SOO6/BzOGAWUwlonoImA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUIX-0005u6-B1; Tue, 15 Oct 2019 21:24:05 +0000 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iKUFc-00038P-Q0 for linux-arm-kernel@lists.infradead.org; Tue, 15 Oct 2019 21:21:08 +0000 Received: by mail-wr1-x42b.google.com with SMTP id p4so9663587wrm.8 for ; Tue, 15 Oct 2019 14:21:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qZFwxifytK6J5kD0v59YNsGgu2jCTfqDp9TJcDoVMVc=; b=WvgPES9AU3VqE7Jl+by0g8/5q780pl3TI0vKHfU4EzLXU3K2lqQmgNe1v0Zb3YK+DF dXggKmGWlYaNvTKBt9/oiRGVI7bxVRLJEjRd60xBsH/EfYbF7SVzeRd2qTPwQoGMHkPy 0ROYsqUXX5Up79z+mYTgWlEuT1Bw5zUxv8wLoYx6kOqX8c3ojSmjgLmj/Z46kTnzEied 4/vUawnXqoGdy1Q/SgLLRD8urTABb1P527faM+ky2CBul9NoTO13wt3w9mAx+vWSKH22 3TWqdNoKgsCQTHW1DG8LHQZMm1zktX3EwPOWqMl58OGfxq8xOrdGyIvKbGxH2dvyLsAo OGPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qZFwxifytK6J5kD0v59YNsGgu2jCTfqDp9TJcDoVMVc=; b=QDUGtxPwOho8mVWCPKkd9JtAcy1ccjbWjFn/xq5TYzO9m/SpY0D3TFNs3V8NyuK33j FVsNVNKk7J0/f/gDwMyzS3JqMpha0x8tKrKG+YczBDwqfiq/XF6Vnf9ENEfiiJ1vYyrs ZXWMdnWqhL7llkx5YNZjsPty71MdmAGnTPDxaNHFvs9Skfo0EjeKrtDFAVb4EGqfvRbN ZNzqtGJXFkFqEFP5ZkwonQgWYBtlcpHbu5KbyMQMamCVlrJtMGjzafgYZIrqq/19iGDM zesIKCzbUt4ZSn+xUlD2HYGP4UWrp3LpcUCBi8/UAPiYK28DBShg4AoxJn+/oo27XMyp 1CjQ== X-Gm-Message-State: APjAAAW8ndQEQx6LErWVanhgUxug84tfsPL5bE+jv8zNE03qZbe5mNql LpOEIi8TK4r2dsoE13zQDsQcCA== X-Google-Smtp-Source: APXvYqzaNDtqMrQb5arHkvoMKD2YC3NMV76diqfZFSQ8tmREAHRmq8TVH6MDekuxp675fIQk0yZkVg== X-Received: by 2002:adf:eb0f:: with SMTP id s15mr30525493wrn.97.1571174462141; Tue, 15 Oct 2019 14:21:02 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6815:3901:39d2:21a2:678a:9501]) by smtp.gmail.com with ESMTPSA id g185sm517649wme.10.2019.10.15.14.21.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 14:21:01 -0700 (PDT) From: Mike Leach To: mike.leach@linaro.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org Subject: [PATCH v3 11/11] coresight: etm4x: docs: Adds detailed document for programming etm4x. Date: Tue, 15 Oct 2019 22:20:04 +0100 Message-Id: <20191015212004.24748-12-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191015212004.24748-1-mike.leach@linaro.org> References: <20191015212004.24748-1-mike.leach@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191015_142104_909201_2BFBE90D X-CRM114-Status: GOOD ( 17.45 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:42b listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gregkh@linuxfoundation.org, suzuki.poulose@arm.com, mathieu.poirier@linaro.org, corbet@lwn.net Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add in detailed programmers reference for users wanting to program the CoreSight ETM 4.x driver using sysfs. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- .../coresight/coresight-etm4x-reference.rst | 798 ++++++++++++++++++ 1 file changed, 798 insertions(+) create mode 100644 Documentation/trace/coresight/coresight-etm4x-reference.rst diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.rst b/Documentation/trace/coresight/coresight-etm4x-reference.rst new file mode 100644 index 000000000000..b64d9a9c79df --- /dev/null +++ b/Documentation/trace/coresight/coresight-etm4x-reference.rst @@ -0,0 +1,798 @@ +=============================================== +ETMv4 sysfs linux driver programming reference. +=============================================== + + :Author: Mike Leach + :Date: October 11th, 2019 + +Supplement to existing ETMv4 driver documentation. + +Sysfs files and directories +--------------------------- + +Root: ``/sys/bus/coresight/devices/etm`` + + +The following paragraphs explain the association between sysfs files and the +ETMv4 registers that they effect. Note the register names are given without +the ‘TRC’ prefix. + +---- + +:File: ``mode`` (rw) +:Trace Registers: {CONFIGR + others} +:Notes: + Bit select trace features. See ‘mode’ section below. Bits + in this will cause equivalent programming of trace config and + other registers to enable the features requested. + +:Syntax & eg: + ``echo bitfield > mode`` + + bitfield up to 32 bits setting trace features. + +:Example: + ``$> echo 0x012 > mode`` + +---- + +:File: ``reset`` (wo) +:Trace Registers: All +:Notes: + Reset all programming to trace nothing / no logic programmed. + +:Syntax: + ``echo 1 > reset`` + +---- + +:File: ``enable_source`` (wo) +:Trace Registers: PRGCTLR, All hardware regs. +:Notes: + - > 0 : Programs up the hardware with the current values held in the driver + and enables trace. + + - = 0 : disable trace hardware. + +:Syntax: + ``echo 1 > enable_source`` + +---- + +:File: ``cpu`` (ro) +:Trace Registers: None. +:Notes: + CPU ID that this ETM is attached to. + +:Example: + ``$> cat cpu`` + + ``$> 0`` + +---- + +:File: ``addr_idx`` (rw) +:Trace Registers: None. +:Notes: + Virtual register to index address comparator and range + features. Set index for first of the pair in a range. + +:Syntax: + ``echo idx > addr_idx`` + + Where idx < nr_addr_cmp x 2 + +---- + +:File: ``addr_range`` (rw) +:Trace Registers: ACVR[idx, idx+1], VIIECTLR +:Notes: + Pair of addresses for a range selected by addr_idx. Include + / exclude according to the optional parameter, or if omitted + uses the current ‘mode’ setting. Select comparator range in + control register. Error if index is odd value. + +:Depends: ``mode, addr_idx`` +:Syntax: + ``echo addr1 addr2 [exclude] > addr_range`` + + Where addr1 and addr2 define the range and addr1 < addr2. + + Optional exclude value:- + + - 0 for include + - 1 for exclude. +:Example: + ``$> echo 0x0000 0x2000 0 > addr_range`` + +---- + +:File: ``addr_single`` (rw) +:Trace Registers: ACVR[idx] +:Notes: + Set a single address comparator according to addr_idx. This + is used if the address comparator is used as part of event + generation logic etc. + +:Depends: ``addr_idx`` +:Syntax: + ``echo addr1 > addr_single`` + +---- + +:File: ``addr_start`` (rw) +:Trace Registers: ACVR[idx], VISSCTLR +:Notes: + Set a trace start address comparator according to addr_idx. + Select comparator in control register. + +:Depends: ``addr_idx`` +:Syntax: + ``echo addr1 > addr_start`` + +---- + +:File: ``addr_stop`` (rw) +:Trace Registers: ACVR[idx], VISSCTLR +:Notes: + Set a trace stop address comparator according to addr_idx. + Select comparator in control register. + +:Depends: ``addr_idx`` +:Syntax: + ``echo addr1 > addr_stop`` + +---- + +:File: ``addr_context`` (rw) +:Trace Registers: ACATR[idx,{6:4}] +:Notes: + Link context ID comparator to address comparator addr_idx + +:Depends: ``addr_idx`` +:Syntax: + ``echo ctxt_idx > addr_context`` + + Where ctxt_idx is the index of the linked context id / vmid + comparator. + +---- + +:File: ``addr_ctxtype`` (rw) +:Trace Registers: ACATR[idx,{3:2}] +:Notes: + Input value string. Set type for linked context ID comparator + +:Depends: ``addr_idx`` +:Syntax: + ``echo type > addr_ctxtype`` + + Type one of {all, vmid, ctxid, none} +:Example: + ``$> echo ctxid > addr_ctxtype`` + +---- + +:File: ``addr_exlevel_s_ns`` (rw) +:Trace Registers: ACATR[idx,{14:8}] +:Notes: + Set the ELx secure and non-secure matching bits for the + selected address comparator + +:Depends: ``addr_idx`` +:Syntax: + ``echo val > addr_exlevel_s_ns`` + + val is a 7 bit value for exception levels to exclude. Input + value shifted to correct bits in register. +:Example: + ``$> echo 0x4F > addr_exlevel_s_ns`` + +---- + +:File: ``addr_instdatatype`` (rw) +:Trace Registers: ACATR[idx,{1:0}] +:Notes: + Set the comparator address type for matching. Driver only + supports setting instruction address type. + +:Depends: ``addr_idx`` + +---- + +:File: ``addr_cmp_view`` (ro) +:Trace Registers: ACVR[idx, idx+1], ACATR[idx], VIIECTLR +:Notes: + Read the currently selected address comparator. If part of + address range then display both addresses. + +:Depends: ``addr_idx`` +:Syntax: + ``cat addr_cmp_view`` +:Example: + ``$> cat addr_cmp_view`` + + ``addr_cmp[0] range 0x0 0xffffffffffffffff include ctrl(0x4b00)`` + +---- + +:File: ``nr_addr_cmp`` (ro) +:Trace Registers: From IDR4 +:Notes: + Number of address comparator pairs + +---- + +:File: ``sshot_idx`` (rw) +:Trace Registers: None +:Notes: + Select single shot register set. + +---- + +:File: ``sshot_ctrl`` (rw) +:Trace Registers: SSCCR[idx] +:Notes: + Access a single shot comparator control register. + +:Depends: ``sshot_idx`` +:Syntax: + ``echo val > sshot_ctrl`` + + Writes val into the selected control register. + +---- + +:File: ``sshot_status`` (ro) +:Trace Registers: SSCSR[idx] +:Notes: + Read a single shot comparator status register + +:Depends: ``sshot_idx`` +:Syntax: + ``cat sshot_status`` + + Read status. +:Example: + ``$> cat sshot_status`` + + ``0x1`` + +---- + +:File: ``sshot_pe_ctrl`` (rw) +:Trace Registers: SSPCICR[idx] +:Notes: + Access a single shot PE comparator input control register. + +:Depends: ``sshot_idx`` +:Syntax: + ``echo val > sshot_pe_ctrl`` + + Writes val into the selected control register. + +---- + +:File: ``ns_exlevel_vinst`` (rw) +:Trace Registers: VICTLR{23:20} +:Notes: + Program non-secure exception level filters. Set / clear NS + exception filter bits. Setting ‘1’ excludes trace from the + exception level. + +:Syntax: + ``echo bitfield > ns_exlevel_viinst`` + + Where bitfield contains bits to set clear for EL0 to EL2 +:Example: + ``%> echo 0x4 > ns_exlevel_viinst`` + + Excludes EL2 NS trace. + +---- + +:File: ``vinst_pe_cmp_start_stop`` (rw) +:Trace Registers: VIPCSSCTLR +:Notes: + Access PE start stop comparator input control registers + +---- + +:File: ``bb_ctrl`` (rw) +:Trace Registers: BBCTLR +:Notes: + Define ranges that Branch Broadcast will operate in. + Default (0x0) is all addresses. + +:Depends: BB enabled. + +---- + +:File: ``cyc_threshold`` (rw) +:Trace Registers: CCCTLR +:Notes: + Set the threshold for which cycle counts will be emitted. + Error if attempt to set below minimum defined in IDR3, masked + to width of valid bits. + +:Depends: CC enabled. + +---- + +:File: ``syncfreq`` (rw) +:Trace Registers: SYNCPR +:Notes: + Set trace synchronisation period. Power of 2 value, 0 (off) + or 8-20. Driver defaults to 12 (every 4096 bytes). + +---- + +:File: ``cntr_idx`` (rw) +:Trace Registers: none +:Notes: + Select the counter to access + +:Syntax: + ``echo idx > cntr_idx`` + + Where idx < nr_cntr + +---- + +:File: ``cntr_ctrl`` (rw) +:Trace Registers: CNTCTLR[idx] +:Notes: + Set counter control value. + +:Depends: ``cntr_idx`` +:Syntax: + ``echo val > cntr_ctrl`` + + Where val is per ETMv4 spec. + +---- + +:File: ``cntrldvr`` (rw) +:Trace Registers: CNTRLDVR[idx] +:Notes: + Set counter reload value. + +:Depends: ``cntr_idx`` +:Syntax: + ``echo val > cntrldvr`` + + Where val is per ETMv4 spec. + +---- + +:File: ``nr_cntr`` (ro) +:Trace Registers: From IDR5 + +:Notes: + Number of counters implemented. + +---- + +:File: ``ctxid_idx`` (rw) +:Trace Registers: None +:Notes: + Select the context ID comparator to access + +:Syntax: + ``echo idx > ctxid_idx`` + + Where idx < numcidc + +---- + +:File: ``ctxid_pid`` (rw) +:Trace Registers: CIDCVR[idx] +:Notes: + Set the context ID comparator value + +:Depends: ``ctxid_idx`` + +---- + +:File: ``ctxid_masks`` (rw) +:Trace Registers: CIDCCTLR0, CIDCCTLR1, CIDCVR<0-7> +:Notes: + Pair of values to set the byte masks for 1-8 context ID + comparators. Automatically clears masked bytes to 0 in CID + value registers. + +:Syntax: + ``echo m3m2m1m0 [m7m6m5m4] > ctxid_masks`` + + 32 bit values made up of mask bytes, where mN represents a + byte mask value for Context ID comparator N. + + Second value not required on systems that have fewer than 4 + context ID comparators + +---- + +:File: ``numcidc`` (ro) +:Trace Registers: From IDR4 +:Notes: + Number of Context ID comparators + +---- + +:File: ``vmid_idx`` (rw) +:Trace Registers: None +:Notes: + Select the VM ID comparator to access. + +:Syntax: + ``echo idx > vmid_idx`` + + Where idx <  numvmidc + +---- + +:File: ``vmid_val`` (rw) +:Trace Registers: VMIDCVR[idx] +:Notes: + Set the VM ID comparator value + +:Depends: ``vmid_idx`` + +---- + +:File: ``vmid_masks`` (rw) +:Trace Registers: VMIDCCTLR0, VMIDCCTLR1, VMIDCVR<0-7> +:Notes: + Pair of values to set the byte masks for 1-8 VM ID comparators. + Automatically clears masked bytes to 0 in VMID value registers. + +:Syntax: + ``echo m3m2m1m0 [m7m6m5m4] > vmid_masks`` + + Where mN represents a byte mask value for VMID comparator N. + Second value not required on systems that have fewer than 4 + VMID comparators. + +---- + +:File: ``numvmidc`` (ro) +:Trace Registers: From IDR4 +:Notes: + Number of VMID comparators + +---- + +:File: ``res_idx`` (rw) +:Trace Registers: None. +:Notes: + Select the resource selector control to access. Must be 2 or + higher as selectors 0 and 1 are hardwired. + +:Syntax: + ``echo idx > res_idx`` + + Where 2 <= idx < nr_resource x 2 + +---- + +:File: ``res_ctrl`` (rw) +:Trace Registers: RSCTLR[idx] +:Notes: + Set resource selector control value. Value per ETMv4 spec. + +:Depends: ``res_idx`` +:Syntax: + ``echo val > res_cntr`` + + Where val is per ETMv4 spec. + +---- + +:File: ``nr_resource`` (ro) +:Trace Registers: From IDR4 +:Notes: + Number of resource selector pairs + +---- + +:File: ``event`` (rw) +:Trace Registers: EVENTCTRL0R +:Notes: + Set up to 4 implemented event fields. + +:Syntax: + ``echo ev3ev2ev1ev0 > event`` + + Where evN is an 8 bit event field. Up to 4 event fields make up the + 32-bit input value. Number of valid fields is implementation dependent, + defined in IDR0. + +---- + +:File: ``event_instren`` (rw) +:Trace Registers: EVENTCTRL1R +:Notes: + Choose events which insert event packets into trace stream. + +:Depends: EVENTCTRL0R +:Syntax: + ``echo bitfield > event_instren`` + + Where bitfield is up to 4 bits according to number of event fields. + +---- + +:File: ``event_ts`` (rw) +:Trace Registers: TSCTLR +:Notes: + Set the event that will generate timestamp requests. + +:Depends: ``TS activated`` +:Syntax: + ``echo evfield > event_ts`` + + Where evfield is an 8 bit event selector. + +---- + +:File: ``seq_idx`` (rw) +:Trace Registers: None +:Notes: + Sequencer event register select - 0 to 2 + +---- + +:File: ``seq_state`` (rw) +:Trace Registers: SEQSTR +:Notes: + Sequencer current state - 0 to 3. + +---- + +:File: ``seq_event`` (rw) +:Trace Registers: SEQEVR[idx] +:Notes: + State transition event registers + +:Depends: ``seq_idx`` +:Syntax: + ``echo evBevF > seq_event`` + + Where evBevF is a 16 bit value made up of two event selectors, + + - evB : back + - evF : forwards. + +---- + +:File: ``seq_reset_event`` (rw) +:Trace Registers: SEQRSTEVR +:Notes: + Sequencer reset event + +:Syntax: + ``echo evfield > seq_reset_event`` + + Where evfield is an 8 bit event selector. + +---- + +:File: ``nrseqstate`` (ro) +:Trace Registers: From IDR5 +:Notes: + Number of sequencer states (0 or 4) + +---- + +:File: ``nr_pe_cmp`` (ro) +:Trace Registers: From IDR4 +:Notes: + Number of PE comparator inputs + +---- + +:File: ``nr_ext_inp`` (ro) +:Trace Registers: From IDR5 +:Notes: + Number of external inputs + +---- + +:File: ``nr_ss_cmp`` (ro) +:Trace Registers: From IDR4 +:Notes: + Number of Single Shot control registers + +---- + +*Note:* When programming any address comparator the driver will tag the +comparator with a type used - i.e. RANGE, SINGLE, START, STOP. Once this tag +is set, then only the values can be changed using the same sysfs file / type +used to program it. + +Thus:: + + % echo 0 > addr_idx ; select address comparator 0 + % echo 0x1000 0x5000 0 > addr_range ; set address range on comparators 0, 1. + % echo 0x2000 > addr_start ; error as comparator 0 is a range comparator + % echo 2 > addr_idx ; select address comparator 2 + % echo 0x2000 > addr_start ; this is OK as comparator 2 is unused. + % echo 0x3000 > addr_stop ; error as comparator 2 set as start address. + % echo 2 > addr_idx ; select address comparator 3 + % echo 0x3000 > addr_stop ; this is OK + +To remove programming on all the comparators (and all the other hardware) use +the reset parameter:: + + % echo 1 > reset + + + +The ‘mode’ sysfs parameter. +--------------------------- + +This is a bitfield selection parameter that sets the overall trace mode for the +ETM. The table below describes the bits, using the defines from the driver +source file, along with a description of the feature these represent. Many +features are optional and therefore dependent on implementation in the +hardware. + +Bit assignments shown below:- + +---- + +**bit (0):** + ETM_MODE_EXCLUDE + +**description:** + This is the default value for the include / exclude function when + setting address ranges. Set 1 for exclude range. When the mode + parameter is set this value is applied to the currently indexed + address range. + + +**bit (4):** + ETM_MODE_BB + +**description:** + Set to enable branch broadcast if supported in hardware [IDR0]. + + +**bit (5):** + ETMv4_MODE_CYCACC + +**description:** + Set to enable cycle accurate trace if supported [IDR0]. + + +**bit (6):** + ETMv4_MODE_CTXID + +**description:** + Set to enable context ID tracing if supported in hardware [IDR2]. + + +**bit (7):** + ETM_MODE_VMID + +**description:** + Set to enable virtual machine ID tracing if supported [IDR2]. + + +**bit (11):** + ETMv4_MODE_TIMESTAMP + +**description:** + Set to enable timestamp generation if supported [IDR0]. + + +**bit (12):** + ETM_MODE_RETURNSTACK +**description:** + Set to enable trace return stack use if supported [IDR0]. + + +**bit (13-14):** + ETM_MODE_QELEM(val) + +**description:** + ‘val’ determines level of Q element support enabled if + implemented by the ETM [IDR0] + + +**bit (19):** + ETM_MODE_ATB_TRIGGER + +**description:** + Set to enable the ATBTRIGGER bit in the event control register + [EVENTCTLR1] if supported [IDR5]. + + +**bit (20):** + ETM_MODE_LPOVERRIDE + +**description:** + Set to enable the LPOVERRIDE bit in the event control register + [EVENTCTLR1], if supported [IDR5]. + + +**bit (21):** + ETM_MODE_ISTALL_EN + +**description:** + Set to enable the ISTALL bit in the stall control register + [STALLCTLR] + + +**bit (23):** + ETM_MODE_INSTPRIO + +**description:** + Set to enable the INSTPRIORITY bit in the stall control register + [STALLCTLR] , if supported [IDR0]. + + +**bit (24):** + ETM_MODE_NOOVERFLOW + +**description:** + Set to enable the NOOVERFLOW bit in the stall control register + [STALLCTLR], if supported [IDR3]. + + +**bit (25):** + ETM_MODE_TRACE_RESET + +**description:** + Set to enable the TRCRESET bit in the viewinst control register + [VICTLR] , if supported [IDR3]. + + +**bit (26):** + ETM_MODE_TRACE_ERR + +**description:** + Set to enable the TRCCTRL bit in the viewinst control register + [VICTLR]. + + +**bit (27):** + ETM_MODE_VIEWINST_STARTSTOP + +**description:** + Set the initial state value of the ViewInst start / stop logic + in the viewinst control register [VICTLR] + + +**bit (30):** + ETM_MODE_EXCL_KERN + +**description:** + Set default trace setup to exclude kernel mode trace (see note a) + + +**bit (31):** + ETM_MODE_EXCL_USER + +**description:** + Set default trace setup to exclude user space trace (see note a) + +---- + +*Note a)* On startup the ETM is programmed to trace the complete address space +using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to +set EL exclude bits for NS state in either user space (EL0) or kernel space +(EL1) in the address range comparator. (the default setting excludes all +secure EL, and NS EL2) + +Once the reset parameter has been used, and/or custom programming has been +implemented - using these bits will result in the EL bits for address +comparator 0 being set in the same way. + +*Note b)* Bits 2-3, 8-10, 15-16, 18, 22, control features that only work with +data trace. As A-profile data trace is architecturally prohibited in ETMv4, +these have been omitted here. Possible uses could be where a kernel has +support for control of R or M profile infrastructure as part of a heterogeneous +system. + +Bits 17, 28-29 are unused.