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[213.102.65.51]) by smtp.gmail.com with ESMTPSA id j191sm1361493lfj.49.2019.10.16.00.07.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2019 00:07:43 -0700 (PDT) From: codekipper@gmail.com To: mripard@kernel.org, wens@csie.org, linux-sunxi@googlegroups.com Date: Wed, 16 Oct 2019 09:07:34 +0200 Message-Id: <20191016070740.121435-2-codekipper@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191016070740.121435-1-codekipper@gmail.com> References: <20191016070740.121435-1-codekipper@gmail.com> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, Marcus Cooper , lgirdwood@gmail.com, linux-kernel@vger.kernel.org, be17068@iperbole.bo.it, broonie@kernel.org, linux-arm-kernel@lists.infradead.org Subject: [alsa-devel] [PATCH v6 1/7] ASoC: sun4i-i2s: Move channel select offset X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Marcus Cooper On the newer SoCs the offset is used to set the mode of the connection. As it is to be used elsewhere then it makes sense to move it to the main structure. Signed-off-by: Marcus Cooper --- sound/soc/sunxi/sun4i-i2s.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index d0a8d5810c0a..f1a80973c450 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -156,7 +156,7 @@ struct sun4i_i2s_quirks { s8 (*get_wss)(const struct sun4i_i2s *, int); int (*set_chan_cfg)(const struct sun4i_i2s *, const struct snd_pcm_hw_params *); - int (*set_fmt)(const struct sun4i_i2s *, unsigned int); + int (*set_fmt)(struct sun4i_i2s *, unsigned int); }; struct sun4i_i2s { @@ -169,6 +169,7 @@ struct sun4i_i2s { unsigned int mclk_freq; unsigned int slots; unsigned int slot_width; + unsigned int offset; struct snd_dmaengine_dai_dma_data capture_dma_data; struct snd_dmaengine_dai_dma_data playback_dma_data; @@ -516,7 +517,7 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, slots, slot_width); } -static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, +static int sun4i_i2s_set_soc_fmt(struct sun4i_i2s *i2s, unsigned int fmt) { u32 val; @@ -589,11 +590,10 @@ static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, return 0; } -static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, +static int sun8i_i2s_set_soc_fmt(struct sun4i_i2s *i2s, unsigned int fmt) { u32 mode, val; - u8 offset; /* * DAI clock polarity @@ -632,27 +632,27 @@ static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_DSP_A: mode = SUN8I_I2S_CTRL_MODE_PCM; - offset = 1; + i2s->offset = 1; break; case SND_SOC_DAIFMT_DSP_B: mode = SUN8I_I2S_CTRL_MODE_PCM; - offset = 0; + i2s->offset = 0; break; case SND_SOC_DAIFMT_I2S: mode = SUN8I_I2S_CTRL_MODE_LEFT; - offset = 1; + i2s->offset = 1; break; case SND_SOC_DAIFMT_LEFT_J: mode = SUN8I_I2S_CTRL_MODE_LEFT; - offset = 0; + i2s->offset = 0; break; case SND_SOC_DAIFMT_RIGHT_J: mode = SUN8I_I2S_CTRL_MODE_RIGHT; - offset = 0; + i2s->offset = 0; break; default: @@ -663,10 +663,10 @@ static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, SUN8I_I2S_CTRL_MODE_MASK, mode); regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, SUN8I_I2S_TX_CHAN_OFFSET_MASK, - SUN8I_I2S_TX_CHAN_OFFSET(offset)); + SUN8I_I2S_TX_CHAN_OFFSET(i2s->offset)); regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, SUN8I_I2S_TX_CHAN_OFFSET_MASK, - SUN8I_I2S_TX_CHAN_OFFSET(offset)); + SUN8I_I2S_TX_CHAN_OFFSET(i2s->offset)); /* DAI clock master masks */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { From patchwork Wed Oct 16 07:07:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Code Kipper X-Patchwork-Id: 11192469 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6CBB813BD for ; Wed, 16 Oct 2019 07:10:30 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 01F0520873 for ; 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[213.102.65.51]) by smtp.gmail.com with ESMTPSA id j191sm1361493lfj.49.2019.10.16.00.07.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2019 00:07:44 -0700 (PDT) From: codekipper@gmail.com To: mripard@kernel.org, wens@csie.org, linux-sunxi@googlegroups.com Date: Wed, 16 Oct 2019 09:07:35 +0200 Message-Id: <20191016070740.121435-3-codekipper@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191016070740.121435-1-codekipper@gmail.com> References: <20191016070740.121435-1-codekipper@gmail.com> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, Marcus Cooper , lgirdwood@gmail.com, linux-kernel@vger.kernel.org, be17068@iperbole.bo.it, broonie@kernel.org, linux-arm-kernel@lists.infradead.org Subject: [alsa-devel] [PATCH v6 2/7] ASoC: sun4i-i2s: Add functions for RX and TX channel offsets X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Marcus Cooper Newer SoCs like the H6 have the channel offset bits in a different position to what is on the H3. As we will eventually add multi- channel support then create function calls as opposed to regmap fields to add support for different devices. Signed-off-by: Marcus Cooper --- sound/soc/sunxi/sun4i-i2s.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index f1a80973c450..875567881f30 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -157,6 +157,8 @@ struct sun4i_i2s_quirks { int (*set_chan_cfg)(const struct sun4i_i2s *, const struct snd_pcm_hw_params *); int (*set_fmt)(struct sun4i_i2s *, unsigned int); + void (*set_txchanoffset)(const struct sun4i_i2s *, int); + void (*set_rxchanoffset)(const struct sun4i_i2s *); }; struct sun4i_i2s { @@ -467,6 +469,23 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, return 0; } +static void sun8i_i2s_set_txchanoffset(const struct sun4i_i2s *i2s, int output) +{ + if (output >= 0 && output < 4) + regmap_update_bits(i2s->regmap, + SUN8I_I2S_TX_CHAN_SEL_REG + (output * 4), + SUN8I_I2S_TX_CHAN_OFFSET_MASK, + SUN8I_I2S_TX_CHAN_OFFSET(i2s->offset)); +} + +static void sun8i_i2s_set_rxchanoffset(const struct sun4i_i2s *i2s) +{ + regmap_update_bits(i2s->regmap, + SUN8I_I2S_RX_CHAN_SEL_REG, + SUN8I_I2S_TX_CHAN_OFFSET_MASK, + SUN8I_I2S_TX_CHAN_OFFSET(i2s->offset)); +} + static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) @@ -661,12 +680,10 @@ static int sun8i_i2s_set_soc_fmt(struct sun4i_i2s *i2s, regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, SUN8I_I2S_CTRL_MODE_MASK, mode); - regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, - SUN8I_I2S_TX_CHAN_OFFSET_MASK, - SUN8I_I2S_TX_CHAN_OFFSET(i2s->offset)); - regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, - SUN8I_I2S_TX_CHAN_OFFSET_MASK, - SUN8I_I2S_TX_CHAN_OFFSET(i2s->offset)); + if (i2s->variant->set_txchanoffset) + i2s->variant->set_txchanoffset(i2s, 0); + if (i2s->variant->set_rxchanoffset) + i2s->variant->set_rxchanoffset(i2s); /* DAI clock master masks */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { @@ -1136,6 +1153,8 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { .get_wss = sun8i_i2s_get_sr_wss, .set_chan_cfg = sun8i_i2s_set_chan_cfg, .set_fmt = sun8i_i2s_set_soc_fmt, + .set_txchanoffset = sun8i_i2s_set_txchanoffset, + .set_rxchanoffset = sun8i_i2s_set_rxchanoffset, }; static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = { From patchwork Wed Oct 16 07:07:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Code Kipper X-Patchwork-Id: 11192471 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A24D313BD for ; Wed, 16 Oct 2019 07:11:18 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 354AD20873 for ; Wed, 16 Oct 2019 07:11:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=alsa-project.org header.i=@alsa-project.org header.b="ObV6kpB0"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TuNdLmYa" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 354AD20873 Authentication-Results: mail.kernel.org; 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[213.102.65.51]) by smtp.gmail.com with ESMTPSA id j191sm1361493lfj.49.2019.10.16.00.07.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2019 00:07:45 -0700 (PDT) From: codekipper@gmail.com To: mripard@kernel.org, wens@csie.org, linux-sunxi@googlegroups.com Date: Wed, 16 Oct 2019 09:07:36 +0200 Message-Id: <20191016070740.121435-4-codekipper@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191016070740.121435-1-codekipper@gmail.com> References: <20191016070740.121435-1-codekipper@gmail.com> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, Marcus Cooper , lgirdwood@gmail.com, linux-kernel@vger.kernel.org, be17068@iperbole.bo.it, broonie@kernel.org, linux-arm-kernel@lists.infradead.org Subject: [alsa-devel] [PATCH v6 3/7] ASoC: sun4i-i2s: Add functions for RX and TX channel enables X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Marcus Cooper Newer SoCs like the H6 have the channel enable bits in a different position to what is on the H3. As we will eventually add multi- channel support then create function calls as opposed to regmap fields to add support for different devices. Signed-off-by: Marcus Cooper --- sound/soc/sunxi/sun4i-i2s.c | 32 +++++++++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 875567881f30..8d28a386872f 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -159,6 +159,8 @@ struct sun4i_i2s_quirks { int (*set_fmt)(struct sun4i_i2s *, unsigned int); void (*set_txchanoffset)(const struct sun4i_i2s *, int); void (*set_rxchanoffset)(const struct sun4i_i2s *); + void (*set_txchanen)(const struct sun4i_i2s *, int, int); + void (*set_rxchanen)(const struct sun4i_i2s *, int); }; struct sun4i_i2s { @@ -462,9 +464,7 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, SUN8I_I2S_FMT0_LRCK_PERIOD_MASK, SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period)); - regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, - SUN8I_I2S_TX_CHAN_EN_MASK, - SUN8I_I2S_TX_CHAN_EN(channels)); + i2s->variant->set_txchanen(i2s, 0, channels); return 0; } @@ -486,6 +486,24 @@ static void sun8i_i2s_set_rxchanoffset(const struct sun4i_i2s *i2s) SUN8I_I2S_TX_CHAN_OFFSET(i2s->offset)); } +static void sun8i_i2s_set_txchanen(const struct sun4i_i2s *i2s, int output, + int channel) +{ + if (output >= 0 && output < 4) + regmap_update_bits(i2s->regmap, + SUN8I_I2S_TX_CHAN_SEL_REG + (output * 4), + SUN8I_I2S_TX_CHAN_EN_MASK, + SUN8I_I2S_TX_CHAN_EN(channel)); +} + +static void sun8i_i2s_set_rxchanen(const struct sun4i_i2s *i2s, int channel) +{ + regmap_update_bits(i2s->regmap, + SUN8I_I2S_RX_CHAN_SEL_REG, + SUN8I_I2S_TX_CHAN_EN_MASK, + SUN8I_I2S_TX_CHAN_EN(channel)); +} + static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) @@ -510,6 +528,12 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, return ret; } + if (i2s->variant->set_txchanen) + i2s->variant->set_txchanen(i2s, 0, channels); + + if (i2s->variant->set_rxchanen) + i2s->variant->set_rxchanen(i2s, channels); + switch (params_physical_width(params)) { case 16: width = DMA_SLAVE_BUSWIDTH_2_BYTES; @@ -1155,6 +1179,8 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { .set_fmt = sun8i_i2s_set_soc_fmt, .set_txchanoffset = sun8i_i2s_set_txchanoffset, .set_rxchanoffset = sun8i_i2s_set_rxchanoffset, + .set_txchanen = sun8i_i2s_set_txchanen, + .set_rxchanen = sun8i_i2s_set_rxchanen, }; static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = { From patchwork Wed Oct 16 07:07:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Code Kipper X-Patchwork-Id: 11192473 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A537B13BD for ; Wed, 16 Oct 2019 07:12:07 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3A0132168B for ; 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[213.102.65.51]) by smtp.gmail.com with ESMTPSA id j191sm1361493lfj.49.2019.10.16.00.07.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2019 00:07:47 -0700 (PDT) From: codekipper@gmail.com To: mripard@kernel.org, wens@csie.org, linux-sunxi@googlegroups.com Date: Wed, 16 Oct 2019 09:07:37 +0200 Message-Id: <20191016070740.121435-5-codekipper@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191016070740.121435-1-codekipper@gmail.com> References: <20191016070740.121435-1-codekipper@gmail.com> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, Marcus Cooper , lgirdwood@gmail.com, linux-kernel@vger.kernel.org, be17068@iperbole.bo.it, broonie@kernel.org, linux-arm-kernel@lists.infradead.org Subject: [alsa-devel] [PATCH v6 4/7] ASoC: sun4i-i2s: Add functions for RX and TX channel selects X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Marcus Cooper Newer SoCs like the H6 have the channel select bits in a different positions than what is on the H3. As we will eventually add multi- channel support then create function calls as opposed to regmap fields to add support for different devices. Signed-off-by: Marcus Cooper --- sound/soc/sunxi/sun4i-i2s.c | 68 ++++++++++++++++++++++++++++++------- 1 file changed, 56 insertions(+), 12 deletions(-) diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 8d28a386872f..19988d61a085 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -120,6 +120,8 @@ #define SUN8I_I2S_TX_CHAN_OFFSET(offset) (offset << 12) #define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4) #define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4) +#define SUN8I_I2S_TX_CHAN_SEL_MASK GENMASK(2, 0) +#define SUN8I_I2S_TX_CHAN_SEL(chan) (chan - 1) #define SUN8I_I2S_RX_CHAN_SEL_REG 0x54 #define SUN8I_I2S_RX_CHAN_MAP_REG 0x58 @@ -161,6 +163,8 @@ struct sun4i_i2s_quirks { void (*set_rxchanoffset)(const struct sun4i_i2s *); void (*set_txchanen)(const struct sun4i_i2s *, int, int); void (*set_rxchanen)(const struct sun4i_i2s *, int); + void (*set_txchansel)(const struct sun4i_i2s *, int, int); + void (*set_rxchansel)(const struct sun4i_i2s *, int); }; struct sun4i_i2s { @@ -405,12 +409,8 @@ static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210); /* Configure the channels */ - regmap_update_bits(i2s->regmap, SUN4I_I2S_TX_CHAN_SEL_REG, - SUN4I_I2S_CHAN_SEL_MASK, - SUN4I_I2S_CHAN_SEL(channels)); - regmap_update_bits(i2s->regmap, SUN4I_I2S_RX_CHAN_SEL_REG, - SUN4I_I2S_CHAN_SEL_MASK, - SUN4I_I2S_CHAN_SEL(channels)); + i2s->variant->set_txchansel(i2s, 0, channels); + i2s->variant->set_rxchansel(i2s, channels); return 0; } @@ -430,12 +430,8 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210); /* Configure the channels */ - regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, - SUN4I_I2S_CHAN_SEL_MASK, - SUN4I_I2S_CHAN_SEL(channels)); - regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, - SUN4I_I2S_CHAN_SEL_MASK, - SUN4I_I2S_CHAN_SEL(channels)); + i2s->variant->set_txchansel(i2s, 0, channels); + i2s->variant->set_rxchansel(i2s, channels); regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK, @@ -504,6 +500,40 @@ static void sun8i_i2s_set_rxchanen(const struct sun4i_i2s *i2s, int channel) SUN8I_I2S_TX_CHAN_EN(channel)); } +static void sun4i_i2s_set_txchansel(const struct sun4i_i2s *i2s, int output, + int channel) +{ + if (output == 0) + regmap_write(i2s->regmap, + SUN4I_I2S_TX_CHAN_SEL_REG, + SUN4I_I2S_CHAN_SEL(channel)); +} + +static void sun8i_i2s_set_txchansel(const struct sun4i_i2s *i2s, int output, + int channel) +{ + if (output >= 0 && output < 4) + regmap_update_bits(i2s->regmap, + SUN8I_I2S_TX_CHAN_SEL_REG + (output * 4), + SUN8I_I2S_TX_CHAN_SEL_MASK, + SUN8I_I2S_TX_CHAN_SEL(channel)); +} + +static void sun4i_i2s_set_rxchansel(const struct sun4i_i2s *i2s, int channel) +{ + regmap_write(i2s->regmap, + SUN4I_I2S_RX_CHAN_SEL_REG, + SUN4I_I2S_CHAN_SEL(channel)); +} + +static void sun8i_i2s_set_rxchansel(const struct sun4i_i2s *i2s, int channel) +{ + regmap_update_bits(i2s->regmap, + SUN8I_I2S_RX_CHAN_SEL_REG, + SUN8I_I2S_TX_CHAN_SEL_MASK, + SUN8I_I2S_TX_CHAN_SEL(channel)); +} + static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) @@ -528,6 +558,10 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, return ret; } + /* Configure the channels */ + i2s->variant->set_txchansel(i2s, 0, channels); + i2s->variant->set_rxchansel(i2s, channels); + if (i2s->variant->set_txchanen) i2s->variant->set_txchanen(i2s, 0, channels); @@ -1118,6 +1152,8 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { .get_wss = sun4i_i2s_get_wss, .set_chan_cfg = sun4i_i2s_set_chan_cfg, .set_fmt = sun4i_i2s_set_soc_fmt, + .set_txchansel = sun4i_i2s_set_txchansel, + .set_rxchansel = sun4i_i2s_set_rxchansel, }; static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { @@ -1136,6 +1172,8 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { .get_wss = sun4i_i2s_get_wss, .set_chan_cfg = sun4i_i2s_set_chan_cfg, .set_fmt = sun4i_i2s_set_soc_fmt, + .set_txchansel = sun4i_i2s_set_txchansel, + .set_rxchansel = sun4i_i2s_set_rxchansel, }; /* @@ -1159,6 +1197,8 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { .get_wss = sun4i_i2s_get_wss, .set_chan_cfg = sun4i_i2s_set_chan_cfg, .set_fmt = sun4i_i2s_set_soc_fmt, + .set_txchansel = sun4i_i2s_set_txchansel, + .set_rxchansel = sun4i_i2s_set_rxchansel, }; static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { @@ -1181,6 +1221,8 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { .set_rxchanoffset = sun8i_i2s_set_rxchanoffset, .set_txchanen = sun8i_i2s_set_txchanen, .set_rxchanen = sun8i_i2s_set_rxchanen, + .set_txchansel = sun8i_i2s_set_txchansel, + .set_rxchansel = sun8i_i2s_set_rxchansel, }; static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = { @@ -1199,6 +1241,8 @@ static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = { .get_wss = sun4i_i2s_get_wss, .set_chan_cfg = sun4i_i2s_set_chan_cfg, .set_fmt = sun4i_i2s_set_soc_fmt, + .set_txchansel = sun4i_i2s_set_txchansel, + .set_rxchansel = sun4i_i2s_set_rxchansel, }; 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[213.102.65.51]) by smtp.gmail.com with ESMTPSA id j191sm1361493lfj.49.2019.10.16.00.07.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2019 00:07:48 -0700 (PDT) From: codekipper@gmail.com To: mripard@kernel.org, wens@csie.org, linux-sunxi@googlegroups.com Date: Wed, 16 Oct 2019 09:07:38 +0200 Message-Id: <20191016070740.121435-6-codekipper@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191016070740.121435-1-codekipper@gmail.com> References: <20191016070740.121435-1-codekipper@gmail.com> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, Marcus Cooper , lgirdwood@gmail.com, linux-kernel@vger.kernel.org, be17068@iperbole.bo.it, broonie@kernel.org, linux-arm-kernel@lists.infradead.org Subject: [alsa-devel] [PATCH v6 5/7] ASoC: sun4i-i2s: Add functions for RX and TX channel mapping X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Marcus Cooper As we will eventually add multi-channel audio support to the i2s then create function calls as opposed to regmap fields to add support for different devices. Signed-off-by: Marcus Cooper --- sound/soc/sunxi/sun4i-i2s.c | 45 +++++++++++++++++++++++++++++++++---- 1 file changed, 41 insertions(+), 4 deletions(-) diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 19988d61a085..63ae9da180f2 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -165,6 +165,8 @@ struct sun4i_i2s_quirks { void (*set_rxchanen)(const struct sun4i_i2s *, int); void (*set_txchansel)(const struct sun4i_i2s *, int, int); void (*set_rxchansel)(const struct sun4i_i2s *, int); + void (*set_txchanmap)(const struct sun4i_i2s *, int, int); + void (*set_rxchanmap)(const struct sun4i_i2s *, int); }; struct sun4i_i2s { @@ -405,8 +407,8 @@ static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, unsigned int channels = params_channels(params); /* Map the channels for playback and capture */ - regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210); - regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210); + i2s->variant->set_txchanmap(i2s, 0, 0x76543210); + i2s->variant->set_rxchanmap(i2s, 0x00003210); /* Configure the channels */ i2s->variant->set_txchansel(i2s, 0, channels); @@ -426,8 +428,8 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, slots = i2s->slots; /* Map the channels for playback and capture */ - regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210); - regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210); + i2s->variant->set_txchanmap(i2s, 0, 0x76543210); + i2s->variant->set_rxchanmap(i2s, 0x00003210); /* Configure the channels */ i2s->variant->set_txchansel(i2s, 0, channels); @@ -534,6 +536,31 @@ static void sun8i_i2s_set_rxchansel(const struct sun4i_i2s *i2s, int channel) SUN8I_I2S_TX_CHAN_SEL(channel)); } +static void sun4i_i2s_set_txchanmap(const struct sun4i_i2s *i2s, int output, + int channel) +{ + if (output == 0) + regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, channel); +} + +static void sun8i_i2s_set_txchanmap(const struct sun4i_i2s *i2s, int output, + int channel) +{ + if (output >= 0 && output < 4) + regmap_write(i2s->regmap, + SUN8I_I2S_TX_CHAN_MAP_REG + (output * 4), channel); +} + +static void sun4i_i2s_set_rxchanmap(const struct sun4i_i2s *i2s, int channel) +{ + regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, channel); +} + +static void sun8i_i2s_set_rxchanmap(const struct sun4i_i2s *i2s, int channel) +{ + regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, channel); +} + static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) @@ -1154,6 +1181,8 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { .set_fmt = sun4i_i2s_set_soc_fmt, .set_txchansel = sun4i_i2s_set_txchansel, .set_rxchansel = sun4i_i2s_set_rxchansel, + .set_txchanmap = sun4i_i2s_set_txchanmap, + .set_rxchanmap = sun4i_i2s_set_rxchanmap, }; static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { @@ -1174,6 +1203,8 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { .set_fmt = sun4i_i2s_set_soc_fmt, .set_txchansel = sun4i_i2s_set_txchansel, .set_rxchansel = sun4i_i2s_set_rxchansel, + .set_txchanmap = sun4i_i2s_set_txchanmap, + .set_rxchanmap = sun4i_i2s_set_rxchanmap, }; /* @@ -1199,6 +1230,8 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { .set_fmt = sun4i_i2s_set_soc_fmt, .set_txchansel = sun4i_i2s_set_txchansel, .set_rxchansel = sun4i_i2s_set_rxchansel, + .set_txchanmap = sun4i_i2s_set_txchanmap, + .set_rxchanmap = sun4i_i2s_set_rxchanmap, }; static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { @@ -1223,6 +1256,8 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { .set_rxchanen = sun8i_i2s_set_rxchanen, .set_txchansel = sun8i_i2s_set_txchansel, .set_rxchansel = sun8i_i2s_set_rxchansel, + .set_txchanmap = sun8i_i2s_set_txchanmap, + .set_rxchanmap = sun8i_i2s_set_rxchanmap, }; static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = { @@ -1243,6 +1278,8 @@ static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = { .set_fmt = sun4i_i2s_set_soc_fmt, .set_txchansel = sun4i_i2s_set_txchansel, .set_rxchansel = sun4i_i2s_set_rxchansel, + .set_txchanmap = sun4i_i2s_set_txchanmap, + .set_rxchanmap = sun4i_i2s_set_rxchanmap, }; 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[213.102.65.51]) by smtp.gmail.com with ESMTPSA id j191sm1361493lfj.49.2019.10.16.00.07.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2019 00:07:49 -0700 (PDT) From: codekipper@gmail.com To: mripard@kernel.org, wens@csie.org, linux-sunxi@googlegroups.com Date: Wed, 16 Oct 2019 09:07:39 +0200 Message-Id: <20191016070740.121435-7-codekipper@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191016070740.121435-1-codekipper@gmail.com> References: <20191016070740.121435-1-codekipper@gmail.com> MIME-Version: 1.0 Cc: Jernej Skrabec , alsa-devel@alsa-project.org, Marcus Cooper , lgirdwood@gmail.com, linux-kernel@vger.kernel.org, be17068@iperbole.bo.it, broonie@kernel.org, linux-arm-kernel@lists.infradead.org Subject: [alsa-devel] [PATCH v6 6/7] dt-bindings: ASoC: sun4i-i2s: Add H6 compatible X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Jernej Skrabec H6 I2S is very similar to H3, except that it supports up to 16 channels and thus few registers have fields on different position. Signed-off-by: Jernej Skrabec Signed-off-by: Marcus Cooper --- .../devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml index eb3992138eec..6928d0a1dcc8 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml @@ -24,6 +24,7 @@ properties: - items: - const: allwinner,sun50i-a64-i2s - const: allwinner,sun8i-h3-i2s + - const: allwinner,sun50i-h6-i2s reg: maxItems: 1 @@ -59,6 +60,7 @@ allOf: - allwinner,sun8i-a83t-i2s - allwinner,sun8i-h3-i2s - allwinner,sun50i-a64-codec-i2s + - allwinner,sun50i-h6-i2s then: required: From patchwork Wed Oct 16 07:07:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Code Kipper X-Patchwork-Id: 11192481 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7C9A113BD for ; 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[213.102.65.51]) by smtp.gmail.com with ESMTPSA id j191sm1361493lfj.49.2019.10.16.00.07.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2019 00:07:51 -0700 (PDT) From: codekipper@gmail.com To: mripard@kernel.org, wens@csie.org, linux-sunxi@googlegroups.com Date: Wed, 16 Oct 2019 09:07:40 +0200 Message-Id: <20191016070740.121435-8-codekipper@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191016070740.121435-1-codekipper@gmail.com> References: <20191016070740.121435-1-codekipper@gmail.com> MIME-Version: 1.0 Cc: Jernej Skrabec , alsa-devel@alsa-project.org, Marcus Cooper , lgirdwood@gmail.com, linux-kernel@vger.kernel.org, be17068@iperbole.bo.it, broonie@kernel.org, linux-arm-kernel@lists.infradead.org Subject: [alsa-devel] [PATCH v6 7/7] ASoC: sun4i-i2s: Add support for H6 I2S X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Jernej Skrabec H6 I2S is very similar to that in H3, except it supports up to 16 channels. Signed-off-by: Jernej Skrabec Signed-off-by: Marcus Cooper --- sound/soc/sunxi/sun4i-i2s.c | 143 ++++++++++++++++++++++++++++++++++++ 1 file changed, 143 insertions(+) diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 63ae9da180f2..564b31788f29 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -126,6 +126,21 @@ #define SUN8I_I2S_RX_CHAN_SEL_REG 0x54 #define SUN8I_I2S_RX_CHAN_MAP_REG 0x58 +/* Defines required for sun50i-h6 support */ +#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK GENMASK(21, 20) +#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset) ((offset) << 20) +#define SUN50I_H6_I2S_TX_CHAN_SEL_MASK GENMASK(19, 16) +#define SUN50I_H6_I2S_TX_CHAN_SEL(chan) ((chan - 1) << 16) +#define SUN50I_H6_I2S_TX_CHAN_EN_MASK GENMASK(15, 0) +#define SUN50I_H6_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1)) + +#define SUN50I_H6_I2S_TX_CHAN_MAP0_REG 0x44 +#define SUN50I_H6_I2S_TX_CHAN_MAP1_REG 0x48 + +#define SUN50I_H6_I2S_RX_CHAN_SEL_REG 0x64 +#define SUN50I_H6_I2S_RX_CHAN_MAP0_REG 0x68 +#define SUN50I_H6_I2S_RX_CHAN_MAP1_REG 0x6C + struct sun4i_i2s; /** @@ -484,6 +499,24 @@ static void sun8i_i2s_set_rxchanoffset(const struct sun4i_i2s *i2s) SUN8I_I2S_TX_CHAN_OFFSET(i2s->offset)); } +static void sun50i_h6_i2s_set_txchanoffset(const struct sun4i_i2s *i2s, int output) +{ + if (output >= 0 && output < 4) + regmap_update_bits(i2s->regmap, + SUN8I_I2S_TX_CHAN_SEL_REG + (output * 4), + SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK, + SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(i2s->offset)); + +} + +static void sun50i_h6_i2s_set_rxchanoffset(const struct sun4i_i2s *i2s) +{ + regmap_update_bits(i2s->regmap, + SUN50I_H6_I2S_RX_CHAN_SEL_REG, + SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK, + SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(i2s->offset)); +} + static void sun8i_i2s_set_txchanen(const struct sun4i_i2s *i2s, int output, int channel) { @@ -502,6 +535,25 @@ static void sun8i_i2s_set_rxchanen(const struct sun4i_i2s *i2s, int channel) SUN8I_I2S_TX_CHAN_EN(channel)); } + +static void sun50i_h6_i2s_set_txchanen(const struct sun4i_i2s *i2s, int output, + int channel) +{ + if (output >= 0 && output < 4) + regmap_update_bits(i2s->regmap, + SUN8I_I2S_TX_CHAN_SEL_REG + (output * 4), + SUN50I_H6_I2S_TX_CHAN_EN_MASK, + SUN50I_H6_I2S_TX_CHAN_EN(channel)); +} + +static void sun50i_h6_i2s_set_rxchanen(const struct sun4i_i2s *i2s, int channel) +{ + regmap_update_bits(i2s->regmap, + SUN50I_H6_I2S_RX_CHAN_SEL_REG, + SUN50I_H6_I2S_TX_CHAN_EN_MASK, + SUN50I_H6_I2S_TX_CHAN_EN(channel)); +} + static void sun4i_i2s_set_txchansel(const struct sun4i_i2s *i2s, int output, int channel) { @@ -536,6 +588,24 @@ static void sun8i_i2s_set_rxchansel(const struct sun4i_i2s *i2s, int channel) SUN8I_I2S_TX_CHAN_SEL(channel)); } +static void sun50i_h6_i2s_set_txchansel(const struct sun4i_i2s *i2s, int output, + int channel) +{ + if (output >= 0 && output < 4) + regmap_update_bits(i2s->regmap, + SUN8I_I2S_TX_CHAN_SEL_REG + (output * 4), + SUN50I_H6_I2S_TX_CHAN_SEL_MASK, + SUN50I_H6_I2S_TX_CHAN_SEL(channel)); +} + +static void sun50i_h6_i2s_set_rxchansel(const struct sun4i_i2s *i2s, int channel) +{ + regmap_update_bits(i2s->regmap, + SUN50I_H6_I2S_RX_CHAN_SEL_REG, + SUN50I_H6_I2S_TX_CHAN_SEL_MASK, + SUN50I_H6_I2S_TX_CHAN_SEL(channel)); +} + static void sun4i_i2s_set_txchanmap(const struct sun4i_i2s *i2s, int output, int channel) { @@ -561,6 +631,20 @@ static void sun8i_i2s_set_rxchanmap(const struct sun4i_i2s *i2s, int channel) regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, channel); } +static void sun50i_h6_i2s_set_txchanmap(const struct sun4i_i2s *i2s, int output, + int channel) +{ + if (output >= 0 && output < 4) + regmap_write(i2s->regmap, + SUN50I_H6_I2S_TX_CHAN_MAP1_REG + (output * 8), + channel); +} + +static void sun50i_h6_i2s_set_rxchanmap(const struct sun4i_i2s *i2s, int channel) +{ + regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, channel); +} + static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) @@ -1073,6 +1157,22 @@ static const struct reg_default sun8i_i2s_reg_defaults[] = { { SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 }, }; +static const struct reg_default sun50i_i2s_reg_defaults[] = { + { SUN4I_I2S_CTRL_REG, 0x00060000 }, + { SUN4I_I2S_FMT0_REG, 0x00000033 }, + { SUN4I_I2S_FMT1_REG, 0x00000030 }, + { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 }, + { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 }, + { SUN4I_I2S_CLK_DIV_REG, 0x00000000 }, + { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 }, + { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 }, + { SUN50I_H6_I2S_TX_CHAN_MAP0_REG, 0x00000000 }, + { SUN50I_H6_I2S_TX_CHAN_MAP1_REG, 0x00000000 }, + { SUN50I_H6_I2S_RX_CHAN_SEL_REG, 0x00000000 }, + { SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0x00000000 }, + { SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x00000000 }, +}; + static const struct regmap_config sun4i_i2s_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -1100,6 +1200,19 @@ static const struct regmap_config sun8i_i2s_regmap_config = { .volatile_reg = sun8i_i2s_volatile_reg, }; +static const struct regmap_config sun50i_i2s_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = SUN50I_H6_I2S_RX_CHAN_MAP1_REG, + .cache_type = REGCACHE_FLAT, + .reg_defaults = sun50i_i2s_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(sun50i_i2s_reg_defaults), + .writeable_reg = sun4i_i2s_wr_reg, + .readable_reg = sun8i_i2s_rd_reg, + .volatile_reg = sun8i_i2s_volatile_reg, +}; + static int sun4i_i2s_runtime_resume(struct device *dev) { struct sun4i_i2s *i2s = dev_get_drvdata(dev); @@ -1282,6 +1395,32 @@ static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = { .set_rxchanmap = sun4i_i2s_set_rxchanmap, }; +static const struct sun4i_i2s_quirks sun50i_h6_i2s_quirks = { + .has_reset = true, + .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, + .sun4i_i2s_regmap = &sun50i_i2s_regmap_config, + .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), + .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), + .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), + .bclk_dividers = sun8i_i2s_clk_div, + .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), + .mclk_dividers = sun8i_i2s_clk_div, + .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), + .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate, + .get_sr = sun8i_i2s_get_sr_wss, + .get_wss = sun8i_i2s_get_sr_wss, + .set_chan_cfg = sun8i_i2s_set_chan_cfg, + .set_fmt = sun8i_i2s_set_soc_fmt, + .set_txchanoffset = sun50i_h6_i2s_set_txchanoffset, + .set_rxchanoffset = sun50i_h6_i2s_set_rxchanoffset, + .set_txchanen = sun50i_h6_i2s_set_txchanen, + .set_rxchanen = sun50i_h6_i2s_set_rxchanen, + .set_txchansel = sun50i_h6_i2s_set_txchansel, + .set_rxchansel = sun50i_h6_i2s_set_rxchansel, + .set_txchanmap = sun50i_h6_i2s_set_txchanmap, + .set_rxchanmap = sun50i_h6_i2s_set_rxchanmap, +}; + static int sun4i_i2s_init_regmap_fields(struct device *dev, struct sun4i_i2s *i2s) { @@ -1451,6 +1590,10 @@ static const struct of_device_id sun4i_i2s_match[] = { .compatible = "allwinner,sun50i-a64-codec-i2s", .data = &sun50i_a64_codec_i2s_quirks, }, + { + .compatible = "allwinner,sun50i-h6-i2s", + .data = &sun50i_h6_i2s_quirks, + }, {} }; MODULE_DEVICE_TABLE(of, sun4i_i2s_match);