From patchwork Wed Oct 16 07:34:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11192527 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 384DF14ED for ; Wed, 16 Oct 2019 07:34:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 108ED21A4C for ; Wed, 16 Oct 2019 07:34:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="LzUjZmEp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732033AbfJPHe2 (ORCPT ); Wed, 16 Oct 2019 03:34:28 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:42438 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732037AbfJPHe1 (ORCPT ); Wed, 16 Oct 2019 03:34:27 -0400 Received: by mail-pg1-f196.google.com with SMTP id f14so8642519pgi.9 for ; Wed, 16 Oct 2019 00:34:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=rO1z1JlGDHGdy6zVD5fls33iWqIXWjt9KmTfIa3Qj2w=; b=LzUjZmEpb4CTUq2TAze15TIpVNPb2PZBWKXXlGpSIhPM3RX/9Bu0Wrgugkkp90yLqT BfxN2xeveGkUuIU73q0mnw3Ech8CAmdOtynmdYGHsKBNCZQRoSab+Z4w3Gfh2eSAyaQC TsPy3rAJw8IgC92PZ8CkB+/FOioFXftl/mIa2RJBB5bjE/q0lBMg5IzZj8XVlUldPZj+ vV5+m5AToJemzw9OeoNCDDzdt9jdjFLwQMU7Q8XoXDHp53b96yxNQrAL7o8hpq6AHNAY HCo0S3C1mYgINkInHdzjMVtXnqV54cj7y0Jgaq/CxJINOepTF3rOji2yuv5X6SQJ8UdG ApyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=rO1z1JlGDHGdy6zVD5fls33iWqIXWjt9KmTfIa3Qj2w=; b=YITRGaXI0P8p3NA7HUOJ1T35sBpVOjadCSI1mjVCuCUrJ3xad3wNlHM1vpwWqV0v1m w7ecqs5yDYOwR3sfMRV1nuxT9mPEYlA3n4PloPl3w+hylRJFiLi7ER2/McuFMzIey9lL X9nBBdDxWd/ersGDkWIiqqc3qG6o7YfqnPXY9filSuLxaO0LfF90Z0FzkZfCKqn4sn36 YUhx4EaJYV4GADxPfBa9JKB6CuVWt5oezIZVKUJyrLQy4XvHXpVkqgd3UQL3sWXBdZ04 au1An3yEgwsyiMQOQUMLsDFuhil9Z4qgXy1V3wi/s/BF2fsCTmlBQ8k7dORx2CcFpG2C aKvA== X-Gm-Message-State: APjAAAWqB1GsxRFBebzqA4XjnXe6lP4UEgsYufpuKcP1cSdsWrB8VFzd lIJoqNqgOvXkMfnuZkyG7CLKzg== X-Google-Smtp-Source: APXvYqxIix7KacqDt1ZmK3NT3IXpglg5xJAaVeGj+FzUTHwHwTlguOm3BIer5zA+D1tkF1fYiRO4Ow== X-Received: by 2002:a63:8541:: with SMTP id u62mr41548173pgd.377.1571211266665; Wed, 16 Oct 2019 00:34:26 -0700 (PDT) Received: from localhost ([49.248.175.127]) by smtp.gmail.com with ESMTPSA id s141sm30601856pfs.13.2019.10.16.00.34.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2019 00:34:26 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH 01/15] drivers: thermal: tsens: Get rid of id field in tsens_sensor Date: Wed, 16 Oct 2019 13:04:00 +0530 Message-Id: <30206cd47d303d2dcaef87f4e3c7173481a0bddd.1571210269.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There are two fields - id and hw_id - to track what sensor an action was to performed on. This was because the sensors connected to a TSENS IP might not be contiguous i.e. 1, 2, 4, 5 with 3 being skipped. This causes confusion in the code which uses hw_id sometimes and id other times (tsens_get_temp, tsens_get_trend). Switch to only using the hw_id field to track the physical ID of the sensor. When we iterate through all the sensors connected to an IP block, we use an index i to loop through the list of sensors, and then return the actual hw_id that is registered on that index. Signed-off-by: Amit Kucheria Reviewed-by: Stephen Boyd Reviewed-by: Daniel Lezcano --- drivers/thermal/qcom/tsens-8960.c | 4 ++-- drivers/thermal/qcom/tsens-common.c | 16 +++++++++------- drivers/thermal/qcom/tsens.c | 11 +++++------ drivers/thermal/qcom/tsens.h | 10 ++++------ 4 files changed, 20 insertions(+), 21 deletions(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index e46a4e3f25c4..fb77acb8d13b 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -245,11 +245,11 @@ static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s) return adc_code * slope + offset; } -static int get_temp_8960(struct tsens_priv *priv, int id, int *temp) +static int get_temp_8960(struct tsens_sensor *s, int *temp) { int ret; u32 code, trdy; - const struct tsens_sensor *s = &priv->sensor[id]; + struct tsens_priv *priv = s->priv; unsigned long timeout; timeout = jiffies + usecs_to_jiffies(TIMEOUT_US); diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 528df8801254..c037bdf92c66 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -83,11 +83,12 @@ static inline int code_to_degc(u32 adc_code, const struct tsens_sensor *s) return degc; } -int get_temp_tsens_valid(struct tsens_priv *priv, int i, int *temp) +int get_temp_tsens_valid(struct tsens_sensor *s, int *temp) { - struct tsens_sensor *s = &priv->sensor[i]; - u32 temp_idx = LAST_TEMP_0 + s->hw_id; - u32 valid_idx = VALID_0 + s->hw_id; + struct tsens_priv *priv = s->priv; + int hw_id = s->hw_id; + u32 temp_idx = LAST_TEMP_0 + hw_id; + u32 valid_idx = VALID_0 + hw_id; u32 last_temp = 0, valid, mask; int ret; @@ -123,12 +124,13 @@ int get_temp_tsens_valid(struct tsens_priv *priv, int i, int *temp) return 0; } -int get_temp_common(struct tsens_priv *priv, int i, int *temp) +int get_temp_common(struct tsens_sensor *s, int *temp) { - struct tsens_sensor *s = &priv->sensor[i]; + struct tsens_priv *priv = s->priv; + int hw_id = s->hw_id; int last_temp = 0, ret; - ret = regmap_field_read(priv->rf[LAST_TEMP_0 + s->hw_id], &last_temp); + ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp); if (ret) return ret; diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 0627d8615c30..6ed687a6e53c 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -14,19 +14,19 @@ static int tsens_get_temp(void *data, int *temp) { - const struct tsens_sensor *s = data; + struct tsens_sensor *s = data; struct tsens_priv *priv = s->priv; - return priv->ops->get_temp(priv, s->id, temp); + return priv->ops->get_temp(s, temp); } static int tsens_get_trend(void *data, int trip, enum thermal_trend *trend) { - const struct tsens_sensor *s = data; + struct tsens_sensor *s = data; struct tsens_priv *priv = s->priv; if (priv->ops->get_trend) - return priv->ops->get_trend(priv, s->id, trend); + return priv->ops->get_trend(s, trend); return -ENOTSUPP; } @@ -86,8 +86,7 @@ static int tsens_register(struct tsens_priv *priv) for (i = 0; i < priv->num_sensors; i++) { priv->sensor[i].priv = priv; - priv->sensor[i].id = i; - tzd = devm_thermal_zone_of_sensor_register(priv->dev, i, + tzd = devm_thermal_zone_of_sensor_register(priv->dev, priv->sensor[i].hw_id, &priv->sensor[i], &tsens_of_ops); if (IS_ERR(tzd)) diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index b89083b61c38..84e5447c5686 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -32,7 +32,6 @@ enum tsens_ver { * @priv: tsens device instance that this sensor is connected to * @tzd: pointer to the thermal zone that this sensor is in * @offset: offset of temperature adjustment curve - * @id: Sensor ID * @hw_id: HW ID can be used in case of platform-specific IDs * @slope: slope of temperature adjustment curve * @status: 8960-specific variable to track 8960 and 8660 status register offset @@ -41,7 +40,6 @@ struct tsens_sensor { struct tsens_priv *priv; struct thermal_zone_device *tzd; int offset; - unsigned int id; unsigned int hw_id; int slope; u32 status; @@ -62,13 +60,13 @@ struct tsens_ops { /* mandatory callbacks */ int (*init)(struct tsens_priv *priv); int (*calibrate)(struct tsens_priv *priv); - int (*get_temp)(struct tsens_priv *priv, int i, int *temp); + int (*get_temp)(struct tsens_sensor *s, int *temp); /* optional callbacks */ int (*enable)(struct tsens_priv *priv, int i); void (*disable)(struct tsens_priv *priv); int (*suspend)(struct tsens_priv *priv); int (*resume)(struct tsens_priv *priv); - int (*get_trend)(struct tsens_priv *priv, int i, enum thermal_trend *trend); + int (*get_trend)(struct tsens_sensor *s, enum thermal_trend *trend); }; #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \ @@ -314,8 +312,8 @@ struct tsens_priv { char *qfprom_read(struct device *dev, const char *cname); void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode); int init_common(struct tsens_priv *priv); -int get_temp_tsens_valid(struct tsens_priv *priv, int i, int *temp); -int get_temp_common(struct tsens_priv *priv, int i, int *temp); +int get_temp_tsens_valid(struct tsens_sensor *s, int *temp); +int get_temp_common(struct tsens_sensor *s, int *temp); /* TSENS target */ extern const struct tsens_plat_data data_8960; From patchwork Wed Oct 16 07:34:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11192535 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3FBBA14ED for ; Wed, 16 Oct 2019 07:34:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1FEBD21A4C for ; Wed, 16 Oct 2019 07:34:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zr8Jj6FL" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732328AbfJPHeb (ORCPT ); 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Wed, 16 Oct 2019 00:34:29 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH 02/15] drivers: thermal: tsens: Simplify code flow in tsens_probe Date: Wed, 16 Oct 2019 13:04:01 +0530 Message-Id: <184422dcc1c12553e71a58c62e01425fd7d1172a.1571210269.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move platform_set_drvdata up to avoid an extra 'if (ret)' check after the call to tsens_register. Signed-off-by: Amit Kucheria Reviewed-by: Stephen Boyd Reviewed-by: Daniel Lezcano --- drivers/thermal/qcom/tsens.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 6ed687a6e53c..542a7f8c3d96 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -149,6 +149,8 @@ static int tsens_probe(struct platform_device *pdev) priv->feat = data->feat; priv->fields = data->fields; + platform_set_drvdata(pdev, priv); + if (!priv->ops || !priv->ops->init || !priv->ops->get_temp) return -EINVAL; @@ -167,11 +169,7 @@ static int tsens_probe(struct platform_device *pdev) } } - ret = tsens_register(priv); - - platform_set_drvdata(pdev, priv); - - return ret; + return tsens_register(priv); } static int tsens_remove(struct platform_device *pdev) From patchwork Wed Oct 16 07:34:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11192581 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 388D814ED for ; Wed, 16 Oct 2019 07:35:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 18DA520873 for ; Wed, 16 Oct 2019 07:35:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="dCFBysYD" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732564AbfJPHeg (ORCPT ); Wed, 16 Oct 2019 03:34:36 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:33655 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732040AbfJPHee (ORCPT ); Wed, 16 Oct 2019 03:34:34 -0400 Received: by mail-pg1-f195.google.com with SMTP id i76so13768652pgc.0 for ; Wed, 16 Oct 2019 00:34:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=4RhmNFrAjG8zCFd7O6KRoEzlzkP2xNrQ5XZHUG6WYMo=; b=dCFBysYDMtrZWkaWVSQ6gElCAcOUUOzQjnnzXReacAYDRsxxrF6pcSz2vUYJL2wuyb 9lXXXGhU0BnfZrvH5fd1wExIx5HcCvOX5JGZ4kjGJX9YY0aRYxUxKBGfxDgVQI1iHugg lu39ANrG4dMc9P1lRSw56+WhLI5wNhtgGm/2prvVjbTjP8NW7NpOg2A2eiawKKhwC72x iajf+VznJ8/MDK2d63PJKKAkokdpE93pXoonLw+cvsX8gg/1dsGHv38NR4OHfVYqamx5 vmy/y4e2rRfHTyjaN3x5ShfIykPkVL6Q8F5fsnR9ZtSAbcm+cpihcfVCxzl7SqvXiBri 25Qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=4RhmNFrAjG8zCFd7O6KRoEzlzkP2xNrQ5XZHUG6WYMo=; b=EIzphg/l1jVQtmDduaxg9gL0Ey6WfWBmOHNzCGc+9nKPzbjT3VUsD1DGd0qARqjuGz OpoyWBZaV1DE/nTypvbuZYc8xnff9xfZKnDna6KxFXaGJG+pq3BmVSCImb/J5OytRjZu icCeSe/IoG9Vb0a+yePiZ1qauSF2ceFVrGuSwnisb9af3zV8907bMm45haRTjNKmwJoG D0hldTOXag+b11rfk0m1shstobbnp5PgyHxOc2X/4GDdVl9pjOLtoQf0nJNS0uGCEOp+ +KjRFUPGCT2oKmYiJ/qOR2guUj76T5uA5w1UO38bAK3HbahhfiMtTBj7hQCWcY+Dkc2J ALNw== X-Gm-Message-State: APjAAAXtIPtVK4f/Eo7S9wOSH7tVIRU7Vj1OOpLnxNwxS3jsgZmV59R1 gAtCCkHc5j8yrzfSATIjxbvTuQ== X-Google-Smtp-Source: APXvYqwihrDW65PEOGJ0kyNKW8RAcSD6I0XTQ+vr82D1QKTjMmX9J5e/RTa7TEUS3fDoL4KiMfmUdA== X-Received: by 2002:a63:1e04:: with SMTP id e4mr22427676pge.4.1571211273858; Wed, 16 Oct 2019 00:34:33 -0700 (PDT) Received: from localhost ([49.248.175.127]) by smtp.gmail.com with ESMTPSA id k124sm12361970pga.83.2019.10.16.00.34.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2019 00:34:33 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH 03/15] drivers: thermal: tsens: Add __func__ identifier to debug statements Date: Wed, 16 Oct 2019 13:04:02 +0530 Message-Id: <18717de35f31098d3ebc12564c2767b6d54d37d8.1571210269.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Printing the function name when enabling debugging makes logs easier to read. Signed-off-by: Amit Kucheria Reviewed-by: Stephen Boyd Reviewed-by: Daniel Lezcano --- drivers/thermal/qcom/tsens-common.c | 8 ++++---- drivers/thermal/qcom/tsens.c | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index c037bdf92c66..7437bfe196e5 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -42,8 +42,8 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *p1, for (i = 0; i < priv->num_sensors; i++) { dev_dbg(priv->dev, - "sensor%d - data_point1:%#x data_point2:%#x\n", - i, p1[i], p2[i]); + "%s: sensor%d - data_point1:%#x data_point2:%#x\n", + __func__, i, p1[i], p2[i]); priv->sensor[i].slope = SLOPE_DEFAULT; if (mode == TWO_PT_CALIB) { @@ -60,7 +60,7 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *p1, priv->sensor[i].offset = (p1[i] * SLOPE_FACTOR) - (CAL_DEGC_PT1 * priv->sensor[i].slope); - dev_dbg(priv->dev, "offset:%d\n", priv->sensor[i].offset); + dev_dbg(priv->dev, "%s: offset:%d\n", __func__, priv->sensor[i].offset); } } @@ -209,7 +209,7 @@ int __init init_common(struct tsens_priv *priv) if (ret) goto err_put_device; if (!enabled) { - dev_err(dev, "tsens device is not enabled\n"); + dev_err(dev, "%s: device not enabled\n", __func__); ret = -ENODEV; goto err_put_device; } diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 542a7f8c3d96..06c6bbd69a1a 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -127,7 +127,7 @@ static int tsens_probe(struct platform_device *pdev) of_property_read_u32(np, "#qcom,sensors", &num_sensors); if (num_sensors <= 0) { - dev_err(dev, "invalid number of sensors\n"); + dev_err(dev, "%s: invalid number of sensors\n", __func__); return -EINVAL; } @@ -156,7 +156,7 @@ static int tsens_probe(struct platform_device *pdev) ret = priv->ops->init(priv); if (ret < 0) { - dev_err(dev, "tsens init failed\n"); + dev_err(dev, "%s: init failed\n", __func__); return ret; } @@ -164,7 +164,7 @@ static int tsens_probe(struct platform_device *pdev) ret = priv->ops->calibrate(priv); if (ret < 0) { if (ret != -EPROBE_DEFER) - dev_err(dev, "tsens calibration failed\n"); + dev_err(dev, "%s: calibration failed\n", __func__); return ret; } } From patchwork Wed Oct 16 07:34:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11192551 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 54F7514ED for ; Wed, 16 Oct 2019 07:34:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2E7D121835 for ; Wed, 16 Oct 2019 07:34:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="m2blUIER" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732857AbfJPHej (ORCPT ); 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Wed, 16 Oct 2019 00:34:37 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH 04/15] drivers: thermal: tsens: Add debugfs support Date: Wed, 16 Oct 2019 13:04:03 +0530 Message-Id: <16e39c1bbfc18b5cf6274620cd72cc63205f53a5.1571210269.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Dump some basic version info and sensor details into debugfs. Example from qcs404 below: --(/sys/kernel/debug) $ ls tsens/ 4a9000.thermal-sensor version --(/sys/kernel/debug) $ cat tsens/version 1.4.0 --(/sys/kernel/debug) $ cat tsens/4a9000.thermal-sensor/sensors max: 11 num: 10 id slope offset ------------------------ 0 3200 404000 1 3200 404000 2 3200 404000 3 3200 404000 4 3200 404000 5 3200 404000 6 3200 404000 7 3200 404000 8 3200 404000 9 3200 404000 Signed-off-by: Amit Kucheria Reviewed-by: Stephen Boyd --- drivers/thermal/qcom/tsens-common.c | 83 +++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.c | 2 + drivers/thermal/qcom/tsens.h | 6 +++ 3 files changed, 91 insertions(+) diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 7437bfe196e5..ea2c46cc6a66 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -3,6 +3,7 @@ * Copyright (c) 2015, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -139,6 +140,77 @@ int get_temp_common(struct tsens_sensor *s, int *temp) return 0; } +#ifdef CONFIG_DEBUG_FS +static int dbg_sensors_show(struct seq_file *s, void *data) +{ + struct platform_device *pdev = s->private; + struct tsens_priv *priv = platform_get_drvdata(pdev); + int i; + + seq_printf(s, "max: %2d\nnum: %2d\n\n", + priv->feat->max_sensors, priv->num_sensors); + + seq_puts(s, " id slope offset\n--------------------------\n"); + for (i = 0; i < priv->num_sensors; i++) { + seq_printf(s, "%8d %8d %8d\n", priv->sensor[i].hw_id, + priv->sensor[i].slope, priv->sensor[i].offset); + } + + return 0; +} + +static int dbg_version_show(struct seq_file *s, void *data) +{ + struct platform_device *pdev = s->private; + struct tsens_priv *priv = platform_get_drvdata(pdev); + u32 maj_ver, min_ver, step_ver; + int ret; + + if (tsens_ver(priv) > VER_0_1) { + ret = regmap_field_read(priv->rf[VER_MAJOR], &maj_ver); + if (ret) + return ret; + ret = regmap_field_read(priv->rf[VER_MINOR], &min_ver); + if (ret) + return ret; + ret = regmap_field_read(priv->rf[VER_STEP], &step_ver); + if (ret) + return ret; + seq_printf(s, "%d.%d.%d\n", maj_ver, min_ver, step_ver); + } else { + seq_puts(s, "0.1.0\n"); + } + + return 0; +} + +DEFINE_SHOW_ATTRIBUTE(dbg_version); +DEFINE_SHOW_ATTRIBUTE(dbg_sensors); + +static void tsens_debug_init(struct platform_device *pdev) +{ + struct tsens_priv *priv = platform_get_drvdata(pdev); + struct dentry *root, *file; + + root = debugfs_lookup("tsens", NULL); + if (!root) + priv->debug_root = debugfs_create_dir("tsens", NULL); + else + priv->debug_root = root; + + file = debugfs_lookup("version", priv->debug_root); + if (!file) + debugfs_create_file("version", 0444, priv->debug_root, + pdev, &dbg_version_fops); + + /* A directory for each instance of the TSENS IP */ + priv->debug = debugfs_create_dir(dev_name(&pdev->dev), priv->debug_root); + debugfs_create_file("sensors", 0444, priv->debug, pdev, &dbg_sensors_fops); +} +#else +static inline void tsens_debug_init(struct platform_device *pdev) {} +#endif + static const struct regmap_config tsens_config = { .name = "tm", .reg_bits = 32, @@ -199,6 +271,15 @@ int __init init_common(struct tsens_priv *priv) goto err_put_device; } + if (tsens_ver(priv) > VER_0_1) { + for (i = VER_MAJOR; i <= VER_STEP; i++) { + priv->rf[i] = devm_regmap_field_alloc(dev, priv->srot_map, + priv->fields[i]); + if (IS_ERR(priv->rf[i])) + return PTR_ERR(priv->rf[i]); + } + } + priv->rf[TSENS_EN] = devm_regmap_field_alloc(dev, priv->srot_map, priv->fields[TSENS_EN]); if (IS_ERR(priv->rf[TSENS_EN])) { @@ -238,6 +319,8 @@ int __init init_common(struct tsens_priv *priv) } } + tsens_debug_init(op); + return 0; err_put_device: diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 06c6bbd69a1a..772aa76b50e1 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -3,6 +3,7 @@ * Copyright (c) 2015, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -176,6 +177,7 @@ static int tsens_remove(struct platform_device *pdev) { struct tsens_priv *priv = platform_get_drvdata(pdev); + debugfs_remove_recursive(priv->debug_root); if (priv->ops->disable) priv->ops->disable(priv); diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 84e5447c5686..00899c17e848 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -293,6 +293,8 @@ struct tsens_context { * @feat: features of the IP * @fields: bitfield locations * @ops: pointer to list of callbacks supported by this device + * @debug_root: pointer to debugfs dentry for all tsens + * @debug: pointer to debugfs dentry for tsens controller * @sensor: list of sensors attached to this device */ struct tsens_priv { @@ -306,6 +308,10 @@ struct tsens_priv { const struct tsens_features *feat; const struct reg_field *fields; const struct tsens_ops *ops; + + struct dentry *debug_root; + struct dentry *debug; + struct tsens_sensor sensor[0]; }; From patchwork Wed Oct 16 07:34:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11192547 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3230617E6 for ; Wed, 16 Oct 2019 07:34:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1434321848 for ; Wed, 16 Oct 2019 07:34:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="nHQTggvo" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733122AbfJPHem (ORCPT ); Wed, 16 Oct 2019 03:34:42 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:42381 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732835AbfJPHel (ORCPT ); Wed, 16 Oct 2019 03:34:41 -0400 Received: by mail-pf1-f195.google.com with SMTP id q12so14153008pff.9 for ; Wed, 16 Oct 2019 00:34:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=N1sFZqwPmR4rpLnTH9EOl8Ec1vu8lx2vJgOvXRwWkdo=; b=nHQTggvoUfAdmuLIISJfzQD+E5MdYiRMIJMZhsaRyVJooc3Na6gQvHL8n7SYjjZ6wr HacXvujAglqyTWjGUDxGzUEeDyCh6z7o+6VceXISis/Ik5gJ5jn6r1FnZiGxjfI+X603 i/Fgm6YM1XcAl7XVQ0QbisND0p7J4xB0MZTTgkhwH2q4pploc79rciwHb8pTFgspqMac q89VeCtNrikU1tlUyyXDFXK/1AA6wQRfjr51H8oVtfUJ9WLHvB+8+v8pPucUf3iNjohO V5QI5nL/N58L01MA7oWhRVM3rLTH0I23adq8XWtwe6hBqX/7iwPy3xFTtSVUq9t1qL6W shHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=N1sFZqwPmR4rpLnTH9EOl8Ec1vu8lx2vJgOvXRwWkdo=; b=OQGZ1jw1fSRmxE/h9RxhUeekqrwwtFaj8DKQWyeZ9V68gSB7dU3P3kw9fQNcsG5Vks Z/XZuPxsaXVfufXWXOSs6gHTFiyoXEUtitXg6xx8+UzcjWMz+3rGXKDH5KpujLofG77O c8/lMt9oqRp9kYW3XRPJIL9jMTm/dqT4ljhCKP245/n4UvD3tEQYK9tZteJ/LnScs2NX c5r6nnfS+F2G0xmQYkVk7u05wCsDqJnvDlRrM+bYCbGWhGCUkqBfocq6g+UKC9T5TPcK 8sDakCQ+C3BV8wlncMPxGgizFuYRuP58WlzmUQrQI9jUeW4yZ4F+ee7JP+jcU2YXdrkL ATGQ== X-Gm-Message-State: APjAAAWqN0NQFyznaifvtAy8pYHdrr4qIryaxA0ritziDoYKqAFIzwMZ CEbJasZZARbaNlLYzqOTgeIrZg== X-Google-Smtp-Source: APXvYqzbI7MOcYzohhn5F8MgUPZtpPBx+xG2u+Ec32GKe2sHF+YG5Eu3VXng0EV25WKSSG9R8SGBDQ== X-Received: by 2002:a17:90a:ac06:: with SMTP id o6mr3233009pjq.133.1571211281067; Wed, 16 Oct 2019 00:34:41 -0700 (PDT) Received: from localhost ([49.248.175.127]) by smtp.gmail.com with ESMTPSA id p190sm29052416pfb.160.2019.10.16.00.34.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2019 00:34:40 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: devicetree@vger.kernel.org Subject: [PATCH 05/15] arm: dts: msm8974: thermal: Add thermal zones for each sensor Date: Wed, 16 Oct 2019 13:04:04 +0530 Message-Id: <72cc755c16888976edea555f1df60a299daa8a1e.1571210269.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org msm8974 has 11 sensors connected to a single TSENS IP. Define a thermal zone for each of those sensors to expose the temperature of each zone. Signed-off-by: Amit Kucheria Tested-by: Brian Masney Reviewed-by: Stephen Boyd --- arch/arm/boot/dts/qcom-msm8974.dtsi | 90 +++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 369e58f64145..33c534370fd5 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -217,6 +217,96 @@ }; }; }; + + q6-dsp-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 1>; + + trips { + q6_dsp_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + modemtx-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 2>; + + trips { + modemtx_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 3>; + + trips { + video_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 4>; + + trips { + wlan_alert0: trip-point0 { + temperature = <105000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + gpu-thermal-top { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 9>; + + trips { + gpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + gpu-thermal-bottom { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 10>; + + trips { + gpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; }; cpu-pmu { From patchwork Wed Oct 16 07:34:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11192549 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5AAE418B8 for ; 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Wed, 16 Oct 2019 00:34:44 -0700 (PDT) Received: from localhost ([49.248.175.127]) by smtp.gmail.com with ESMTPSA id bx18sm1468650pjb.26.2019.10.16.00.34.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2019 00:34:44 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: devicetree@vger.kernel.org Subject: [PATCH 06/15] arm64: dts: msm8916: thermal: Fixup HW ids for cpu sensors Date: Wed, 16 Oct 2019 13:04:05 +0530 Message-Id: <1726fdbf7cf7200ac5dc2a4c811aaee7edc47fd5.1571210269.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org msm8916 uses sensors 0, 1, 2, 4 and 5. Sensor 3 is NOT used. Fixup the device tree so that the correct sensor ID is used and as a result we can actually check the temperature for the cpu2_3 sensor. Signed-off-by: Amit Kucheria Reviewed-by: Daniel Lezcano Reviewed-by: Stephen Boyd --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 5ea9fb8f2f87..8686e101905c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -179,7 +179,7 @@ polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&tsens 4>; + thermal-sensors = <&tsens 5>; trips { cpu0_1_alert0: trip-point@0 { @@ -209,7 +209,7 @@ polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&tsens 3>; + thermal-sensors = <&tsens 4>; trips { cpu2_3_alert0: trip-point@0 { From patchwork Wed Oct 16 07:34:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11192559 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B617F14ED for ; Wed, 16 Oct 2019 07:34:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8634321928 for ; Wed, 16 Oct 2019 07:34:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="FZ1QcHMU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389343AbfJPHev (ORCPT ); Wed, 16 Oct 2019 03:34:51 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:33176 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389289AbfJPHev (ORCPT ); Wed, 16 Oct 2019 03:34:51 -0400 Received: by mail-pf1-f196.google.com with SMTP id q10so14173387pfl.0 for ; Wed, 16 Oct 2019 00:34:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=o1n3hiXAD5eewTTz2SUMbD7SrZji7TFMiwE3m9ZwcRg=; b=FZ1QcHMUsgYQzcEwY6lCVBW3Y7LVGnLAJLnaPCYXUZVTjGTBJ166W53Gwlc9IC0q8a 0cqQG2VYbTU7v7Sw6j/binXdgZG8lhZe6L8L3xJ3B6Xu66ts+ZgqT9vaezwGXJFX9cMn W9VAhXb4oFIyvF5dVxXDz9ijszAKlzpM+yeUZjS0SayGBl2tjW8PHNFPXcZsp9vcTTBK RGvACTEblgF50GJzwZJrP+amvXGMW5wtAEM1CLr5eSMDw+YKZJmYYqx6FSgAGLb5ayls MxJ+u+Nvct+go3fPqkrS+Sdb5q8Ns9jvH/WvfmeA973owSYC4iC8Q6ar87+FfLMHmAiJ pf7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=o1n3hiXAD5eewTTz2SUMbD7SrZji7TFMiwE3m9ZwcRg=; b=ca/W9F+kUHsjC4LaBKWVD04egGqmm8Cj9FhfHjC6uC1bKnGKnHN/xqSXh19WVQKFoG Z/yrgpRw9bWLUVpoVTz2zM4nuxB47bOl0cpeh96gxLZxySoVOgHJXlWP4scIr8UzI5J5 BC8zquOkxlqzisTm/z6Nn6T80kfS9eY4PfyoNRUiZ937EyQpy2p95ivAnJBbiNMtNL6/ DEx1Vby+8SZvfsS/pXlqgiRVEUWvoIk8cKww3WCfUMBP/UEatX3YTFI8ZHONi/vfRgcy oecsMgwI7zFFddoCnFsRe2aG5n+jNIEB/QJZUpa+aOv5V6IDo9n9DTNdco6/p5VnIYcH HAPw== X-Gm-Message-State: APjAAAWJT0kv/1TW1Iq6DSen2KV4Elut4mX3CTWAi5bwBCII/r8wnSLO xxLR17mjg+I8ZC718lj/ZCvymg== X-Google-Smtp-Source: APXvYqydsWv5p6uNzEe8YXtgVCtHJwMC0IymouGWbnmVJHJJMvh0oLF72Gp5XfOGVyE48z+XWa2M2Q== X-Received: by 2002:a17:90a:d141:: with SMTP id t1mr3186556pjw.103.1571211288614; Wed, 16 Oct 2019 00:34:48 -0700 (PDT) Received: from localhost ([49.248.175.127]) by smtp.gmail.com with ESMTPSA id t3sm1787408pje.7.2019.10.16.00.34.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2019 00:34:48 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 07/15] dt-bindings: thermal: tsens: Convert over to a yaml schema Date: Wed, 16 Oct 2019 13:04:06 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Older IP only supports the 'uplow' interrupt, but newer IP supports 'uplow' and 'critical' interrupts. Document interrupt support in the tsens driver by converting over to a YAML schema. Suggested-by: Stephen Boyd Signed-off-by: Amit Kucheria Reviewed-by: Rob Herring --- .../bindings/thermal/qcom-tsens.txt | 55 ------ .../bindings/thermal/qcom-tsens.yaml | 168 ++++++++++++++++++ MAINTAINERS | 1 + 3 files changed, 169 insertions(+), 55 deletions(-) delete mode 100644 Documentation/devicetree/bindings/thermal/qcom-tsens.txt create mode 100644 Documentation/devicetree/bindings/thermal/qcom-tsens.yaml diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt deleted file mode 100644 index 673cc1831ee9..000000000000 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt +++ /dev/null @@ -1,55 +0,0 @@ -* QCOM SoC Temperature Sensor (TSENS) - -Required properties: -- compatible: - Must be one of the following: - - "qcom,msm8916-tsens" (MSM8916) - - "qcom,msm8974-tsens" (MSM8974) - - "qcom,msm8996-tsens" (MSM8996) - - "qcom,qcs404-tsens", "qcom,tsens-v1" (QCS404) - - "qcom,msm8998-tsens", "qcom,tsens-v2" (MSM8998) - - "qcom,sdm845-tsens", "qcom,tsens-v2" (SDM845) - The generic "qcom,tsens-v2" property must be used as a fallback for any SoC - with version 2 of the TSENS IP. MSM8996 is the only exception because the - generic property did not exist when support was added. - Similarly, the generic "qcom,tsens-v1" property must be used as a fallback for - any SoC with version 1 of the TSENS IP. - -- reg: Address range of the thermal registers. - New platforms containing v2.x.y of the TSENS IP must specify the SROT and TM - register spaces separately, with order being TM before SROT. - See Example 2, below. - -- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description. -- #qcom,sensors: Number of sensors in tsens block -- Refer to Documentation/devicetree/bindings/nvmem/nvmem.txt to know how to specify -nvmem cells - -Example 1 (legacy support before a fallback tsens-v2 property was introduced): -tsens: thermal-sensor@900000 { - compatible = "qcom,msm8916-tsens"; - reg = <0x4a8000 0x2000>; - nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; - nvmem-cell-names = "caldata", "calsel"; - #thermal-sensor-cells = <1>; - }; - -Example 2 (for any platform containing v2 of the TSENS IP): -tsens0: thermal-sensor@c263000 { - compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; - reg = <0xc263000 0x1ff>, /* TM */ - <0xc222000 0x1ff>; /* SROT */ - #qcom,sensors = <13>; - #thermal-sensor-cells = <1>; - }; - -Example 3 (for any platform containing v1 of the TSENS IP): -tsens: thermal-sensor@4a9000 { - compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; - reg = <0x004a9000 0x1000>, /* TM */ - <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>; - nvmem-cell-names = "calib"; - #qcom,sensors = <10>; - #thermal-sensor-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml new file mode 100644 index 000000000000..23afc7bf5a44 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -0,0 +1,168 @@ +# SPDX-License-Identifier: (GPL-2.0 OR MIT) +# Copyright 2019 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QCOM SoC Temperature Sensor (TSENS) + +maintainers: + - Amit Kucheria + +description: | + QCOM SoCs have TSENS IP to allow temperature measurement. There are currently + three distinct major versions of the IP that is supported by a single driver. + The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures + everything before v1 when there was no versioning information. + +properties: + compatible: + oneOf: + - description: v0.1 of TSENS + items: + - enum: + - qcom,msm8916-tsens + - qcom,msm8974-tsens + - const: qcom,tsens-v0_1 + + - description: v1 of TSENS + items: + - enum: + - qcom,qcs404-tsens + - const: qcom,tsens-v1 + + - description: v2 of TSENS + items: + - enum: + - qcom,msm8996-tsens + - qcom,msm8998-tsens + - qcom,sdm845-tsens + - const: qcom,tsens-v2 + + reg: + maxItems: 2 + items: + - description: TM registers + - description: SROT registers + + nvmem-cells: + minItems: 1 + maxItems: 2 + description: + Reference to an nvmem node for the calibration data + + nvmem-cells-names: + minItems: 1 + maxItems: 2 + items: + - enum: + - caldata + - calsel + + "#qcom,sensors": + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 1 + - maximum: 16 + description: + Number of sensors enabled on this platform + + "#thermal-sensor-cells": + const: 1 + description: + Number of cells required to uniquely identify the thermal sensors. Since + we have multiple sensors this is set to 1 + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8916-tsens + - qcom,msm8974-tsens + - qcom,qcs404-tsens + - qcom,tsens-v0_1 + - qcom,tsens-v1 + then: + properties: + interrupts: + items: + - description: Combined interrupt if upper or lower threshold crossed + interrupt-names: + items: + - const: uplow + + else: + properties: + interrupts: + items: + - description: Combined interrupt if upper or lower threshold crossed + - description: Interrupt if critical threshold crossed + interrupt-names: + items: + - const: uplow + - const: critical + +required: + - compatible + - reg + - "#qcom,sensors" + - interrupts + - interrupt-names + - "#thermal-sensor-cells" + +examples: + - | + #include + // Example 1 (legacy: for pre v1 IP): + tsens1: thermal-sensor@900000 { + compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ + + nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; + nvmem-cell-names = "caldata", "calsel"; + + interrupts = ; + interrupt-names = "uplow"; + + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; + + - | + #include + // Example 2 (for any platform containing v1 of the TSENS IP): + tsens2: thermal-sensor@4a9000 { + compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + + nvmem-cells = <&tsens_caldata>; + nvmem-cell-names = "calib"; + + interrupts = ; + interrupt-names = "uplow"; + + #qcom,sensors = <10>; + #thermal-sensor-cells = <1>; + }; + + - | + #include + // Example 3 (for any platform containing v2 of the TSENS IP): + tsens3: thermal-sensor@c263000 { + compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; + reg = <0xc263000 0x1ff>, + <0xc222000 0x1ff>; + + interrupts = , + ; + interrupt-names = "uplow", "critical"; + + #qcom,sensors = <13>; + #thermal-sensor-cells = <1>; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index a69e6db80c79..c4df814b87b0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13513,6 +13513,7 @@ L: linux-pm@vger.kernel.org L: linux-arm-msm@vger.kernel.org S: Maintained F: drivers/thermal/qcom/ +F: Documentation/devicetree/bindings/thermal/qcom-tsens.yaml QUALCOMM VENUS VIDEO ACCELERATOR DRIVER M: Stanimir Varbanov From patchwork Wed Oct 16 07:34:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11192557 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1A0A414ED for ; Wed, 16 Oct 2019 07:34:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EF45920873 for ; Wed, 16 Oct 2019 07:34:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="lODSxo7Z" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388971AbfJPHex (ORCPT ); Wed, 16 Oct 2019 03:34:53 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:44542 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389616AbfJPHex (ORCPT ); Wed, 16 Oct 2019 03:34:53 -0400 Received: by mail-pg1-f193.google.com with SMTP id e10so9766047pgd.11 for ; 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Wed, 16 Oct 2019 00:34:52 -0700 (PDT) Received: from localhost ([49.248.175.127]) by smtp.gmail.com with ESMTPSA id s3sm1536452pjq.32.2019.10.16.00.34.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2019 00:34:51 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: devicetree@vger.kernel.org Subject: [PATCH 08/15] arm64: dts: sdm845: thermal: Add interrupt support Date: Wed, 16 Oct 2019 13:04:07 +0530 Message-Id: <5a96df48e546576f90081bbde218e7cff88ae8ce.1571210269.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Register upper-lower interrupts for each of the two tsens controllers. Signed-off-by: Amit Kucheria Reviewed-by: Stephen Boyd --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index f406a4340b05..0990d5761860 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2950,6 +2950,8 @@ reg = <0 0x0c263000 0 0x1ff>, /* TM */ <0 0x0c222000 0 0x1ff>; /* SROT */ #qcom,sensors = <13>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; @@ -2958,6 +2960,8 @@ reg = <0 0x0c265000 0 0x1ff>, /* TM */ <0 0x0c223000 0 0x1ff>; /* SROT */ #qcom,sensors = <8>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; From patchwork Wed Oct 16 07:34:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11192579 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5E477912 for ; Wed, 16 Oct 2019 07:35:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3F13921925 for ; Wed, 16 Oct 2019 07:35:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Xx6xD6kV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389803AbfJPHe5 (ORCPT ); Wed, 16 Oct 2019 03:34:57 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:39901 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388794AbfJPHe4 (ORCPT ); Wed, 16 Oct 2019 03:34:56 -0400 Received: by mail-pg1-f195.google.com with SMTP id p12so4424241pgn.6 for ; Wed, 16 Oct 2019 00:34:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=4K812X2lC+GYM/4odmaRwgr1rxs2vpAuXCpq25weRAs=; b=Xx6xD6kVfeR3/JFqZsiOJQRbB4MJyUPL5aomJ+HRatBXvwNIGYCZjEjWCS80qXfNha hNqIwJsDPgQdeKOb32Dg77GT22ekUALjj76wpjLT9ABAIEL+/gUSPy+GRMmPvjkpfTA3 n5D9wn7VRoQxvbYu6jbl2nIIch1FgwueJwQuxGi29QBC0pam23Lhv0dJV8hG2bfZWCDp iBRqu6DCgCVSaCnonaxu/YYl542PtlaI3LO1O7TkjAmbsY6JEPgi9eECLZy6DjB4gW8U DDexwG4JUORqW+tF2aTQr7okJCJFMmVirrMncKV5ty2XEIOqeIe1K7c0yymYkDnLTHME XxbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=4K812X2lC+GYM/4odmaRwgr1rxs2vpAuXCpq25weRAs=; b=etfTcpqMYzi5FiTBbVI77/PR9cMnJLvZBJu+GAaO2IMrxq+5fEuWYIQPSzG4QbxZsG C2m+F1lu68Q847ZdCtZmL9rQPZQkeLRH6Kp788HkwgdtWVRZPuRTlXiGQwqIYjIYbr5E ZF0gnfHrBXtGdoZtajw1ofdN/hBxzsmS8dWYoloOExyPREqhsbcH4tQDrN6rEFJOtGwz X1OKFHgitV1eDmPdb6Q2llDh4Z08nl9ZAQoTTEcMDp7wNhwoxEVdqz/Z7Wj+MHpecDyQ 7067ouV1K9xSTW+btijOqrD+SpKtAiZ5AX27AQrx5E6t2yXr793m5Qe5FtX7TCjU+n38 3pBQ== X-Gm-Message-State: APjAAAVAV7I9yfNJVQqFUYCFruGPwK4PBeLu6fbiXwAJ0YIadYJYjJvf azhhn/VOc0NvtWPzjnb7ZQ8mzA== X-Google-Smtp-Source: APXvYqwsNRx3WNxoT4VeviLzs1ILoUNER9h+t26mhtuQLy5POR2lX08st0WtdhT1VWFsmu6NgDru2A== X-Received: by 2002:a63:b907:: with SMTP id z7mr5209236pge.142.1571211295665; Wed, 16 Oct 2019 00:34:55 -0700 (PDT) Received: from localhost ([49.248.175.127]) by smtp.gmail.com with ESMTPSA id h70sm22045544pgc.48.2019.10.16.00.34.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2019 00:34:55 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: devicetree@vger.kernel.org Subject: [PATCH 09/15] arm64: dts: msm8996: thermal: Add interrupt support Date: Wed, 16 Oct 2019 13:04:08 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Register upper-lower interrupts for each of the two tsens controllers. Signed-off-by: Amit Kucheria --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 87f4d9c1b0d4..4ca2e7b44559 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -591,6 +591,8 @@ reg = <0x4a9000 0x1000>, /* TM */ <0x4a8000 0x1000>; /* SROT */ #qcom,sensors = <13>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; @@ -599,6 +601,8 @@ reg = <0x4ad000 0x1000>, /* TM */ <0x4ac000 0x1000>; /* SROT */ #qcom,sensors = <8>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; From patchwork Wed Oct 16 07:34:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11192577 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BA67714ED for ; Wed, 16 Oct 2019 07:35:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9B30B21925 for ; Wed, 16 Oct 2019 07:35:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="OKvnywfa" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389929AbfJPHfE (ORCPT ); Wed, 16 Oct 2019 03:35:04 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:39697 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389853AbfJPHfA (ORCPT ); Wed, 16 Oct 2019 03:35:00 -0400 Received: by mail-pf1-f193.google.com with SMTP id v4so14157956pff.6 for ; Wed, 16 Oct 2019 00:34:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=srw60QlGCW1mVn48ORh0gXVEibw1bp8x1qlk8iY4/Hk=; b=OKvnywfaYaF1zd+2IMbDb7Neej+sPGjeqFgET8fbA/ZZQ2QOQI8KBRhv9/IIlgN+j/ vESY/46MDh1HSo9p73Y5++ls3PAyGTedjunvL2yZNci+pSFgojTn5W+vO2BVR6w6kat4 urhL3YnWABlyDdhvYOCOYz2QD7M3dPNRegk2dg/sPbfPOP1tVaXphWEM9G9tqxYt8HH2 4uXQ5bHZwnsyhDcXTFkBfxHPOHdBI9V+3gBevsrsBgPZ8wSbc+R3cWdLx9feGdqKvAUe wf0HqjHbRpaaAb8ArSFbyLV1Bq9q1g6JQIIc7QNfAyjgeGUE89fi4b9X7RpHrxqeywG2 Sb7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=srw60QlGCW1mVn48ORh0gXVEibw1bp8x1qlk8iY4/Hk=; b=Ma2kNH3e8fqI9L7RGuJfGYwWUOScoYDZtoAeYC0sK3z1WuQsDe2kOAK8ME0VbF1a/q 5dCxO6S1Bg7UPG9+UU80weiiBOfBncGw6mOoy77LsDH4N0QtqPatWoYRXJnk3wz4EgD4 zzhcfq799tYgGP89H6ytmuquQV4lo9RpTmMq61Rgifpz4VY75tuXyxiBP7/8oLTqIxZw xsQX2k8jHns25r3xUaGJcBmLaBXzMI0NrOtivV+g+KlSkpRTdkg2Yerr+zmMPyK90NGc HL1hktS0dANHPhIUrDA/+BKmVESsPzTAeyDuSi0zfXgHBmJEbphYWmjWRjQTs4CQPW/z TJnw== X-Gm-Message-State: APjAAAVUl97lMZVO9KfX1YJFyDB/O7wh8LUCgdwIZU7at6TLu+iiCcJJ AzYEq8Ll0gdFKxehfjITeqD19g== X-Google-Smtp-Source: APXvYqxpyqtZKR6Y2VJgW86MAXucFdZTnIZa80a9Ab2niEAGq6fx62Fhuwh0C+49YNUrmK8MSe9L5A== X-Received: by 2002:a17:90a:a416:: with SMTP id y22mr3324992pjp.74.1571211299384; Wed, 16 Oct 2019 00:34:59 -0700 (PDT) Received: from localhost ([49.248.175.127]) by smtp.gmail.com with ESMTPSA id h8sm24716360pfo.64.2019.10.16.00.34.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2019 00:34:58 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: devicetree@vger.kernel.org Subject: [PATCH 10/15] arm64: dts: msm8998: thermal: Add interrupt support Date: Wed, 16 Oct 2019 13:04:09 +0530 Message-Id: <2735b57bb1e9477926bfef6f6b8ff84b926f5a1b.1571210269.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Register upper-lower interrupts for each of the two tsens controllers. Signed-off-by: Amit Kucheria --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index c6f81431983e..489d631a9610 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -816,8 +816,9 @@ compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; reg = <0x010ab000 0x1000>, /* TM */ <0x010aa000 0x1000>; /* SROT */ - #qcom,sensors = <14>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; @@ -825,8 +826,9 @@ compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; reg = <0x010ae000 0x1000>, /* TM */ <0x010ad000 0x1000>; /* SROT */ - #qcom,sensors = <8>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; From patchwork Wed Oct 16 07:34:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11192563 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3B82D912 for ; Wed, 16 Oct 2019 07:35:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1C7932168B for ; Wed, 16 Oct 2019 07:35:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="eFrfxwuX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389903AbfJPHfE (ORCPT ); Wed, 16 Oct 2019 03:35:04 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:40156 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389892AbfJPHfD (ORCPT ); Wed, 16 Oct 2019 03:35:03 -0400 Received: by mail-pg1-f193.google.com with SMTP id e13so5552340pga.7 for ; Wed, 16 Oct 2019 00:35:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=aMdrJzILxuSr5g6YT+uoh2+W6L6BuGxRIbKk0lFLJqE=; b=eFrfxwuX98m0mVPWQgy0cowYXczi0HbPFwOzG0WXPWDMKhxZNa2L/BnbDyE8HZFs6p 1d3qJ+Oyockzuq8VqIuYGZPTvcKemsVj3el1JZ9vK/pt0K8Twj4ysuhMHIBDJ8ZYSOk/ L+eWvz006UruJo4tnbK0GyQKVPmSD/7O+EyqoKrifnBP+uO0sT7fHmCs0C2+fEVqyu/s 5lloeBdzKA46Vja3aVGdGAnoTe7EEtvl+7AcP2yGDSXUxOF+uGlrZrCRawPY53gD7G0O a9K7iXwWZj6osIOEXgS8vMp8NJdpBD6G1hA9BiOoDDyqeaEPDQko0FJLQbkD1QBe46jz HHrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=aMdrJzILxuSr5g6YT+uoh2+W6L6BuGxRIbKk0lFLJqE=; b=FAzpGoGvWp1/JPc24qdOZrFx00mokZTDjELzxQr8kzGPAJylTMhhsQHMTtlf6UIDwa WQs2bC554GxEcRFiVau5z78XCy5lcDZrqghBz4//xzBCbRWad5vrhgt7BKuV8i+XjJuF mJYZLAK5nMPlhrrmpvtoBflZcqBjgn4eSJyLiYvnoXMrAxR+gNIMgsMqrdysfcf2EbeV Siu+Nn/ej3g/a375NEZiMdcAsgN2B3N0WRTGDZvG8fnHALMb27+tbgJaVT/rD/EMAuBD uSm+Nx2nXNBbDSWS0nDU2ye5Z8FAtWWklCVajznJoF7HU0NCScTbrEMmPwIkqvhEW9su 4AGg== X-Gm-Message-State: APjAAAWXdYRbzQoc0jdZoqMp+ubyUvHRd15qnlgGffjMi8qJyWzd78Yb afoiaAwHckLWsH9HWQOxob8/Dg== X-Google-Smtp-Source: APXvYqxVG9NAkBqkoExE8mqtLpk30e1uae5egg5SfnPaBqxGtmxrby6ezxyMeLYuZDb9VA2YQtT39Q== X-Received: by 2002:a63:5520:: with SMTP id j32mr2064328pgb.162.1571211302908; Wed, 16 Oct 2019 00:35:02 -0700 (PDT) Received: from localhost ([49.248.175.127]) by smtp.gmail.com with ESMTPSA id t13sm21590605pfh.12.2019.10.16.00.35.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2019 00:35:02 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: devicetree@vger.kernel.org Subject: [PATCH 11/15] arm64: dts: qcs404: thermal: Add interrupt support Date: Wed, 16 Oct 2019 13:04:10 +0530 Message-Id: <63d6b0b8bba0d217c2f7bb4240c587ead933b6be.1571210269.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Register upper-lower interrupt for the tsens controller. Signed-off-by: Amit Kucheria --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index a97eeb4569c0..b6a4e6073936 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -290,6 +290,8 @@ nvmem-cells = <&tsens_caldata>; nvmem-cell-names = "calib"; #qcom,sensors = <10>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; From patchwork Wed Oct 16 07:34:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11192575 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6EBF514ED for ; Wed, 16 Oct 2019 07:35:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4ECAB218DE for ; Wed, 16 Oct 2019 07:35:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="gc/KMCmI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389952AbfJPHfZ (ORCPT ); Wed, 16 Oct 2019 03:35:25 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:42506 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390353AbfJPHfH (ORCPT ); Wed, 16 Oct 2019 03:35:07 -0400 Received: by mail-pg1-f195.google.com with SMTP id f14so8643566pgi.9 for ; Wed, 16 Oct 2019 00:35:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=K+JloZswXmm4BpvcNOHfxY9LNAmaq3HM2wD0uVSFvPc=; b=gc/KMCmIeHHhA5CTiQuXhuXCGs8zdCkC0+uXOGsRaewyOVs3PwC8r5E2WjzwjXxZnR iFmRDhGszAMo5AnU1BhzDVdlXBedkCtZUjiZzJhGWuXWgjIhBT5Q4145dmaZpuDPs7pX 6rx3SuzudupipdVWV2LQeuuFOi7vO+/PhqV0cCfB9O6vkt3I5D+i60vv8JGSRqpZWemb dVWEMwyqWldf4vE/7AvgMpTzZPro4CMXdq42i7ZYfKSyx7tYT/a6Ef0uulvNv020OAPD jKd7sqRbpLTGIlgm8auFOmqUDk+eBROQvmyH/xW5XBX1Wt1GtEpVvfkLPuZvadrcKz6T e0Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=K+JloZswXmm4BpvcNOHfxY9LNAmaq3HM2wD0uVSFvPc=; b=jOsh3JebzwZQA3b5GX2o1K1bTbgoegQrykgjLgjXFwDc6pN7eitxfYO5FZoknYY8zP 8TDkE2tgLRL2ip2A1mOPAyD69JuBH1s84iPiI4eZ/NITuc81/t0sPXqZI+aHhZl+kgm/ 5dVZ1Yt10nw6zq7fSppuL/xFUWIygRSUN9twWTOouBPDsbMSArqywirLWQvItb0A0Afj cKEmgS4VfXzJBShvkt82Dd8HJh+vCCy/dhjZV98w8F3J97ihsJMGXpHHYyGybP6nQ5Y6 khHWlhNxYS22YxZvgA2y4n3xoC/AmzZ3TsTvBKhi7CuhUCl1W80K1IN/CIIuwoKcNaeH Jpjw== X-Gm-Message-State: APjAAAUq76ViXvf9uqKBzUs/bhAvdAAm+XLw3wiEzF+TL0l8dNMQGa1H bxEdGSfRPUO2SfgQeB9epKJAyQ== X-Google-Smtp-Source: APXvYqyM69gXN9ucY0u0Z331l43PMGaxd5Nz0wHcYtRF/zyAnePozLUY3rayNt3oewSq4CFpEwzWrg== X-Received: by 2002:a65:5586:: with SMTP id j6mr614871pgs.252.1571211306505; Wed, 16 Oct 2019 00:35:06 -0700 (PDT) Received: from localhost ([49.248.175.127]) by smtp.gmail.com with ESMTPSA id c4sm4194968pgd.3.2019.10.16.00.35.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2019 00:35:05 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: devicetree@vger.kernel.org Subject: [PATCH 12/15] arm: dts: msm8974: thermal: Add interrupt support Date: Wed, 16 Oct 2019 13:04:11 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Register upper-lower interrupt for the tsens controller. Signed-off-by: Amit Kucheria Tested-by: Brian Masney --- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 33c534370fd5..c1a3a7d7161c 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -531,6 +531,8 @@ nvmem-cells = <&tsens_calib>, <&tsens_backup>; nvmem-cell-names = "calib", "calib_backup"; #qcom,sensors = <11>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; From patchwork Wed Oct 16 07:34:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11192573 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4E53F912 for ; Wed, 16 Oct 2019 07:35:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2F98220854 for ; Wed, 16 Oct 2019 07:35:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="X4D5Ac/v" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390688AbfJPHfL (ORCPT ); Wed, 16 Oct 2019 03:35:11 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:33878 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390374AbfJPHfL (ORCPT ); Wed, 16 Oct 2019 03:35:11 -0400 Received: by mail-pg1-f196.google.com with SMTP id k20so6408532pgi.1 for ; Wed, 16 Oct 2019 00:35:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=03jpeb+1aJx4bxpcdPiavfJJhVJ5WBvL1EOxBoz3J+I=; b=X4D5Ac/vX8qbhhnG/SRIM90B0+FmV6AycTSj/JtrullgPcisRI70iJjTkjiIMfyi/H QhssR6y42idqaSNfRGO5AVREd9915qBuIXFx5EV+4gIzMHAQr/p1a8REtGA9cfSZKsmI PWp5a2RaRyTOA8Ki2AoHQ3/WAxaO3Rg2RGtb1Z1GvMXas458/hA1SSPuRzfojyFyWFL7 td8pqUQrvLIhjkogvgzcfK4BGdZzYFhJsEFJxSn26/snm4bs1h1urgmrwhLPPNyIxmWz ONpJaLJ3eApPbWqGwuOBFv5BOLamb9huJXIkx7cabTmnkVM7sFciLLaBHM7zV6jpwMvN g+ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=03jpeb+1aJx4bxpcdPiavfJJhVJ5WBvL1EOxBoz3J+I=; b=f5okji/imEnCvCBHzZDeAX8sVurMRXIROoPygp5XCkGhHX7P3FXJy8TVhd/vWLP3R+ z+gOol8OzkbVos/w9LhVxrbdw00tUMAiRnEJffkG3R8oUMb0gO4uPjWkjnwf60FREPf4 eJyPPzYFYh+oF4d2GsnR+tlsGT8po/luh8IafxwLolfOx53Ayl/dDeG6RoMOTck5MpXZ uAnguaCM70IYNICiL69le7fJOnPikM8Brq3u40cruRE/I0SJu68V9pOj4H3Koz0BrjMu ypYiQcwGAk+DmuDFA50WBBRKdzBQMXHpAneK0Djjw95ON488MuqrS/LNmFc0bLXXXToE oVuA== X-Gm-Message-State: APjAAAWpdhW5wDCxYdl1InJrIyFCFB5JWUQ2uNeH+YHbVTyXLImErypv K41iZuwY41EqXyRnc7rnTtsZbQ== X-Google-Smtp-Source: APXvYqxLAdFUelj0nGlA72+kn0HnBJlREcJf6ke7gmZg2QchUPKPdi3nc8YGKl4qzUSdSd5kYYWf0Q== X-Received: by 2002:a63:c748:: with SMTP id v8mr43605412pgg.348.1571211310066; Wed, 16 Oct 2019 00:35:10 -0700 (PDT) Received: from localhost ([49.248.175.127]) by smtp.gmail.com with ESMTPSA id z4sm27413149pfn.45.2019.10.16.00.35.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2019 00:35:09 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: devicetree@vger.kernel.org Subject: [PATCH 13/15] arm64: dts: msm8916: thermal: Add interrupt support Date: Wed, 16 Oct 2019 13:04:12 +0530 Message-Id: <88eff964b708c8aff57b24370d2e14389ace09e9.1571210269.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Register upper-lower interrupt for the tsens controller. Signed-off-by: Amit Kucheria --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 8686e101905c..807f86a4535e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -816,6 +816,8 @@ nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; nvmem-cell-names = "calib", "calib_sel"; #qcom,sensors = <5>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; From patchwork Wed Oct 16 07:34:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11192565 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DC20F912 for ; Wed, 16 Oct 2019 07:35:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BCAD621835 for ; Wed, 16 Oct 2019 07:35:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="QmzymGkd" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390811AbfJPHfO (ORCPT ); Wed, 16 Oct 2019 03:35:14 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:46963 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390610AbfJPHfO (ORCPT ); Wed, 16 Oct 2019 03:35:14 -0400 Received: by mail-pf1-f194.google.com with SMTP id q5so14131153pfg.13 for ; Wed, 16 Oct 2019 00:35:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=/kNhWSzT1XF3+/kAR7Dxjp13J1ZI+CyyKCX+EYBQmx8=; b=QmzymGkdzTKuxhlQQbG1q+cOpiRxZSL4bdv7TTVHrcS7uAjgk0NhCFOkhZSDoi0agg dfs2fDlBES/nfc5WbMchIaqgOFuKZZZ5lnP2maSL3pITe59vcfuNo+veBb7BWXWh9MIN elCftBIxAO646pb6sAd0Ej0vLFEYSQITYp6Y1C3BT1toeeScAk8P/zDRxnmDSmdaP4JT SDHTUIwg1v6fpMQH3w4yZ5qhnIESZOLl4EL2Q4xdx0dlu1CDgtHge5LJx29Lta020jge pnkaZ+gNJ1FCG7Dde3tKXqfEqG87y6g1uMl1gNWmZKMty67hlR5rzQjDrGWHmmnaQV/4 QLfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=/kNhWSzT1XF3+/kAR7Dxjp13J1ZI+CyyKCX+EYBQmx8=; b=Y7rzc2V7QL8qI3RDbgw8m4pc22P5fQKAinvSDfoKX1RRiAoeLVk6OqgYEVKdqOV95R 4cyUqroqp3Q9mpWFuSASZztHqD1QXXIbCP1Q5bb27E70+gGMj5ODnTrTjTOL9AobTe0s Dk+pQvglqhgpXHqX+BAL8E1H1651T3iV6+C5IfsCxPq4LR8m2tAtle5j22cxvz9QH3wG LhmDmdCF/cAuP5xNaa/n406+soRf9D7gWFxg5S18ky9jScpgCVc5KaEegpDhUiN3IHVV E6eB7KZvru9l0CBQtOt1rwyakHK7xbPVJUyh7/yY8cPj+CG/NCMnwwkb0Ey47jMKRQGM g9+g== X-Gm-Message-State: APjAAAXAji7fhruhFhFMoM/n4RUOt6hnIS9U0Ybc0nwuwSkKxo/4aJjt nxYhIU8naz8oCJcL/aVfR/MmZA== X-Google-Smtp-Source: APXvYqzW3Yokr508aGfspxAB1bRkDKPRBSHVECG1pH9ihR8mBDtUA5nnuAE4IIQT+9sNJ6KNK6RUCA== X-Received: by 2002:aa7:93de:: with SMTP id y30mr42412010pff.98.1571211313730; Wed, 16 Oct 2019 00:35:13 -0700 (PDT) Received: from localhost ([49.248.175.127]) by smtp.gmail.com with ESMTPSA id v68sm28026272pfv.47.2019.10.16.00.35.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2019 00:35:13 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH 14/15] drivers: thermal: tsens: Create function to return sign-extended temperature Date: Wed, 16 Oct 2019 13:04:13 +0530 Message-Id: <0689917475cf83b7e01f6978504fd37352a5e3ca.1571210269.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hide the details of how to convert values read from TSENS HW to mCelsius behind a function. All versions of the IP can be supported as a result. Signed-off-by: Amit Kucheria Reviewed-by: Stephen Boyd --- drivers/thermal/qcom/tsens-common.c | 49 ++++++++++++++++++++--------- 1 file changed, 35 insertions(+), 14 deletions(-) diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index ea2c46cc6a66..c34a1a26ce29 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -84,13 +84,46 @@ static inline int code_to_degc(u32 adc_code, const struct tsens_sensor *s) return degc; } +/** + * tsens_hw_to_mC - Return sign-extended temperature in mCelsius. + * @s: Pointer to sensor struct + * @field: Index into regmap_field array pointing to temperature data + * + * This function handles temperature returned in ADC code or deciCelsius + * depending on IP version. + * + * Return: Temperature in milliCelsius on success, a negative errno will + * be returned in error cases + */ +static int tsens_hw_to_mC(struct tsens_sensor *s, int field) +{ + struct tsens_priv *priv = s->priv; + u32 resolution; + u32 temp = 0; + int ret; + + resolution = priv->fields[LAST_TEMP_0].msb - + priv->fields[LAST_TEMP_0].lsb; + + ret = regmap_field_read(priv->rf[field], &temp); + if (ret) + return ret; + + /* Convert temperature from ADC code to milliCelsius */ + if (priv->feat->adc) + return code_to_degc(temp, s) * 1000; + + /* deciCelsius -> milliCelsius along with sign extension */ + return sign_extend32(temp, resolution) * 100; +} + int get_temp_tsens_valid(struct tsens_sensor *s, int *temp) { struct tsens_priv *priv = s->priv; int hw_id = s->hw_id; u32 temp_idx = LAST_TEMP_0 + hw_id; u32 valid_idx = VALID_0 + hw_id; - u32 last_temp = 0, valid, mask; + u32 valid; int ret; ret = regmap_field_read(priv->rf[valid_idx], &valid); @@ -108,19 +141,7 @@ int get_temp_tsens_valid(struct tsens_sensor *s, int *temp) } /* Valid bit is set, OK to read the temperature */ - ret = regmap_field_read(priv->rf[temp_idx], &last_temp); - if (ret) - return ret; - - if (priv->feat->adc) { - /* Convert temperature from ADC code to milliCelsius */ - *temp = code_to_degc(last_temp, s) * 1000; - } else { - mask = GENMASK(priv->fields[LAST_TEMP_0].msb, - priv->fields[LAST_TEMP_0].lsb); - /* Convert temperature from deciCelsius to milliCelsius */ - *temp = sign_extend32(last_temp, fls(mask) - 1) * 100; - } + *temp = tsens_hw_to_mC(s, temp_idx); return 0; } From patchwork Wed Oct 16 07:34:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11192569 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F2B0C14ED for ; Wed, 16 Oct 2019 07:35:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B92C420873 for ; Wed, 16 Oct 2019 07:35:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="S6yVuQrT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390863AbfJPHfU (ORCPT ); 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Wed, 16 Oct 2019 00:35:17 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH 15/15] drivers: thermal: tsens: Add interrupt support Date: Wed, 16 Oct 2019 13:04:14 +0530 Message-Id: <74dacd3da32f5f31f9296afe89802140099652c6.1571210269.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Depending on the IP version, TSENS supports upper, lower and critical threshold interrupts. We only add support for upper and lower threshold interrupts for now. TSENSv2 has an irq [status|clear|mask] bit tuple for each sensor while earlier versions only have a single bit per sensor to denote status and clear. These differences are handled transparently by the interrupt handler. At each interrupt, we reprogram the new upper and lower threshold in the .set_trip callback. Signed-off-by: Amit Kucheria Reviewed-by: Stephen Boyd --- drivers/thermal/qcom/tsens-common.c | 377 ++++++++++++++++++++++++++-- drivers/thermal/qcom/tsens-v0_1.c | 11 + drivers/thermal/qcom/tsens-v1.c | 29 +++ drivers/thermal/qcom/tsens-v2.c | 13 + drivers/thermal/qcom/tsens.c | 31 ++- drivers/thermal/qcom/tsens.h | 270 ++++++++++++++++---- 6 files changed, 669 insertions(+), 62 deletions(-) diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index c34a1a26ce29..03bf1b8133ea 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -13,6 +13,31 @@ #include #include "tsens.h" +/** + * struct tsens_irq_data - IRQ status and temperature violations + * @up_viol: upper threshold violated + * @up_thresh: upper threshold temperature value + * @up_irq_mask: mask register for upper threshold irqs + * @up_irq_clear: clear register for uppper threshold irqs + * @low_viol: lower threshold violated + * @low_thresh: lower threshold temperature value + * @low_irq_mask: mask register for lower threshold irqs + * @low_irq_clear: clear register for lower threshold irqs + * + * Structure containing data about temperature threshold settings and + * irq status if they were violated. + */ +struct tsens_irq_data { + u32 up_viol; + int up_thresh; + u32 up_irq_mask; + u32 up_irq_clear; + u32 low_viol; + int low_thresh; + u32 low_irq_mask; + u32 low_irq_clear; +}; + char *qfprom_read(struct device *dev, const char *cname) { struct nvmem_cell *cell; @@ -65,6 +90,14 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *p1, } } +static inline u32 degc_to_code(int degc, const struct tsens_sensor *s) +{ + u64 code = (degc * s->slope + s->offset) / SLOPE_FACTOR; + + pr_debug("%s: raw_code: 0x%llx, degc:%d\n", __func__, code, degc); + return clamp_val(code, THRESHOLD_MIN_ADC_CODE, THRESHOLD_MAX_ADC_CODE); +} + static inline int code_to_degc(u32 adc_code, const struct tsens_sensor *s) { int degc, num, den; @@ -117,6 +150,313 @@ static int tsens_hw_to_mC(struct tsens_sensor *s, int field) return sign_extend32(temp, resolution) * 100; } +/** + * tsens_mC_to_hw - Convert temperature to hardware register value + * @s: Pointer to sensor struct + * @temp: temperature in milliCelsius to be programmed to hardware + * + * This function outputs the value to be written to hardware in ADC code + * or deciCelsius depending on IP version. + * + * Return: ADC code or temperature in deciCelsius. + */ +static int tsens_mC_to_hw(struct tsens_sensor *s, int temp) +{ + struct tsens_priv *priv = s->priv; + + /* milliC to adc code */ + if (priv->feat->adc) + return degc_to_code(temp / 1000, s); + + /* milliC to deciC */ + return temp / 100; +} + +static inline enum tsens_ver tsens_version(struct tsens_priv *priv) +{ + return priv->feat->ver_major; +} + +static void tsens_set_interrupt_v1(struct tsens_priv *priv, u32 hw_id, + enum tsens_irq_type irq_type, bool enable) +{ + u32 index; + + switch (irq_type) { + case UPPER: + index = UP_INT_CLEAR_0 + hw_id; + break; + case LOWER: + index = LOW_INT_CLEAR_0 + hw_id; + break; + } + regmap_field_write(priv->rf[index], enable ? 0 : 1); +} + +static void tsens_set_interrupt_v2(struct tsens_priv *priv, u32 hw_id, + enum tsens_irq_type irq_type, bool enable) +{ + u32 index_mask, index_clear; + + /* + * To enable the interrupt flag for a sensor: + * - clear the mask bit + * To disable the interrupt flag for a sensor: + * - Mask further interrupts for this sensor + * - Write 1 followed by 0 to clear the interrupt + */ + switch (irq_type) { + case UPPER: + index_mask = UP_INT_MASK_0 + hw_id; + index_clear = UP_INT_CLEAR_0 + hw_id; + break; + case LOWER: + index_mask = LOW_INT_MASK_0 + hw_id; + index_clear = LOW_INT_CLEAR_0 + hw_id; + break; + } + + if (enable) { + regmap_field_write(priv->rf[index_mask], 0); + } else { + regmap_field_write(priv->rf[index_mask], 1); + regmap_field_write(priv->rf[index_clear], 1); + regmap_field_write(priv->rf[index_clear], 0); + } +} + +/** + * tsens_set_interrupt - Set state of an interrupt + * @priv: Pointer to tsens controller private data + * @hw_id: Hardware ID aka. sensor number + * @irq_type: irq_type from enum tsens_irq_type + * @enable: false = disable, true = enable + * + * Call IP-specific function to set state of an interrupt + * + * Return: void + */ +static void tsens_set_interrupt(struct tsens_priv *priv, u32 hw_id, + enum tsens_irq_type irq_type, bool enable) +{ + dev_dbg(priv->dev, "[%u] %s: %s -> %s\n", hw_id, __func__, + irq_type ? ((irq_type == 1) ? "UP" : "CRITICAL") : "LOW", + enable ? "en" : "dis"); + if (tsens_version(priv) > VER_1_X) + tsens_set_interrupt_v2(priv, hw_id, irq_type, enable); + else + tsens_set_interrupt_v1(priv, hw_id, irq_type, enable); +} + +/** + * tsens_threshold_violated - Check if a sensor temperature violated a preset threshold + * @priv: Pointer to tsens controller private data + * @hw_id: Hardware ID aka. sensor number + * @d: Pointer to irq state data + * + * Return: 0 if threshold was not violated, 1 if it was violated and negative + * errno in case of errors + */ +static int tsens_threshold_violated(struct tsens_priv *priv, u32 hw_id, + struct tsens_irq_data *d) +{ + int ret; + + ret = regmap_field_read(priv->rf[UPPER_STATUS_0 + hw_id], &d->up_viol); + if (ret) + return ret; + ret = regmap_field_read(priv->rf[LOWER_STATUS_0 + hw_id], &d->low_viol); + if (ret) + return ret; + if (d->up_viol || d->low_viol) + return 1; + + return 0; +} + +static int tsens_read_irq_state(struct tsens_priv *priv, u32 hw_id, + struct tsens_sensor *s, struct tsens_irq_data *d) +{ + int ret; + + ret = regmap_field_read(priv->rf[UP_INT_CLEAR_0 + hw_id], &d->up_irq_clear); + if (ret) + return ret; + ret = regmap_field_read(priv->rf[LOW_INT_CLEAR_0 + hw_id], &d->low_irq_clear); + if (ret) + return ret; + if (tsens_version(priv) > VER_1_X) { + ret = regmap_field_read(priv->rf[UP_INT_MASK_0 + hw_id], &d->up_irq_mask); + if (ret) + return ret; + ret = regmap_field_read(priv->rf[LOW_INT_MASK_0 + hw_id], &d->low_irq_mask); + if (ret) + return ret; + } else { + /* No mask register on older TSENS */ + d->up_irq_mask = 0; + d->low_irq_mask = 0; + } + + d->up_thresh = tsens_hw_to_mC(s, UP_THRESH_0 + hw_id); + d->low_thresh = tsens_hw_to_mC(s, LOW_THRESH_0 + hw_id); + + dev_dbg(priv->dev, "[%u] %s%s: status(%u|%u) | clr(%u|%u) | mask(%u|%u)\n", + hw_id, __func__, (d->up_viol || d->low_viol) ? "(V)" : "", + d->low_viol, d->up_viol, d->low_irq_clear, d->up_irq_clear, + d->low_irq_mask, d->up_irq_mask); + dev_dbg(priv->dev, "[%u] %s%s: thresh: (%d:%d)\n", hw_id, __func__, + (d->up_viol || d->low_viol) ? "(violation)" : "", + d->low_thresh, d->up_thresh); + + return 0; +} + +static inline u32 masked_irq(u32 hw_id, u32 mask, enum tsens_ver ver) +{ + if (ver > VER_1_X) + return mask & (1 << hw_id); + + /* v1, v0.1 don't have a irq mask register */ + return 0; +} + +/** + * tsens_irq_thread - Threaded interrupt handler for uplow interrupts + * @irq: irq number + * @data: tsens controller private data + * + * Check all sensors to find ones that violated their threshold limits. If the + * temperature is still outside the limits, call thermal_zone_device_update() to + * update the thresholds, else re-enable the interrupts. + * + * The level-triggered interrupt might deassert if the temperature returned to + * within the threshold limits by the time the handler got scheduled. We + * consider the irq to have been handled in that case. + * + * Return: IRQ_HANDLED + */ +irqreturn_t tsens_irq_thread(int irq, void *data) +{ + struct tsens_priv *priv = data; + struct tsens_irq_data d; + bool enable = true, disable = false; + unsigned long flags; + int temp, ret, i; + + for (i = 0; i < priv->num_sensors; i++) { + bool trigger = false; + struct tsens_sensor *s = &priv->sensor[i]; + u32 hw_id = s->hw_id; + + if (IS_ERR(priv->sensor[i].tzd)) + continue; + if (!tsens_threshold_violated(priv, hw_id, &d)) + continue; + ret = get_temp_tsens_valid(s, &temp); + if (ret) { + dev_err(priv->dev, "[%u] %s: error reading sensor\n", hw_id, __func__); + continue; + } + + spin_lock_irqsave(&priv->ul_lock, flags); + + tsens_read_irq_state(priv, hw_id, s, &d); + + if (d.up_viol && + !masked_irq(hw_id, d.up_irq_mask, tsens_version(priv))) { + tsens_set_interrupt(priv, hw_id, UPPER, disable); + if (d.up_thresh > temp) { + dev_dbg(priv->dev, "[%u] %s: re-arm upper\n", + priv->sensor[i].hw_id, __func__); + tsens_set_interrupt(priv, hw_id, UPPER, enable); + } else { + trigger = true; + /* Keep irq masked */ + } + } else if (d.low_viol && + !masked_irq(hw_id, d.low_irq_mask, tsens_version(priv))) { + tsens_set_interrupt(priv, hw_id, LOWER, disable); + if (d.low_thresh < temp) { + dev_dbg(priv->dev, "[%u] %s: re-arm low\n", + priv->sensor[i].hw_id, __func__); + tsens_set_interrupt(priv, hw_id, LOWER, enable); + } else { + trigger = true; + /* Keep irq masked */ + } + } + + spin_unlock_irqrestore(&priv->ul_lock, flags); + + if (trigger) { + dev_dbg(priv->dev, "[%u] %s: TZ update trigger (%d mC)\n", + hw_id, __func__, temp); + thermal_zone_device_update(priv->sensor[i].tzd, + THERMAL_EVENT_UNSPECIFIED); + } else { + dev_dbg(priv->dev, "[%u] %s: no violation: %d\n", + hw_id, __func__, temp); + } + } + + return IRQ_HANDLED; +} + +int tsens_set_trips(void *_sensor, int low, int high) +{ + struct tsens_sensor *s = _sensor; + struct tsens_priv *priv = s->priv; + struct device *dev = priv->dev; + struct tsens_irq_data d; + unsigned long flags; + int high_val, low_val, cl_high, cl_low; + u32 hw_id = s->hw_id; + + dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n", + hw_id, __func__, low, high); + + cl_high = clamp_val(high, -40000, 120000); + cl_low = clamp_val(low, -40000, 120000); + + high_val = tsens_mC_to_hw(s, cl_high); + low_val = tsens_mC_to_hw(s, cl_low); + + spin_lock_irqsave(&priv->ul_lock, flags); + + tsens_read_irq_state(priv, hw_id, s, &d); + + /* Write the new thresholds and clear the status */ + regmap_field_write(priv->rf[LOW_THRESH_0 + hw_id], low_val); + regmap_field_write(priv->rf[UP_THRESH_0 + hw_id], high_val); + tsens_set_interrupt(priv, hw_id, LOWER, true); + tsens_set_interrupt(priv, hw_id, UPPER, true); + + spin_unlock_irqrestore(&priv->ul_lock, flags); + + dev_dbg(dev, "[%u] %s: (%d:%d)->(%d:%d)\n", + s->hw_id, __func__, d.low_thresh, d.up_thresh, cl_low, cl_high); + + return 0; +} + +int tsens_enable_irq(struct tsens_priv *priv) +{ + int ret; + int val = tsens_version(priv) > VER_1_X ? 7 : 1; + + ret = regmap_field_write(priv->rf[INT_EN], val); + if (ret < 0) + dev_err(priv->dev, "%s: failed to enable interrupts\n", __func__); + + return ret; +} + +void tsens_disable_irq(struct tsens_priv *priv) +{ + regmap_field_write(priv->rf[INT_EN], 0); +} + int get_temp_tsens_valid(struct tsens_sensor *s, int *temp) { struct tsens_priv *priv = s->priv; @@ -187,7 +527,7 @@ static int dbg_version_show(struct seq_file *s, void *data) u32 maj_ver, min_ver, step_ver; int ret; - if (tsens_ver(priv) > VER_0_1) { + if (tsens_version(priv) > VER_0_1) { ret = regmap_field_read(priv->rf[VER_MAJOR], &maj_ver); if (ret) return ret; @@ -292,7 +632,7 @@ int __init init_common(struct tsens_priv *priv) goto err_put_device; } - if (tsens_ver(priv) > VER_0_1) { + if (tsens_version(priv) > VER_0_1) { for (i = VER_MAJOR; i <= VER_STEP; i++) { priv->rf[i] = devm_regmap_field_alloc(dev, priv->srot_map, priv->fields[i]); @@ -322,24 +662,29 @@ int __init init_common(struct tsens_priv *priv) ret = PTR_ERR(priv->rf[SENSOR_EN]); goto err_put_device; } - /* now alloc regmap_fields in tm_map */ - for (i = 0, j = LAST_TEMP_0; i < priv->feat->max_sensors; i++, j++) { - priv->rf[j] = devm_regmap_field_alloc(dev, priv->tm_map, - priv->fields[j]); - if (IS_ERR(priv->rf[j])) { - ret = PTR_ERR(priv->rf[j]); - goto err_put_device; - } + priv->rf[INT_EN] = devm_regmap_field_alloc(dev, priv->tm_map, + priv->fields[INT_EN]); + if (IS_ERR(priv->rf[INT_EN])) { + ret = PTR_ERR(priv->rf[INT_EN]); + goto err_put_device; } - for (i = 0, j = VALID_0; i < priv->feat->max_sensors; i++, j++) { - priv->rf[j] = devm_regmap_field_alloc(dev, priv->tm_map, - priv->fields[j]); - if (IS_ERR(priv->rf[j])) { - ret = PTR_ERR(priv->rf[j]); - goto err_put_device; + + /* This loop might need changes if enum regfield_ids is reordered */ + for (j = LAST_TEMP_0; j <= UP_THRESH_15; j += 16) { + for (i = 0; i < priv->feat->max_sensors; i++) { + int idx = j + i; + + priv->rf[idx] = devm_regmap_field_alloc(dev, priv->tm_map, + priv->fields[idx]); + if (IS_ERR(priv->rf[idx])) { + ret = PTR_ERR(priv->rf[idx]); + goto err_put_device; + } } } + spin_lock_init(&priv->ul_lock); + tsens_enable_irq(priv); tsens_debug_init(op); return 0; diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 055647bcee67..4b8dd6de02ce 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -347,9 +347,20 @@ static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = { /* INTERRUPT ENABLE */ [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0), + /* UPPER/LOWER TEMPERATURE THRESHOLDS */ + REG_FIELD_FOR_EACH_SENSOR11(LOW_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 0, 9), + REG_FIELD_FOR_EACH_SENSOR11(UP_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 10, 19), + + /* UPPER/LOWER INTERRUPTS [CLEAR/STATUS] */ + REG_FIELD_FOR_EACH_SENSOR11(LOW_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 20, 20), + REG_FIELD_FOR_EACH_SENSOR11(UP_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 21, 21), + + /* NO CRITICAL INTERRUPT SUPPORT on v0.1 */ + /* Sn_STATUS */ REG_FIELD_FOR_EACH_SENSOR11(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 9), /* No VALID field on v0.1 */ + /* xxx_STATUS bits: 1 == threshold violated */ REG_FIELD_FOR_EACH_SENSOR11(MIN_STATUS, TM_Sn_STATUS_OFF, 10, 10), REG_FIELD_FOR_EACH_SENSOR11(LOWER_STATUS, TM_Sn_STATUS_OFF, 11, 11), REG_FIELD_FOR_EACH_SENSOR11(UPPER_STATUS, TM_Sn_STATUS_OFF, 12, 12), diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 870f502f2cb6..7d33a0c8cd3e 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -17,6 +17,8 @@ #define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF 0x0004 #define TM_Sn_STATUS_OFF 0x0044 #define TM_TRDY_OFF 0x0084 +#define TM_HIGH_LOW_INT_STATUS_OFF 0x0088 +#define TM_HIGH_LOW_Sn_INT_THRESHOLD_OFF 0x0090 /* eeprom layout data for qcs404/405 (v1) */ #define BASE0_MASK 0x000007f8 @@ -168,9 +170,36 @@ static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { /* INTERRUPT ENABLE */ [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0), + /* UPPER/LOWER TEMPERATURE THRESHOLDS */ + REG_FIELD_FOR_EACH_SENSOR11(LOW_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 0, 9), + REG_FIELD_FOR_EACH_SENSOR11(UP_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 10, 19), + + /* UPPER/LOWER INTERRUPTS [CLEAR/STATUS] */ + REG_FIELD_FOR_EACH_SENSOR11(LOW_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 20, 20), + REG_FIELD_FOR_EACH_SENSOR11(UP_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 21, 21), + [LOW_INT_STATUS_0] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 0, 0), + [LOW_INT_STATUS_1] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 1, 1), + [LOW_INT_STATUS_2] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 2, 2), + [LOW_INT_STATUS_3] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 3, 3), + [LOW_INT_STATUS_4] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 4, 4), + [LOW_INT_STATUS_5] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 5, 5), + [LOW_INT_STATUS_6] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 6, 6), + [LOW_INT_STATUS_7] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 7, 7), + [UP_INT_STATUS_0] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 8, 8), + [UP_INT_STATUS_1] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 9, 9), + [UP_INT_STATUS_2] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 10, 10), + [UP_INT_STATUS_3] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 11, 11), + [UP_INT_STATUS_4] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 12, 12), + [UP_INT_STATUS_5] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 13, 13), + [UP_INT_STATUS_6] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 14, 14), + [UP_INT_STATUS_7] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 15, 15), + + /* NO CRITICAL INTERRUPT SUPPORT on v1 */ + /* Sn_STATUS */ REG_FIELD_FOR_EACH_SENSOR11(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 9), REG_FIELD_FOR_EACH_SENSOR11(VALID, TM_Sn_STATUS_OFF, 14, 14), + /* xxx_STATUS bits: 1 == threshold violated */ REG_FIELD_FOR_EACH_SENSOR11(MIN_STATUS, TM_Sn_STATUS_OFF, 10, 10), REG_FIELD_FOR_EACH_SENSOR11(LOWER_STATUS, TM_Sn_STATUS_OFF, 11, 11), REG_FIELD_FOR_EACH_SENSOR11(UPPER_STATUS, TM_Sn_STATUS_OFF, 12, 12), diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index 0a4f2b8fcab6..a4d15e1abfdd 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -50,9 +50,22 @@ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { /* v2 has separate enables for UPPER/LOWER/CRITICAL interrupts */ [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 2), + /* TEMPERATURE THRESHOLDS */ + REG_FIELD_FOR_EACH_SENSOR16(LOW_THRESH, TM_Sn_UPPER_LOWER_THRESHOLD_OFF, 0, 11), + REG_FIELD_FOR_EACH_SENSOR16(UP_THRESH, TM_Sn_UPPER_LOWER_THRESHOLD_OFF, 12, 23), + + /* INTERRUPTS [CLEAR/STATUS/MASK] */ + REG_FIELD_SPLIT_BITS_0_15(LOW_INT_STATUS, TM_UPPER_LOWER_INT_STATUS_OFF), + REG_FIELD_SPLIT_BITS_0_15(LOW_INT_CLEAR, TM_UPPER_LOWER_INT_CLEAR_OFF), + REG_FIELD_SPLIT_BITS_0_15(LOW_INT_MASK, TM_UPPER_LOWER_INT_MASK_OFF), + REG_FIELD_SPLIT_BITS_16_31(UP_INT_STATUS, TM_UPPER_LOWER_INT_STATUS_OFF), + REG_FIELD_SPLIT_BITS_16_31(UP_INT_CLEAR, TM_UPPER_LOWER_INT_CLEAR_OFF), + REG_FIELD_SPLIT_BITS_16_31(UP_INT_MASK, TM_UPPER_LOWER_INT_MASK_OFF), + /* Sn_STATUS */ REG_FIELD_FOR_EACH_SENSOR16(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 11), REG_FIELD_FOR_EACH_SENSOR16(VALID, TM_Sn_STATUS_OFF, 21, 21), + /* xxx_STATUS bits: 1 == threshold violated */ REG_FIELD_FOR_EACH_SENSOR16(MIN_STATUS, TM_Sn_STATUS_OFF, 16, 16), REG_FIELD_FOR_EACH_SENSOR16(LOWER_STATUS, TM_Sn_STATUS_OFF, 17, 17), REG_FIELD_FOR_EACH_SENSOR16(UPPER_STATUS, TM_Sn_STATUS_OFF, 18, 18), diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 772aa76b50e1..eeb68dd261b3 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -78,12 +79,14 @@ MODULE_DEVICE_TABLE(of, tsens_table); static const struct thermal_zone_of_device_ops tsens_of_ops = { .get_temp = tsens_get_temp, .get_trend = tsens_get_trend, + .set_trips = tsens_set_trips, }; static int tsens_register(struct tsens_priv *priv) { - int i; + int i, ret, irq; struct thermal_zone_device *tzd; + struct platform_device *pdev; for (i = 0; i < priv->num_sensors; i++) { priv->sensor[i].priv = priv; @@ -96,7 +99,32 @@ static int tsens_register(struct tsens_priv *priv) if (priv->ops->enable) priv->ops->enable(priv, i); } + + pdev = of_find_device_by_node(priv->dev->of_node); + if (!pdev) + return -ENODEV; + + irq = platform_get_irq_byname(pdev, "uplow"); + if (irq < 0) { + ret = irq; + goto err_put_device; + } + + ret = devm_request_threaded_irq(&pdev->dev, irq, + NULL, tsens_irq_thread, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, + dev_name(&pdev->dev), priv); + if (ret) { + dev_err(&pdev->dev, "%s: failed to get irq\n", __func__); + goto err_put_device; + } + + enable_irq_wake(irq); return 0; + +err_put_device: + put_device(&pdev->dev); + return ret; } static int tsens_probe(struct platform_device *pdev) @@ -178,6 +206,7 @@ static int tsens_remove(struct platform_device *pdev) struct tsens_priv *priv = platform_get_drvdata(pdev); debugfs_remove_recursive(priv->debug_root); + tsens_disable_irq(priv); if (priv->ops->disable) priv->ops->disable(priv); diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 00899c17e848..8b20f28c5c51 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -13,8 +13,10 @@ #define CAL_DEGC_PT2 120 #define SLOPE_FACTOR 1000 #define SLOPE_DEFAULT 3200 +#define THRESHOLD_MAX_ADC_CODE 0x3ff +#define THRESHOLD_MIN_ADC_CODE 0x0 - +#include #include #include #include @@ -27,6 +29,11 @@ enum tsens_ver { VER_2_X, }; +enum tsens_irq_type { + LOWER, + UPPER, +}; + /** * struct tsens_sensor - data for each sensor connected to the tsens device * @priv: tsens device instance that this sensor is connected to @@ -100,22 +107,66 @@ struct tsens_ops { [_name##_##14] = REG_FIELD(_offset + 56, _startbit, _stopbit), \ [_name##_##15] = REG_FIELD(_offset + 60, _startbit, _stopbit) -/* reg_field IDs to use as an index into an array */ +#define REG_FIELD_SPLIT_BITS_0_15(_name, _offset) \ + [_name##_##0] = REG_FIELD(_offset, 0, 0), \ + [_name##_##1] = REG_FIELD(_offset, 1, 1), \ + [_name##_##2] = REG_FIELD(_offset, 2, 2), \ + [_name##_##3] = REG_FIELD(_offset, 3, 3), \ + [_name##_##4] = REG_FIELD(_offset, 4, 4), \ + [_name##_##5] = REG_FIELD(_offset, 5, 5), \ + [_name##_##6] = REG_FIELD(_offset, 6, 6), \ + [_name##_##7] = REG_FIELD(_offset, 7, 7), \ + [_name##_##8] = REG_FIELD(_offset, 8, 8), \ + [_name##_##9] = REG_FIELD(_offset, 9, 9), \ + [_name##_##10] = REG_FIELD(_offset, 10, 10), \ + [_name##_##11] = REG_FIELD(_offset, 11, 11), \ + [_name##_##12] = REG_FIELD(_offset, 12, 12), \ + [_name##_##13] = REG_FIELD(_offset, 13, 13), \ + [_name##_##14] = REG_FIELD(_offset, 14, 14), \ + [_name##_##15] = REG_FIELD(_offset, 15, 15) + +#define REG_FIELD_SPLIT_BITS_16_31(_name, _offset) \ + [_name##_##0] = REG_FIELD(_offset, 16, 16), \ + [_name##_##1] = REG_FIELD(_offset, 17, 17), \ + [_name##_##2] = REG_FIELD(_offset, 18, 18), \ + [_name##_##3] = REG_FIELD(_offset, 19, 19), \ + [_name##_##4] = REG_FIELD(_offset, 20, 20), \ + [_name##_##5] = REG_FIELD(_offset, 21, 21), \ + [_name##_##6] = REG_FIELD(_offset, 22, 22), \ + [_name##_##7] = REG_FIELD(_offset, 23, 23), \ + [_name##_##8] = REG_FIELD(_offset, 24, 24), \ + [_name##_##9] = REG_FIELD(_offset, 25, 25), \ + [_name##_##10] = REG_FIELD(_offset, 26, 26), \ + [_name##_##11] = REG_FIELD(_offset, 27, 27), \ + [_name##_##12] = REG_FIELD(_offset, 28, 28), \ + [_name##_##13] = REG_FIELD(_offset, 29, 29), \ + [_name##_##14] = REG_FIELD(_offset, 30, 30), \ + [_name##_##15] = REG_FIELD(_offset, 31, 31) + +/* + * reg_field IDs to use as an index into an array + * If you change the order of the entries, check the devm_regmap_field_alloc() + * calls in init_common() + */ enum regfield_ids { /* ----- SROT ------ */ /* HW_VER */ - VER_MAJOR = 0, + VER_MAJOR, VER_MINOR, VER_STEP, /* CTRL_OFFSET */ - TSENS_EN = 3, + TSENS_EN, TSENS_SW_RST, SENSOR_EN, CODE_OR_TEMP, /* ----- TM ------ */ + /* TRDY */ + TRDY, + /* INTERRUPT ENABLE */ + INT_EN, /* v2+ has separate enables for crit, upper and lower irq */ /* STATUS */ - LAST_TEMP_0 = 7, /* Last temperature reading */ + LAST_TEMP_0, /* Last temperature reading */ LAST_TEMP_1, LAST_TEMP_2, LAST_TEMP_3, @@ -131,7 +182,7 @@ enum regfield_ids { LAST_TEMP_13, LAST_TEMP_14, LAST_TEMP_15, - VALID_0 = 23, /* VALID reading or not */ + VALID_0, /* VALID reading or not */ VALID_1, VALID_2, VALID_3, @@ -147,38 +198,6 @@ enum regfield_ids { VALID_13, VALID_14, VALID_15, - MIN_STATUS_0, /* MIN threshold violated */ - MIN_STATUS_1, - MIN_STATUS_2, - MIN_STATUS_3, - MIN_STATUS_4, - MIN_STATUS_5, - MIN_STATUS_6, - MIN_STATUS_7, - MIN_STATUS_8, - MIN_STATUS_9, - MIN_STATUS_10, - MIN_STATUS_11, - MIN_STATUS_12, - MIN_STATUS_13, - MIN_STATUS_14, - MIN_STATUS_15, - MAX_STATUS_0, /* MAX threshold violated */ - MAX_STATUS_1, - MAX_STATUS_2, - MAX_STATUS_3, - MAX_STATUS_4, - MAX_STATUS_5, - MAX_STATUS_6, - MAX_STATUS_7, - MAX_STATUS_8, - MAX_STATUS_9, - MAX_STATUS_10, - MAX_STATUS_11, - MAX_STATUS_12, - MAX_STATUS_13, - MAX_STATUS_14, - MAX_STATUS_15, LOWER_STATUS_0, /* LOWER threshold violated */ LOWER_STATUS_1, LOWER_STATUS_2, @@ -195,6 +214,70 @@ enum regfield_ids { LOWER_STATUS_13, LOWER_STATUS_14, LOWER_STATUS_15, + LOW_INT_STATUS_0, /* LOWER interrupt status */ + LOW_INT_STATUS_1, + LOW_INT_STATUS_2, + LOW_INT_STATUS_3, + LOW_INT_STATUS_4, + LOW_INT_STATUS_5, + LOW_INT_STATUS_6, + LOW_INT_STATUS_7, + LOW_INT_STATUS_8, + LOW_INT_STATUS_9, + LOW_INT_STATUS_10, + LOW_INT_STATUS_11, + LOW_INT_STATUS_12, + LOW_INT_STATUS_13, + LOW_INT_STATUS_14, + LOW_INT_STATUS_15, + LOW_INT_CLEAR_0, /* LOWER interrupt clear */ + LOW_INT_CLEAR_1, + LOW_INT_CLEAR_2, + LOW_INT_CLEAR_3, + LOW_INT_CLEAR_4, + LOW_INT_CLEAR_5, + LOW_INT_CLEAR_6, + LOW_INT_CLEAR_7, + LOW_INT_CLEAR_8, + LOW_INT_CLEAR_9, + LOW_INT_CLEAR_10, + LOW_INT_CLEAR_11, + LOW_INT_CLEAR_12, + LOW_INT_CLEAR_13, + LOW_INT_CLEAR_14, + LOW_INT_CLEAR_15, + LOW_INT_MASK_0, /* LOWER interrupt mask */ + LOW_INT_MASK_1, + LOW_INT_MASK_2, + LOW_INT_MASK_3, + LOW_INT_MASK_4, + LOW_INT_MASK_5, + LOW_INT_MASK_6, + LOW_INT_MASK_7, + LOW_INT_MASK_8, + LOW_INT_MASK_9, + LOW_INT_MASK_10, + LOW_INT_MASK_11, + LOW_INT_MASK_12, + LOW_INT_MASK_13, + LOW_INT_MASK_14, + LOW_INT_MASK_15, + LOW_THRESH_0, /* LOWER threshold values */ + LOW_THRESH_1, + LOW_THRESH_2, + LOW_THRESH_3, + LOW_THRESH_4, + LOW_THRESH_5, + LOW_THRESH_6, + LOW_THRESH_7, + LOW_THRESH_8, + LOW_THRESH_9, + LOW_THRESH_10, + LOW_THRESH_11, + LOW_THRESH_12, + LOW_THRESH_13, + LOW_THRESH_14, + LOW_THRESH_15, UPPER_STATUS_0, /* UPPER threshold violated */ UPPER_STATUS_1, UPPER_STATUS_2, @@ -211,6 +294,70 @@ enum regfield_ids { UPPER_STATUS_13, UPPER_STATUS_14, UPPER_STATUS_15, + UP_INT_STATUS_0, /* UPPER interrupt status */ + UP_INT_STATUS_1, + UP_INT_STATUS_2, + UP_INT_STATUS_3, + UP_INT_STATUS_4, + UP_INT_STATUS_5, + UP_INT_STATUS_6, + UP_INT_STATUS_7, + UP_INT_STATUS_8, + UP_INT_STATUS_9, + UP_INT_STATUS_10, + UP_INT_STATUS_11, + UP_INT_STATUS_12, + UP_INT_STATUS_13, + UP_INT_STATUS_14, + UP_INT_STATUS_15, + UP_INT_CLEAR_0, /* UPPER interrupt clear */ + UP_INT_CLEAR_1, + UP_INT_CLEAR_2, + UP_INT_CLEAR_3, + UP_INT_CLEAR_4, + UP_INT_CLEAR_5, + UP_INT_CLEAR_6, + UP_INT_CLEAR_7, + UP_INT_CLEAR_8, + UP_INT_CLEAR_9, + UP_INT_CLEAR_10, + UP_INT_CLEAR_11, + UP_INT_CLEAR_12, + UP_INT_CLEAR_13, + UP_INT_CLEAR_14, + UP_INT_CLEAR_15, + UP_INT_MASK_0, /* UPPER interrupt mask */ + UP_INT_MASK_1, + UP_INT_MASK_2, + UP_INT_MASK_3, + UP_INT_MASK_4, + UP_INT_MASK_5, + UP_INT_MASK_6, + UP_INT_MASK_7, + UP_INT_MASK_8, + UP_INT_MASK_9, + UP_INT_MASK_10, + UP_INT_MASK_11, + UP_INT_MASK_12, + UP_INT_MASK_13, + UP_INT_MASK_14, + UP_INT_MASK_15, + UP_THRESH_0, /* UPPER threshold values */ + UP_THRESH_1, + UP_THRESH_2, + UP_THRESH_3, + UP_THRESH_4, + UP_THRESH_5, + UP_THRESH_6, + UP_THRESH_7, + UP_THRESH_8, + UP_THRESH_9, + UP_THRESH_10, + UP_THRESH_11, + UP_THRESH_12, + UP_THRESH_13, + UP_THRESH_14, + UP_THRESH_15, CRITICAL_STATUS_0, /* CRITICAL threshold violated */ CRITICAL_STATUS_1, CRITICAL_STATUS_2, @@ -227,13 +374,38 @@ enum regfield_ids { CRITICAL_STATUS_13, CRITICAL_STATUS_14, CRITICAL_STATUS_15, - /* TRDY */ - TRDY, - /* INTERRUPT ENABLE */ - INT_EN, /* Pre-V1, V1.x */ - LOW_INT_EN, /* V2.x */ - UP_INT_EN, /* V2.x */ - CRIT_INT_EN, /* V2.x */ + MIN_STATUS_0, /* MIN threshold violated */ + MIN_STATUS_1, + MIN_STATUS_2, + MIN_STATUS_3, + MIN_STATUS_4, + MIN_STATUS_5, + MIN_STATUS_6, + MIN_STATUS_7, + MIN_STATUS_8, + MIN_STATUS_9, + MIN_STATUS_10, + MIN_STATUS_11, + MIN_STATUS_12, + MIN_STATUS_13, + MIN_STATUS_14, + MIN_STATUS_15, + MAX_STATUS_0, /* MAX threshold violated */ + MAX_STATUS_1, + MAX_STATUS_2, + MAX_STATUS_3, + MAX_STATUS_4, + MAX_STATUS_5, + MAX_STATUS_6, + MAX_STATUS_7, + MAX_STATUS_8, + MAX_STATUS_9, + MAX_STATUS_10, + MAX_STATUS_11, + MAX_STATUS_12, + MAX_STATUS_13, + MAX_STATUS_14, + MAX_STATUS_15, /* Keep last */ MAX_REGFIELDS @@ -303,6 +475,10 @@ struct tsens_priv { struct regmap *tm_map; struct regmap *srot_map; u32 tm_offset; + + /* lock for upper/lower threshold interrupts */ + spinlock_t ul_lock; + struct regmap_field *rf[MAX_REGFIELDS]; struct tsens_context ctx; const struct tsens_features *feat; @@ -320,6 +496,10 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mo int init_common(struct tsens_priv *priv); int get_temp_tsens_valid(struct tsens_sensor *s, int *temp); int get_temp_common(struct tsens_sensor *s, int *temp); +int tsens_enable_irq(struct tsens_priv *priv); +void tsens_disable_irq(struct tsens_priv *priv); +int tsens_set_trips(void *_sensor, int low, int high); +irqreturn_t tsens_irq_thread(int irq, void *data); /* TSENS target */ extern const struct tsens_plat_data data_8960;