From patchwork Fri Oct 18 15:34:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198711 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 11FA7112B for ; Fri, 18 Oct 2019 15:32:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E747B222D0 for ; Fri, 18 Oct 2019 15:32:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="PwrYcDff" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2410601AbfJRPcH (ORCPT ); Fri, 18 Oct 2019 11:32:07 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:37070 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2410589AbfJRPcF (ORCPT ); Fri, 18 Oct 2019 11:32:05 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW30J064225; Fri, 18 Oct 2019 10:32:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571412724; bh=j99x0LUGCJ69WgqO6pLApz0kcnPMoOP7gpKZ5+4Wc4s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=PwrYcDffNRGqHy/KOEkoUP4W1d7im000TzLudCw09ioujSpSBiOyj4S0hkjVuhEOJ PtjfBkOwWAxjslmbJJmR1sRus/o2DYrbDh/VcxysCEjTTuv595wHJ2hW1eoEb7hMyy s2Vx2U4aIon7Med1lBM5XDVQoShPFYlIwG1q0gUg= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9IFW3et084570 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Oct 2019 10:32:03 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:31:55 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:32:03 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW15F080266; Fri, 18 Oct 2019 10:32:03 -0500 From: Benoit Parrot To: Hans Verkuil , Rob Herring CC: , , , Benoit Parrot Subject: [Patch 01/19] dt-bindings: media: cal: update binding to use syscon Date: Fri, 18 Oct 2019 10:34:19 -0500 Message-ID: <20191018153437.20614-2-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018153437.20614-1-bparrot@ti.com> References: <20191018153437.20614-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Update Device Tree bindings for the CAL driver to use syscon to access the phy config register instead of trying to map it directly. Signed-off-by: Benoit Parrot --- Documentation/devicetree/bindings/media/ti-cal.txt | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/media/ti-cal.txt b/Documentation/devicetree/bindings/media/ti-cal.txt index ae9b52f37576..782f801b12a9 100644 --- a/Documentation/devicetree/bindings/media/ti-cal.txt +++ b/Documentation/devicetree/bindings/media/ti-cal.txt @@ -10,9 +10,14 @@ Required properties: - compatible: must be "ti,dra72-cal" - reg: CAL Top level, Receiver Core #0, Receiver Core #1 and Camera RX control address space -- reg-names: cal_top, cal_rx_core0, cal_rx_core1, and camerrx_control +- reg-names: cal_top, cal_rx_core0, cal_rx_core1 and camerrx_control registers - interrupts: should contain IRQ line for the CAL; +- syscon-camerrx: phandle to the device control module and offset to the + control_camerarx_core register + This node is meant to replace the "camerrx_control" reg + entry above but "camerrx_control" is still handled + for backward compatibility. CAL supports 2 camera port nodes on MIPI bus. Each CSI2 camera port nodes should contain a 'port' child node with child 'endpoint' node. Please @@ -25,13 +30,12 @@ Example: ti,hwmods = "cal"; reg = <0x4845B000 0x400>, <0x4845B800 0x40>, - <0x4845B900 0x40>, - <0x4A002e94 0x4>; + <0x4845B900 0x40>; reg-names = "cal_top", "cal_rx_core0", - "cal_rx_core1", - "camerrx_control"; + "cal_rx_core1"; interrupts = ; + syscon-camerrx = <&scm_conf 0xE94>; #address-cells = <1>; #size-cells = <0>; From patchwork Fri Oct 18 15:34:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198713 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 841FA14ED for ; Fri, 18 Oct 2019 15:32:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 64C75222C3 for ; Fri, 18 Oct 2019 15:32:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="IWGYNEUX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2410609AbfJRPcH (ORCPT ); Fri, 18 Oct 2019 11:32:07 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:47644 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2410487AbfJRPcH (ORCPT ); Fri, 18 Oct 2019 11:32:07 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW4EV013333; Fri, 18 Oct 2019 10:32:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571412724; bh=1IFsv4aHfGxY2ANuXmzhcs4OdarMkTUyT1n5qDGGa7c=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IWGYNEUXK5dFD9FbMBRxPOvPH0apkpXxglU1ibA+7opOVY81RZOx7obpCSb89cLnJ TNngqVsE6H46nHYQvx6uKSswGA12Ui+HHUa8G1aHS9fXKyLfru6uBisFLBV69gKFa3 qZb3HVR41CjT7nWf1ow6XjIyvT9NlFJXkHX6xCV8= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW4DD105555; Fri, 18 Oct 2019 10:32:04 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:31:56 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:31:56 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW15G080266; Fri, 18 Oct 2019 10:32:04 -0500 From: Benoit Parrot To: Hans Verkuil , Rob Herring CC: , , , Benoit Parrot Subject: [Patch 02/19] dt-bindings: media: cal: update binding example Date: Fri, 18 Oct 2019 10:34:20 -0500 Message-ID: <20191018153437.20614-3-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018153437.20614-1-bparrot@ti.com> References: <20191018153437.20614-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Update binding example to show proper endpoint properties and linkage. Signed-off-by: Benoit Parrot --- .../devicetree/bindings/media/ti-cal.txt | 32 ++++++++++--------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/media/ti-cal.txt b/Documentation/devicetree/bindings/media/ti-cal.txt index 782f801b12a9..6b56fddcfc4a 100644 --- a/Documentation/devicetree/bindings/media/ti-cal.txt +++ b/Documentation/devicetree/bindings/media/ti-cal.txt @@ -27,7 +27,6 @@ Documentation/devicetree/bindings/media/video-interfaces.txt. Example: cal: cal@4845b000 { compatible = "ti,dra72-cal"; - ti,hwmods = "cal"; reg = <0x4845B000 0x400>, <0x4845B800 0x40>, <0x4845B900 0x40>; @@ -45,9 +44,10 @@ Example: csi2_0: port@0 { reg = <0>; - endpoint { - slave-mode; - remote-endpoint = <&ar0330_1>; + csi2_phy0: endpoint@0 { + remote-endpoint = <&csi2_cam0>; + clock-lanes = <0>; + data-lanes = <1 2>; }; }; csi2_1: port@1 { @@ -57,19 +57,21 @@ Example: }; i2c5: i2c@4807c000 { - ar0330@10 { - compatible = "ti,ar0330"; - reg = <0x10>; + status = "okay"; + clock-frequency = <400000>; - port { - #address-cells = <1>; - #size-cells = <0>; + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; - ar0330_1: endpoint { - reg = <0>; - clock-lanes = <1>; - data-lanes = <0 2 3 4>; - remote-endpoint = <&csi2_0>; + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2_phy0>; + clock-lanes = <0>; + data-lanes = <1 2>; }; }; }; From patchwork Fri Oct 18 15:34:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198745 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EDE66112B for ; Fri, 18 Oct 2019 15:33:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B58F1222C5 for ; Fri, 18 Oct 2019 15:33:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="hqj4UAEp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2505123AbfJRPcI (ORCPT ); Fri, 18 Oct 2019 11:32:08 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:47646 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2410600AbfJRPcI (ORCPT ); Fri, 18 Oct 2019 11:32:08 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW5U4013340; Fri, 18 Oct 2019 10:32:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571412725; bh=Nlh6upxYhOieNJD7MW/qDml7WrFkn9NVQpn1e0i2QaQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hqj4UAEpTNpyRQYs10oQn8txCrFG4ck1WaivUrLZnpFSo3aZAmU+2PE1XFUUqa3d5 22x0bVH6cws+uKBT94vX7ahoXrxoywCuTxiHvNXFTMegrTlh+XLydmZZrw0fvpkWaj 1fUdH5NG22Wn8lzZeELam2WT6/T04pJaP+M/unJU= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW5Ua105576; Fri, 18 Oct 2019 10:32:05 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:31:57 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:32:05 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW15H080266; Fri, 18 Oct 2019 10:32:05 -0500 From: Benoit Parrot To: Hans Verkuil , Rob Herring CC: , , , Benoit Parrot Subject: [Patch 03/19] media: ti-vpe: cal: Add per platform data support Date: Fri, 18 Oct 2019 10:34:21 -0500 Message-ID: <20191018153437.20614-4-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018153437.20614-1-bparrot@ti.com> References: <20191018153437.20614-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org First this patch adds a method to access the CTRL_CORE_CAMERRX_CONTROL register to use the syscon mechanism. For backward compatibility we also handle using the existing camerrx_control "reg" entry if a syscon node is not found. In addition the register bit layout for the CTRL_CORE_CAMERRX_CONTROL changes depending on the device. In order to support this we need to use a register access scheme based on data configuration instead of using static macro. In this case we make use of the regmap facility and create data set based on the various device and phy available. Signed-off-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 281 +++++++++++++++++++++------- 1 file changed, 212 insertions(+), 69 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 223161f9c403..26f95a81e4ed 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include #include #include @@ -220,20 +222,66 @@ struct cal_dmaqueue { int ini_jiffies; }; -struct cm_data { +struct cc_data { void __iomem *base; struct resource *res; - unsigned int camerrx_control; - struct platform_device *pdev; }; -struct cc_data { - void __iomem *base; - struct resource *res; +/* CTRL_CORE_CAMERRX_CONTROL register field id */ +enum cal_camerarx_field { + F_CTRLCLKEN, + F_CAMMODE, + F_LANEENABLE, + F_CSI_MODE, - struct platform_device *pdev; + F_MAX_FIELDS, +}; + +struct cal_csi2_phy { + struct regmap_field *fields[F_MAX_FIELDS]; + struct reg_field *base_fields; + const int num_lanes; +}; + +struct cal_data { + const int num_csi2_phy; + struct cal_csi2_phy *csi2_phy_core; + + const unsigned int flags; +}; + +static struct reg_field dra72x_ctrl_core_csi0_reg_fields[F_MAX_FIELDS] = { + [F_CTRLCLKEN] = REG_FIELD(0, 10, 10), + [F_CAMMODE] = REG_FIELD(0, 11, 12), + [F_LANEENABLE] = REG_FIELD(0, 13, 16), + [F_CSI_MODE] = REG_FIELD(0, 17, 17), +}; + +static struct reg_field dra72x_ctrl_core_csi1_reg_fields[F_MAX_FIELDS] = { + [F_CTRLCLKEN] = REG_FIELD(0, 0, 0), + [F_CAMMODE] = REG_FIELD(0, 1, 2), + [F_LANEENABLE] = REG_FIELD(0, 3, 4), + [F_CSI_MODE] = REG_FIELD(0, 5, 5), +}; + +static struct cal_csi2_phy dra72x_cal_csi_phy[] = { + { + .base_fields = dra72x_ctrl_core_csi0_reg_fields, + .num_lanes = 4, + }, + { + .base_fields = dra72x_ctrl_core_csi1_reg_fields, + .num_lanes = 2, + }, +}; + +static struct cal_data dra72x_cal_data = { + .csi2_phy_core = dra72x_cal_csi_phy, + .num_csi2_phy = ARRAY_SIZE(dra72x_cal_csi_phy), + + .flags = 0, }; /* @@ -247,8 +295,15 @@ struct cal_dev { struct platform_device *pdev; struct v4l2_device v4l2_dev; + /* Controller flags for special cases */ + unsigned int flags; + + struct cal_data *data; + /* Control Module handle */ - struct cm_data *cm; + struct regmap *syscon_camerrx; + u32 syscon_camerrx_offset; + /* Camera Core Module handle */ struct cc_data *cc[CAL_NUM_CSI2_PORTS]; @@ -359,73 +414,113 @@ static inline void set_field(u32 *valp, u32 field, u32 mask) *valp = val; } -/* - * Control Module block access - */ -static struct cm_data *cm_create(struct cal_dev *dev) +static u32 cal_data_get_phy_max_lanes(struct cal_ctx *ctx) { - struct platform_device *pdev = dev->pdev; - struct cm_data *cm; + struct cal_dev *dev = ctx->dev; + u32 phy_id = ctx->csi2_port - 1; - cm = devm_kzalloc(&pdev->dev, sizeof(*cm), GFP_KERNEL); - if (!cm) - return ERR_PTR(-ENOMEM); + return dev->data->csi2_phy_core[phy_id].num_lanes; +} + +static u32 cal_data_get_num_csi2_phy(struct cal_dev *dev) +{ + return dev->data->num_csi2_phy; +} + +static int cal_camerarx_regmap_init(struct cal_dev *dev) +{ + struct reg_field *field; + struct cal_csi2_phy *phy; + int i, j; + + if (!dev->data) + return -EINVAL; - cm->res = platform_get_resource_byname(pdev, IORESOURCE_MEM, - "camerrx_control"); - cm->base = devm_ioremap_resource(&pdev->dev, cm->res); - if (IS_ERR(cm->base)) { + for (i = 0; i < cal_data_get_num_csi2_phy(dev); i++) { + phy = &dev->data->csi2_phy_core[i]; + for (j = 0; j < F_MAX_FIELDS; j++) { + field = &phy->base_fields[j]; + /* + * Here we update the reg offset with the + * value found in DT + */ + field->reg = dev->syscon_camerrx_offset; + phy->fields[j] = + devm_regmap_field_alloc(&dev->pdev->dev, + dev->syscon_camerrx, + *field); + if (IS_ERR(phy->fields[j])) { + cal_err(dev, "Unable to allocate regmap fields\n"); + return PTR_ERR(phy->fields[j]); + } + } + } + return 0; +} + +static const struct regmap_config cal_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + +static struct regmap *cal_get_camerarx_regmap(struct cal_dev *dev) +{ + struct platform_device *pdev = dev->pdev; + struct regmap *regmap; + void __iomem *base; + u32 reg_io_width; + struct regmap_config r_config = cal_regmap_config; + struct resource *res; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "camerrx_control"); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) { cal_err(dev, "failed to ioremap\n"); - return ERR_CAST(cm->base); + return ERR_CAST(base); } cal_dbg(1, dev, "ioresource %s at %pa - %pa\n", - cm->res->name, &cm->res->start, &cm->res->end); + res->name, &res->start, &res->end); + + reg_io_width = 4; + r_config.reg_stride = reg_io_width; + r_config.val_bits = reg_io_width * 8; + r_config.max_register = resource_size(res) - reg_io_width; - return cm; + regmap = regmap_init_mmio(NULL, base, &r_config); + if (IS_ERR(regmap)) + pr_err("regmap init failed\n"); + + return regmap; } +/* + * Control Module CAMERARX block access + */ static void camerarx_phy_enable(struct cal_ctx *ctx) { - u32 val; - - if (!ctx->dev->cm->base) { - ctx_err(ctx, "cm not mapped\n"); - return; - } - - val = reg_read(ctx->dev->cm, CM_CTRL_CORE_CAMERRX_CONTROL); - if (ctx->csi2_port == 1) { - set_field(&val, 1, CM_CAMERRX_CTRL_CSI0_CTRLCLKEN_MASK); - set_field(&val, 0, CM_CAMERRX_CTRL_CSI0_CAMMODE_MASK); - /* enable all lanes by default */ - set_field(&val, 0xf, CM_CAMERRX_CTRL_CSI0_LANEENABLE_MASK); - set_field(&val, 1, CM_CAMERRX_CTRL_CSI0_MODE_MASK); - } else if (ctx->csi2_port == 2) { - set_field(&val, 1, CM_CAMERRX_CTRL_CSI1_CTRLCLKEN_MASK); - set_field(&val, 0, CM_CAMERRX_CTRL_CSI1_CAMMODE_MASK); - /* enable all lanes by default */ - set_field(&val, 0x3, CM_CAMERRX_CTRL_CSI1_LANEENABLE_MASK); - set_field(&val, 1, CM_CAMERRX_CTRL_CSI1_MODE_MASK); - } - reg_write(ctx->dev->cm, CM_CTRL_CORE_CAMERRX_CONTROL, val); + struct cal_csi2_phy *phy; + u32 phy_id = ctx->csi2_port - 1; + u32 max_lanes; + + phy = &ctx->dev->data->csi2_phy_core[phy_id]; + regmap_field_write(phy->fields[F_CAMMODE], 0); + /* Always enable all lanes at the phy control level */ + max_lanes = (1 << cal_data_get_phy_max_lanes(ctx)) - 1; + regmap_field_write(phy->fields[F_LANEENABLE], max_lanes); + regmap_field_write(phy->fields[F_CSI_MODE], 1); + regmap_field_write(phy->fields[F_CTRLCLKEN], 1); } static void camerarx_phy_disable(struct cal_ctx *ctx) { - u32 val; - - if (!ctx->dev->cm->base) { - ctx_err(ctx, "cm not mapped\n"); - return; - } + struct cal_csi2_phy *phy; + u32 phy_id = ctx->csi2_port - 1; - val = reg_read(ctx->dev->cm, CM_CTRL_CORE_CAMERRX_CONTROL); - if (ctx->csi2_port == 1) - set_field(&val, 0x0, CM_CAMERRX_CTRL_CSI0_CTRLCLKEN_MASK); - else if (ctx->csi2_port == 2) - set_field(&val, 0x0, CM_CAMERRX_CTRL_CSI1_CTRLCLKEN_MASK); - reg_write(ctx->dev->cm, CM_CTRL_CORE_CAMERRX_CONTROL, val); + phy = &ctx->dev->data->csi2_phy_core[phy_id]; + regmap_field_write(phy->fields[F_CTRLCLKEN], 0); } /* @@ -508,12 +603,6 @@ static void cal_quickdump_regs(struct cal_dev *dev) resource_size(dev->ctx[1]->cc->res), false); } - - cal_info(dev, "CAMERRX_Control Registers @ %pa:\n", - &dev->cm->res->start); - print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4, - (__force const void *)dev->cm->base, - resource_size(dev->cm->res), false); } /* @@ -1804,10 +1893,16 @@ static struct cal_ctx *cal_create_instance(struct cal_dev *dev, int inst) return NULL; } +static const struct of_device_id cal_of_match[]; + static int cal_probe(struct platform_device *pdev) { struct cal_dev *dev; struct cal_ctx *ctx; + const struct of_device_id *match; + struct device_node *parent = pdev->dev.of_node; + struct regmap *syscon_camerrx = NULL; + u32 syscon_camerrx_offset = 0; int ret; int irq; int i; @@ -1816,6 +1911,18 @@ static int cal_probe(struct platform_device *pdev) if (!dev) return -ENOMEM; + match = of_match_device(of_match_ptr(cal_of_match), &pdev->dev); + if (!match) + return -ENODEV; + + if (match->data) { + dev->data = (struct cal_data *)match->data; + dev->flags = dev->data->flags; + } else { + dev_err(&pdev->dev, "Could not get feature data based on compatible version\n"); + return -ENODEV; + } + /* set pseudo v4l2 device name so we can use v4l2_printk */ strscpy(dev->v4l2_dev.name, CAL_MODULE_NAME, sizeof(dev->v4l2_dev.name)); @@ -1823,6 +1930,43 @@ static int cal_probe(struct platform_device *pdev) /* save pdev pointer */ dev->pdev = pdev; + if (parent && of_property_read_bool(parent, "syscon-camerrx")) { + syscon_camerrx = + syscon_regmap_lookup_by_phandle(parent, + "syscon-camerrx"); + if (IS_ERR(syscon_camerrx)) { + dev_err(&pdev->dev, "failed to get syscon-camerrx regmap\n"); + return PTR_ERR(syscon_camerrx); + } + + if (of_property_read_u32_index(parent, "syscon-camerrx", 1, + &syscon_camerrx_offset)) { + dev_err(&pdev->dev, "failed to get syscon-camerrx offset\n"); + return -EINVAL; + } + } else { + /* + * Backward DTS compatibility. + * If syscon entry is not present then check if the + * camerrx_control resource is present. + */ + syscon_camerrx = cal_get_camerarx_regmap(dev); + if (IS_ERR(syscon_camerrx)) { + dev_err(&pdev->dev, "failed to get camerrx_control regmap\n"); + return PTR_ERR(syscon_camerrx); + } + /* In this case the base already point to the direct + * CM register so no need for an offset + */ + syscon_camerrx_offset = 0; + } + + dev->syscon_camerrx = syscon_camerrx; + dev->syscon_camerrx_offset = syscon_camerrx_offset; + ret = cal_camerarx_regmap_init(dev); + if (ret) + return ret; + dev->res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cal_top"); dev->base = devm_ioremap_resource(&pdev->dev, dev->res); @@ -1841,10 +1985,6 @@ static int cal_probe(struct platform_device *pdev) platform_set_drvdata(pdev, dev); - dev->cm = cm_create(dev); - if (IS_ERR(dev->cm)) - return PTR_ERR(dev->cm); - dev->cc[0] = cc_create(dev, 0); if (IS_ERR(dev->cc[0])) return PTR_ERR(dev->cc[0]); @@ -1924,7 +2064,10 @@ static int cal_remove(struct platform_device *pdev) #if defined(CONFIG_OF) static const struct of_device_id cal_of_match[] = { - { .compatible = "ti,dra72-cal", }, + { + .compatible = "ti,dra72-cal", + .data = (void *)&dra72x_cal_data, + }, {}, }; MODULE_DEVICE_TABLE(of, cal_of_match); From patchwork Fri Oct 18 15:34:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198747 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EF16B112C for ; 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Fri, 18 Oct 2019 10:32:06 -0500 From: Benoit Parrot To: Hans Verkuil , Rob Herring CC: , , , Benoit Parrot , Jyri Sarha Subject: [Patch 04/19] media: ti-vpe: cal: Enable DMABUF export Date: Fri, 18 Oct 2019 10:34:22 -0500 Message-ID: <20191018153437.20614-5-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018153437.20614-1-bparrot@ti.com> References: <20191018153437.20614-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Allow CAL to be able to export DMA buffer. Signed-off-by: Benoit Parrot Signed-off-by: Jyri Sarha --- drivers/media/platform/ti-vpe/cal.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 26f95a81e4ed..78fe2da61d77 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -1488,6 +1488,7 @@ static const struct v4l2_ioctl_ops cal_ioctl_ops = { .vidioc_querybuf = vb2_ioctl_querybuf, .vidioc_qbuf = vb2_ioctl_qbuf, .vidioc_dqbuf = vb2_ioctl_dqbuf, + .vidioc_expbuf = vb2_ioctl_expbuf, .vidioc_enum_input = cal_enum_input, .vidioc_g_input = cal_g_input, .vidioc_s_input = cal_s_input, From patchwork Fri Oct 18 15:34:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198743 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 043A7112C for ; Fri, 18 Oct 2019 15:33:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D9ECF222C6 for ; Fri, 18 Oct 2019 15:33:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="WM8Wf5U9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2634327AbfJRPdY (ORCPT ); Fri, 18 Oct 2019 11:33:24 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:47662 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2633187AbfJRPcK (ORCPT ); Fri, 18 Oct 2019 11:32:10 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW8QG013363; Fri, 18 Oct 2019 10:32:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571412728; bh=LoEq1nITaEuLag1pCdHbi9mndG1mH/UweEifXFbzijk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=WM8Wf5U9EypMRQPd4hycc4eY8Pn4lcwikNhoH3FaBEmxQ3hws+VO9cixIyRywS9vL yNLhGc4ppfgBszdWIEDKJfLyGFU/buXWK36LJkbojXzB07T1nutU8i5jqPxbxmviCO vqFqO7fO2Wm8sE2aZSPF1nZhWcJ9ZoB6nyyHzNKw= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9IFW8uw112697 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Oct 2019 10:32:08 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:32:00 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:32:08 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW15J080266; Fri, 18 Oct 2019 10:32:08 -0500 From: Benoit Parrot To: Hans Verkuil , Rob Herring CC: , , , Nikhil Devshatwar , Benoit Parrot Subject: [Patch 05/19] media: ti-vpe: cal: Restrict DMA to avoid memory corruption Date: Fri, 18 Oct 2019 10:34:23 -0500 Message-ID: <20191018153437.20614-6-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018153437.20614-1-bparrot@ti.com> References: <20191018153437.20614-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Nikhil Devshatwar When setting DMA for video capture from CSI channel, if the DMA size is not given, it ends up writing as much data as sent by the camera. This may lead to overwriting the buffers causing memory corruption. Observed green lines on the default framebuffer. Restrict the DMA to maximum height as specified in the S_FMT ioctl. Signed-off-by: Nikhil Devshatwar Signed-off-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 78fe2da61d77..62aeedb705e9 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -769,12 +769,13 @@ static void pix_proc_config(struct cal_ctx *ctx) } static void cal_wr_dma_config(struct cal_ctx *ctx, - unsigned int width) + unsigned int width, unsigned int height) { u32 val; val = reg_read(ctx->dev, CAL_WR_DMA_CTRL(ctx->csi2_port)); set_field(&val, ctx->csi2_port, CAL_WR_DMA_CTRL_CPORT_MASK); + set_field(&val, height, CAL_WR_DMA_CTRL_YSIZE_MASK); set_field(&val, CAL_WR_DMA_CTRL_DTAG_PIX_DAT, CAL_WR_DMA_CTRL_DTAG_MASK); set_field(&val, CAL_WR_DMA_CTRL_MODE_CONST, @@ -1397,7 +1398,8 @@ static int cal_start_streaming(struct vb2_queue *vq, unsigned int count) csi2_lane_config(ctx); csi2_ctx_config(ctx); pix_proc_config(ctx); - cal_wr_dma_config(ctx, ctx->v_fmt.fmt.pix.bytesperline); + cal_wr_dma_config(ctx, ctx->v_fmt.fmt.pix.bytesperline, + ctx->v_fmt.fmt.pix.height); cal_wr_dma_addr(ctx, addr); csi2_ppi_enable(ctx); From patchwork Fri Oct 18 15:34:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198739 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A0054112B for ; Fri, 18 Oct 2019 15:33:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 804CD222C6 for ; Fri, 18 Oct 2019 15:33:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="jHsdcfLY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2410623AbfJRPcO (ORCPT ); Fri, 18 Oct 2019 11:32:14 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:47674 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2633278AbfJRPcL (ORCPT ); Fri, 18 Oct 2019 11:32:11 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW9N4013374; Fri, 18 Oct 2019 10:32:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571412729; bh=uq1i+tWOuS4mskWSGZzRgqiAOAAKC9B8IF3qNOEobQw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jHsdcfLYcaRgy8ddrm1EwQL5JkP4OaF5gX/2vvnnbuFsz9Eix8zJkt25Cf7i4s+Jv BHUlmSrN/lZj1uzg9bPo93yLmuuoWjeHod82exjEopN+Tped7xrVzo8uxLfFigNQRD IbovdgaOiv8DUJf4yW/oN5Twn2X2cHADjmDVrYXE= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9IFW99c080454 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Oct 2019 10:32:09 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:32:01 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:32:01 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW15K080266; Fri, 18 Oct 2019 10:32:09 -0500 From: Benoit Parrot To: Hans Verkuil , Rob Herring CC: , , , Benoit Parrot , Jyri Sarha Subject: [Patch 06/19] dt-bindings: media: cal: update binding to add PHY LDO errata support Date: Fri, 18 Oct 2019 10:34:24 -0500 Message-ID: <20191018153437.20614-7-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018153437.20614-1-bparrot@ti.com> References: <20191018153437.20614-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Update Device Tree bindings for the CAL driver to add support for the CSI2 PHY LDO errata workaround for pre-es2 devices. Signed-off-by: Benoit Parrot Signed-off-by: Jyri Sarha Acked-by: Rob Herring --- Documentation/devicetree/bindings/media/ti-cal.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/ti-cal.txt b/Documentation/devicetree/bindings/media/ti-cal.txt index 6b56fddcfc4a..d43870a2324b 100644 --- a/Documentation/devicetree/bindings/media/ti-cal.txt +++ b/Documentation/devicetree/bindings/media/ti-cal.txt @@ -7,7 +7,9 @@ processing capability to connect CSI2 image-sensor modules to the DRA72x device. Required properties: -- compatible: must be "ti,dra72-cal" +- compatible: + Should be "ti,dra72-cal", for DRA72 controllers + Should be "ti,dra72-pre-es2-cal", for DRA72 controllers pre ES2.0 - reg: CAL Top level, Receiver Core #0, Receiver Core #1 and Camera RX control address space - reg-names: cal_top, cal_rx_core0, cal_rx_core1 and camerrx_control From patchwork Fri Oct 18 15:34:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198741 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A5095112B for ; Fri, 18 Oct 2019 15:33:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7C532222D3 for ; Fri, 18 Oct 2019 15:33:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="filJIWvV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2410615AbfJRPcN (ORCPT ); Fri, 18 Oct 2019 11:32:13 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:47682 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2633375AbfJRPcM (ORCPT ); Fri, 18 Oct 2019 11:32:12 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFWBQ7013383; Fri, 18 Oct 2019 10:32:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571412731; bh=ZJfZ53pYIRfGAB29qt+twF5p9lOD9hiLOcYLhuZ1TDo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=filJIWvVsvAVztE+/jMTuGWerVMYrSC2tkbDeJHz536mHKR3RV0fA+ivMWlIBddu8 Y8e6C2dqVQ0vvD1LY5U8/XwXmg0A8ZBFpIOuhzpgaaryLmFfwU8l2EN4nkONpNtuDS Fc0Zn5I2OoSMVtVinwSX3lHyuvYNuNCMaC3LIkb0= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9IFWB19080525 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Oct 2019 10:32:11 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:32:02 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:32:02 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW15L080266; Fri, 18 Oct 2019 10:32:10 -0500 From: Benoit Parrot To: Hans Verkuil , Rob Herring CC: , , , Benoit Parrot , Jyri Sarha Subject: [Patch 07/19] media: ti-vpe: cal: add CSI2 PHY LDO errata support Date: Fri, 18 Oct 2019 10:34:25 -0500 Message-ID: <20191018153437.20614-8-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018153437.20614-1-bparrot@ti.com> References: <20191018153437.20614-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Apply Errata i913 every time the functional clock is enabled. This should take care of suspend/resume case as well. Signed-off-by: Benoit Parrot Signed-off-by: Jyri Sarha --- drivers/media/platform/ti-vpe/cal.c | 56 +++++++++++++++++++++++- drivers/media/platform/ti-vpe/cal_regs.h | 27 ++++++++++++ 2 files changed, 82 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 62aeedb705e9..3cbc4dca6de8 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -284,6 +284,13 @@ static struct cal_data dra72x_cal_data = { .flags = 0, }; +static struct cal_data dra72x_es1_cal_data = { + .csi2_phy_core = dra72x_cal_csi_phy, + .num_csi2_phy = ARRAY_SIZE(dra72x_cal_csi_phy), + + .flags = DRA72_CAL_PRE_ES2_LDO_DISABLE, +}; + /* * there is one cal_dev structure in the driver, it is shared by * all instances. @@ -569,9 +576,52 @@ static void cal_get_hwinfo(struct cal_dev *dev) hwinfo); } +/* + * Errata i913: CSI2 LDO Needs to be disabled when module is powered on + * + * Enabling CSI2 LDO shorts it to core supply. It is crucial the 2 CSI2 + * LDOs on the device are disabled if CSI-2 module is powered on + * (0x4845 B304 | 0x4845 B384 [28:27] = 0x1) or in ULPS (0x4845 B304 + * | 0x4845 B384 [28:27] = 0x2) mode. Common concerns include: high + * current draw on the module supply in active mode. + * + * Errata does not apply when CSI-2 module is powered off + * (0x4845 B304 | 0x4845 B384 [28:27] = 0x0). + * + * SW Workaround: + * Set the following register bits to disable the LDO, + * which is essentially CSI2 REG10 bit 6: + * + * Core 0: 0x4845 B828 = 0x0000 0040 + * Core 1: 0x4845 B928 = 0x0000 0040 + */ +static void i913_errata(struct cal_dev *dev, unsigned int port) +{ + u32 reg10 = reg_read(dev->cc[port], CAL_CSI2_PHY_REG10); + + set_field(®10, CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE, + CAL_CSI2_PHY_REG10_I933_LDO_DISABLE_MASK); + + cal_dbg(1, dev, "CSI2_%d_REG10 = 0x%08x\n", port, reg10); + reg_write(dev->cc[port], CAL_CSI2_PHY_REG10, reg10); +} + static inline int cal_runtime_get(struct cal_dev *dev) { - return pm_runtime_get_sync(&dev->pdev->dev); + int r; + + r = pm_runtime_get_sync(&dev->pdev->dev); + + if (dev->flags & DRA72_CAL_PRE_ES2_LDO_DISABLE) { + /* + * Apply errata on both port eveytime we (re-)enable + * the clock + */ + i913_errata(dev, 0); + i913_errata(dev, 1); + } + + return r; } static inline void cal_runtime_put(struct cal_dev *dev) @@ -2071,6 +2121,10 @@ static const struct of_device_id cal_of_match[] = { .compatible = "ti,dra72-cal", .data = (void *)&dra72x_cal_data, }, + { + .compatible = "ti,dra72-pre-es2-cal", + .data = (void *)&dra72x_es1_cal_data, + }, {}, }; MODULE_DEVICE_TABLE(of, cal_of_match); diff --git a/drivers/media/platform/ti-vpe/cal_regs.h b/drivers/media/platform/ti-vpe/cal_regs.h index 68cfc922b422..78d6f015c9ea 100644 --- a/drivers/media/platform/ti-vpe/cal_regs.h +++ b/drivers/media/platform/ti-vpe/cal_regs.h @@ -10,6 +10,30 @@ #ifndef __TI_CAL_REGS_H #define __TI_CAL_REGS_H +/* + * struct cal_dev.flags possibilities + * + * DRA72_CAL_PRE_ES2_LDO_DISABLE: + * Errata i913: CSI2 LDO Needs to be disabled when module is powered on + * + * Enabling CSI2 LDO shorts it to core supply. It is crucial the 2 CSI2 + * LDOs on the device are disabled if CSI-2 module is powered on + * (0x4845 B304 | 0x4845 B384 [28:27] = 0x1) or in ULPS (0x4845 B304 + * | 0x4845 B384 [28:27] = 0x2) mode. Common concerns include: high + * current draw on the module supply in active mode. + * + * Errata does not apply when CSI-2 module is powered off + * (0x4845 B304 | 0x4845 B384 [28:27] = 0x0). + * + * SW Workaround: + * Set the following register bits to disable the LDO, + * which is essentially CSI2 REG10 bit 6: + * + * Core 0: 0x4845 B828 = 0x0000 0040 + * Core 1: 0x4845 B928 = 0x0000 0040 + */ +#define DRA72_CAL_PRE_ES2_LDO_DISABLE BIT(0) + #define CAL_NUM_CSI2_PORTS 2 /* CAL register offsets */ @@ -71,6 +95,7 @@ #define CAL_CSI2_PHY_REG0 0x000 #define CAL_CSI2_PHY_REG1 0x004 #define CAL_CSI2_PHY_REG2 0x008 +#define CAL_CSI2_PHY_REG10 0x028 /* CAL Control Module Core Camerrx Control register offsets */ #define CM_CTRL_CORE_CAMERRX_CONTROL 0x000 @@ -458,6 +483,8 @@ #define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_SUCCESS 0 #define CAL_CSI2_PHY_REG1_RESET_DONE_STATUS_MASK GENMASK(29, 28) +#define CAL_CSI2_PHY_REG10_I933_LDO_DISABLE_MASK BIT_MASK(6) + #define CAL_CSI2_PHY_REG2_CCP2_SYNC_PATTERN_MASK GENMASK(23, 0) #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC3_MASK GENMASK(25, 24) #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC2_MASK GENMASK(27, 26) From patchwork Fri Oct 18 15:34:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198737 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 31DDB112C for ; Fri, 18 Oct 2019 15:33:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0BEC72245A for ; Fri, 18 Oct 2019 15:33:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ZPr7sUPt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2410634AbfJRPcP (ORCPT ); Fri, 18 Oct 2019 11:32:15 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:40692 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2410600AbfJRPcO (ORCPT ); Fri, 18 Oct 2019 11:32:14 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFWC7r002673; Fri, 18 Oct 2019 10:32:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571412732; bh=snCJ1tnmbn2uyMmdiDmCwT4l4jUu5MQnjOFAlIELEyo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZPr7sUPt2KOd43fwV+QC3y29VzoO/2VymE1QfQY2H0cHzo97nVb5OvfogWL6wV3iV 7roI5RtXi2Ifw8IFmboQcVAV2B1yHJDsyLt5wM8e5gp3yAQC7cFPLo+w0G6GGNCVRt uKsIzHe3NAhcp45JNCv+E4Kd24g4SqmlderCAlHk= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFWCVE105748; Fri, 18 Oct 2019 10:32:12 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:32:03 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:32:03 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW15M080266; Fri, 18 Oct 2019 10:32:12 -0500 From: Benoit Parrot To: Hans Verkuil , Rob Herring CC: , , , Benoit Parrot Subject: [Patch 08/19] media: ti-vpe: cal: Fix ths_term/ths_settle parameters Date: Fri, 18 Oct 2019 10:34:26 -0500 Message-ID: <20191018153437.20614-9-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018153437.20614-1-bparrot@ti.com> References: <20191018153437.20614-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The current method to calculate the ddr clk period is wrong. Therefore the ths_term calculation is incorrect. Also it was wrongly assumed that the ths_settle parameter was based on the control clock instead of the pixel clock. Since the DPHY can tolerate quite a bit a of variation, capture was still mostly working with the 2 tested modes when the pixel clock was close to the control clock (i.e. 96 Mhz). But it would quickly stops working when using different modes or when customers used different sensors altogether. Calculating the DDRClk period needs to take into account the pixel bit width and the number of active data lanes. Based on the latest technical reference manual these parameters should now be calculated as follows: THS_TERM: Programmed value = floor(20 ns/DDRClk period) THS_SETTLE: Programmed value = floor(105 ns/DDRClk period) + 4 Also originally 'depth' was used to represent the number of bits a pixel would use once stored in memory (i.e. the container size). To accurately calculate the THS_* parameters we need to use the actual number of bits per pixels coming in from the sensor. So we are renaming 'depth' to 'bpp' (bits per pixels) and update the format table to show the actual number of bits per pixel being received. The "container" size will be derived from the "bpp" value. Signed-off-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 98 +++++++++++++---------------- 1 file changed, 44 insertions(+), 54 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 3cbc4dca6de8..5cc44c5b0ad8 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -73,8 +73,6 @@ static const struct v4l2_fract #define CAL_NUM_INPUT 1 #define CAL_NUM_CONTEXT 2 -#define bytes_per_line(pixel, bpp) (ALIGN(pixel * bpp, 16)) - #define reg_read(dev, offset) ioread32(dev->base + offset) #define reg_write(dev, offset, val) iowrite32(val, dev->base + offset) @@ -93,102 +91,103 @@ static const struct v4l2_fract struct cal_fmt { u32 fourcc; u32 code; - u8 depth; + /* Bits per pixel */ + u8 bpp; }; static struct cal_fmt cal_formats[] = { { .fourcc = V4L2_PIX_FMT_YUYV, .code = MEDIA_BUS_FMT_YUYV8_2X8, - .depth = 16, + .bpp = 16, }, { .fourcc = V4L2_PIX_FMT_UYVY, .code = MEDIA_BUS_FMT_UYVY8_2X8, - .depth = 16, + .bpp = 16, }, { .fourcc = V4L2_PIX_FMT_YVYU, .code = MEDIA_BUS_FMT_YVYU8_2X8, - .depth = 16, + .bpp = 16, }, { .fourcc = V4L2_PIX_FMT_VYUY, .code = MEDIA_BUS_FMT_VYUY8_2X8, - .depth = 16, + .bpp = 16, }, { .fourcc = V4L2_PIX_FMT_RGB565, /* gggbbbbb rrrrrggg */ .code = MEDIA_BUS_FMT_RGB565_2X8_LE, - .depth = 16, + .bpp = 16, }, { .fourcc = V4L2_PIX_FMT_RGB565X, /* rrrrrggg gggbbbbb */ .code = MEDIA_BUS_FMT_RGB565_2X8_BE, - .depth = 16, + .bpp = 16, }, { .fourcc = V4L2_PIX_FMT_RGB555, /* gggbbbbb arrrrrgg */ .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, - .depth = 16, + .bpp = 16, }, { .fourcc = V4L2_PIX_FMT_RGB555X, /* arrrrrgg gggbbbbb */ .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, - .depth = 16, + .bpp = 16, }, { .fourcc = V4L2_PIX_FMT_RGB24, /* rgb */ .code = MEDIA_BUS_FMT_RGB888_2X12_LE, - .depth = 24, + .bpp = 24, }, { .fourcc = V4L2_PIX_FMT_BGR24, /* bgr */ .code = MEDIA_BUS_FMT_RGB888_2X12_BE, - .depth = 24, + .bpp = 24, }, { .fourcc = V4L2_PIX_FMT_RGB32, /* argb */ .code = MEDIA_BUS_FMT_ARGB8888_1X32, - .depth = 32, + .bpp = 32, }, { .fourcc = V4L2_PIX_FMT_SBGGR8, .code = MEDIA_BUS_FMT_SBGGR8_1X8, - .depth = 8, + .bpp = 8, }, { .fourcc = V4L2_PIX_FMT_SGBRG8, .code = MEDIA_BUS_FMT_SGBRG8_1X8, - .depth = 8, + .bpp = 8, }, { .fourcc = V4L2_PIX_FMT_SGRBG8, .code = MEDIA_BUS_FMT_SGRBG8_1X8, - .depth = 8, + .bpp = 8, }, { .fourcc = V4L2_PIX_FMT_SRGGB8, .code = MEDIA_BUS_FMT_SRGGB8_1X8, - .depth = 8, + .bpp = 8, }, { .fourcc = V4L2_PIX_FMT_SBGGR10, .code = MEDIA_BUS_FMT_SBGGR10_1X10, - .depth = 16, + .bpp = 10, }, { .fourcc = V4L2_PIX_FMT_SGBRG10, .code = MEDIA_BUS_FMT_SGBRG10_1X10, - .depth = 16, + .bpp = 10, }, { .fourcc = V4L2_PIX_FMT_SGRBG10, .code = MEDIA_BUS_FMT_SGRBG10_1X10, - .depth = 16, + .bpp = 10, }, { .fourcc = V4L2_PIX_FMT_SRGGB10, .code = MEDIA_BUS_FMT_SRGGB10_1X10, - .depth = 16, + .bpp = 10, }, { .fourcc = V4L2_PIX_FMT_SBGGR12, .code = MEDIA_BUS_FMT_SBGGR12_1X12, - .depth = 16, + .bpp = 12, }, { .fourcc = V4L2_PIX_FMT_SGBRG12, .code = MEDIA_BUS_FMT_SGBRG12_1X12, - .depth = 16, + .bpp = 12, }, { .fourcc = V4L2_PIX_FMT_SGRBG12, .code = MEDIA_BUS_FMT_SGRBG12_1X12, - .depth = 16, + .bpp = 12, }, { .fourcc = V4L2_PIX_FMT_SRGGB12, .code = MEDIA_BUS_FMT_SRGGB12_1X12, - .depth = 16, + .bpp = 12, }, }; @@ -873,41 +872,28 @@ static void cal_wr_dma_addr(struct cal_ctx *ctx, unsigned int dmaaddr) #define TCLK_TERM 0 #define TCLK_MISS 1 #define TCLK_SETTLE 14 -#define THS_SETTLE 15 static void csi2_phy_config(struct cal_ctx *ctx) { unsigned int reg0, reg1; unsigned int ths_term, ths_settle; - unsigned int ddrclkperiod_us; + unsigned int csi2_ddrclk_khz; + struct v4l2_fwnode_bus_mipi_csi2 *mipi_csi2 = + &ctx->endpoint.bus.mipi_csi2; + u32 num_lanes = mipi_csi2->num_data_lanes; - /* - * THS_TERM: Programmed value = floor(20 ns/DDRClk period) - 2. - */ - ddrclkperiod_us = ctx->external_rate / 2000000; - ddrclkperiod_us = 1000000 / ddrclkperiod_us; - ctx_dbg(1, ctx, "ddrclkperiod_us: %d\n", ddrclkperiod_us); + /* DPHY timing configuration */ + /* CSI-2 is DDR and we only count used lanes. */ + csi2_ddrclk_khz = ctx->external_rate / 1000 + / (2 * num_lanes) * ctx->fmt->bpp; + ctx_dbg(1, ctx, "csi2_ddrclk_khz: %d\n", csi2_ddrclk_khz); - ths_term = 20000 / ddrclkperiod_us; - ths_term = (ths_term >= 2) ? ths_term - 2 : ths_term; + /* THS_TERM: Programmed value = floor(20 ns/DDRClk period) */ + ths_term = 20 * csi2_ddrclk_khz / 1000000; ctx_dbg(1, ctx, "ths_term: %d (0x%02x)\n", ths_term, ths_term); - /* - * THS_SETTLE: Programmed value = floor(176.3 ns/CtrlClk period) - 1. - * Since CtrlClk is fixed at 96Mhz then we get - * ths_settle = floor(176.3 / 10.416) - 1 = 15 - * If we ever switch to a dynamic clock then this code might be useful - * - * unsigned int ctrlclkperiod_us; - * ctrlclkperiod_us = 96000000 / 1000000; - * ctrlclkperiod_us = 1000000 / ctrlclkperiod_us; - * ctx_dbg(1, ctx, "ctrlclkperiod_us: %d\n", ctrlclkperiod_us); - - * ths_settle = 176300 / ctrlclkperiod_us; - * ths_settle = (ths_settle > 1) ? ths_settle - 1 : ths_settle; - */ - - ths_settle = THS_SETTLE; + /* THS_SETTLE: Programmed value = floor(105 ns/DDRClk period) + 4 */ + ths_settle = (105 * csi2_ddrclk_khz / 1000000) + 4; ctx_dbg(1, ctx, "ths_settle: %d (0x%02x)\n", ths_settle, ths_settle); reg0 = reg_read(ctx->cc, CAL_CSI2_PHY_REG0); @@ -1119,6 +1105,8 @@ static int cal_calc_format_size(struct cal_ctx *ctx, const struct cal_fmt *fmt, struct v4l2_format *f) { + u32 bpl; + if (!fmt) { ctx_dbg(3, ctx, "No cal_fmt provided!\n"); return -EINVAL; @@ -1126,8 +1114,10 @@ static int cal_calc_format_size(struct cal_ctx *ctx, v4l_bound_align_image(&f->fmt.pix.width, 48, MAX_WIDTH, 2, &f->fmt.pix.height, 32, MAX_HEIGHT, 0, 0); - f->fmt.pix.bytesperline = bytes_per_line(f->fmt.pix.width, - fmt->depth >> 3); + + bpl = (f->fmt.pix.width * ALIGN(fmt->bpp, 8)) >> 3; + f->fmt.pix.bytesperline = ALIGN(bpl, 16); + f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; From patchwork Fri Oct 18 15:34:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198735 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C93E3112C for ; Fri, 18 Oct 2019 15:33:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A9D25222C6 for ; Fri, 18 Oct 2019 15:33:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="QxUYLsLx" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2633634AbfJRPdK (ORCPT ); Fri, 18 Oct 2019 11:33:10 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:40702 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2410630AbfJRPcP (ORCPT ); Fri, 18 Oct 2019 11:32:15 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFWDSM002679; Fri, 18 Oct 2019 10:32:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571412733; bh=F50/RQJNOxsnpe90vtLT83eiWsQ06kHCDvs+8O3qD8k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=QxUYLsLxGIGWjQZzSjm+XkKfEzDkjaDaBXY8X1L16m+RciRnKNnoX59SOuMwrNC9a LQqQ0biidUQCHn5z+opbxMkPElZvdJEWfcgYGPXSKpkIsrihwCRNFEXQfkKwrTsdk0 K4qw8PIfBVASb6mEzI9ghX4gBBeneeMyON7v5IS8= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9IFWDnw112849 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Oct 2019 10:32:13 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:32:05 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:32:05 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW15N080266; Fri, 18 Oct 2019 10:32:13 -0500 From: Benoit Parrot To: Hans Verkuil , Rob Herring CC: , , , Benoit Parrot Subject: [Patch 09/19] media: ti-vpe: cal: Fix pixel processing parameters Date: Fri, 18 Oct 2019 10:34:27 -0500 Message-ID: <20191018153437.20614-10-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018153437.20614-1-bparrot@ti.com> References: <20191018153437.20614-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The pixel processing unit was hard coded to only handle 8 bits per pixel from input to output. We now add handling for 10, 12 and 16 bits per pixel at the source and setting the in-memory size (i.e. container size) to 16 bits for these 3 cases. Signed-off-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 41 ++++++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 5cc44c5b0ad8..3c293e263397 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -803,13 +803,48 @@ static void csi2_ctx_config(struct cal_ctx *ctx) static void pix_proc_config(struct cal_ctx *ctx) { - u32 val; + u32 val, extract, pack; + + switch (ctx->fmt->bpp) { + case 8: + extract = CAL_PIX_PROC_EXTRACT_B8; + pack = CAL_PIX_PROC_PACK_B8; + break; + case 10: + extract = CAL_PIX_PROC_EXTRACT_B10_MIPI; + pack = CAL_PIX_PROC_PACK_B16; + break; + case 12: + extract = CAL_PIX_PROC_EXTRACT_B12_MIPI; + pack = CAL_PIX_PROC_PACK_B16; + break; + case 16: + extract = CAL_PIX_PROC_EXTRACT_B16_LE; + pack = CAL_PIX_PROC_PACK_B16; + break; + default: + /* + * If you see this warning then it means that you added + * some new entry in the cal_formats[] array with a different + * bit per pixel values then the one supported below. + * Either add support for the new bpp value below or adjust + * the new entry to use one of the value below. + * + * Instead of failing here just use 8 bpp as a default. + */ + dev_warn_once(&ctx->dev->pdev->dev, + "%s:%d:%s: bpp:%d unsupported! Overwritten with 8.\n", + __FILE__, __LINE__, __func__, ctx->fmt->bpp); + extract = CAL_PIX_PROC_EXTRACT_B8; + pack = CAL_PIX_PROC_PACK_B8; + break; + } val = reg_read(ctx->dev, CAL_PIX_PROC(ctx->csi2_port)); - set_field(&val, CAL_PIX_PROC_EXTRACT_B8, CAL_PIX_PROC_EXTRACT_MASK); + set_field(&val, extract, CAL_PIX_PROC_EXTRACT_MASK); set_field(&val, CAL_PIX_PROC_DPCMD_BYPASS, CAL_PIX_PROC_DPCMD_MASK); set_field(&val, CAL_PIX_PROC_DPCME_BYPASS, CAL_PIX_PROC_DPCME_MASK); - set_field(&val, CAL_PIX_PROC_PACK_B8, CAL_PIX_PROC_PACK_MASK); + set_field(&val, pack, CAL_PIX_PROC_PACK_MASK); set_field(&val, ctx->csi2_port, CAL_PIX_PROC_CPORT_MASK); set_field(&val, CAL_GEN_ENABLE, CAL_PIX_PROC_EN_MASK); reg_write(ctx->dev, CAL_PIX_PROC(ctx->csi2_port), val); From patchwork Fri Oct 18 15:34:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198733 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 479BE112B for ; Fri, 18 Oct 2019 15:33:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 18695222C5 for ; Fri, 18 Oct 2019 15:33:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="dO1fOncv" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2410723AbfJRPdD (ORCPT ); Fri, 18 Oct 2019 11:33:03 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:44798 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2410637AbfJRPcR (ORCPT ); Fri, 18 Oct 2019 11:32:17 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFWEWh117080; Fri, 18 Oct 2019 10:32:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571412734; bh=vQXelJibkXd5wKVqcEHkVbrn+8AeeTrkzg5vYTTtFQ4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dO1fOncvqyKu2UqiOAtditUNJ0CYuxQwdC0XrUipYeACWQC+PTnID2JtSoWI8Raou ifTBnyJ/FfkDfUoW8/Nnh5lGXSgfjAE+6wXmcwZXzQs6K/WBmk8TpxNPlsd/eG1DK2 Jj5VYA430ZSDJc5Ks2voCFp/C+gfTYXk5n5h0arw= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFWExT105850; Fri, 18 Oct 2019 10:32:14 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:32:06 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:32:14 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW15O080266; Fri, 18 Oct 2019 10:32:14 -0500 From: Benoit Parrot To: Hans Verkuil , Rob Herring CC: , , , Benoit Parrot Subject: [Patch 10/19] media: ti-vpe: cal: Align DPHY init sequence with docs Date: Fri, 18 Oct 2019 10:34:28 -0500 Message-ID: <20191018153437.20614-11-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018153437.20614-1-bparrot@ti.com> References: <20191018153437.20614-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The current CSI2 DPHY initialization sequence although functional does not match with the documented sequence in the Technical Reference Manual. This may affect capture re-startability in stop/start situations. Signed-off-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 199 ++++++++++++++++++++++++---- 1 file changed, 172 insertions(+), 27 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 3c293e263397..c912ea82b534 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -689,29 +689,76 @@ static void disable_irqs(struct cal_ctx *ctx) reg_write(ctx->dev, CAL_CSI2_VC_IRQENABLE(1), 0); } -static void csi2_init(struct cal_ctx *ctx) +static void csi2_phy_config(struct cal_ctx *ctx); + +static void csi2_phy_init(struct cal_ctx *ctx) { int i; u32 val; + /* Steps + * 1. Configure D-PHY mode and enable required lanes + * 2. Reset complex IO - Wait for completion of reset + * Note if the external sensor is not sending byte clock, + * the reset will timeout + * 3 Program Stop States + * A. Program THS_TERM, THS_SETTLE, etc... Timings parameters + * in terms of DDR clock periods + * B. Enable stop state transition timeouts + * 4.Force FORCERXMODE + * D. Enable pull down using pad control + * E. Power up PHY + * F. Wait for power up completion + * G. Wait for all enabled lane to reach stop state + * H. Disable pull down using pad control + */ + + /* 1. Configure D-PHY mode and enable required lanes */ + camerarx_phy_enable(ctx); + + /* 2. Reset complex IO - Do not wait for reset completion */ + val = reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)); + set_field(&val, CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_OPERATIONAL, + CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK); + reg_write(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), val); + ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x De-assert Complex IO Reset\n", + ctx->csi2_port, + reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port))); + + /* Dummy read to allow SCP to complete */ + val = reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)); + + /* 3.A. Program Phy Timing Parameters */ + csi2_phy_config(ctx); + + /* 3.B. Program Stop States */ val = reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port)); - set_field(&val, CAL_GEN_ENABLE, - CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK); set_field(&val, CAL_GEN_ENABLE, CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK); set_field(&val, CAL_GEN_DISABLE, CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK); set_field(&val, 407, CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK); reg_write(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), val); - ctx_dbg(3, ctx, "CAL_CSI2_TIMING(%d) = 0x%08x\n", ctx->csi2_port, + ctx_dbg(3, ctx, "CAL_CSI2_TIMING(%d) = 0x%08x Stop States\n", + ctx->csi2_port, + reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port))); + + /* 4. Force FORCERXMODE */ + val = reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port)); + set_field(&val, CAL_GEN_ENABLE, + CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK); + reg_write(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), val); + ctx_dbg(3, ctx, "CAL_CSI2_TIMING(%d) = 0x%08x Force RXMODE\n", + ctx->csi2_port, reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port))); + /* E. Power up the PHY using the complex IO */ val = reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)); - set_field(&val, CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_OPERATIONAL, - CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK); set_field(&val, CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON, CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK); reg_write(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), val); + + /* F. Wait for power up completion */ for (i = 0; i < 10; i++) { if (reg_read_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), @@ -720,18 +767,104 @@ static void csi2_init(struct cal_ctx *ctx) break; usleep_range(1000, 1100); } - ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x\n", ctx->csi2_port, - reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port))); + ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Powered UP %s\n", + ctx->csi2_port, + reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)), + (i >= 10) ? "(timeout)" : ""); +} - val = reg_read(ctx->dev, CAL_CTRL); - set_field(&val, CAL_CTRL_BURSTSIZE_BURST128, CAL_CTRL_BURSTSIZE_MASK); - set_field(&val, 0xF, CAL_CTRL_TAGCNT_MASK); - set_field(&val, CAL_CTRL_POSTED_WRITES_NONPOSTED, - CAL_CTRL_POSTED_WRITES_MASK); - set_field(&val, 0xFF, CAL_CTRL_MFLAGL_MASK); - set_field(&val, 0xFF, CAL_CTRL_MFLAGH_MASK); - reg_write(ctx->dev, CAL_CTRL, val); - ctx_dbg(3, ctx, "CAL_CTRL = 0x%08x\n", reg_read(ctx->dev, CAL_CTRL)); +static void csi2_wait_for_phy(struct cal_ctx *ctx) +{ + int i; + + /* Steps + * 2. Wait for completion of reset + * Note if the external sensor is not sending byte clock, + * the reset will timeout + * 4.Force FORCERXMODE + * G. Wait for all enabled lane to reach stop state + * H. Disable pull down using pad control + */ + + /* 2. Wait for reset completion */ + for (i = 0; i < 250; i++) { + if (reg_read_field(ctx->dev, + CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), + CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) == + CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED) + break; + usleep_range(1000, 1100); + } + ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO Reset Done (%d) %s\n", + ctx->csi2_port, + reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)), i, + (i >= 250) ? "(timeout)" : ""); + + /* 4. G. Wait for all enabled lane to reach stop state */ + for (i = 0; i < 10; i++) { + if (reg_read_field(ctx->dev, + CAL_CSI2_TIMING(ctx->csi2_port), + CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) == + CAL_GEN_DISABLE) + break; + usleep_range(1000, 1100); + } + ctx_dbg(3, ctx, "CAL_CSI2_TIMING(%d) = 0x%08x Stop State Reached %s\n", + ctx->csi2_port, + reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port)), + (i >= 10) ? "(timeout)" : ""); + + ctx_dbg(1, ctx, "CSI2_%d_REG1 = 0x%08x (Bit(31,28) should be set!)\n", + (ctx->csi2_port - 1), reg_read(ctx->cc, CAL_CSI2_PHY_REG1)); +} + +static void csi2_phy_deinit(struct cal_ctx *ctx) +{ + int i; + u32 val; + + /* Power down the PHY using the complex IO */ + val = reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)); + set_field(&val, CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF, + CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK); + reg_write(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), val); + + /* Wait for power down completion */ + for (i = 0; i < 10; i++) { + if (reg_read_field(ctx->dev, + CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), + CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK) == + CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_OFF) + break; + usleep_range(1000, 1100); + } + ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Powered Down %s\n", + ctx->csi2_port, + reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)), + (i >= 10) ? "(timeout)" : ""); + + /* Assert Comple IO Reset */ + val = reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)); + set_field(&val, CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL, + CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK); + reg_write(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), val); + + /* Wait for power down completion */ + for (i = 0; i < 10; i++) { + if (reg_read_field(ctx->dev, + CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), + CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) == + CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETONGOING) + break; + usleep_range(1000, 1100); + } + ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO in Reset (%d) %s\n", + ctx->csi2_port, + reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)), i, + (i >= 10) ? "(timeout)" : ""); + + /* Disable the phy */ + camerarx_phy_disable(ctx); } static void csi2_lane_config(struct cal_ctx *ctx) @@ -894,6 +1027,16 @@ static void cal_wr_dma_config(struct cal_ctx *ctx, reg_write(ctx->dev, CAL_WR_DMA_XSIZE(ctx->csi2_port), val); ctx_dbg(3, ctx, "CAL_WR_DMA_XSIZE(%d) = 0x%08x\n", ctx->csi2_port, reg_read(ctx->dev, CAL_WR_DMA_XSIZE(ctx->csi2_port))); + + val = reg_read(ctx->dev, CAL_CTRL); + set_field(&val, CAL_CTRL_BURSTSIZE_BURST128, CAL_CTRL_BURSTSIZE_MASK); + set_field(&val, 0xF, CAL_CTRL_TAGCNT_MASK); + set_field(&val, CAL_CTRL_POSTED_WRITES_NONPOSTED, + CAL_CTRL_POSTED_WRITES_MASK); + set_field(&val, 0xFF, CAL_CTRL_MFLAGL_MASK); + set_field(&val, 0xFF, CAL_CTRL_MFLAGH_MASK); + reg_write(ctx->dev, CAL_CTRL, val); + ctx_dbg(3, ctx, "CAL_CTRL = 0x%08x\n", reg_read(ctx->dev, CAL_CTRL)); } static void cal_wr_dma_addr(struct cal_ctx *ctx, unsigned int dmaaddr) @@ -1466,17 +1609,14 @@ static int cal_start_streaming(struct vb2_queue *vq, unsigned int count) cal_runtime_get(ctx->dev); - enable_irqs(ctx); - camerarx_phy_enable(ctx); - csi2_init(ctx); - csi2_phy_config(ctx); - csi2_lane_config(ctx); csi2_ctx_config(ctx); pix_proc_config(ctx); cal_wr_dma_config(ctx, ctx->v_fmt.fmt.pix.bytesperline, ctx->v_fmt.fmt.pix.height); - cal_wr_dma_addr(ctx, addr); - csi2_ppi_enable(ctx); + csi2_lane_config(ctx); + + enable_irqs(ctx); + csi2_phy_init(ctx); ret = v4l2_subdev_call(ctx->sensor, video, s_stream, 1); if (ret) { @@ -1485,6 +1625,10 @@ static int cal_start_streaming(struct vb2_queue *vq, unsigned int count) goto err; } + csi2_wait_for_phy(ctx); + cal_wr_dma_addr(ctx, addr); + csi2_ppi_enable(ctx); + if (debug >= 4) cal_quickdump_regs(ctx->dev); @@ -1505,11 +1649,12 @@ static void cal_stop_streaming(struct vb2_queue *vq) struct cal_buffer *buf, *tmp; unsigned long flags; - if (v4l2_subdev_call(ctx->sensor, video, s_stream, 0)) - ctx_err(ctx, "stream off failed in subdev\n"); - csi2_ppi_disable(ctx); disable_irqs(ctx); + csi2_phy_deinit(ctx); + + if (v4l2_subdev_call(ctx->sensor, video, s_stream, 0)) + ctx_err(ctx, "stream off failed in subdev\n"); /* Release all active buffers */ spin_lock_irqsave(&ctx->slock, flags); From patchwork Fri Oct 18 15:34:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198715 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DCCC9112C for ; Fri, 18 Oct 2019 15:32:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BDE72222D2 for ; Fri, 18 Oct 2019 15:32:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="nWU0iafn" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2410665AbfJRPcU (ORCPT ); Fri, 18 Oct 2019 11:32:20 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:37106 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2410644AbfJRPcR (ORCPT ); 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Fri, 18 Oct 2019 10:32:07 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW15P080266; Fri, 18 Oct 2019 10:32:15 -0500 From: Benoit Parrot To: Hans Verkuil , Rob Herring CC: , , , Benoit Parrot Subject: [Patch 11/19] dt-bindings: media: cal: update binding to add DRA76x support Date: Fri, 18 Oct 2019 10:34:29 -0500 Message-ID: <20191018153437.20614-12-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018153437.20614-1-bparrot@ti.com> References: <20191018153437.20614-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Update Device Tree bindings for the CAL driver to add DRA76x support. Signed-off-by: Benoit Parrot Acked-by: Rob Herring --- Documentation/devicetree/bindings/media/ti-cal.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/media/ti-cal.txt b/Documentation/devicetree/bindings/media/ti-cal.txt index d43870a2324b..29fbbfb8be0d 100644 --- a/Documentation/devicetree/bindings/media/ti-cal.txt +++ b/Documentation/devicetree/bindings/media/ti-cal.txt @@ -10,6 +10,7 @@ Required properties: - compatible: Should be "ti,dra72-cal", for DRA72 controllers Should be "ti,dra72-pre-es2-cal", for DRA72 controllers pre ES2.0 + Should be "ti,dra76-cal", for DRA76 controllers - reg: CAL Top level, Receiver Core #0, Receiver Core #1 and Camera RX control address space - reg-names: cal_top, cal_rx_core0, cal_rx_core1 and camerrx_control From patchwork Fri Oct 18 15:34:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198729 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 02752112C for ; Fri, 18 Oct 2019 15:32:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D7090222C5 for ; Fri, 18 Oct 2019 15:32:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="LdSLvwMj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2410661AbfJRPcU (ORCPT ); Fri, 18 Oct 2019 11:32:20 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:40708 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2410600AbfJRPcS (ORCPT ); Fri, 18 Oct 2019 11:32:18 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFWHFJ002693; Fri, 18 Oct 2019 10:32:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571412737; bh=fOWgVpmqUokvYHMT4mlXfALvalPrfwrOzlcnd0f6R94=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LdSLvwMjC2eEIRq+N0l9Hwc4wiAYwGpdQKt+K/Jq56PKrAm/ugExFfOLwQ/X7zyHP ++MWtOC4jJX342xnugGdWx8ZlsXdsIFWm1yagj5AbJbSDt3HRbjSfi0ymTbsnBj7tc zbTQYFK+zSWZacUy58VAVrHrI8Hs2WQHuSF82iY8= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFWH0O105954; Fri, 18 Oct 2019 10:32:17 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:32:08 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:32:17 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW15Q080266; Fri, 18 Oct 2019 10:32:17 -0500 From: Benoit Parrot To: Hans Verkuil , Rob Herring CC: , , , Benoit Parrot Subject: [Patch 12/19] media: ti-vpe: cal: Add DRA76x support Date: Fri, 18 Oct 2019 10:34:30 -0500 Message-ID: <20191018153437.20614-13-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018153437.20614-1-bparrot@ti.com> References: <20191018153437.20614-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add the needed control module register bit layout to support the DRA76x family of devices. Signed-off-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 36 +++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index c912ea82b534..f590fe712d3d 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -290,6 +290,38 @@ static struct cal_data dra72x_es1_cal_data = { .flags = DRA72_CAL_PRE_ES2_LDO_DISABLE, }; +static struct reg_field dra76x_ctrl_core_csi0_reg_fields[F_MAX_FIELDS] = { + [F_CTRLCLKEN] = REG_FIELD(0, 8, 8), + [F_CAMMODE] = REG_FIELD(0, 9, 10), + [F_CSI_MODE] = REG_FIELD(0, 11, 11), + [F_LANEENABLE] = REG_FIELD(0, 27, 31), +}; + +static struct reg_field dra76x_ctrl_core_csi1_reg_fields[F_MAX_FIELDS] = { + [F_CTRLCLKEN] = REG_FIELD(0, 0, 0), + [F_CAMMODE] = REG_FIELD(0, 1, 2), + [F_CSI_MODE] = REG_FIELD(0, 3, 3), + [F_LANEENABLE] = REG_FIELD(0, 24, 26), +}; + +static struct cal_csi2_phy dra76x_cal_csi_phy[] = { + { + .base_fields = dra76x_ctrl_core_csi0_reg_fields, + .num_lanes = 5, + }, + { + .base_fields = dra76x_ctrl_core_csi1_reg_fields, + .num_lanes = 3, + }, +}; + +static struct cal_data dra76x_cal_data = { + .csi2_phy_core = dra76x_cal_csi_phy, + .num_csi2_phy = ARRAY_SIZE(dra76x_cal_csi_phy), + + .flags = 0, +}; + /* * there is one cal_dev structure in the driver, it is shared by * all instances. @@ -2295,6 +2327,10 @@ static const struct of_device_id cal_of_match[] = { .compatible = "ti,dra72-pre-es2-cal", .data = (void *)&dra72x_es1_cal_data, }, + { + .compatible = "ti,dra76-cal", + .data = (void *)&dra76x_cal_data, + }, {}, }; MODULE_DEVICE_TABLE(of, cal_of_match); From patchwork Fri Oct 18 15:34:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198731 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D3C34112C for ; Fri, 18 Oct 2019 15:33:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B4401222C5 for ; Fri, 18 Oct 2019 15:33:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="YfN3c+9r" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2505155AbfJRPc5 (ORCPT ); Fri, 18 Oct 2019 11:32:57 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:47696 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2410656AbfJRPcU (ORCPT ); Fri, 18 Oct 2019 11:32:20 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFWIjn013401; Fri, 18 Oct 2019 10:32:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571412738; bh=ocDig6m7hMxk+9WkuMz+XpgOO+fIPZp9QBn6JbkNoi4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=YfN3c+9rI0baegP+xudYb332XR5vyrO3mx/gaFpsSz8T05Jaqr4TkRkmK4OmgGBv3 bC0bDJtXc7baRJINnUdmssnOAuf95kxu1UqR8znZeoPrCtGjJw2X+GQRBJqAXll1i6 YSGx//VAqx6ZTe3ZXggo2tyT1QkUE4WMFbNI1srU= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9IFWIxH080798 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Oct 2019 10:32:18 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:32:10 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:32:10 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW15R080266; Fri, 18 Oct 2019 10:32:18 -0500 From: Benoit Parrot To: Hans Verkuil , Rob Herring CC: , , , Benoit Parrot Subject: [Patch 13/19] dt-bindings: media: cal: update binding to add AM654 support Date: Fri, 18 Oct 2019 10:34:31 -0500 Message-ID: <20191018153437.20614-14-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018153437.20614-1-bparrot@ti.com> References: <20191018153437.20614-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Update Device Tree bindings for the CAL driver to add AM654 support. Signed-off-by: Benoit Parrot Acked-by: Rob Herring --- Documentation/devicetree/bindings/media/ti-cal.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/media/ti-cal.txt b/Documentation/devicetree/bindings/media/ti-cal.txt index 29fbbfb8be0d..b7bf8492dc2a 100644 --- a/Documentation/devicetree/bindings/media/ti-cal.txt +++ b/Documentation/devicetree/bindings/media/ti-cal.txt @@ -11,6 +11,7 @@ Required properties: Should be "ti,dra72-cal", for DRA72 controllers Should be "ti,dra72-pre-es2-cal", for DRA72 controllers pre ES2.0 Should be "ti,dra76-cal", for DRA76 controllers + Should be "ti,am654-cal", for AM654 controllers - reg: CAL Top level, Receiver Core #0, Receiver Core #1 and Camera RX control address space - reg-names: cal_top, cal_rx_core0, cal_rx_core1 and camerrx_control From patchwork Fri Oct 18 15:34:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198725 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D63AD112C for ; Fri, 18 Oct 2019 15:32:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B661A222CD for ; Fri, 18 Oct 2019 15:32:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ZevOt9ld" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2410677AbfJRPcW (ORCPT ); Fri, 18 Oct 2019 11:32:22 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:44830 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2410668AbfJRPcV (ORCPT ); Fri, 18 Oct 2019 11:32:21 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFWKdO117113; Fri, 18 Oct 2019 10:32:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571412740; bh=r5gqWhuoa2gJ1iIJ0GdWbvBLizT1eB9GcyotAuDXfac=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZevOt9ld7M6nhyVxwr0+s5B4kZMvbBXn5HnHbyFB4xtictTSPFXTW55WeDj6fb+2c l4jiV/foNA+TTitr0Rfk9uPNZCutVfK7ifEzeTkrEaC7Wy+BVW7KZxJAii2QFxabbf pbfapOvCI/n473Jner3xOS6dSOF122C8cv2f93e4= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9IFWKab080890 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Oct 2019 10:32:20 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:32:11 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:32:11 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW15S080266; Fri, 18 Oct 2019 10:32:19 -0500 From: Benoit Parrot To: Hans Verkuil , Rob Herring CC: , , , Benoit Parrot Subject: [Patch 14/19] media: ti-vpe: cal: Add AM654 support Date: Fri, 18 Oct 2019 10:34:32 -0500 Message-ID: <20191018153437.20614-15-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018153437.20614-1-bparrot@ti.com> References: <20191018153437.20614-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add the needed control module register bit layout to support the AM654 family of devices. Signed-off-by: Benoit Parrot --- drivers/media/platform/Kconfig | 2 +- drivers/media/platform/ti-vpe/cal.c | 28 +++++++++++++++++++++++++++- 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index 997de1a83ff9..24713e79c1ec 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -151,7 +151,7 @@ source "drivers/media/platform/sunxi/Kconfig" config VIDEO_TI_CAL tristate "TI CAL (Camera Adaptation Layer) driver" depends on VIDEO_DEV && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API - depends on SOC_DRA7XX || COMPILE_TEST + depends on SOC_DRA7XX || ARCH_K3 || COMPILE_TEST select VIDEOBUF2_DMA_CONTIG select V4L2_FWNODE help diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index f590fe712d3d..42b0063b610e 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -322,6 +322,26 @@ static struct cal_data dra76x_cal_data = { .flags = 0, }; +static struct reg_field am654_ctrl_core_csi0_reg_fields[F_MAX_FIELDS] = { + [F_CTRLCLKEN] = REG_FIELD(0, 15, 15), + [F_CAMMODE] = REG_FIELD(0, 24, 25), + [F_LANEENABLE] = REG_FIELD(0, 0, 4), +}; + +static struct cal_csi2_phy am654_cal_csi_phy[] = { + { + .base_fields = am654_ctrl_core_csi0_reg_fields, + .num_lanes = 5, + }, +}; + +static struct cal_data am654_cal_data = { + .csi2_phy_core = am654_cal_csi_phy, + .num_csi2_phy = ARRAY_SIZE(am654_cal_csi_phy), + + .flags = 0, +}; + /* * there is one cal_dev structure in the driver, it is shared by * all instances. @@ -548,7 +568,9 @@ static void camerarx_phy_enable(struct cal_ctx *ctx) /* Always enable all lanes at the phy control level */ max_lanes = (1 << cal_data_get_phy_max_lanes(ctx)) - 1; regmap_field_write(phy->fields[F_LANEENABLE], max_lanes); - regmap_field_write(phy->fields[F_CSI_MODE], 1); + /* F_CSI_MODE is not present on every architecture */ + if (phy->fields[F_CSI_MODE]) + regmap_field_write(phy->fields[F_CSI_MODE], 1); regmap_field_write(phy->fields[F_CTRLCLKEN], 1); } @@ -2331,6 +2353,10 @@ static const struct of_device_id cal_of_match[] = { .compatible = "ti,dra76-cal", .data = (void *)&dra76x_cal_data, }, + { + .compatible = "ti,am654-cal", + .data = (void *)&am654_cal_data, + }, {}, }; MODULE_DEVICE_TABLE(of, cal_of_match); From patchwork Fri Oct 18 15:34:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198727 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 99ECA112B for ; Fri, 18 Oct 2019 15:32:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7A149222C5 for ; Fri, 18 Oct 2019 15:32:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="I24zH4pm" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2633495AbfJRPcu (ORCPT ); Fri, 18 Oct 2019 11:32:50 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:47712 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2392694AbfJRPcW (ORCPT ); Fri, 18 Oct 2019 11:32:22 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFWLBD013415; Fri, 18 Oct 2019 10:32:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571412741; bh=fKnbl4rI7lxj8OVyJOMnIhdivu5BzUFIAmoern9RyCY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=I24zH4pmc+ZVwZkX6fe0RVNdjB4YZ4BL+L3DxYnmYz+Ng+2EvQ6YDDlkVmH/5/I9L u5ebqs/T8rFjBZU1ar6d/aXnkddj1WoS7zGeYLPDYZ5OprOw8AMMDiSL9zCMI2ooM4 Shdlk2nhOMSA157FFduME3WOBeiPrBx/Q4/t205A= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFWLYV106161; Fri, 18 Oct 2019 10:32:21 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:32:12 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:32:20 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW15T080266; Fri, 18 Oct 2019 10:32:20 -0500 From: Benoit Parrot To: Hans Verkuil , Rob Herring CC: , , , Benoit Parrot Subject: [Patch 15/19] media: ti-vpe: cal: Add subdev s_power hooks Date: Fri, 18 Oct 2019 10:34:33 -0500 Message-ID: <20191018153437.20614-16-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018153437.20614-1-bparrot@ti.com> References: <20191018153437.20614-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Based on V4L2 documentations bridge driver must power on and off sub device explicitly if media-controller mode is not used. Signed-off-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 42b0063b610e..e61d2f3fd1da 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -1661,6 +1661,12 @@ static int cal_start_streaming(struct vb2_queue *vq, unsigned int count) if (ret < 0) goto err; + ret = v4l2_subdev_call(ctx->sensor, core, s_power, 1); + if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV) { + ctx_err(ctx, "power on failed in subdev\n"); + goto err; + } + cal_runtime_get(ctx->dev); csi2_ctx_config(ctx); @@ -1674,6 +1680,7 @@ static int cal_start_streaming(struct vb2_queue *vq, unsigned int count) ret = v4l2_subdev_call(ctx->sensor, video, s_stream, 1); if (ret) { + v4l2_subdev_call(ctx->sensor, core, s_power, 0); ctx_err(ctx, "stream on failed in subdev\n"); cal_runtime_put(ctx->dev); goto err; @@ -1702,6 +1709,7 @@ static void cal_stop_streaming(struct vb2_queue *vq) struct cal_dmaqueue *dma_q = &ctx->vidq; struct cal_buffer *buf, *tmp; unsigned long flags; + int ret; csi2_ppi_disable(ctx); disable_irqs(ctx); @@ -1710,6 +1718,10 @@ static void cal_stop_streaming(struct vb2_queue *vq) if (v4l2_subdev_call(ctx->sensor, video, s_stream, 0)) ctx_err(ctx, "stream off failed in subdev\n"); + ret = v4l2_subdev_call(ctx->sensor, core, s_power, 0); + if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV) + ctx_err(ctx, "power off failed in subdev\n"); + /* Release all active buffers */ spin_lock_irqsave(&ctx->slock, flags); list_for_each_entry_safe(buf, tmp, &dma_q->active, list) { From patchwork Fri Oct 18 15:34:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198723 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A35CC112C for ; Fri, 18 Oct 2019 15:32:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 83BBE22470 for ; Fri, 18 Oct 2019 15:32:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="H9ZkOQpl" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404953AbfJRPcm (ORCPT ); Fri, 18 Oct 2019 11:32:42 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:44842 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2410688AbfJRPcY (ORCPT ); Fri, 18 Oct 2019 11:32:24 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFWNju117124; Fri, 18 Oct 2019 10:32:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571412743; bh=Gnev1/nUK6kia0qBTPA020FCXW4FagJcU0jgSzyPRRI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=H9ZkOQplb/ylnwjF8I86pA6AYkS/NmZQpgmt7+spwTP+RyjAm1LvThH+/pe64oAP2 JVAYrqMqvtt89zrGiZJ2Cxp9mHidrx0BkRvdi5rSSOsA9gGu1yhlhAcV0sN6QPrtSH 8so6iQls54noCLmh+jELH+igSZpUg+i1krk/2KHM= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9IFWNJ2113243 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Oct 2019 10:32:23 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:32:14 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:32:14 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW15U080266; Fri, 18 Oct 2019 10:32:22 -0500 From: Benoit Parrot To: Hans Verkuil , Rob Herring CC: , , , Benoit Parrot Subject: [Patch 16/19] media: ti-vpe: cal: Properly calculate max resolution boundary Date: Fri, 18 Oct 2019 10:34:34 -0500 Message-ID: <20191018153437.20614-17-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018153437.20614-1-bparrot@ti.com> References: <20191018153437.20614-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Currently we were using an arbitrarily small maximum resolution mostly based on available sensor capabilities. However the hardware DMA limits are much higher than the statically define maximum resolution we were using. There we rework the boundary check code to handle the maximum width and height based on the maximum line width in bytes and re-calculating the pixel width based on the given pixel format. Signed-off-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index e61d2f3fd1da..a0ff67412410 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -34,8 +34,8 @@ #define CAL_MODULE_NAME "cal" -#define MAX_WIDTH 1920 -#define MAX_HEIGHT 1200 +#define MAX_WIDTH_BYTES (8192 * 8) +#define MAX_HEIGHT_LINES 16383 #define CAL_VERSION "0.1.0" @@ -1337,15 +1337,21 @@ static int cal_calc_format_size(struct cal_ctx *ctx, const struct cal_fmt *fmt, struct v4l2_format *f) { - u32 bpl; + u32 bpl, max_width; if (!fmt) { ctx_dbg(3, ctx, "No cal_fmt provided!\n"); return -EINVAL; } - v4l_bound_align_image(&f->fmt.pix.width, 48, MAX_WIDTH, 2, - &f->fmt.pix.height, 32, MAX_HEIGHT, 0, 0); + /* + * Maximum width is bound by the DMA max width in bytes. + * We need to recalculate the actual maxi width depending on the + * number of bytes per pixels required. + */ + max_width = MAX_WIDTH_BYTES / (ALIGN(fmt->bpp, 8) >> 3); + v4l_bound_align_image(&f->fmt.pix.width, 48, max_width, 2, + &f->fmt.pix.height, 32, MAX_HEIGHT_LINES, 0, 0); bpl = (f->fmt.pix.width * ALIGN(fmt->bpp, 8)) >> 3; f->fmt.pix.bytesperline = ALIGN(bpl, 16); From patchwork Fri Oct 18 15:34:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198717 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 84A69112C for ; Fri, 18 Oct 2019 15:32:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 65AC2222CD for ; Fri, 18 Oct 2019 15:32:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="d064I8aD" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2410703AbfJRPc1 (ORCPT ); Fri, 18 Oct 2019 11:32:27 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:37128 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2410695AbfJRPcZ (ORCPT ); Fri, 18 Oct 2019 11:32:25 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFWOKA064295; Fri, 18 Oct 2019 10:32:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571412744; bh=5ZErgPTAHa8AtWbEG4acFfzKns2sK6aTZaCmYFQYBz8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=d064I8aDyn0A3MO5XRNpvhdUqDCFHxXjiTJQ9yO2aANdhSa2RpfAOx6eQ4QEziWeg s63wVRnk+VdYCObU86Rr4Yn9A8SX4z8unSLsHexVpmPCJQKOwMyBRo0iL8tZfdbGb6 dLqzT5mrpCoc1IyFtF2D5lOlUOVuBoYAXOdEPkMg= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9IFWOYj081108 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Oct 2019 10:32:24 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:32:15 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:32:15 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW15V080266; Fri, 18 Oct 2019 10:32:24 -0500 From: Benoit Parrot To: Hans Verkuil , Rob Herring CC: , , , Benoit Parrot Subject: [Patch 17/19] media: ti-vpe: cal: Fix a WARN issued when start streaming fails Date: Fri, 18 Oct 2019 10:34:35 -0500 Message-ID: <20191018153437.20614-18-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018153437.20614-1-bparrot@ti.com> References: <20191018153437.20614-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org When start_streaming fails after the buffers have been queued we have to make sure all buffers are returned to user-space properly otherwise a v4l2 level WARN is generated. Signed-off-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index a0ff67412410..b55987ee70dd 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -1702,10 +1702,15 @@ static int cal_start_streaming(struct vb2_queue *vq, unsigned int count) return 0; err: + spin_lock_irqsave(&ctx->slock, flags); + vb2_buffer_done(&ctx->cur_frm->vb.vb2_buf, VB2_BUF_STATE_QUEUED); + ctx->cur_frm = NULL; + ctx->next_frm = NULL; list_for_each_entry_safe(buf, tmp, &dma_q->active, list) { list_del(&buf->list); vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED); } + spin_unlock_irqrestore(&ctx->slock, flags); return ret; } From patchwork Fri Oct 18 15:34:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198721 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 76E37112B for ; Fri, 18 Oct 2019 15:32:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5769E222D0 for ; Fri, 18 Oct 2019 15:32:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="I2LPEQU1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2505142AbfJRPch (ORCPT ); Fri, 18 Oct 2019 11:32:37 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:47732 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727211AbfJRPc1 (ORCPT ); Fri, 18 Oct 2019 11:32:27 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFWP6X013435; Fri, 18 Oct 2019 10:32:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571412746; bh=ADM1me0Put+VJ63c2ujPwgjbNLqYMOSh7Lbu/rGYcTk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=I2LPEQU1bV7hd/Y2BmrBbXZUgz2+102padDSO4mPjDrrBI+GS50K/sLkSVpslCCrZ m+m8fU1NW0z7WANwRs/aLsr1QGnY6PKOwzFtQ/BYKDqNZZDByscZDe4aSCVbbCXXvr MmkXDvvLVYJwXMEVJ1tL+4Y+ZlThAQkaZhI11q6A= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9IFWPZY113363 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Oct 2019 10:32:26 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:32:17 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:32:17 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW15W080266; Fri, 18 Oct 2019 10:32:25 -0500 From: Benoit Parrot To: Hans Verkuil , Rob Herring CC: , , , Benoit Parrot Subject: [Patch 18/19] media: ti-vpe: cal: fix enum_mbus_code/frame_size subdev arguments Date: Fri, 18 Oct 2019 10:34:36 -0500 Message-ID: <20191018153437.20614-19-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018153437.20614-1-bparrot@ti.com> References: <20191018153437.20614-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Make sure that both enum_mbus_code() and enum_framesize() properly populate the .which parameter member, otherwise -EINVAL is return causing the subdev asynchronous registration handshake to fail. Signed-off-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index b55987ee70dd..6a404350edb3 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -1500,6 +1500,7 @@ static int cal_enum_framesizes(struct file *file, void *fh, fse.index = fsize->index; fse.pad = 0; fse.code = fmt->code; + fse.which = V4L2_SUBDEV_FORMAT_ACTIVE; ret = v4l2_subdev_call(ctx->sensor, pad, enum_frame_size, NULL, &fse); if (ret) @@ -1840,6 +1841,7 @@ static int cal_async_bound(struct v4l2_async_notifier *notifier, memset(&mbus_code, 0, sizeof(mbus_code)); mbus_code.index = j; + mbus_code.which = V4L2_SUBDEV_FORMAT_ACTIVE; ret = v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL, &mbus_code); if (ret) From patchwork Fri Oct 18 15:34:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198719 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2DE38112B for ; Fri, 18 Oct 2019 15:32:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F1CDD222D0 for ; Fri, 18 Oct 2019 15:32:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="jLqp5H1E" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2501940AbfJRPca (ORCPT ); Fri, 18 Oct 2019 11:32:30 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:40728 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2410707AbfJRPc2 (ORCPT ); Fri, 18 Oct 2019 11:32:28 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFWRnv002721; Fri, 18 Oct 2019 10:32:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571412747; bh=WCW45BFjyaYF9dFU+6TLiqhLXA6kwWxcmbGkdoJoeto=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jLqp5H1E4cR8HOR3dLLt7E/aX5o+dSiMXk0tXgLGjqkAfXIRAnDivXZWJxbAsrD2M ghv8l2opGiDIGJZLMQbhQB4vOYTDa7GjYN3SHOr9ohFjn0Bglpf/rEb2HWVGZ99nhg zNHj6wbLdbxPwsY9QAMWDOjYjv0U60azXkW7zkDA= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9IFWRKd081245 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Oct 2019 10:32:27 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:32:19 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:32:18 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFW15X080266; Fri, 18 Oct 2019 10:32:27 -0500 From: Benoit Parrot To: Hans Verkuil , Rob Herring CC: , , , Benoit Parrot Subject: [Patch 19/19] dt-bindings: media: cal: convert binding to yaml Date: Fri, 18 Oct 2019 10:34:37 -0500 Message-ID: <20191018153437.20614-20-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018153437.20614-1-bparrot@ti.com> References: <20191018153437.20614-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Convert ti-cal.txt to ti,cal.yaml. Signed-off-by: Benoit Parrot --- .../devicetree/bindings/media/ti,cal.yaml | 186 ++++++++++++++++++ .../devicetree/bindings/media/ti-cal.txt | 82 -------- 2 files changed, 186 insertions(+), 82 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/ti,cal.yaml delete mode 100644 Documentation/devicetree/bindings/media/ti-cal.txt diff --git a/Documentation/devicetree/bindings/media/ti,cal.yaml b/Documentation/devicetree/bindings/media/ti,cal.yaml new file mode 100644 index 000000000000..c3fbb22b4571 --- /dev/null +++ b/Documentation/devicetree/bindings/media/ti,cal.yaml @@ -0,0 +1,186 @@ +# SPDX-License-Identifier: (GPL-2.0) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/ti,cal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments DRA72x CAMERA ADAPTATION LAYER (CAL) Device Tree Bindings + +maintainers: + - Benoit Parrot + +description: |- + The Camera Adaptation Layer (CAL) is a key component for image capture + applications. The capture module provides the system interface and the + processing capability to connect CSI2 image-sensor modules to the + DRA72x device. + + CAL supports 2 camera port nodes on MIPI bus. Each CSI2 camera port nodes + should contain a 'port' child node with child 'endpoint' node. Please + refer to the bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + + compatible should be + "ti,dra72-cal", for DRA72 controllers + "ti,dra72-pre-es2-cal", for DRA72 controllers pre ES2.0 + "ti,dra76-cal", for DRA76 controllers + "ti,am654-cal", for AM654 controllers + +properties: + compatible: + items: + - enum: + - ti,dra72-cal + - ti,dra72-pre-es2-cal + - ti,dra76-cal + - ti,am654-cal + + reg: + minItems: 2 + items: + - description: The CAL main register region + - description: The RX Core0 (DPHY0) register region + - description: The RX Core1 (DPHY1) register region + + reg-names: + minItems: 2 + items: + - const: cal_top + - const: cal_rx_core0 + - const: cal_rx_core1 + + interrupts: + maxItems: 1 + + syscon-camerrx: + maxItems: 1 + items: + - description: + phandle to the device control module and offset to the + control_camerarx_core register + + clocks: + maxItems: 1 + description: functional clock + + clock-names: + items: + - const: fck + + power-domains: + description: + List of phandle and PM domain specifier as documented in + Documentation/devicetree/bindings/power/power_domain.txt + maxItems: 1 + + # See ./video-interfaces.txt for details + ports: + maxItems: 1 + type: object + additionalProperties: false + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + '^port@[0-9a-fA-F]+$': + minItems: 1 + maxItems: 2 + type: object + additionalProperties: false + + properties: + reg: + minItems: 1 + items: + - description: The port id + + patternProperties: + '^endpoint@[0-9a-fA-F]+$': + minItems: 1 + type: object + additionalProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + remote-endpoint: true + + required: + - remote-endpoint + + required: + - reg + +required: + - compatible + - reg + - reg-names + - interrupts + - syscon-camerrx + +additionalProperties: false + +examples: + - | + #include + + cal: cal@4845b000 { + compatible = "ti,dra72-cal"; + reg = <0x4845B000 0x400>, + <0x4845B800 0x40>, + <0x4845B900 0x40>; + reg-names = "cal_top", + "cal_rx_core0", + "cal_rx_core1"; + interrupts = ; + syscon-camerrx = <&scm_conf 0xE94>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_0: port@0 { + reg = <0>; + csi2_phy0: endpoint@0 { + remote-endpoint = <&csi2_cam0>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + i2c5: i2c@4807c000 { + status = "okay"; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + port { + csi2_cam0: endpoint@0 { + remote-endpoint = <&csi2_phy0>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/media/ti-cal.txt b/Documentation/devicetree/bindings/media/ti-cal.txt deleted file mode 100644 index b7bf8492dc2a..000000000000 --- a/Documentation/devicetree/bindings/media/ti-cal.txt +++ /dev/null @@ -1,82 +0,0 @@ -Texas Instruments DRA72x CAMERA ADAPTATION LAYER (CAL) ------------------------------------------------------- - -The Camera Adaptation Layer (CAL) is a key component for image capture -applications. The capture module provides the system interface and the -processing capability to connect CSI2 image-sensor modules to the -DRA72x device. - -Required properties: -- compatible: - Should be "ti,dra72-cal", for DRA72 controllers - Should be "ti,dra72-pre-es2-cal", for DRA72 controllers pre ES2.0 - Should be "ti,dra76-cal", for DRA76 controllers - Should be "ti,am654-cal", for AM654 controllers -- reg: CAL Top level, Receiver Core #0, Receiver Core #1 and Camera RX - control address space -- reg-names: cal_top, cal_rx_core0, cal_rx_core1 and camerrx_control - registers -- interrupts: should contain IRQ line for the CAL; -- syscon-camerrx: phandle to the device control module and offset to the - control_camerarx_core register - This node is meant to replace the "camerrx_control" reg - entry above but "camerrx_control" is still handled - for backward compatibility. - -CAL supports 2 camera port nodes on MIPI bus. Each CSI2 camera port nodes -should contain a 'port' child node with child 'endpoint' node. Please -refer to the bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - cal: cal@4845b000 { - compatible = "ti,dra72-cal"; - reg = <0x4845B000 0x400>, - <0x4845B800 0x40>, - <0x4845B900 0x40>; - reg-names = "cal_top", - "cal_rx_core0", - "cal_rx_core1"; - interrupts = ; - syscon-camerrx = <&scm_conf 0xE94>; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - csi2_0: port@0 { - reg = <0>; - csi2_phy0: endpoint@0 { - remote-endpoint = <&csi2_cam0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - csi2_1: port@1 { - reg = <1>; - }; - }; - }; - - i2c5: i2c@4807c000 { - status = "okay"; - clock-frequency = <400000>; - - ov5640@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - - clocks = <&clk_ov5640_fixed>; - clock-names = "xclk"; - - port { - csi2_cam0: endpoint { - remote-endpoint = <&csi2_phy0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - };