From patchwork Sun Oct 20 10:11:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 11200867 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2F6AB139A for ; Sun, 20 Oct 2019 10:11:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0747F222C3 for ; Sun, 20 Oct 2019 10:11:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1571566297; bh=R9nxM6A3Yhddcl9A7C/26LLhq+KqjO+NyOwb1yqAA94=; h=From:To:Cc:Subject:Date:List-ID:From; b=LAGGwOf4eIcNeXqUdP4+RI4LtnteQwdV+CkvpjRHta8TnTfUn/IibYRsLbpV+5b0Z KTsM107Owpm3pQ08Umqm7xaQD1fFLWJHRC7DCEhaLpD0VM23fqbhO5F+FMjJsO5GZH p8Ict+us70JuukcN5mZqkWd1IfUh3Vn+3n0DLHR8= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726019AbfJTKLf (ORCPT ); Sun, 20 Oct 2019 06:11:35 -0400 Received: from mail.kernel.org ([198.145.29.99]:55320 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725893AbfJTKLf (ORCPT ); Sun, 20 Oct 2019 06:11:35 -0400 Received: from big-swifty.lan (78.163-31-62.static.virginmediabusiness.co.uk [62.31.163.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 89A342190F; Sun, 20 Oct 2019 10:11:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1571566294; bh=R9nxM6A3Yhddcl9A7C/26LLhq+KqjO+NyOwb1yqAA94=; h=From:To:Cc:Subject:Date:From; b=wZl1P5TR+YzkoKz8Z0Krfdf4skT5kHoKhxSmiYkJoZu/u3uDDGVRFMn0t4GTos/u9 +masS9rK4tdB5WNUk7ko/gKMJTmaJTpuqTCTETNz91MjZ+XPLk1mF3T/760PDMMKB5 cAFy5HjwCjjvImUIHXutqDnA9xTObx4YpNbz5uQk= From: Marc Zyngier To: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= Cc: Julien Thierry , Suzuki K Poulose , James Morse , Andrew Murray , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Subject: [GIT PULL] KVM/arm fixes for 5.4-rc5 Date: Sun, 20 Oct 2019 11:11:25 +0100 Message-Id: <20191020101129.2612-1-maz@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Paolo, Radim, Here's the latest (and hopefully last) set of KVM/arm fixes for 5.4. 4 patches exclusively covering our PMU emulation, which exhibited several different flavours of brokenness. Please pull, M. The following changes since commit da0c9ea146cbe92b832f1b0f694840ea8eb33cce: Linux 5.4-rc2 (2019-10-06 14:27:30 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git tags/kvmarm-fixes-5.4-2 for you to fetch changes up to 8c3252c06516eac22c4f8e2506122171abedcc09: KVM: arm64: pmu: Reset sample period on overflow handling (2019-10-20 10:47:07 +0100) ---------------------------------------------------------------- KVM/arm fixes for 5.4, take #2 Special PMU edition: - Fix cycle counter truncation - Fix cycle counter overflow limit on pure 64bit system - Allow chained events to be actually functional - Correct sample period after overflow ---------------------------------------------------------------- Marc Zyngier (4): KVM: arm64: pmu: Fix cycle counter truncation arm64: KVM: Handle PMCR_EL0.LC as RES1 on pure AArch64 systems KVM: arm64: pmu: Set the CHAINED attribute before creating the in-kernel event KVM: arm64: pmu: Reset sample period on overflow handling arch/arm64/kvm/sys_regs.c | 4 ++++ virt/kvm/arm/pmu.c | 48 ++++++++++++++++++++++++++++++++++------------- 2 files changed, 39 insertions(+), 13 deletions(-) From patchwork Sun Oct 20 10:11:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 11200871 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6FC0014ED for ; Sun, 20 Oct 2019 10:11:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 434DB222D2 for ; Sun, 20 Oct 2019 10:11:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1571566302; bh=azhX068/Llc0POTSFJ7hQa0blYq+N0fFcX/ZEjAr9sY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=IqjatqmEhRH1ZieQNJHw2XNyoP0bx/eGnBNiNX8FhMXVqZq0Hhv6DlqVVX81y+M4n GQn01IZzSMTB4VHF0fLxsUr7npdfzTPL8fnwsNLHwxA383FjflTJuQXOojbK0fL3+8 FYtkn4xYFCDGfUqZfLfwJP1lUpG2gMmJhJEMuWK8= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726258AbfJTKLl (ORCPT ); Sun, 20 Oct 2019 06:11:41 -0400 Received: from mail.kernel.org ([198.145.29.99]:55366 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726212AbfJTKLl (ORCPT ); Sun, 20 Oct 2019 06:11:41 -0400 Received: from big-swifty.lan (78.163-31-62.static.virginmediabusiness.co.uk [62.31.163.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 481CB2190F; Sun, 20 Oct 2019 10:11:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1571566300; bh=azhX068/Llc0POTSFJ7hQa0blYq+N0fFcX/ZEjAr9sY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HCve6BGyoxxbhjwhXItirYvlpIK6Wp1TyfF5jyy3UCbpT9/+nOdAlaLZ8zMu0/aGb +aHMhQ0zj322GshIh/8gAma86d6kBcqUpIDuYVv/wsJdlMH59V/Xzt98xRKBr8bA3h JTE9WtuBVDzyPNYwjmo36ejQ9cKJGhNXKg9pR9hw= From: Marc Zyngier To: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= Cc: Julien Thierry , Suzuki K Poulose , James Morse , Andrew Murray , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Subject: [PATCH 2/4] arm64: KVM: Handle PMCR_EL0.LC as RES1 on pure AArch64 systems Date: Sun, 20 Oct 2019 11:11:27 +0100 Message-Id: <20191020101129.2612-3-maz@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191020101129.2612-1-maz@kernel.org> References: <20191020101129.2612-1-maz@kernel.org> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Of PMCR_EL0.LC, the ARMv8 ARM says: "In an AArch64 only implementation, this field is RES 1." So be it. Fixes: ab9468340d2bc ("arm64: KVM: Add access handler for PMCR register") Reviewed-by: Andrew Murray Signed-off-by: Marc Zyngier --- arch/arm64/kvm/sys_regs.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 2071260a275b..46822afc57e0 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -632,6 +632,8 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) */ val = ((pmcr & ~ARMV8_PMU_PMCR_MASK) | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E); + if (!system_supports_32bit_el0()) + val |= ARMV8_PMU_PMCR_LC; __vcpu_sys_reg(vcpu, r->reg) = val; } @@ -682,6 +684,8 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, val = __vcpu_sys_reg(vcpu, PMCR_EL0); val &= ~ARMV8_PMU_PMCR_MASK; val |= p->regval & ARMV8_PMU_PMCR_MASK; + if (!system_supports_32bit_el0()) + val |= ARMV8_PMU_PMCR_LC; __vcpu_sys_reg(vcpu, PMCR_EL0) = val; kvm_pmu_handle_pmcr(vcpu, val); kvm_vcpu_pmu_restore_guest(vcpu); From patchwork Sun Oct 20 10:11:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 11200873 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 76479139A for ; Sun, 20 Oct 2019 10:11:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4B283222CD for ; Sun, 20 Oct 2019 10:11:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1571566305; bh=Syg7JpTSjO3UDfWlqULqNwmrn1vfNkZUjqNdeFNbT8c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=Es/HPw5q89Ymu5bE6+v+D93jMQxPeEWPvMkYTDs7pJAPX/ZEKfDAS6QOg0SwQrZZW RII6epJy9a2D65IIWhsJkV1b97LpzkWvLJ7hz4LqECmCMuw5U0YL40Z2v4JdAf5IGj 9Mi4Kc1ekVGCSbp9P1M2KhWkfCNYFN7BRna3iAPQ= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726265AbfJTKLo (ORCPT ); Sun, 20 Oct 2019 06:11:44 -0400 Received: from mail.kernel.org ([198.145.29.99]:55432 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726194AbfJTKLo (ORCPT ); Sun, 20 Oct 2019 06:11:44 -0400 Received: from big-swifty.lan (78.163-31-62.static.virginmediabusiness.co.uk [62.31.163.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 59CEF222BD; Sun, 20 Oct 2019 10:11:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1571566303; bh=Syg7JpTSjO3UDfWlqULqNwmrn1vfNkZUjqNdeFNbT8c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=t1nAb5ChLYmSWCc2pr0VVskYWZu2pdancAXCgfmvHAw4nfVbhLMAr9pfMBkL/+JGx E16M4+CSRQxIwt5DQaAjg137rwxJ9kz1n3foB8ty/1U0BHwkDJ+qbvUHOzdDkPExBV q7bB3qIjiwhVHYEdJgaiz4Qr/I3Lo64SZZo/o6ak= From: Marc Zyngier To: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= Cc: Julien Thierry , Suzuki K Poulose , James Morse , Andrew Murray , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Subject: [PATCH 3/4] KVM: arm64: pmu: Set the CHAINED attribute before creating the in-kernel event Date: Sun, 20 Oct 2019 11:11:28 +0100 Message-Id: <20191020101129.2612-4-maz@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191020101129.2612-1-maz@kernel.org> References: <20191020101129.2612-1-maz@kernel.org> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The current convention for KVM to request a chained event from the host PMU is to set bit[0] in attr.config1 (PERF_ATTR_CFG1_KVM_PMU_CHAINED). But as it turns out, this bit gets set *after* we create the kernel event that backs our virtual counter, meaning that we never get a 64bit counter. Moving the setting to an earlier point solves the problem. Fixes: 80f393a23be6 ("KVM: arm/arm64: Support chained PMU counters") Reviewed-by: Andrew Murray Signed-off-by: Marc Zyngier --- virt/kvm/arm/pmu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index c30c3a74fc7f..f291d4ac3519 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -569,12 +569,12 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx) * high counter. */ attr.sample_period = (-counter) & GENMASK(63, 0); + if (kvm_pmu_counter_is_enabled(vcpu, pmc->idx + 1)) + attr.config1 |= PERF_ATTR_CFG1_KVM_PMU_CHAINED; + event = perf_event_create_kernel_counter(&attr, -1, current, kvm_pmu_perf_overflow, pmc + 1); - - if (kvm_pmu_counter_is_enabled(vcpu, pmc->idx + 1)) - attr.config1 |= PERF_ATTR_CFG1_KVM_PMU_CHAINED; } else { /* The initial sample period (overflow count) of an event. */ if (kvm_pmu_idx_is_64bit(vcpu, pmc->idx)) From patchwork Sun Oct 20 10:11:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 11200875 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 32A9D14ED for ; Sun, 20 Oct 2019 10:11:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 11A24222D0 for ; Sun, 20 Oct 2019 10:11:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1571566308; bh=om3Cj3Gh8W38m+op9WkaTNAgw+rHdyTrhOQkkaQCz40=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=X/OKLUkALAopZPOiYVi+3Zo/zdENFMSTh5iT+d3B/pmDfORznOk73nGqaLtSvQill qLDT+q8SXLMS2FogE1WRMlXictxRmexoafhCoTvBzfJY6dkNsDORsdVcDSZS0GKdl2 pycis/aOF7tcn9EtbZYbM7QmhOd2XTf+M43hGYuw= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726289AbfJTKLr (ORCPT ); Sun, 20 Oct 2019 06:11:47 -0400 Received: from mail.kernel.org ([198.145.29.99]:55488 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726206AbfJTKLr (ORCPT ); Sun, 20 Oct 2019 06:11:47 -0400 Received: from big-swifty.lan (78.163-31-62.static.virginmediabusiness.co.uk [62.31.163.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 3B37D2190F; Sun, 20 Oct 2019 10:11:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1571566306; bh=om3Cj3Gh8W38m+op9WkaTNAgw+rHdyTrhOQkkaQCz40=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mRCCWvskMmuSgZrasQVj9s6NTQm49gUlfviEBCz4nKzWyEJ9yPX/sPN13N05vxt12 3QKIlNPSs0zoMYczKpfjNsS43TeVOlvm13dCuIcXCz1URXTcGVQTc3lZYW59N2L4Eo //Y/+847gu1WQSofWjKIGbKX4UnT5AAKXiVhmeC4= From: Marc Zyngier To: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= Cc: Julien Thierry , Suzuki K Poulose , James Morse , Andrew Murray , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Subject: [PATCH 4/4] KVM: arm64: pmu: Reset sample period on overflow handling Date: Sun, 20 Oct 2019 11:11:29 +0100 Message-Id: <20191020101129.2612-5-maz@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191020101129.2612-1-maz@kernel.org> References: <20191020101129.2612-1-maz@kernel.org> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The PMU emulation code uses the perf event sample period to trigger the overflow detection. This works fine for the *first* overflow handling, but results in a huge number of interrupts on the host, unrelated to the number of interrupts handled in the guest (a x20 factor is pretty common for the cycle counter). On a slow system (such as a SW model), this can result in the guest only making forward progress at a glacial pace. It turns out that the clue is in the name. The sample period is exactly that: a period. And once the an overflow has occured, the following period should be the full width of the associated counter, instead of whatever the guest had initially programed. Reset the sample period to the architected value in the overflow handler, which now results in a number of host interrupts that is much closer to the number of interrupts in the guest. Fixes: b02386eb7dac ("arm64: KVM: Add PMU overflow interrupt routing") Reviewed-by: Andrew Murray Signed-off-by: Marc Zyngier --- virt/kvm/arm/pmu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index f291d4ac3519..8731dfeced8b 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -442,8 +443,25 @@ static void kvm_pmu_perf_overflow(struct perf_event *perf_event, struct pt_regs *regs) { struct kvm_pmc *pmc = perf_event->overflow_handler_context; + struct arm_pmu *cpu_pmu = to_arm_pmu(perf_event->pmu); struct kvm_vcpu *vcpu = kvm_pmc_to_vcpu(pmc); int idx = pmc->idx; + u64 period; + + cpu_pmu->pmu.stop(perf_event, PERF_EF_UPDATE); + + /* + * Reset the sample period to the architectural limit, + * i.e. the point where the counter overflows. + */ + period = -(local64_read(&perf_event->count)); + + if (!kvm_pmu_idx_is_64bit(vcpu, pmc->idx)) + period &= GENMASK(31, 0); + + local64_set(&perf_event->hw.period_left, 0); + perf_event->attr.sample_period = period; + perf_event->hw.sample_period = period; __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= BIT(idx); @@ -451,6 +469,8 @@ static void kvm_pmu_perf_overflow(struct perf_event *perf_event, kvm_make_request(KVM_REQ_IRQ_PENDING, vcpu); kvm_vcpu_kick(vcpu); } + + cpu_pmu->pmu.start(perf_event, PERF_EF_RELOAD); } /**