From patchwork Mon Oct 21 10:35:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11201825 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2207A13BD for ; Mon, 21 Oct 2019 10:35:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EA65F20882 for ; Mon, 21 Oct 2019 10:35:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zL8ZrW5N" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728231AbfJUKfv (ORCPT ); Mon, 21 Oct 2019 06:35:51 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:33161 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728216AbfJUKfs (ORCPT ); Mon, 21 Oct 2019 06:35:48 -0400 Received: by mail-pg1-f193.google.com with SMTP id i76so7567328pgc.0 for ; Mon, 21 Oct 2019 03:35:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=LZlCeZrRTo7/0do93bbsot+ttbvRMEOWIgpwlWXPhlQ=; b=zL8ZrW5Nswpqr8PYA8T7fIK4mVVnRxIouA8raLosaE/PRRBX49O1fSlHN5VI8HgYBN k3HX+93GASSwAaW2Mn08tXvJs0GA6WM37fnYn9PCAIwsmy9SM+ot/qANbHPHBl9ik8YL Eo7lRjXkBjDkz5kpZifLl+Po8Enh6n1zjrEPtH6BULz2eWr6eOereG1CV9T3Qsns8ZWV 4MxHWd2Niz8bHkgJaYiDGSEWO49AUS4v1wTPWJSD/i4QtHqyTz3i4AS/JAxUFD0gxk0c 7OwwH6stPyXXs2oTWl3kj2bhEK6jjO7x9QEJcBUK3YTC3aVpewXYRIFztzII2rLnuddY /dZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=LZlCeZrRTo7/0do93bbsot+ttbvRMEOWIgpwlWXPhlQ=; b=CUKNYRHGwoUxu6BvT3aBy3QGWLwWBGMLTOEaO+IZw7OdLuiLN/2HqopthlM6sKNO/y mSV1EcxvJ9TQGuGkh6cpSjpukdXxkgssK0MHk5VO4cuWAy5AM3faYKoD9ZeFb6FWwU66 iKNJ1sfdG/FIDFoF+Dx1tXP6Ak4YMEZjqz6S1mgcvJPtvaUlCDXZDFY9yf8txA3Pe8AD o6sq1yJibUiid2rTO+wPeat2lARmUkpJ1i44RTABunlvlX3CSne5F9AohLRZx0exi8qZ Ey4izR/h03ptFXNF8gLPaAtF20hnH6DnznY63cybs0aVtgYaRrz6TSLTSiuC888gVeje tIKg== X-Gm-Message-State: APjAAAUKSOHNc29vUfro1X5gSSbXjfoiQ9WDBtYOhVfmo0uujCqMz2zI 1k82sw3jAnQHgCBCi0BQI2FFTA== X-Google-Smtp-Source: APXvYqwshX4O5zWNP1T1Eiu1EB7HBw2yPucOWeclwK3FwlsDCV3dOt9lJ+kmTxRAA/ffWzcDk2Y8Kg== X-Received: by 2002:a62:750d:: with SMTP id q13mr21620042pfc.58.1571654145915; Mon, 21 Oct 2019 03:35:45 -0700 (PDT) Received: from localhost ([49.248.62.222]) by smtp.gmail.com with ESMTPSA id t21sm15041040pgi.87.2019.10.21.03.35.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 Oct 2019 03:35:45 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, julia.lawall@lip6.fr, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH v6 01/15] drivers: thermal: tsens: Get rid of id field in tsens_sensor Date: Mon, 21 Oct 2019 16:05:20 +0530 Message-Id: <30206cd47d303d2dcaef87f4e3c7173481a0bddd.1571652874.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There are two fields - id and hw_id - to track what sensor an action was to performed on. This was because the sensors connected to a TSENS IP might not be contiguous i.e. 1, 2, 4, 5 with 3 being skipped. This causes confusion in the code which uses hw_id sometimes and id other times (tsens_get_temp, tsens_get_trend). Switch to only using the hw_id field to track the physical ID of the sensor. When we iterate through all the sensors connected to an IP block, we use an index i to loop through the list of sensors, and then return the actual hw_id that is registered on that index. Signed-off-by: Amit Kucheria Reviewed-by: Stephen Boyd Reviewed-by: Daniel Lezcano --- drivers/thermal/qcom/tsens-8960.c | 4 ++-- drivers/thermal/qcom/tsens-common.c | 16 +++++++++------- drivers/thermal/qcom/tsens.c | 11 +++++------ drivers/thermal/qcom/tsens.h | 10 ++++------ 4 files changed, 20 insertions(+), 21 deletions(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index e46a4e3f25c42..fb77acb8d13b9 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -245,11 +245,11 @@ static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s) return adc_code * slope + offset; } -static int get_temp_8960(struct tsens_priv *priv, int id, int *temp) +static int get_temp_8960(struct tsens_sensor *s, int *temp) { int ret; u32 code, trdy; - const struct tsens_sensor *s = &priv->sensor[id]; + struct tsens_priv *priv = s->priv; unsigned long timeout; timeout = jiffies + usecs_to_jiffies(TIMEOUT_US); diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 528df88012543..c037bdf92c663 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -83,11 +83,12 @@ static inline int code_to_degc(u32 adc_code, const struct tsens_sensor *s) return degc; } -int get_temp_tsens_valid(struct tsens_priv *priv, int i, int *temp) +int get_temp_tsens_valid(struct tsens_sensor *s, int *temp) { - struct tsens_sensor *s = &priv->sensor[i]; - u32 temp_idx = LAST_TEMP_0 + s->hw_id; - u32 valid_idx = VALID_0 + s->hw_id; + struct tsens_priv *priv = s->priv; + int hw_id = s->hw_id; + u32 temp_idx = LAST_TEMP_0 + hw_id; + u32 valid_idx = VALID_0 + hw_id; u32 last_temp = 0, valid, mask; int ret; @@ -123,12 +124,13 @@ int get_temp_tsens_valid(struct tsens_priv *priv, int i, int *temp) return 0; } -int get_temp_common(struct tsens_priv *priv, int i, int *temp) +int get_temp_common(struct tsens_sensor *s, int *temp) { - struct tsens_sensor *s = &priv->sensor[i]; + struct tsens_priv *priv = s->priv; + int hw_id = s->hw_id; int last_temp = 0, ret; - ret = regmap_field_read(priv->rf[LAST_TEMP_0 + s->hw_id], &last_temp); + ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp); if (ret) return ret; diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 0627d8615c307..6ed687a6e53cd 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -14,19 +14,19 @@ static int tsens_get_temp(void *data, int *temp) { - const struct tsens_sensor *s = data; + struct tsens_sensor *s = data; struct tsens_priv *priv = s->priv; - return priv->ops->get_temp(priv, s->id, temp); + return priv->ops->get_temp(s, temp); } static int tsens_get_trend(void *data, int trip, enum thermal_trend *trend) { - const struct tsens_sensor *s = data; + struct tsens_sensor *s = data; struct tsens_priv *priv = s->priv; if (priv->ops->get_trend) - return priv->ops->get_trend(priv, s->id, trend); + return priv->ops->get_trend(s, trend); return -ENOTSUPP; } @@ -86,8 +86,7 @@ static int tsens_register(struct tsens_priv *priv) for (i = 0; i < priv->num_sensors; i++) { priv->sensor[i].priv = priv; - priv->sensor[i].id = i; - tzd = devm_thermal_zone_of_sensor_register(priv->dev, i, + tzd = devm_thermal_zone_of_sensor_register(priv->dev, priv->sensor[i].hw_id, &priv->sensor[i], &tsens_of_ops); if (IS_ERR(tzd)) diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index b89083b61c383..84e5447c56860 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -32,7 +32,6 @@ enum tsens_ver { * @priv: tsens device instance that this sensor is connected to * @tzd: pointer to the thermal zone that this sensor is in * @offset: offset of temperature adjustment curve - * @id: Sensor ID * @hw_id: HW ID can be used in case of platform-specific IDs * @slope: slope of temperature adjustment curve * @status: 8960-specific variable to track 8960 and 8660 status register offset @@ -41,7 +40,6 @@ struct tsens_sensor { struct tsens_priv *priv; struct thermal_zone_device *tzd; int offset; - unsigned int id; unsigned int hw_id; int slope; u32 status; @@ -62,13 +60,13 @@ struct tsens_ops { /* mandatory callbacks */ int (*init)(struct tsens_priv *priv); int (*calibrate)(struct tsens_priv *priv); - int (*get_temp)(struct tsens_priv *priv, int i, int *temp); + int (*get_temp)(struct tsens_sensor *s, int *temp); /* optional callbacks */ int (*enable)(struct tsens_priv *priv, int i); void (*disable)(struct tsens_priv *priv); int (*suspend)(struct tsens_priv *priv); int (*resume)(struct tsens_priv *priv); - int (*get_trend)(struct tsens_priv *priv, int i, enum thermal_trend *trend); + int (*get_trend)(struct tsens_sensor *s, enum thermal_trend *trend); }; #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \ @@ -314,8 +312,8 @@ struct tsens_priv { char *qfprom_read(struct device *dev, const char *cname); void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode); int init_common(struct tsens_priv *priv); -int get_temp_tsens_valid(struct tsens_priv *priv, int i, int *temp); -int get_temp_common(struct tsens_priv *priv, int i, int *temp); +int get_temp_tsens_valid(struct tsens_sensor *s, int *temp); +int get_temp_common(struct tsens_sensor *s, int *temp); /* TSENS target */ extern const struct tsens_plat_data data_8960; From patchwork Mon Oct 21 10:35:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11201827 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4D62F1515 for ; Mon, 21 Oct 2019 10:35:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2BA2020882 for ; Mon, 21 Oct 2019 10:35:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="F20sjx0y" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728244AbfJUKfy (ORCPT ); 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Mon, 21 Oct 2019 03:35:48 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, julia.lawall@lip6.fr, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH v6 02/15] drivers: thermal: tsens: Simplify code flow in tsens_probe Date: Mon, 21 Oct 2019 16:05:21 +0530 Message-Id: <184422dcc1c12553e71a58c62e01425fd7d1172a.1571652874.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move platform_set_drvdata up to avoid an extra 'if (ret)' check after the call to tsens_register. Signed-off-by: Amit Kucheria Reviewed-by: Stephen Boyd Reviewed-by: Daniel Lezcano --- drivers/thermal/qcom/tsens.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 6ed687a6e53cd..542a7f8c3d962 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -149,6 +149,8 @@ static int tsens_probe(struct platform_device *pdev) priv->feat = data->feat; priv->fields = data->fields; + platform_set_drvdata(pdev, priv); + if (!priv->ops || !priv->ops->init || !priv->ops->get_temp) return -EINVAL; @@ -167,11 +169,7 @@ static int tsens_probe(struct platform_device *pdev) } } - ret = tsens_register(priv); - - platform_set_drvdata(pdev, priv); - - return ret; + return tsens_register(priv); } static int tsens_remove(struct platform_device *pdev) From patchwork Mon Oct 21 10:35:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11201829 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7909314E5 for ; Mon, 21 Oct 2019 10:35:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 577B7214B2 for ; Mon, 21 Oct 2019 10:35:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="H0BE8wee" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728243AbfJUKfz (ORCPT ); Mon, 21 Oct 2019 06:35:55 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:41305 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728228AbfJUKfz (ORCPT ); Mon, 21 Oct 2019 06:35:55 -0400 Received: by mail-pf1-f196.google.com with SMTP id q7so8164900pfh.8 for ; Mon, 21 Oct 2019 03:35:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=cALbZwSOU8EvtF0iOAGpF4/JluhlENqnhyD2XhJQYmg=; b=H0BE8weeGQn2WySiuRb+gKaFVKFQ7KMLVZ3dRmtUOI8X5pcqHTFM7GXNw27rl2sawo P7jYI09TXntT0JzSLhGxYPIHV5GSPV6U+4apNg7kDFWtz5vu5CCgmtfyD5nbC02pl5Rl 47uIDf+hqdDydBjT1xdlYLy21GCjcBGTFliZYzQylLmwe5Ir/cs6FWAuy5wfGfJEIt9t VoQiw1oiGRpqByof/t7G6Tn1i/MVgJpqkCMzusZPJwmlgptfgbk/YvIX0QIbnyQr2LSC 5nfNsPnqowCRjdXzkCDfhdKpRkc4cjTfno9WAppgdirgW2zMsG6FJN3n+FLzNBlNYmIk 7MOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=cALbZwSOU8EvtF0iOAGpF4/JluhlENqnhyD2XhJQYmg=; b=JvTsGyEBJtsGXvwH+cl/acdPxk65SAUKGMHsjThf4tLBm+pyMmc/Mp8GZUA82kz/PA S2zAW/qsW4EPAKXErfVuVPt50tzD6R7qY6GFmwI344Gj7bSEkLXJNv5PRvKIbhi6FioH 3bqCWPPjMmTXoTVh33RHKv05+itELpwWJcr4nMPtZ/TrnuGtmdXSOAUxZNhGDlHlOn4b x66HhvO5OxAAHFyARig/YJxQtF6G2OzldT+IlMgoShbiC6gfjbWAJb7a9ZTS9+Xq+8Rg zsBXb9Jkeibb71QehcEJ71QO0yhikSVYcYbNEWZ5GpgAJPUi0dKweyopUJfhjC8li4p2 e14w== X-Gm-Message-State: APjAAAXe7hJ4bCuZwAt9Umxa6IpmgLXX8D9Fs8FQ8qQCjdZ61P2nd2hr FGdrZt+odLqWVsH8EeMRbYLp+g== X-Google-Smtp-Source: APXvYqxwkCdW3hoZGhMouiok1E3s+a9UAP5ShBjMBhUBTUWzHLBGV5I+r7kyAAQ6ox9BpaKt3icvCw== X-Received: by 2002:a17:90a:aa98:: with SMTP id l24mr27995872pjq.96.1571654152956; Mon, 21 Oct 2019 03:35:52 -0700 (PDT) Received: from localhost ([49.248.62.222]) by smtp.gmail.com with ESMTPSA id r30sm15644244pfl.42.2019.10.21.03.35.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 Oct 2019 03:35:52 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, julia.lawall@lip6.fr, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH v6 03/15] drivers: thermal: tsens: Add __func__ identifier to debug statements Date: Mon, 21 Oct 2019 16:05:22 +0530 Message-Id: <18717de35f31098d3ebc12564c2767b6d54d37d8.1571652874.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Printing the function name when enabling debugging makes logs easier to read. Signed-off-by: Amit Kucheria Reviewed-by: Stephen Boyd Reviewed-by: Daniel Lezcano --- drivers/thermal/qcom/tsens-common.c | 8 ++++---- drivers/thermal/qcom/tsens.c | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index c037bdf92c663..7437bfe196e50 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -42,8 +42,8 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *p1, for (i = 0; i < priv->num_sensors; i++) { dev_dbg(priv->dev, - "sensor%d - data_point1:%#x data_point2:%#x\n", - i, p1[i], p2[i]); + "%s: sensor%d - data_point1:%#x data_point2:%#x\n", + __func__, i, p1[i], p2[i]); priv->sensor[i].slope = SLOPE_DEFAULT; if (mode == TWO_PT_CALIB) { @@ -60,7 +60,7 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *p1, priv->sensor[i].offset = (p1[i] * SLOPE_FACTOR) - (CAL_DEGC_PT1 * priv->sensor[i].slope); - dev_dbg(priv->dev, "offset:%d\n", priv->sensor[i].offset); + dev_dbg(priv->dev, "%s: offset:%d\n", __func__, priv->sensor[i].offset); } } @@ -209,7 +209,7 @@ int __init init_common(struct tsens_priv *priv) if (ret) goto err_put_device; if (!enabled) { - dev_err(dev, "tsens device is not enabled\n"); + dev_err(dev, "%s: device not enabled\n", __func__); ret = -ENODEV; goto err_put_device; } diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 542a7f8c3d962..06c6bbd69a1a7 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -127,7 +127,7 @@ static int tsens_probe(struct platform_device *pdev) of_property_read_u32(np, "#qcom,sensors", &num_sensors); if (num_sensors <= 0) { - dev_err(dev, "invalid number of sensors\n"); + dev_err(dev, "%s: invalid number of sensors\n", __func__); return -EINVAL; } @@ -156,7 +156,7 @@ static int tsens_probe(struct platform_device *pdev) ret = priv->ops->init(priv); if (ret < 0) { - dev_err(dev, "tsens init failed\n"); + dev_err(dev, "%s: init failed\n", __func__); return ret; } @@ -164,7 +164,7 @@ static int tsens_probe(struct platform_device *pdev) ret = priv->ops->calibrate(priv); if (ret < 0) { if (ret != -EPROBE_DEFER) - dev_err(dev, "tsens calibration failed\n"); + dev_err(dev, "%s: calibration failed\n", __func__); return ret; } } From patchwork Mon Oct 21 10:35:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11201835 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E1AE31515 for ; Mon, 21 Oct 2019 10:35:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C054B2166E for ; Mon, 21 Oct 2019 10:35:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="vRxWMzYJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728261AbfJUKf6 (ORCPT ); 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Mon, 21 Oct 2019 03:35:56 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, julia.lawall@lip6.fr, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH v6 04/15] drivers: thermal: tsens: Add debugfs support Date: Mon, 21 Oct 2019 16:05:23 +0530 Message-Id: <16e39c1bbfc18b5cf6274620cd72cc63205f53a5.1571652874.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Dump some basic version info and sensor details into debugfs. Example from qcs404 below: --(/sys/kernel/debug) $ ls tsens/ 4a9000.thermal-sensor version --(/sys/kernel/debug) $ cat tsens/version 1.4.0 --(/sys/kernel/debug) $ cat tsens/4a9000.thermal-sensor/sensors max: 11 num: 10 id slope offset ------------------------ 0 3200 404000 1 3200 404000 2 3200 404000 3 3200 404000 4 3200 404000 5 3200 404000 6 3200 404000 7 3200 404000 8 3200 404000 9 3200 404000 Signed-off-by: Amit Kucheria Reviewed-by: Stephen Boyd --- drivers/thermal/qcom/tsens-common.c | 83 +++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.c | 2 + drivers/thermal/qcom/tsens.h | 6 +++ 3 files changed, 91 insertions(+) diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 7437bfe196e50..ea2c46cc6a66a 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -3,6 +3,7 @@ * Copyright (c) 2015, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -139,6 +140,77 @@ int get_temp_common(struct tsens_sensor *s, int *temp) return 0; } +#ifdef CONFIG_DEBUG_FS +static int dbg_sensors_show(struct seq_file *s, void *data) +{ + struct platform_device *pdev = s->private; + struct tsens_priv *priv = platform_get_drvdata(pdev); + int i; + + seq_printf(s, "max: %2d\nnum: %2d\n\n", + priv->feat->max_sensors, priv->num_sensors); + + seq_puts(s, " id slope offset\n--------------------------\n"); + for (i = 0; i < priv->num_sensors; i++) { + seq_printf(s, "%8d %8d %8d\n", priv->sensor[i].hw_id, + priv->sensor[i].slope, priv->sensor[i].offset); + } + + return 0; +} + +static int dbg_version_show(struct seq_file *s, void *data) +{ + struct platform_device *pdev = s->private; + struct tsens_priv *priv = platform_get_drvdata(pdev); + u32 maj_ver, min_ver, step_ver; + int ret; + + if (tsens_ver(priv) > VER_0_1) { + ret = regmap_field_read(priv->rf[VER_MAJOR], &maj_ver); + if (ret) + return ret; + ret = regmap_field_read(priv->rf[VER_MINOR], &min_ver); + if (ret) + return ret; + ret = regmap_field_read(priv->rf[VER_STEP], &step_ver); + if (ret) + return ret; + seq_printf(s, "%d.%d.%d\n", maj_ver, min_ver, step_ver); + } else { + seq_puts(s, "0.1.0\n"); + } + + return 0; +} + +DEFINE_SHOW_ATTRIBUTE(dbg_version); +DEFINE_SHOW_ATTRIBUTE(dbg_sensors); + +static void tsens_debug_init(struct platform_device *pdev) +{ + struct tsens_priv *priv = platform_get_drvdata(pdev); + struct dentry *root, *file; + + root = debugfs_lookup("tsens", NULL); + if (!root) + priv->debug_root = debugfs_create_dir("tsens", NULL); + else + priv->debug_root = root; + + file = debugfs_lookup("version", priv->debug_root); + if (!file) + debugfs_create_file("version", 0444, priv->debug_root, + pdev, &dbg_version_fops); + + /* A directory for each instance of the TSENS IP */ + priv->debug = debugfs_create_dir(dev_name(&pdev->dev), priv->debug_root); + debugfs_create_file("sensors", 0444, priv->debug, pdev, &dbg_sensors_fops); +} +#else +static inline void tsens_debug_init(struct platform_device *pdev) {} +#endif + static const struct regmap_config tsens_config = { .name = "tm", .reg_bits = 32, @@ -199,6 +271,15 @@ int __init init_common(struct tsens_priv *priv) goto err_put_device; } + if (tsens_ver(priv) > VER_0_1) { + for (i = VER_MAJOR; i <= VER_STEP; i++) { + priv->rf[i] = devm_regmap_field_alloc(dev, priv->srot_map, + priv->fields[i]); + if (IS_ERR(priv->rf[i])) + return PTR_ERR(priv->rf[i]); + } + } + priv->rf[TSENS_EN] = devm_regmap_field_alloc(dev, priv->srot_map, priv->fields[TSENS_EN]); if (IS_ERR(priv->rf[TSENS_EN])) { @@ -238,6 +319,8 @@ int __init init_common(struct tsens_priv *priv) } } + tsens_debug_init(op); + return 0; err_put_device: diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 06c6bbd69a1a7..772aa76b50e12 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -3,6 +3,7 @@ * Copyright (c) 2015, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -176,6 +177,7 @@ static int tsens_remove(struct platform_device *pdev) { struct tsens_priv *priv = platform_get_drvdata(pdev); + debugfs_remove_recursive(priv->debug_root); if (priv->ops->disable) priv->ops->disable(priv); diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 84e5447c56860..00899c17e848c 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -293,6 +293,8 @@ struct tsens_context { * @feat: features of the IP * @fields: bitfield locations * @ops: pointer to list of callbacks supported by this device + * @debug_root: pointer to debugfs dentry for all tsens + * @debug: pointer to debugfs dentry for tsens controller * @sensor: list of sensors attached to this device */ struct tsens_priv { @@ -306,6 +308,10 @@ struct tsens_priv { const struct tsens_features *feat; const struct reg_field *fields; const struct tsens_ops *ops; + + struct dentry *debug_root; + struct dentry *debug; + struct tsens_sensor sensor[0]; }; From patchwork Mon Oct 21 10:35:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11201871 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 35CB414E5 for ; Mon, 21 Oct 2019 10:36:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1477220882 for ; Mon, 21 Oct 2019 10:36:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="GB/iNLsV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728263AbfJUKgC (ORCPT ); Mon, 21 Oct 2019 06:36:02 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:39329 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728265AbfJUKgA (ORCPT ); Mon, 21 Oct 2019 06:36:00 -0400 Received: by mail-pf1-f195.google.com with SMTP id v4so8169156pff.6 for ; Mon, 21 Oct 2019 03:36:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=cUh1ZeV5zyjcsg3Iod3jbARGXcyJz+PpaHp2DpcKIvo=; b=GB/iNLsVk+ApucmOndcOCjbvj0CgYAqzijKY5FGCBUbaN+U/kVWyXWHbkpG7BSggYp f6IbuQNNH5x5j+409JsPqM3ZQJarU5yMHogMhB0PyoyaikyLZmvxEEFHMiSBDwnffIZO WpvIzsaXwYEBhjSwBfaeE2vmVUoU73KJFSPVsLn90WenyvhMqiwWhbDif/QJuCDnGWc5 QgXpc2EGiPmug9U5kBGw8Ffwt+Aim18NdbY+U0BbBw/UwfYMUdtjT2C1unkOxVNPrF1x db8UIVOYhkcOd4txq4pUd3AbSig2rXuqT4iyIRnPiEhWEDPRWyMaVBApa3utcJEO4DMQ BXUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=cUh1ZeV5zyjcsg3Iod3jbARGXcyJz+PpaHp2DpcKIvo=; b=dYVMEhHyxEan1I41cl2ma0fOI77yvPABQ4wDBnWrgiBWIBldT6Lnmrk3X4vyDBlgZ4 qGjZ3XVo7X8ZC/bpzLztdpkd2UKRFqgD5bcI7Vfh156ziMuhQppwZI4mLjxm+/hSEr9w WeNK7dAlHy422xUQ35mjyX2GUJj8tT9d4F1ZDDj7aabNSzh/Q1DUL1uHEKTNRPX70gHH 4ojRA8lDN2vFn/hPmZ9uZrMbJ1A3hz/5Zadp4PErvlrwbIXPnGLgbGHF2nTt9mmmoQZY Eeib4HTz+Kdq/lQJKgaUhRUYNZbiQtH9SoW5tDrPvkAxi7hGU5afwwbWDaHswfHPu35u 7Jcg== X-Gm-Message-State: APjAAAVtiifwxM9/wERgaW/1HHj1ROmPLMiK/ffyDuHNusHr8gL8RGow Heh4E1TnhpB3kA3QZX0DvmBJ2g== X-Google-Smtp-Source: APXvYqzu4KtmcnKs1aGYq5s9UfB37tPDNG7pn1yvfavKMydIQjaFEEQUfn6CZX3PmLG1fG1PQEM1CQ== X-Received: by 2002:a63:934d:: with SMTP id w13mr6975734pgm.185.1571654160053; Mon, 21 Oct 2019 03:36:00 -0700 (PDT) Received: from localhost ([49.248.62.222]) by smtp.gmail.com with ESMTPSA id e14sm15420515pgk.70.2019.10.21.03.35.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 Oct 2019 03:35:59 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, julia.lawall@lip6.fr, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: devicetree@vger.kernel.org Subject: [PATCH v6 05/15] arm: dts: msm8974: thermal: Add thermal zones for each sensor Date: Mon, 21 Oct 2019 16:05:24 +0530 Message-Id: <72cc755c16888976edea555f1df60a299daa8a1e.1571652874.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org msm8974 has 11 sensors connected to a single TSENS IP. Define a thermal zone for each of those sensors to expose the temperature of each zone. Signed-off-by: Amit Kucheria Tested-by: Brian Masney Reviewed-by: Stephen Boyd --- arch/arm/boot/dts/qcom-msm8974.dtsi | 90 +++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 369e58f64145d..33c534370fd5c 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -217,6 +217,96 @@ }; }; }; + + q6-dsp-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 1>; + + trips { + q6_dsp_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + modemtx-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 2>; + + trips { + modemtx_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 3>; + + trips { + video_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 4>; + + trips { + wlan_alert0: trip-point0 { + temperature = <105000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + gpu-thermal-top { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 9>; + + trips { + gpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + gpu-thermal-bottom { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 10>; + + trips { + gpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; }; cpu-pmu { From patchwork Mon Oct 21 10:35:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11201837 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DDD8513BD for ; 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Mon, 21 Oct 2019 03:36:03 -0700 (PDT) Received: from localhost ([49.248.62.222]) by smtp.gmail.com with ESMTPSA id y15sm22091643pfp.111.2019.10.21.03.36.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 Oct 2019 03:36:03 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, julia.lawall@lip6.fr, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: devicetree@vger.kernel.org Subject: [PATCH v6 06/15] arm64: dts: msm8916: thermal: Fixup HW ids for cpu sensors Date: Mon, 21 Oct 2019 16:05:25 +0530 Message-Id: <1726fdbf7cf7200ac5dc2a4c811aaee7edc47fd5.1571652874.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org msm8916 uses sensors 0, 1, 2, 4 and 5. Sensor 3 is NOT used. Fixup the device tree so that the correct sensor ID is used and as a result we can actually check the temperature for the cpu2_3 sensor. Signed-off-by: Amit Kucheria Reviewed-by: Daniel Lezcano Reviewed-by: Stephen Boyd --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 5ea9fb8f2f87d..8686e101905cc 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -179,7 +179,7 @@ polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&tsens 4>; + thermal-sensors = <&tsens 5>; trips { cpu0_1_alert0: trip-point@0 { @@ -209,7 +209,7 @@ polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&tsens 3>; + thermal-sensors = <&tsens 4>; trips { cpu2_3_alert0: trip-point@0 { From patchwork Mon Oct 21 10:35:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11201841 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 50C4614E5 for ; Mon, 21 Oct 2019 10:36:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1ABC8217D7 for ; Mon, 21 Oct 2019 10:36:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="LuJceAlT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728290AbfJUKgL (ORCPT ); Mon, 21 Oct 2019 06:36:11 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:37120 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728298AbfJUKgI (ORCPT ); Mon, 21 Oct 2019 06:36:08 -0400 Received: by mail-pf1-f196.google.com with SMTP id y5so8167275pfo.4 for ; Mon, 21 Oct 2019 03:36:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=Y1D9GXv8iFsbyUTQXSk3tQ7he1bQJKyJg/Sy93IDnQw=; b=LuJceAlTyDjs0N0lQ1d6C2rSZI0y9R1ZPC4xAVQ/JuMMFQ27pslP1zgtQNfMVgaI/8 9ZBVChUaUMJJ+hqppareYb5m72AXeMOFYl4DmXifJBBM6LVPf6q7R1/O//NHhwAr161J ucoaBhmxl/QIvLJZ3V+LAViNjknh9OfyPPFEIuK6jFSXjx3m4+cDpchrKFmaLZvrXu74 w6u7FWVCu8Af37t8bbTqdGYMpZPKkgJ5kK33J41K0hDebcLE2hzj09Yiqh7gymOXbBpw qC/cgkbUsG18pGxXZAf0bcu/kponnQPrqaO1fH2F0rWX3x75VXuKMg2+6C7c+/tj9pOY 4eWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=Y1D9GXv8iFsbyUTQXSk3tQ7he1bQJKyJg/Sy93IDnQw=; b=kDE4QSkDRTUAq0MPdrn9pr9NSILrkmiuB8ewolmgHQa/w5NmT/wzEwR5i5bRbvTN8q 3IurkBRXYSEmjnuo7ht1dOt55czESqiOAX5IChiN/PqffsQM8ZSsEtr6o73DcFd4dm7m gYuFH52VQJkBTdzwkBRjZtqr7Ea0dybcitb4zOHmq5YQGj6/Qmo11KEal1JR+iBvgVqk dB++U5WZkcSY+NETzHg6LkgB4bX1qj8KLrrfUlYmODD7woIXNOURqoi1VpBwGR2VdwZg HU8JPnjp9c3xA4TtEzYWusF8rtpBqgSYc1NDPTE18B8vd8hscR47is9MLn6hApRdAzj9 4d6w== X-Gm-Message-State: APjAAAVUF4+ALq9KlhllFbF63BmmITkVGcHRXBnMVb8wzXuDRiabVp+c 2+nGtJtf66S1qrd25Ly4qQxOLs8qk7unoA== X-Google-Smtp-Source: APXvYqzAQS1XkCHFpWgszUyKPETKwnvYtKkjXgee9N+IYe/yKm+9Krr022WM9TQL2v46siir6QUQeA== X-Received: by 2002:a63:c40e:: with SMTP id h14mr24850505pgd.254.1571654167287; Mon, 21 Oct 2019 03:36:07 -0700 (PDT) Received: from localhost ([49.248.62.222]) by smtp.gmail.com with ESMTPSA id p190sm15257278pfb.160.2019.10.21.03.36.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 Oct 2019 03:36:06 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, julia.lawall@lip6.fr, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 07/15] dt-bindings: thermal: tsens: Convert over to a yaml schema Date: Mon, 21 Oct 2019 16:05:26 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Older IP only supports the 'uplow' interrupt, but newer IP supports 'uplow' and 'critical' interrupts. Document interrupt support in the tsens driver by converting over to a YAML schema. Suggested-by: Stephen Boyd Signed-off-by: Amit Kucheria Reviewed-by: Rob Herring --- .../bindings/thermal/qcom-tsens.txt | 55 ------ .../bindings/thermal/qcom-tsens.yaml | 168 ++++++++++++++++++ MAINTAINERS | 1 + 3 files changed, 169 insertions(+), 55 deletions(-) delete mode 100644 Documentation/devicetree/bindings/thermal/qcom-tsens.txt create mode 100644 Documentation/devicetree/bindings/thermal/qcom-tsens.yaml diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt deleted file mode 100644 index 673cc1831ee9d..0000000000000 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt +++ /dev/null @@ -1,55 +0,0 @@ -* QCOM SoC Temperature Sensor (TSENS) - -Required properties: -- compatible: - Must be one of the following: - - "qcom,msm8916-tsens" (MSM8916) - - "qcom,msm8974-tsens" (MSM8974) - - "qcom,msm8996-tsens" (MSM8996) - - "qcom,qcs404-tsens", "qcom,tsens-v1" (QCS404) - - "qcom,msm8998-tsens", "qcom,tsens-v2" (MSM8998) - - "qcom,sdm845-tsens", "qcom,tsens-v2" (SDM845) - The generic "qcom,tsens-v2" property must be used as a fallback for any SoC - with version 2 of the TSENS IP. MSM8996 is the only exception because the - generic property did not exist when support was added. - Similarly, the generic "qcom,tsens-v1" property must be used as a fallback for - any SoC with version 1 of the TSENS IP. - -- reg: Address range of the thermal registers. - New platforms containing v2.x.y of the TSENS IP must specify the SROT and TM - register spaces separately, with order being TM before SROT. - See Example 2, below. - -- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description. -- #qcom,sensors: Number of sensors in tsens block -- Refer to Documentation/devicetree/bindings/nvmem/nvmem.txt to know how to specify -nvmem cells - -Example 1 (legacy support before a fallback tsens-v2 property was introduced): -tsens: thermal-sensor@900000 { - compatible = "qcom,msm8916-tsens"; - reg = <0x4a8000 0x2000>; - nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; - nvmem-cell-names = "caldata", "calsel"; - #thermal-sensor-cells = <1>; - }; - -Example 2 (for any platform containing v2 of the TSENS IP): -tsens0: thermal-sensor@c263000 { - compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; - reg = <0xc263000 0x1ff>, /* TM */ - <0xc222000 0x1ff>; /* SROT */ - #qcom,sensors = <13>; - #thermal-sensor-cells = <1>; - }; - -Example 3 (for any platform containing v1 of the TSENS IP): -tsens: thermal-sensor@4a9000 { - compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; - reg = <0x004a9000 0x1000>, /* TM */ - <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>; - nvmem-cell-names = "calib"; - #qcom,sensors = <10>; - #thermal-sensor-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml new file mode 100644 index 0000000000000..23afc7bf5a44d --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -0,0 +1,168 @@ +# SPDX-License-Identifier: (GPL-2.0 OR MIT) +# Copyright 2019 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QCOM SoC Temperature Sensor (TSENS) + +maintainers: + - Amit Kucheria + +description: | + QCOM SoCs have TSENS IP to allow temperature measurement. There are currently + three distinct major versions of the IP that is supported by a single driver. + The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures + everything before v1 when there was no versioning information. + +properties: + compatible: + oneOf: + - description: v0.1 of TSENS + items: + - enum: + - qcom,msm8916-tsens + - qcom,msm8974-tsens + - const: qcom,tsens-v0_1 + + - description: v1 of TSENS + items: + - enum: + - qcom,qcs404-tsens + - const: qcom,tsens-v1 + + - description: v2 of TSENS + items: + - enum: + - qcom,msm8996-tsens + - qcom,msm8998-tsens + - qcom,sdm845-tsens + - const: qcom,tsens-v2 + + reg: + maxItems: 2 + items: + - description: TM registers + - description: SROT registers + + nvmem-cells: + minItems: 1 + maxItems: 2 + description: + Reference to an nvmem node for the calibration data + + nvmem-cells-names: + minItems: 1 + maxItems: 2 + items: + - enum: + - caldata + - calsel + + "#qcom,sensors": + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 1 + - maximum: 16 + description: + Number of sensors enabled on this platform + + "#thermal-sensor-cells": + const: 1 + description: + Number of cells required to uniquely identify the thermal sensors. Since + we have multiple sensors this is set to 1 + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8916-tsens + - qcom,msm8974-tsens + - qcom,qcs404-tsens + - qcom,tsens-v0_1 + - qcom,tsens-v1 + then: + properties: + interrupts: + items: + - description: Combined interrupt if upper or lower threshold crossed + interrupt-names: + items: + - const: uplow + + else: + properties: + interrupts: + items: + - description: Combined interrupt if upper or lower threshold crossed + - description: Interrupt if critical threshold crossed + interrupt-names: + items: + - const: uplow + - const: critical + +required: + - compatible + - reg + - "#qcom,sensors" + - interrupts + - interrupt-names + - "#thermal-sensor-cells" + +examples: + - | + #include + // Example 1 (legacy: for pre v1 IP): + tsens1: thermal-sensor@900000 { + compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ + + nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; + nvmem-cell-names = "caldata", "calsel"; + + interrupts = ; + interrupt-names = "uplow"; + + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; + + - | + #include + // Example 2 (for any platform containing v1 of the TSENS IP): + tsens2: thermal-sensor@4a9000 { + compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + + nvmem-cells = <&tsens_caldata>; + nvmem-cell-names = "calib"; + + interrupts = ; + interrupt-names = "uplow"; + + #qcom,sensors = <10>; + #thermal-sensor-cells = <1>; + }; + + - | + #include + // Example 3 (for any platform containing v2 of the TSENS IP): + tsens3: thermal-sensor@c263000 { + compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; + reg = <0xc263000 0x1ff>, + <0xc222000 0x1ff>; + + interrupts = , + ; + interrupt-names = "uplow", "critical"; + + #qcom,sensors = <13>; + #thermal-sensor-cells = <1>; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index a69e6db80c79e..c4df814b87b0d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13513,6 +13513,7 @@ L: linux-pm@vger.kernel.org L: linux-arm-msm@vger.kernel.org S: Maintained F: drivers/thermal/qcom/ +F: Documentation/devicetree/bindings/thermal/qcom-tsens.yaml QUALCOMM VENUS VIDEO ACCELERATOR DRIVER M: Stanimir Varbanov From patchwork Mon Oct 21 10:35:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11201843 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AAB8A13BD for ; Mon, 21 Oct 2019 10:36:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 888FE214B2 for ; Mon, 21 Oct 2019 10:36:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="LCE4IgXY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728320AbfJUKgO (ORCPT ); Mon, 21 Oct 2019 06:36:14 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:42060 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728298AbfJUKgL (ORCPT ); Mon, 21 Oct 2019 06:36:11 -0400 Received: by mail-pg1-f195.google.com with SMTP id f14so7538809pgi.9 for ; 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Mon, 21 Oct 2019 03:36:10 -0700 (PDT) Received: from localhost ([49.248.62.222]) by smtp.gmail.com with ESMTPSA id x10sm13478847pgl.53.2019.10.21.03.36.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 Oct 2019 03:36:10 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, julia.lawall@lip6.fr, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: devicetree@vger.kernel.org Subject: [PATCH v6 08/15] arm64: dts: sdm845: thermal: Add interrupt support Date: Mon, 21 Oct 2019 16:05:27 +0530 Message-Id: <5a96df48e546576f90081bbde218e7cff88ae8ce.1571652874.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Register upper-lower interrupts for each of the two tsens controllers. Signed-off-by: Amit Kucheria Reviewed-by: Stephen Boyd --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index f406a4340b05e..0990d5761860a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2950,6 +2950,8 @@ reg = <0 0x0c263000 0 0x1ff>, /* TM */ <0 0x0c222000 0 0x1ff>; /* SROT */ #qcom,sensors = <13>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; @@ -2958,6 +2960,8 @@ reg = <0 0x0c265000 0 0x1ff>, /* TM */ <0 0x0c223000 0 0x1ff>; /* SROT */ #qcom,sensors = <8>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; From patchwork Mon Oct 21 10:35:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11201845 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AE24213BD for ; Mon, 21 Oct 2019 10:36:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8B940214B2 for ; Mon, 21 Oct 2019 10:36:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="BjSuOJtK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728327AbfJUKgQ (ORCPT ); Mon, 21 Oct 2019 06:36:16 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:44429 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728323AbfJUKgP (ORCPT ); Mon, 21 Oct 2019 06:36:15 -0400 Received: by mail-pg1-f196.google.com with SMTP id e10so7540838pgd.11 for ; Mon, 21 Oct 2019 03:36:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=2IiRgiTM6F9vxDGGzT2NtAOpx6JcpVZXk6Y75BALIx4=; b=BjSuOJtK3drQAP8E7EwmzkokCuHGKPJ357gj1CcflWKavwzbuGvGoPsEavjboOpPSn t79OVYbPbAK2TUQ/bbC3InUym6paGm7OZbppRpSb0VzwnLrRkmeoHlX9IN8DtUlpYWU9 Gm3NOAYISoPAFq1TSYaZXr3bjGcnKEgn3UR11mlwYpB9ptJ0QTh2D7iQFOgu5A0IVwp2 vx6q4T/uhXGj9YOwwe5fj3GhV/pt8gViBuzzG0rNT/fJIWhdLBu7251pq0X8/Bor1nG3 RexJMFNN6rxZOoQGNr9x5uc2BXJ3Hv9Ezt68ET2UqG9gXXHd0ChHK2+QPf4rv+cEYAWv 6Eyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=2IiRgiTM6F9vxDGGzT2NtAOpx6JcpVZXk6Y75BALIx4=; b=pGr4kQaDrckkFUNLAm6iiSUNsa457ZmoEdFv5jpu+M1aQ8Wdc+iotmHgu/3C5oys/k YjTO5QAghwGFBhZFy+v+Tzgn5mtR9alCSyKySh76BDrAVb0la2MDk161Lf25s6IaqfL3 vQ7BNoC6vIL2K1JgmFesH6xactlEieQw/Q2eCAoggUkFIuiBNrH0p8qDJAY6LosW0xBQ Lvtnq216eGi1tqfMGuPxURah/dQ56rstyoTPmffKvUno27gKDsyhEWoRGV0MSVt1rQg3 nLgJEoqsGzAtYn+ywj+Cg4U08MtKJdYtkFWlK28MF0KM2YLGX64bMym2ldlvI326ZzrM c90w== X-Gm-Message-State: APjAAAXiIzcG2XCro3VT8E2siOfgQRSgL4eqHQMx6mSq6+1kBczQuHbj VAbQYjNrZc5Oz3LS6Y8WbpM/Jg== X-Google-Smtp-Source: APXvYqw1fEzQjhS+g3UEeDIGHuYnFx7WoBGPaKuPP90vouHu1+lQZ3qQaJbJvcyEOagIJpn0waN5kw== X-Received: by 2002:a63:f743:: with SMTP id f3mr25362784pgk.410.1571654174769; Mon, 21 Oct 2019 03:36:14 -0700 (PDT) Received: from localhost ([49.248.62.222]) by smtp.gmail.com with ESMTPSA id v9sm14754293pfe.109.2019.10.21.03.36.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 Oct 2019 03:36:14 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, julia.lawall@lip6.fr, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: devicetree@vger.kernel.org Subject: [PATCH v6 09/15] arm64: dts: msm8996: thermal: Add interrupt support Date: Mon, 21 Oct 2019 16:05:28 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Register upper-lower interrupts for each of the two tsens controllers. Signed-off-by: Amit Kucheria --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 87f4d9c1b0d4c..4ca2e7b44559c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -591,6 +591,8 @@ reg = <0x4a9000 0x1000>, /* TM */ <0x4a8000 0x1000>; /* SROT */ #qcom,sensors = <13>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; @@ -599,6 +601,8 @@ reg = <0x4ad000 0x1000>, /* TM */ <0x4ac000 0x1000>; /* SROT */ #qcom,sensors = <8>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; From patchwork Mon Oct 21 10:35:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11201869 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A396B1515 for ; Mon, 21 Oct 2019 10:36:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 838C82084C for ; Mon, 21 Oct 2019 10:36:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="m844zhng" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728137AbfJUKgs (ORCPT ); Mon, 21 Oct 2019 06:36:48 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:32800 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728336AbfJUKgT (ORCPT ); Mon, 21 Oct 2019 06:36:19 -0400 Received: by mail-pf1-f194.google.com with SMTP id q10so8193202pfl.0 for ; Mon, 21 Oct 2019 03:36:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=QjsxaA91mEwEtCjMqajdkCWO8TyKKmvK1rye+wLjlGg=; b=m844zhngeP6JmRlLw3Q9yAiYZVqDDiNowu3C0CL8lrG5BXKUahbeMsaww7iO0ty/za fdtGtKxaLgoykDPHWOWk5i6kx0Sh3TN/NUb3L/ijSG3akcBVehElk9CQm8G9cyQyd3N/ r4BKGlQMdEACKR37SKoqApGxIeMST/1CDK/9ExvDKbPmWac8ZF8McT89JAxGLj7cDFYC /XZ5t6W5H7MsMzAASJRW4uZVR4XALG2ulxlNsaUiRdr8UUD0okq0fcUctBMQk/b/N1nC LjvBmWHEXbXx5EvaRbbsjeM5mTYO1VUyNPA2sdiF8G5iaVTOF1plngFLm6+jd6qXYTy6 AEQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=QjsxaA91mEwEtCjMqajdkCWO8TyKKmvK1rye+wLjlGg=; b=W905CNSXukG0T/RiHsUldS98FSRiFxKZi7VdlQDDmjKRZb4jkVXN4WaHMHzdS37riA 2wowlUrHc3osf0Lb4QmnpWwzULk8a0rupE43tr1NsJXK+X/0TAqf8ak3vvqUxwYF5R7X uHdTjm42V/oT+HE5sJYewr+T3k8nWKxD2C02XsvKxCj0atLP8cqZhZbyQZxQCRSmxv6n sHHVSDD3ns8onofKyWiQNLwDj4N8gsmTTbV+m5Zxs0NOcoc1vHx4aFcCcJtk3mI6GVeW cZ6ep2YK06MUIatyCyF8HeeJqjVP56wsdz9tJXKwa+FzKHTygpLNbCpIF8lmz5j2Bjvb skrg== X-Gm-Message-State: APjAAAXOxtBNQVdAO/OldUupwV86luqWINjEltasGX5MMQrQzYzOTuhp 8YzNYaM13qdSLkjuRZYFSqHRHg== X-Google-Smtp-Source: APXvYqy3A8C9r4CuE6DrW3r1dKAtN3bno4gt1UEh08PPn6ctTudHq+Irk12K+SPNnG1bjix7ZB6FyA== X-Received: by 2002:a63:82:: with SMTP id 124mr26253814pga.112.1571654178595; Mon, 21 Oct 2019 03:36:18 -0700 (PDT) Received: from localhost ([49.248.62.222]) by smtp.gmail.com with ESMTPSA id q143sm15543184pfq.103.2019.10.21.03.36.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 Oct 2019 03:36:17 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, julia.lawall@lip6.fr, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: devicetree@vger.kernel.org Subject: [PATCH v6 10/15] arm64: dts: msm8998: thermal: Add interrupt support Date: Mon, 21 Oct 2019 16:05:29 +0530 Message-Id: <2735b57bb1e9477926bfef6f6b8ff84b926f5a1b.1571652874.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Register upper-lower interrupts for each of the two tsens controllers. Signed-off-by: Amit Kucheria --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index c6f81431983ee..489d631a96104 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -816,8 +816,9 @@ compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; reg = <0x010ab000 0x1000>, /* TM */ <0x010aa000 0x1000>; /* SROT */ - #qcom,sensors = <14>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; @@ -825,8 +826,9 @@ compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; reg = <0x010ae000 0x1000>, /* TM */ <0x010ad000 0x1000>; /* SROT */ - #qcom,sensors = <8>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; From patchwork Mon Oct 21 10:35:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11201847 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 244BE14E5 for ; Mon, 21 Oct 2019 10:36:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 02E172173B for ; Mon, 21 Oct 2019 10:36:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="S8Bihem9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727832AbfJUKgY (ORCPT ); Mon, 21 Oct 2019 06:36:24 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:46870 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728361AbfJUKgX (ORCPT ); Mon, 21 Oct 2019 06:36:23 -0400 Received: by mail-pf1-f196.google.com with SMTP id q5so8155929pfg.13 for ; Mon, 21 Oct 2019 03:36:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=vAk0yGeiCW4SKIjJnq+f9xqPKX6m5wwJtivbwF55fLs=; b=S8Bihem9RpDcOyr4KCVSnTKgeUfPM47uXgFRw0WH/pp1ZI/CGMgOaRarY4+jS8r4gS PZpQcWGZJydjFrJx+3/rQeLATVNn+cjQP78gMtCe7O3pARui+qlMs6eRZJgxCjP2i+S9 zexPLrcg0i73kjZjwihN4Bei1fNq1WVTYQ5v0l6Q7AhZjLbA7OTGd6eZNsBQFLIl0P6z MuP6Jc07fhAxSwYpluUMayVoKIkd89LX0INf8iTC0i3POAmGNGI0l9R2lIvdBYXAixEL U7Bfklp9rj0e4JB2/ZjWLoYflbAl246lin6/JZsAc6eGDBUKkoJem52JZkMxarUnsSqw HkQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=vAk0yGeiCW4SKIjJnq+f9xqPKX6m5wwJtivbwF55fLs=; b=tAFHtru6kjSb7qc3an33vvcmoAz7T5c6VsE5fktmSUSI0GQzDqO5FQsvxjWpIFMIKi b4PN2U7D4gaQChxKUe0kuWgIverCgFdD2kLVrF8W4I5pDksazGZcKZdJtgL2eN7kEbSB sQB/0vXiHNsDKO8xt8H7xWDxtB8AAalPZDzsoHrg0eRQkTgFgnV/OirJ01XHz84tN/SX se/0WWbtUAO7kuM6+3EFxGvVIZ/MsFKbKi6dy4mMSvIIhOib/d+Nc6DlQav5gKXq+www lpheiePaznw/PRbikh495t8+IvHgtdJkMDZiiIp1EAizR8asveAkJdihmeIU2Bw+2VM4 uWHw== X-Gm-Message-State: APjAAAXOR+JfQOCRermHGp4Q+ksfKL268gxysM0L0jTXhKiWQu1rS3kr C7tvDMFm7BRoxOjy+rclnwTb5g== X-Google-Smtp-Source: APXvYqw5wwC5YcvuabWh6R87MJJua4G4qRlb7eFz5yGtKtbysUKwbLA8bUKJcPJmbaNuXHSaejJowg== X-Received: by 2002:a63:7d53:: with SMTP id m19mr25458922pgn.450.1571654182214; Mon, 21 Oct 2019 03:36:22 -0700 (PDT) Received: from localhost ([49.248.62.222]) by smtp.gmail.com with ESMTPSA id 19sm14665031pjd.23.2019.10.21.03.36.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 Oct 2019 03:36:21 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, julia.lawall@lip6.fr, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: devicetree@vger.kernel.org Subject: [PATCH v6 11/15] arm64: dts: qcs404: thermal: Add interrupt support Date: Mon, 21 Oct 2019 16:05:30 +0530 Message-Id: <63d6b0b8bba0d217c2f7bb4240c587ead933b6be.1571652874.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Register upper-lower interrupt for the tsens controller. Signed-off-by: Amit Kucheria --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index a97eeb4569c00..b6a4e60739362 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -290,6 +290,8 @@ nvmem-cells = <&tsens_caldata>; nvmem-cell-names = "calib"; #qcom,sensors = <10>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; From patchwork Mon Oct 21 10:35:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11201849 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D50FE14E5 for ; Mon, 21 Oct 2019 10:36:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B4D5F217D7 for ; Mon, 21 Oct 2019 10:36:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="S9EG7QY/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728374AbfJUKg1 (ORCPT ); Mon, 21 Oct 2019 06:36:27 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:40295 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728361AbfJUKg1 (ORCPT ); Mon, 21 Oct 2019 06:36:27 -0400 Received: by mail-pf1-f194.google.com with SMTP id x127so8170613pfb.7 for ; Mon, 21 Oct 2019 03:36:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=iVqqU2LAVSCsGxONMpzjN5OaSzKTS+PP+RlrbsDHeMo=; b=S9EG7QY/ZgkmqHhRziKbvL3c/VYqOHXyxeTbUYe3phmidMNW6VBcGWA5qYT94oVvwV FcDAXIrZHnwKaZPodf4BPLNtpvyHt05p/WPYzzGomf3ic9a1bgRqcT47c3YQX1kTBzTP TPm2ahWz0pTsWGK1/SUEJ7Eq8+CeuaX+8RSWgQaP+HdnHfbZfdDo2skD2ZdD0OnEMidt mKa3+5D7lLpBUC5WYONM+bjVgGtcN/CH+LHb3+baXgPFR+unyWMICbOgLOWfzCi/Od3z +zswnyNg6Q+4KhQqLJbYtWR5WeASo8JWdwRweB759Abf+83GPYHQHcfBc+UQYlQBDpIa FLoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=iVqqU2LAVSCsGxONMpzjN5OaSzKTS+PP+RlrbsDHeMo=; b=UA3CWetVhsV88mufBItN7o77Ua4sTEUBqY7jGm2yIarUOFl53oBoX5uU3HJQGbPCgI HzYl5cY1BLJIpYveADzTsROY2CfUMRV/PWbySNt/ydPjd5mC/RcI2uzJcr7NVGRA3P0y f1FPIzgHuTNnJd8J/Z3D6nvEVMCAFgK4HXZHZNcLvQeP9mLCwFgBNL1d8ayJuqbhqze2 TQlDosxJok3taihSP2fO3+47qYE+MEy3XQOxHD7yhfLv+xVCwhUHdiwkFLGJ73VzdbDR Unvzoe34d1vBy3Q08c7K2rHKlqVOMfkv3LuU9Iqj5PcDr1AT6gEglMB9iTaPvCzQUoH5 14Iw== X-Gm-Message-State: APjAAAUHdsq5juaskrQzNlc2rvN7jCOduOGAWLW920/ZnNffl1Op3l+V H9V59ejleXDY2YDYccR0WJc/BA== X-Google-Smtp-Source: APXvYqzEHGDZ6oIR4ZkTsgaawzrSiWXv0qd13sPs8zKa+jMYleM9/V8ML0gtBkC0Oq7Pc4bCnCZdKw== X-Received: by 2002:a63:cc4a:: with SMTP id q10mr11017952pgi.221.1571654185644; Mon, 21 Oct 2019 03:36:25 -0700 (PDT) Received: from localhost ([49.248.62.222]) by smtp.gmail.com with ESMTPSA id e192sm15379176pfh.83.2019.10.21.03.36.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 Oct 2019 03:36:25 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, julia.lawall@lip6.fr, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: devicetree@vger.kernel.org Subject: [PATCH v6 12/15] arm: dts: msm8974: thermal: Add interrupt support Date: Mon, 21 Oct 2019 16:05:31 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Register upper-lower interrupt for the tsens controller. Signed-off-by: Amit Kucheria Tested-by: Brian Masney --- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 33c534370fd5c..c1a3a7d7161cd 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -531,6 +531,8 @@ nvmem-cells = <&tsens_calib>, <&tsens_backup>; nvmem-cell-names = "calib", "calib_backup"; #qcom,sensors = <11>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; From patchwork Mon Oct 21 10:35:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11201853 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1D30D14E5 for ; Mon, 21 Oct 2019 10:36:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EF8AB214B2 for ; Mon, 21 Oct 2019 10:36:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="dfN7WGSg" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728384AbfJUKga (ORCPT ); Mon, 21 Oct 2019 06:36:30 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:34732 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728385AbfJUKga (ORCPT ); Mon, 21 Oct 2019 06:36:30 -0400 Received: by mail-pf1-f195.google.com with SMTP id b128so8190063pfa.1 for ; Mon, 21 Oct 2019 03:36:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=raRv91SuwpaXlGeT2wU6HLI9/SHJRwKCyqG5FDUj7WM=; b=dfN7WGSgkXXOa/URlH/ad/gRg6gnfjIsMBdB5HASF7KGk6e3vgPOKuBUdrQonzvxbl ZabWSM5RBGxt9NZhV2CYQS7Re/oJH5LHCS76bWGl3dYzeWFKFBemK6203svGG9zzeErK R7SubW3IktLLP9997uvwDu5MDI/8VHhY0dVMH+OBFiRIeKkawfreLDLFufFg++ep0JJu 8aTHfZcuchruuOfibLzKpvpmuCJQOD9bfiZHBFbS7MXOhnnwVBPG41CS9RisyJfs2Dui lLPGF0KkbdVE34XIzLU+DIbaUYZBrC2+83vdWkUscpdsWoFc7H15PLXEPR/klZ1ea5qr NC9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=raRv91SuwpaXlGeT2wU6HLI9/SHJRwKCyqG5FDUj7WM=; b=Sxc8IstMcHS91nBDq194AxROsoST/mmkWocdN/5LAfBU5XAkZF3XP0aIqUE27pwhMd w+fRzKGkL2WYLIV3fOSEcuaMtmIeMItcyVDGa21lnuy+2UdFcpJkVCmWyZhrvUnNPdej b7bsxd+iZHZI+xAJyr0OVeRwBp5VG+r0T5WLrgVSxX/FzuJ4RdzAI7VipdU5JgJuFJKV mSdpG7SMhEqQyTyxb62mp4Avf9k3uG3mPMhqfZa5ZTksQjNzOhiCnfKApXfdFwhGRbES YddLV7merWxD+v/19cgePfpB/Aw78LmdV52u7hnqNj3co/kcp8eGQAgLCKSbE9A4xagN k+DA== X-Gm-Message-State: APjAAAUqcnwN2s6jhRz2dqUenHiDn3KTEN35kyC4akdWrGiKuqQAPT3M CpImn0FxN9889xC/rh7SURntnuzqcJBG1w== X-Google-Smtp-Source: APXvYqwCpYHYXSMroItXhbGj9D6u5ioe8pubcuLdwxrRirA+DapJicFWgsOu+QaSERbHJmDVv7rX+g== X-Received: by 2002:a17:90a:86c7:: with SMTP id y7mr26839634pjv.82.1571654189240; Mon, 21 Oct 2019 03:36:29 -0700 (PDT) Received: from localhost ([49.248.62.222]) by smtp.gmail.com with ESMTPSA id y22sm13192289pjn.12.2019.10.21.03.36.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 Oct 2019 03:36:28 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, julia.lawall@lip6.fr, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: devicetree@vger.kernel.org Subject: [PATCH v6 13/15] arm64: dts: msm8916: thermal: Add interrupt support Date: Mon, 21 Oct 2019 16:05:32 +0530 Message-Id: <88eff964b708c8aff57b24370d2e14389ace09e9.1571652874.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Register upper-lower interrupt for the tsens controller. Signed-off-by: Amit Kucheria --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 8686e101905cc..807f86a4535e0 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -816,6 +816,8 @@ nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; nvmem-cell-names = "calib", "calib_sel"; #qcom,sensors = <5>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; From patchwork Mon Oct 21 10:35:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11201855 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A330F13BD for ; Mon, 21 Oct 2019 10:36:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 81BBC2067B for ; Mon, 21 Oct 2019 10:36:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="BuiQwH1N" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728400AbfJUKge (ORCPT ); Mon, 21 Oct 2019 06:36:34 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:45549 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728396AbfJUKgd (ORCPT ); Mon, 21 Oct 2019 06:36:33 -0400 Received: by mail-pl1-f195.google.com with SMTP id y24so2471820plr.12 for ; Mon, 21 Oct 2019 03:36:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=0WsTUto1EYkvMJZ+e6vQdDqYayMlmhgUas0MuLlp+q8=; b=BuiQwH1NuI9rAQ1fNEk95k5s7p7HCgQHuiuf4lSnqToB9zfnVQdTxIWcYh+AzYJSgi 6DZcFpM5mQXM44D1usVII25lesoY3vJwT6lG85Waj5JbOt1YjwX76iaevWi1k0gnAatK CemNiPO51im7lMFWfCPsXl00qbm4xeNUKbEFuCnTlIQuLYTLTvQBMxhIZl9dteKECikG Zd5tv/df2quGJ+fm4aHBG99HtO8UwW4+HWLe8zO3gHPDaRTEYCsX1+LimJXozZcZ8aiz AOttS8XF14h9IVT+9Rwpb5GOtd62RRHXezu86KXVDqW/xqhsej+GFW/fzWyuCgy9HhB7 2OZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=0WsTUto1EYkvMJZ+e6vQdDqYayMlmhgUas0MuLlp+q8=; b=NuVXa8nN7khxk7yqfqoyVvkmKCwc1wyl5fyoMqa2ESNCmEoP8aMEJ8aVvxqKu49+pJ +M3wXFaohLL/Gl5LPxCia/5h/tllp/1oGnvxymd6paEJ+P/2H701K2vcAMTI3jzywagn l3icEgTv0C/hzrstRVXWCSUBDTF6ZIeF1Syij2m5wVJXBcmS+CmgG+TjkJIAVPqySh4M 1DwHbFs1+zEHBqhEoQ0NG0am4R2RF0QkMf3Hds94PDEJZXd0rWA5UUr9u6vnqadjV9BM rZBmAeKDHjS/8JQCtpvsOnfLCI4YphW6E5yelGgBhpMNgkC3lU8GhSTmXgI4JzJNmW6m pJoA== X-Gm-Message-State: APjAAAWzULt/82TSoC7RozPU7nziZ07PfKtaXFm3tLkLsiBKV+3VBHP8 /UPzUXkp2j5b/LnXabGfQPKOpw== X-Google-Smtp-Source: APXvYqz4qY1pzInsqF+/DLgEGRbW7/FZgMPVWcaEtlgxH519WfQrnOuiWr5pEtx/dCuGz95VNs3wkw== X-Received: by 2002:a17:902:a618:: with SMTP id u24mr23620577plq.112.1571654192631; Mon, 21 Oct 2019 03:36:32 -0700 (PDT) Received: from localhost ([49.248.62.222]) by smtp.gmail.com with ESMTPSA id p36sm6572055pgm.55.2019.10.21.03.36.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 Oct 2019 03:36:32 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, julia.lawall@lip6.fr, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH v6 14/15] drivers: thermal: tsens: Create function to return sign-extended temperature Date: Mon, 21 Oct 2019 16:05:33 +0530 Message-Id: <0689917475cf83b7e01f6978504fd37352a5e3ca.1571652874.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hide the details of how to convert values read from TSENS HW to mCelsius behind a function. All versions of the IP can be supported as a result. Signed-off-by: Amit Kucheria Reviewed-by: Stephen Boyd --- drivers/thermal/qcom/tsens-common.c | 49 ++++++++++++++++++++--------- 1 file changed, 35 insertions(+), 14 deletions(-) diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index ea2c46cc6a66a..c34a1a26ce298 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -84,13 +84,46 @@ static inline int code_to_degc(u32 adc_code, const struct tsens_sensor *s) return degc; } +/** + * tsens_hw_to_mC - Return sign-extended temperature in mCelsius. + * @s: Pointer to sensor struct + * @field: Index into regmap_field array pointing to temperature data + * + * This function handles temperature returned in ADC code or deciCelsius + * depending on IP version. + * + * Return: Temperature in milliCelsius on success, a negative errno will + * be returned in error cases + */ +static int tsens_hw_to_mC(struct tsens_sensor *s, int field) +{ + struct tsens_priv *priv = s->priv; + u32 resolution; + u32 temp = 0; + int ret; + + resolution = priv->fields[LAST_TEMP_0].msb - + priv->fields[LAST_TEMP_0].lsb; + + ret = regmap_field_read(priv->rf[field], &temp); + if (ret) + return ret; + + /* Convert temperature from ADC code to milliCelsius */ + if (priv->feat->adc) + return code_to_degc(temp, s) * 1000; + + /* deciCelsius -> milliCelsius along with sign extension */ + return sign_extend32(temp, resolution) * 100; +} + int get_temp_tsens_valid(struct tsens_sensor *s, int *temp) { struct tsens_priv *priv = s->priv; int hw_id = s->hw_id; u32 temp_idx = LAST_TEMP_0 + hw_id; u32 valid_idx = VALID_0 + hw_id; - u32 last_temp = 0, valid, mask; + u32 valid; int ret; ret = regmap_field_read(priv->rf[valid_idx], &valid); @@ -108,19 +141,7 @@ int get_temp_tsens_valid(struct tsens_sensor *s, int *temp) } /* Valid bit is set, OK to read the temperature */ - ret = regmap_field_read(priv->rf[temp_idx], &last_temp); - if (ret) - return ret; - - if (priv->feat->adc) { - /* Convert temperature from ADC code to milliCelsius */ - *temp = code_to_degc(last_temp, s) * 1000; - } else { - mask = GENMASK(priv->fields[LAST_TEMP_0].msb, - priv->fields[LAST_TEMP_0].lsb); - /* Convert temperature from deciCelsius to milliCelsius */ - *temp = sign_extend32(last_temp, fls(mask) - 1) * 100; - } + *temp = tsens_hw_to_mC(s, temp_idx); return 0; } From patchwork Mon Oct 21 10:35:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 11201861 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 194BE1515 for ; Mon, 21 Oct 2019 10:36:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D927F21906 for ; Mon, 21 Oct 2019 10:36:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="lphZzpU5" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728416AbfJUKgj (ORCPT ); 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Mon, 21 Oct 2019 03:36:36 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, masneyb@onstation.org, swboyd@chromium.org, julia.lawall@lip6.fr, Amit Kucheria , Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH v6 15/15] drivers: thermal: tsens: Add interrupt support Date: Mon, 21 Oct 2019 16:05:34 +0530 Message-Id: <1a93be94efb9779d9305b95992677478f4900ab1.1571652874.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Depending on the IP version, TSENS supports upper, lower and critical threshold interrupts. We only add support for upper and lower threshold interrupts for now. TSENSv2 has an irq [status|clear|mask] bit tuple for each sensor while earlier versions only have a single bit per sensor to denote status and clear. These differences are handled transparently by the interrupt handler. At each interrupt, we reprogram the new upper and lower threshold in the .set_trip callback. Signed-off-by: Amit Kucheria Reviewed-by: Stephen Boyd --- drivers/thermal/qcom/tsens-common.c | 377 ++++++++++++++++++++++++++-- drivers/thermal/qcom/tsens-v0_1.c | 11 + drivers/thermal/qcom/tsens-v1.c | 29 +++ drivers/thermal/qcom/tsens-v2.c | 13 + drivers/thermal/qcom/tsens.c | 32 ++- drivers/thermal/qcom/tsens.h | 270 ++++++++++++++++---- 6 files changed, 669 insertions(+), 63 deletions(-) diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index c34a1a26ce298..03bf1b8133eac 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -13,6 +13,31 @@ #include #include "tsens.h" +/** + * struct tsens_irq_data - IRQ status and temperature violations + * @up_viol: upper threshold violated + * @up_thresh: upper threshold temperature value + * @up_irq_mask: mask register for upper threshold irqs + * @up_irq_clear: clear register for uppper threshold irqs + * @low_viol: lower threshold violated + * @low_thresh: lower threshold temperature value + * @low_irq_mask: mask register for lower threshold irqs + * @low_irq_clear: clear register for lower threshold irqs + * + * Structure containing data about temperature threshold settings and + * irq status if they were violated. + */ +struct tsens_irq_data { + u32 up_viol; + int up_thresh; + u32 up_irq_mask; + u32 up_irq_clear; + u32 low_viol; + int low_thresh; + u32 low_irq_mask; + u32 low_irq_clear; +}; + char *qfprom_read(struct device *dev, const char *cname) { struct nvmem_cell *cell; @@ -65,6 +90,14 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *p1, } } +static inline u32 degc_to_code(int degc, const struct tsens_sensor *s) +{ + u64 code = (degc * s->slope + s->offset) / SLOPE_FACTOR; + + pr_debug("%s: raw_code: 0x%llx, degc:%d\n", __func__, code, degc); + return clamp_val(code, THRESHOLD_MIN_ADC_CODE, THRESHOLD_MAX_ADC_CODE); +} + static inline int code_to_degc(u32 adc_code, const struct tsens_sensor *s) { int degc, num, den; @@ -117,6 +150,313 @@ static int tsens_hw_to_mC(struct tsens_sensor *s, int field) return sign_extend32(temp, resolution) * 100; } +/** + * tsens_mC_to_hw - Convert temperature to hardware register value + * @s: Pointer to sensor struct + * @temp: temperature in milliCelsius to be programmed to hardware + * + * This function outputs the value to be written to hardware in ADC code + * or deciCelsius depending on IP version. + * + * Return: ADC code or temperature in deciCelsius. + */ +static int tsens_mC_to_hw(struct tsens_sensor *s, int temp) +{ + struct tsens_priv *priv = s->priv; + + /* milliC to adc code */ + if (priv->feat->adc) + return degc_to_code(temp / 1000, s); + + /* milliC to deciC */ + return temp / 100; +} + +static inline enum tsens_ver tsens_version(struct tsens_priv *priv) +{ + return priv->feat->ver_major; +} + +static void tsens_set_interrupt_v1(struct tsens_priv *priv, u32 hw_id, + enum tsens_irq_type irq_type, bool enable) +{ + u32 index; + + switch (irq_type) { + case UPPER: + index = UP_INT_CLEAR_0 + hw_id; + break; + case LOWER: + index = LOW_INT_CLEAR_0 + hw_id; + break; + } + regmap_field_write(priv->rf[index], enable ? 0 : 1); +} + +static void tsens_set_interrupt_v2(struct tsens_priv *priv, u32 hw_id, + enum tsens_irq_type irq_type, bool enable) +{ + u32 index_mask, index_clear; + + /* + * To enable the interrupt flag for a sensor: + * - clear the mask bit + * To disable the interrupt flag for a sensor: + * - Mask further interrupts for this sensor + * - Write 1 followed by 0 to clear the interrupt + */ + switch (irq_type) { + case UPPER: + index_mask = UP_INT_MASK_0 + hw_id; + index_clear = UP_INT_CLEAR_0 + hw_id; + break; + case LOWER: + index_mask = LOW_INT_MASK_0 + hw_id; + index_clear = LOW_INT_CLEAR_0 + hw_id; + break; + } + + if (enable) { + regmap_field_write(priv->rf[index_mask], 0); + } else { + regmap_field_write(priv->rf[index_mask], 1); + regmap_field_write(priv->rf[index_clear], 1); + regmap_field_write(priv->rf[index_clear], 0); + } +} + +/** + * tsens_set_interrupt - Set state of an interrupt + * @priv: Pointer to tsens controller private data + * @hw_id: Hardware ID aka. sensor number + * @irq_type: irq_type from enum tsens_irq_type + * @enable: false = disable, true = enable + * + * Call IP-specific function to set state of an interrupt + * + * Return: void + */ +static void tsens_set_interrupt(struct tsens_priv *priv, u32 hw_id, + enum tsens_irq_type irq_type, bool enable) +{ + dev_dbg(priv->dev, "[%u] %s: %s -> %s\n", hw_id, __func__, + irq_type ? ((irq_type == 1) ? "UP" : "CRITICAL") : "LOW", + enable ? "en" : "dis"); + if (tsens_version(priv) > VER_1_X) + tsens_set_interrupt_v2(priv, hw_id, irq_type, enable); + else + tsens_set_interrupt_v1(priv, hw_id, irq_type, enable); +} + +/** + * tsens_threshold_violated - Check if a sensor temperature violated a preset threshold + * @priv: Pointer to tsens controller private data + * @hw_id: Hardware ID aka. sensor number + * @d: Pointer to irq state data + * + * Return: 0 if threshold was not violated, 1 if it was violated and negative + * errno in case of errors + */ +static int tsens_threshold_violated(struct tsens_priv *priv, u32 hw_id, + struct tsens_irq_data *d) +{ + int ret; + + ret = regmap_field_read(priv->rf[UPPER_STATUS_0 + hw_id], &d->up_viol); + if (ret) + return ret; + ret = regmap_field_read(priv->rf[LOWER_STATUS_0 + hw_id], &d->low_viol); + if (ret) + return ret; + if (d->up_viol || d->low_viol) + return 1; + + return 0; +} + +static int tsens_read_irq_state(struct tsens_priv *priv, u32 hw_id, + struct tsens_sensor *s, struct tsens_irq_data *d) +{ + int ret; + + ret = regmap_field_read(priv->rf[UP_INT_CLEAR_0 + hw_id], &d->up_irq_clear); + if (ret) + return ret; + ret = regmap_field_read(priv->rf[LOW_INT_CLEAR_0 + hw_id], &d->low_irq_clear); + if (ret) + return ret; + if (tsens_version(priv) > VER_1_X) { + ret = regmap_field_read(priv->rf[UP_INT_MASK_0 + hw_id], &d->up_irq_mask); + if (ret) + return ret; + ret = regmap_field_read(priv->rf[LOW_INT_MASK_0 + hw_id], &d->low_irq_mask); + if (ret) + return ret; + } else { + /* No mask register on older TSENS */ + d->up_irq_mask = 0; + d->low_irq_mask = 0; + } + + d->up_thresh = tsens_hw_to_mC(s, UP_THRESH_0 + hw_id); + d->low_thresh = tsens_hw_to_mC(s, LOW_THRESH_0 + hw_id); + + dev_dbg(priv->dev, "[%u] %s%s: status(%u|%u) | clr(%u|%u) | mask(%u|%u)\n", + hw_id, __func__, (d->up_viol || d->low_viol) ? "(V)" : "", + d->low_viol, d->up_viol, d->low_irq_clear, d->up_irq_clear, + d->low_irq_mask, d->up_irq_mask); + dev_dbg(priv->dev, "[%u] %s%s: thresh: (%d:%d)\n", hw_id, __func__, + (d->up_viol || d->low_viol) ? "(violation)" : "", + d->low_thresh, d->up_thresh); + + return 0; +} + +static inline u32 masked_irq(u32 hw_id, u32 mask, enum tsens_ver ver) +{ + if (ver > VER_1_X) + return mask & (1 << hw_id); + + /* v1, v0.1 don't have a irq mask register */ + return 0; +} + +/** + * tsens_irq_thread - Threaded interrupt handler for uplow interrupts + * @irq: irq number + * @data: tsens controller private data + * + * Check all sensors to find ones that violated their threshold limits. If the + * temperature is still outside the limits, call thermal_zone_device_update() to + * update the thresholds, else re-enable the interrupts. + * + * The level-triggered interrupt might deassert if the temperature returned to + * within the threshold limits by the time the handler got scheduled. We + * consider the irq to have been handled in that case. + * + * Return: IRQ_HANDLED + */ +irqreturn_t tsens_irq_thread(int irq, void *data) +{ + struct tsens_priv *priv = data; + struct tsens_irq_data d; + bool enable = true, disable = false; + unsigned long flags; + int temp, ret, i; + + for (i = 0; i < priv->num_sensors; i++) { + bool trigger = false; + struct tsens_sensor *s = &priv->sensor[i]; + u32 hw_id = s->hw_id; + + if (IS_ERR(priv->sensor[i].tzd)) + continue; + if (!tsens_threshold_violated(priv, hw_id, &d)) + continue; + ret = get_temp_tsens_valid(s, &temp); + if (ret) { + dev_err(priv->dev, "[%u] %s: error reading sensor\n", hw_id, __func__); + continue; + } + + spin_lock_irqsave(&priv->ul_lock, flags); + + tsens_read_irq_state(priv, hw_id, s, &d); + + if (d.up_viol && + !masked_irq(hw_id, d.up_irq_mask, tsens_version(priv))) { + tsens_set_interrupt(priv, hw_id, UPPER, disable); + if (d.up_thresh > temp) { + dev_dbg(priv->dev, "[%u] %s: re-arm upper\n", + priv->sensor[i].hw_id, __func__); + tsens_set_interrupt(priv, hw_id, UPPER, enable); + } else { + trigger = true; + /* Keep irq masked */ + } + } else if (d.low_viol && + !masked_irq(hw_id, d.low_irq_mask, tsens_version(priv))) { + tsens_set_interrupt(priv, hw_id, LOWER, disable); + if (d.low_thresh < temp) { + dev_dbg(priv->dev, "[%u] %s: re-arm low\n", + priv->sensor[i].hw_id, __func__); + tsens_set_interrupt(priv, hw_id, LOWER, enable); + } else { + trigger = true; + /* Keep irq masked */ + } + } + + spin_unlock_irqrestore(&priv->ul_lock, flags); + + if (trigger) { + dev_dbg(priv->dev, "[%u] %s: TZ update trigger (%d mC)\n", + hw_id, __func__, temp); + thermal_zone_device_update(priv->sensor[i].tzd, + THERMAL_EVENT_UNSPECIFIED); + } else { + dev_dbg(priv->dev, "[%u] %s: no violation: %d\n", + hw_id, __func__, temp); + } + } + + return IRQ_HANDLED; +} + +int tsens_set_trips(void *_sensor, int low, int high) +{ + struct tsens_sensor *s = _sensor; + struct tsens_priv *priv = s->priv; + struct device *dev = priv->dev; + struct tsens_irq_data d; + unsigned long flags; + int high_val, low_val, cl_high, cl_low; + u32 hw_id = s->hw_id; + + dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n", + hw_id, __func__, low, high); + + cl_high = clamp_val(high, -40000, 120000); + cl_low = clamp_val(low, -40000, 120000); + + high_val = tsens_mC_to_hw(s, cl_high); + low_val = tsens_mC_to_hw(s, cl_low); + + spin_lock_irqsave(&priv->ul_lock, flags); + + tsens_read_irq_state(priv, hw_id, s, &d); + + /* Write the new thresholds and clear the status */ + regmap_field_write(priv->rf[LOW_THRESH_0 + hw_id], low_val); + regmap_field_write(priv->rf[UP_THRESH_0 + hw_id], high_val); + tsens_set_interrupt(priv, hw_id, LOWER, true); + tsens_set_interrupt(priv, hw_id, UPPER, true); + + spin_unlock_irqrestore(&priv->ul_lock, flags); + + dev_dbg(dev, "[%u] %s: (%d:%d)->(%d:%d)\n", + s->hw_id, __func__, d.low_thresh, d.up_thresh, cl_low, cl_high); + + return 0; +} + +int tsens_enable_irq(struct tsens_priv *priv) +{ + int ret; + int val = tsens_version(priv) > VER_1_X ? 7 : 1; + + ret = regmap_field_write(priv->rf[INT_EN], val); + if (ret < 0) + dev_err(priv->dev, "%s: failed to enable interrupts\n", __func__); + + return ret; +} + +void tsens_disable_irq(struct tsens_priv *priv) +{ + regmap_field_write(priv->rf[INT_EN], 0); +} + int get_temp_tsens_valid(struct tsens_sensor *s, int *temp) { struct tsens_priv *priv = s->priv; @@ -187,7 +527,7 @@ static int dbg_version_show(struct seq_file *s, void *data) u32 maj_ver, min_ver, step_ver; int ret; - if (tsens_ver(priv) > VER_0_1) { + if (tsens_version(priv) > VER_0_1) { ret = regmap_field_read(priv->rf[VER_MAJOR], &maj_ver); if (ret) return ret; @@ -292,7 +632,7 @@ int __init init_common(struct tsens_priv *priv) goto err_put_device; } - if (tsens_ver(priv) > VER_0_1) { + if (tsens_version(priv) > VER_0_1) { for (i = VER_MAJOR; i <= VER_STEP; i++) { priv->rf[i] = devm_regmap_field_alloc(dev, priv->srot_map, priv->fields[i]); @@ -322,24 +662,29 @@ int __init init_common(struct tsens_priv *priv) ret = PTR_ERR(priv->rf[SENSOR_EN]); goto err_put_device; } - /* now alloc regmap_fields in tm_map */ - for (i = 0, j = LAST_TEMP_0; i < priv->feat->max_sensors; i++, j++) { - priv->rf[j] = devm_regmap_field_alloc(dev, priv->tm_map, - priv->fields[j]); - if (IS_ERR(priv->rf[j])) { - ret = PTR_ERR(priv->rf[j]); - goto err_put_device; - } + priv->rf[INT_EN] = devm_regmap_field_alloc(dev, priv->tm_map, + priv->fields[INT_EN]); + if (IS_ERR(priv->rf[INT_EN])) { + ret = PTR_ERR(priv->rf[INT_EN]); + goto err_put_device; } - for (i = 0, j = VALID_0; i < priv->feat->max_sensors; i++, j++) { - priv->rf[j] = devm_regmap_field_alloc(dev, priv->tm_map, - priv->fields[j]); - if (IS_ERR(priv->rf[j])) { - ret = PTR_ERR(priv->rf[j]); - goto err_put_device; + + /* This loop might need changes if enum regfield_ids is reordered */ + for (j = LAST_TEMP_0; j <= UP_THRESH_15; j += 16) { + for (i = 0; i < priv->feat->max_sensors; i++) { + int idx = j + i; + + priv->rf[idx] = devm_regmap_field_alloc(dev, priv->tm_map, + priv->fields[idx]); + if (IS_ERR(priv->rf[idx])) { + ret = PTR_ERR(priv->rf[idx]); + goto err_put_device; + } } } + spin_lock_init(&priv->ul_lock); + tsens_enable_irq(priv); tsens_debug_init(op); return 0; diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 055647bcee67d..4b8dd6de02ce4 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -347,9 +347,20 @@ static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = { /* INTERRUPT ENABLE */ [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0), + /* UPPER/LOWER TEMPERATURE THRESHOLDS */ + REG_FIELD_FOR_EACH_SENSOR11(LOW_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 0, 9), + REG_FIELD_FOR_EACH_SENSOR11(UP_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 10, 19), + + /* UPPER/LOWER INTERRUPTS [CLEAR/STATUS] */ + REG_FIELD_FOR_EACH_SENSOR11(LOW_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 20, 20), + REG_FIELD_FOR_EACH_SENSOR11(UP_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 21, 21), + + /* NO CRITICAL INTERRUPT SUPPORT on v0.1 */ + /* Sn_STATUS */ REG_FIELD_FOR_EACH_SENSOR11(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 9), /* No VALID field on v0.1 */ + /* xxx_STATUS bits: 1 == threshold violated */ REG_FIELD_FOR_EACH_SENSOR11(MIN_STATUS, TM_Sn_STATUS_OFF, 10, 10), REG_FIELD_FOR_EACH_SENSOR11(LOWER_STATUS, TM_Sn_STATUS_OFF, 11, 11), REG_FIELD_FOR_EACH_SENSOR11(UPPER_STATUS, TM_Sn_STATUS_OFF, 12, 12), diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 870f502f2cb6c..7d33a0c8cd3ec 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -17,6 +17,8 @@ #define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF 0x0004 #define TM_Sn_STATUS_OFF 0x0044 #define TM_TRDY_OFF 0x0084 +#define TM_HIGH_LOW_INT_STATUS_OFF 0x0088 +#define TM_HIGH_LOW_Sn_INT_THRESHOLD_OFF 0x0090 /* eeprom layout data for qcs404/405 (v1) */ #define BASE0_MASK 0x000007f8 @@ -168,9 +170,36 @@ static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { /* INTERRUPT ENABLE */ [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0), + /* UPPER/LOWER TEMPERATURE THRESHOLDS */ + REG_FIELD_FOR_EACH_SENSOR11(LOW_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 0, 9), + REG_FIELD_FOR_EACH_SENSOR11(UP_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 10, 19), + + /* UPPER/LOWER INTERRUPTS [CLEAR/STATUS] */ + REG_FIELD_FOR_EACH_SENSOR11(LOW_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 20, 20), + REG_FIELD_FOR_EACH_SENSOR11(UP_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 21, 21), + [LOW_INT_STATUS_0] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 0, 0), + [LOW_INT_STATUS_1] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 1, 1), + [LOW_INT_STATUS_2] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 2, 2), + [LOW_INT_STATUS_3] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 3, 3), + [LOW_INT_STATUS_4] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 4, 4), + [LOW_INT_STATUS_5] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 5, 5), + [LOW_INT_STATUS_6] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 6, 6), + [LOW_INT_STATUS_7] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 7, 7), + [UP_INT_STATUS_0] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 8, 8), + [UP_INT_STATUS_1] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 9, 9), + [UP_INT_STATUS_2] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 10, 10), + [UP_INT_STATUS_3] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 11, 11), + [UP_INT_STATUS_4] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 12, 12), + [UP_INT_STATUS_5] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 13, 13), + [UP_INT_STATUS_6] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 14, 14), + [UP_INT_STATUS_7] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 15, 15), + + /* NO CRITICAL INTERRUPT SUPPORT on v1 */ + /* Sn_STATUS */ REG_FIELD_FOR_EACH_SENSOR11(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 9), REG_FIELD_FOR_EACH_SENSOR11(VALID, TM_Sn_STATUS_OFF, 14, 14), + /* xxx_STATUS bits: 1 == threshold violated */ REG_FIELD_FOR_EACH_SENSOR11(MIN_STATUS, TM_Sn_STATUS_OFF, 10, 10), REG_FIELD_FOR_EACH_SENSOR11(LOWER_STATUS, TM_Sn_STATUS_OFF, 11, 11), REG_FIELD_FOR_EACH_SENSOR11(UPPER_STATUS, TM_Sn_STATUS_OFF, 12, 12), diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index 0a4f2b8fcab6c..a4d15e1abfddd 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -50,9 +50,22 @@ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { /* v2 has separate enables for UPPER/LOWER/CRITICAL interrupts */ [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 2), + /* TEMPERATURE THRESHOLDS */ + REG_FIELD_FOR_EACH_SENSOR16(LOW_THRESH, TM_Sn_UPPER_LOWER_THRESHOLD_OFF, 0, 11), + REG_FIELD_FOR_EACH_SENSOR16(UP_THRESH, TM_Sn_UPPER_LOWER_THRESHOLD_OFF, 12, 23), + + /* INTERRUPTS [CLEAR/STATUS/MASK] */ + REG_FIELD_SPLIT_BITS_0_15(LOW_INT_STATUS, TM_UPPER_LOWER_INT_STATUS_OFF), + REG_FIELD_SPLIT_BITS_0_15(LOW_INT_CLEAR, TM_UPPER_LOWER_INT_CLEAR_OFF), + REG_FIELD_SPLIT_BITS_0_15(LOW_INT_MASK, TM_UPPER_LOWER_INT_MASK_OFF), + REG_FIELD_SPLIT_BITS_16_31(UP_INT_STATUS, TM_UPPER_LOWER_INT_STATUS_OFF), + REG_FIELD_SPLIT_BITS_16_31(UP_INT_CLEAR, TM_UPPER_LOWER_INT_CLEAR_OFF), + REG_FIELD_SPLIT_BITS_16_31(UP_INT_MASK, TM_UPPER_LOWER_INT_MASK_OFF), + /* Sn_STATUS */ REG_FIELD_FOR_EACH_SENSOR16(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 11), REG_FIELD_FOR_EACH_SENSOR16(VALID, TM_Sn_STATUS_OFF, 21, 21), + /* xxx_STATUS bits: 1 == threshold violated */ REG_FIELD_FOR_EACH_SENSOR16(MIN_STATUS, TM_Sn_STATUS_OFF, 16, 16), REG_FIELD_FOR_EACH_SENSOR16(LOWER_STATUS, TM_Sn_STATUS_OFF, 17, 17), REG_FIELD_FOR_EACH_SENSOR16(UPPER_STATUS, TM_Sn_STATUS_OFF, 18, 18), diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 772aa76b50e12..7d317660211e1 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -78,12 +79,14 @@ MODULE_DEVICE_TABLE(of, tsens_table); static const struct thermal_zone_of_device_ops tsens_of_ops = { .get_temp = tsens_get_temp, .get_trend = tsens_get_trend, + .set_trips = tsens_set_trips, }; static int tsens_register(struct tsens_priv *priv) { - int i; + int i, ret, irq; struct thermal_zone_device *tzd; + struct platform_device *pdev; for (i = 0; i < priv->num_sensors; i++) { priv->sensor[i].priv = priv; @@ -96,7 +99,31 @@ static int tsens_register(struct tsens_priv *priv) if (priv->ops->enable) priv->ops->enable(priv, i); } - return 0; + + pdev = of_find_device_by_node(priv->dev->of_node); + if (!pdev) + return -ENODEV; + + irq = platform_get_irq_byname(pdev, "uplow"); + if (irq < 0) { + ret = irq; + goto err_put_device; + } + + ret = devm_request_threaded_irq(&pdev->dev, irq, + NULL, tsens_irq_thread, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, + dev_name(&pdev->dev), priv); + if (ret) { + dev_err(&pdev->dev, "%s: failed to get irq\n", __func__); + goto err_put_device; + } + + enable_irq_wake(irq); + +err_put_device: + put_device(&pdev->dev); + return ret; } static int tsens_probe(struct platform_device *pdev) @@ -178,6 +205,7 @@ static int tsens_remove(struct platform_device *pdev) struct tsens_priv *priv = platform_get_drvdata(pdev); debugfs_remove_recursive(priv->debug_root); + tsens_disable_irq(priv); if (priv->ops->disable) priv->ops->disable(priv); diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 00899c17e848c..8b20f28c5c512 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -13,8 +13,10 @@ #define CAL_DEGC_PT2 120 #define SLOPE_FACTOR 1000 #define SLOPE_DEFAULT 3200 +#define THRESHOLD_MAX_ADC_CODE 0x3ff +#define THRESHOLD_MIN_ADC_CODE 0x0 - +#include #include #include #include @@ -27,6 +29,11 @@ enum tsens_ver { VER_2_X, }; +enum tsens_irq_type { + LOWER, + UPPER, +}; + /** * struct tsens_sensor - data for each sensor connected to the tsens device * @priv: tsens device instance that this sensor is connected to @@ -100,22 +107,66 @@ struct tsens_ops { [_name##_##14] = REG_FIELD(_offset + 56, _startbit, _stopbit), \ [_name##_##15] = REG_FIELD(_offset + 60, _startbit, _stopbit) -/* reg_field IDs to use as an index into an array */ +#define REG_FIELD_SPLIT_BITS_0_15(_name, _offset) \ + [_name##_##0] = REG_FIELD(_offset, 0, 0), \ + [_name##_##1] = REG_FIELD(_offset, 1, 1), \ + [_name##_##2] = REG_FIELD(_offset, 2, 2), \ + [_name##_##3] = REG_FIELD(_offset, 3, 3), \ + [_name##_##4] = REG_FIELD(_offset, 4, 4), \ + [_name##_##5] = REG_FIELD(_offset, 5, 5), \ + [_name##_##6] = REG_FIELD(_offset, 6, 6), \ + [_name##_##7] = REG_FIELD(_offset, 7, 7), \ + [_name##_##8] = REG_FIELD(_offset, 8, 8), \ + [_name##_##9] = REG_FIELD(_offset, 9, 9), \ + [_name##_##10] = REG_FIELD(_offset, 10, 10), \ + [_name##_##11] = REG_FIELD(_offset, 11, 11), \ + [_name##_##12] = REG_FIELD(_offset, 12, 12), \ + [_name##_##13] = REG_FIELD(_offset, 13, 13), \ + [_name##_##14] = REG_FIELD(_offset, 14, 14), \ + [_name##_##15] = REG_FIELD(_offset, 15, 15) + +#define REG_FIELD_SPLIT_BITS_16_31(_name, _offset) \ + [_name##_##0] = REG_FIELD(_offset, 16, 16), \ + [_name##_##1] = REG_FIELD(_offset, 17, 17), \ + [_name##_##2] = REG_FIELD(_offset, 18, 18), \ + [_name##_##3] = REG_FIELD(_offset, 19, 19), \ + [_name##_##4] = REG_FIELD(_offset, 20, 20), \ + [_name##_##5] = REG_FIELD(_offset, 21, 21), \ + [_name##_##6] = REG_FIELD(_offset, 22, 22), \ + [_name##_##7] = REG_FIELD(_offset, 23, 23), \ + [_name##_##8] = REG_FIELD(_offset, 24, 24), \ + [_name##_##9] = REG_FIELD(_offset, 25, 25), \ + [_name##_##10] = REG_FIELD(_offset, 26, 26), \ + [_name##_##11] = REG_FIELD(_offset, 27, 27), \ + [_name##_##12] = REG_FIELD(_offset, 28, 28), \ + [_name##_##13] = REG_FIELD(_offset, 29, 29), \ + [_name##_##14] = REG_FIELD(_offset, 30, 30), \ + [_name##_##15] = REG_FIELD(_offset, 31, 31) + +/* + * reg_field IDs to use as an index into an array + * If you change the order of the entries, check the devm_regmap_field_alloc() + * calls in init_common() + */ enum regfield_ids { /* ----- SROT ------ */ /* HW_VER */ - VER_MAJOR = 0, + VER_MAJOR, VER_MINOR, VER_STEP, /* CTRL_OFFSET */ - TSENS_EN = 3, + TSENS_EN, TSENS_SW_RST, SENSOR_EN, CODE_OR_TEMP, /* ----- TM ------ */ + /* TRDY */ + TRDY, + /* INTERRUPT ENABLE */ + INT_EN, /* v2+ has separate enables for crit, upper and lower irq */ /* STATUS */ - LAST_TEMP_0 = 7, /* Last temperature reading */ + LAST_TEMP_0, /* Last temperature reading */ LAST_TEMP_1, LAST_TEMP_2, LAST_TEMP_3, @@ -131,7 +182,7 @@ enum regfield_ids { LAST_TEMP_13, LAST_TEMP_14, LAST_TEMP_15, - VALID_0 = 23, /* VALID reading or not */ + VALID_0, /* VALID reading or not */ VALID_1, VALID_2, VALID_3, @@ -147,38 +198,6 @@ enum regfield_ids { VALID_13, VALID_14, VALID_15, - MIN_STATUS_0, /* MIN threshold violated */ - MIN_STATUS_1, - MIN_STATUS_2, - MIN_STATUS_3, - MIN_STATUS_4, - MIN_STATUS_5, - MIN_STATUS_6, - MIN_STATUS_7, - MIN_STATUS_8, - MIN_STATUS_9, - MIN_STATUS_10, - MIN_STATUS_11, - MIN_STATUS_12, - MIN_STATUS_13, - MIN_STATUS_14, - MIN_STATUS_15, - MAX_STATUS_0, /* MAX threshold violated */ - MAX_STATUS_1, - MAX_STATUS_2, - MAX_STATUS_3, - MAX_STATUS_4, - MAX_STATUS_5, - MAX_STATUS_6, - MAX_STATUS_7, - MAX_STATUS_8, - MAX_STATUS_9, - MAX_STATUS_10, - MAX_STATUS_11, - MAX_STATUS_12, - MAX_STATUS_13, - MAX_STATUS_14, - MAX_STATUS_15, LOWER_STATUS_0, /* LOWER threshold violated */ LOWER_STATUS_1, LOWER_STATUS_2, @@ -195,6 +214,70 @@ enum regfield_ids { LOWER_STATUS_13, LOWER_STATUS_14, LOWER_STATUS_15, + LOW_INT_STATUS_0, /* LOWER interrupt status */ + LOW_INT_STATUS_1, + LOW_INT_STATUS_2, + LOW_INT_STATUS_3, + LOW_INT_STATUS_4, + LOW_INT_STATUS_5, + LOW_INT_STATUS_6, + LOW_INT_STATUS_7, + LOW_INT_STATUS_8, + LOW_INT_STATUS_9, + LOW_INT_STATUS_10, + LOW_INT_STATUS_11, + LOW_INT_STATUS_12, + LOW_INT_STATUS_13, + LOW_INT_STATUS_14, + LOW_INT_STATUS_15, + LOW_INT_CLEAR_0, /* LOWER interrupt clear */ + LOW_INT_CLEAR_1, + LOW_INT_CLEAR_2, + LOW_INT_CLEAR_3, + LOW_INT_CLEAR_4, + LOW_INT_CLEAR_5, + LOW_INT_CLEAR_6, + LOW_INT_CLEAR_7, + LOW_INT_CLEAR_8, + LOW_INT_CLEAR_9, + LOW_INT_CLEAR_10, + LOW_INT_CLEAR_11, + LOW_INT_CLEAR_12, + LOW_INT_CLEAR_13, + LOW_INT_CLEAR_14, + LOW_INT_CLEAR_15, + LOW_INT_MASK_0, /* LOWER interrupt mask */ + LOW_INT_MASK_1, + LOW_INT_MASK_2, + LOW_INT_MASK_3, + LOW_INT_MASK_4, + LOW_INT_MASK_5, + LOW_INT_MASK_6, + LOW_INT_MASK_7, + LOW_INT_MASK_8, + LOW_INT_MASK_9, + LOW_INT_MASK_10, + LOW_INT_MASK_11, + LOW_INT_MASK_12, + LOW_INT_MASK_13, + LOW_INT_MASK_14, + LOW_INT_MASK_15, + LOW_THRESH_0, /* LOWER threshold values */ + LOW_THRESH_1, + LOW_THRESH_2, + LOW_THRESH_3, + LOW_THRESH_4, + LOW_THRESH_5, + LOW_THRESH_6, + LOW_THRESH_7, + LOW_THRESH_8, + LOW_THRESH_9, + LOW_THRESH_10, + LOW_THRESH_11, + LOW_THRESH_12, + LOW_THRESH_13, + LOW_THRESH_14, + LOW_THRESH_15, UPPER_STATUS_0, /* UPPER threshold violated */ UPPER_STATUS_1, UPPER_STATUS_2, @@ -211,6 +294,70 @@ enum regfield_ids { UPPER_STATUS_13, UPPER_STATUS_14, UPPER_STATUS_15, + UP_INT_STATUS_0, /* UPPER interrupt status */ + UP_INT_STATUS_1, + UP_INT_STATUS_2, + UP_INT_STATUS_3, + UP_INT_STATUS_4, + UP_INT_STATUS_5, + UP_INT_STATUS_6, + UP_INT_STATUS_7, + UP_INT_STATUS_8, + UP_INT_STATUS_9, + UP_INT_STATUS_10, + UP_INT_STATUS_11, + UP_INT_STATUS_12, + UP_INT_STATUS_13, + UP_INT_STATUS_14, + UP_INT_STATUS_15, + UP_INT_CLEAR_0, /* UPPER interrupt clear */ + UP_INT_CLEAR_1, + UP_INT_CLEAR_2, + UP_INT_CLEAR_3, + UP_INT_CLEAR_4, + UP_INT_CLEAR_5, + UP_INT_CLEAR_6, + UP_INT_CLEAR_7, + UP_INT_CLEAR_8, + UP_INT_CLEAR_9, + UP_INT_CLEAR_10, + UP_INT_CLEAR_11, + UP_INT_CLEAR_12, + UP_INT_CLEAR_13, + UP_INT_CLEAR_14, + UP_INT_CLEAR_15, + UP_INT_MASK_0, /* UPPER interrupt mask */ + UP_INT_MASK_1, + UP_INT_MASK_2, + UP_INT_MASK_3, + UP_INT_MASK_4, + UP_INT_MASK_5, + UP_INT_MASK_6, + UP_INT_MASK_7, + UP_INT_MASK_8, + UP_INT_MASK_9, + UP_INT_MASK_10, + UP_INT_MASK_11, + UP_INT_MASK_12, + UP_INT_MASK_13, + UP_INT_MASK_14, + UP_INT_MASK_15, + UP_THRESH_0, /* UPPER threshold values */ + UP_THRESH_1, + UP_THRESH_2, + UP_THRESH_3, + UP_THRESH_4, + UP_THRESH_5, + UP_THRESH_6, + UP_THRESH_7, + UP_THRESH_8, + UP_THRESH_9, + UP_THRESH_10, + UP_THRESH_11, + UP_THRESH_12, + UP_THRESH_13, + UP_THRESH_14, + UP_THRESH_15, CRITICAL_STATUS_0, /* CRITICAL threshold violated */ CRITICAL_STATUS_1, CRITICAL_STATUS_2, @@ -227,13 +374,38 @@ enum regfield_ids { CRITICAL_STATUS_13, CRITICAL_STATUS_14, CRITICAL_STATUS_15, - /* TRDY */ - TRDY, - /* INTERRUPT ENABLE */ - INT_EN, /* Pre-V1, V1.x */ - LOW_INT_EN, /* V2.x */ - UP_INT_EN, /* V2.x */ - CRIT_INT_EN, /* V2.x */ + MIN_STATUS_0, /* MIN threshold violated */ + MIN_STATUS_1, + MIN_STATUS_2, + MIN_STATUS_3, + MIN_STATUS_4, + MIN_STATUS_5, + MIN_STATUS_6, + MIN_STATUS_7, + MIN_STATUS_8, + MIN_STATUS_9, + MIN_STATUS_10, + MIN_STATUS_11, + MIN_STATUS_12, + MIN_STATUS_13, + MIN_STATUS_14, + MIN_STATUS_15, + MAX_STATUS_0, /* MAX threshold violated */ + MAX_STATUS_1, + MAX_STATUS_2, + MAX_STATUS_3, + MAX_STATUS_4, + MAX_STATUS_5, + MAX_STATUS_6, + MAX_STATUS_7, + MAX_STATUS_8, + MAX_STATUS_9, + MAX_STATUS_10, + MAX_STATUS_11, + MAX_STATUS_12, + MAX_STATUS_13, + MAX_STATUS_14, + MAX_STATUS_15, /* Keep last */ MAX_REGFIELDS @@ -303,6 +475,10 @@ struct tsens_priv { struct regmap *tm_map; struct regmap *srot_map; u32 tm_offset; + + /* lock for upper/lower threshold interrupts */ + spinlock_t ul_lock; + struct regmap_field *rf[MAX_REGFIELDS]; struct tsens_context ctx; const struct tsens_features *feat; @@ -320,6 +496,10 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mo int init_common(struct tsens_priv *priv); int get_temp_tsens_valid(struct tsens_sensor *s, int *temp); int get_temp_common(struct tsens_sensor *s, int *temp); +int tsens_enable_irq(struct tsens_priv *priv); +void tsens_disable_irq(struct tsens_priv *priv); +int tsens_set_trips(void *_sensor, int low, int high); +irqreturn_t tsens_irq_thread(int irq, void *data); /* TSENS target */ extern const struct tsens_plat_data data_8960;