From patchwork Thu Oct 24 13:06:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 11209523 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D61391864 for ; Thu, 24 Oct 2019 13:07:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B493C20663 for ; Thu, 24 Oct 2019 13:07:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="PqkQRrWH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393537AbfJXNHP (ORCPT ); Thu, 24 Oct 2019 09:07:15 -0400 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:39928 "EHLO us-smtp-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2393528AbfJXNHO (ORCPT ); Thu, 24 Oct 2019 09:07:14 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1571922433; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mx2vnlJNR1H+BwVBhLpFkf4hbUqMBk6qNpXvPCTht54=; b=PqkQRrWHlg9djbi9XdY6ZmcAPFnjimUf8xbItOVa+a6LjK/UYwZkb7ISeuHjItEC9unEvP 7FBtkdgEh3zXhdQjLNS4kTSKWfrWq0SxaN1JuSdHMUo1+cnToCakP6XAGf82rxeNiuKFzc cVwuvK5HeCLxefu1rVDY3KEd8JADPow= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-154-WZ_bPr6_Og2X583XrRUEzQ-1; Thu, 24 Oct 2019 09:07:06 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 997031800E00; Thu, 24 Oct 2019 13:07:05 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9237354560; Thu, 24 Oct 2019 13:07:04 +0000 (UTC) From: Andrew Jones To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, Andre Przywara Subject: [PULL 01/10] arm: gic: check_acked: add test description Date: Thu, 24 Oct 2019 15:06:52 +0200 Message-Id: <20191024130701.31238-2-drjones@redhat.com> In-Reply-To: <20191024130701.31238-1-drjones@redhat.com> References: <20191024130701.31238-1-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: WZ_bPr6_Og2X583XrRUEzQ-1 X-Mimecast-Spam-Score: 0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Andre Przywara At the moment the check_acked() IRQ helper function just prints a generic "Completed" or "Timed out" message, without given a more detailed test description. To be able to tell the different IRQ tests apart, and also to allow re-using it more easily, add a "description" parameter string, which is prefixing the output line. This gives more information on what exactly was tested. This also splits the variable output part of the line (duration of IRQ delivery) into a separate INFO: line, to not confuse testing frameworks. Signed-off-by: Andre Przywara Reviewed-by: Andrew Jones Signed-off-by: Andrew Jones --- arm/gic.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/arm/gic.c b/arm/gic.c index ed5642e74f70..2ec4070fbaf9 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -60,7 +60,7 @@ static void stats_reset(void) smp_wmb(); } -static void check_acked(cpumask_t *mask) +static void check_acked(const char *testname, cpumask_t *mask) { int missing = 0, extra = 0, unexpected = 0; int nr_pass, cpu, i; @@ -88,7 +88,9 @@ static void check_acked(cpumask_t *mask) } } if (nr_pass == nr_cpus) { - report("Completed in %d ms", !bad, ++i * 100); + report("%s", !bad, testname); + if (i) + report_info("took more than %d ms", i * 100); return; } } @@ -105,8 +107,9 @@ static void check_acked(cpumask_t *mask) } } - report("Timed-out (5s). ACKS: missing=%d extra=%d unexpected=%d", - false, missing, extra, unexpected); + report("%s", false, testname); + report_info("Timed-out (5s). ACKS: missing=%d extra=%d unexpected=%d", + missing, extra, unexpected); } static void check_spurious(void) @@ -185,7 +188,7 @@ static void ipi_test_self(void) cpumask_clear(&mask); cpumask_set_cpu(smp_processor_id(), &mask); gic->ipi.send_self(); - check_acked(&mask); + check_acked("IPI: self", &mask); report_prefix_pop(); } @@ -200,7 +203,7 @@ static void ipi_test_smp(void) for (i = smp_processor_id() & 1; i < nr_cpus; i += 2) cpumask_clear_cpu(i, &mask); gic_ipi_send_mask(IPI_IRQ, &mask); - check_acked(&mask); + check_acked("IPI: directed", &mask); report_prefix_pop(); report_prefix_push("broadcast"); @@ -208,7 +211,7 @@ static void ipi_test_smp(void) cpumask_copy(&mask, &cpu_present_mask); cpumask_clear_cpu(smp_processor_id(), &mask); gic->ipi.send_broadcast(); - check_acked(&mask); + check_acked("IPI: broadcast", &mask); report_prefix_pop(); } From patchwork Thu Oct 24 13:06:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 11209529 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 78A0B13BD for ; Thu, 24 Oct 2019 13:07:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 580A920663 for ; Thu, 24 Oct 2019 13:07:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="KQnGUrHK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393532AbfJXNHO (ORCPT ); Thu, 24 Oct 2019 09:07:14 -0400 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:55625 "EHLO us-smtp-delivery-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726484AbfJXNHN (ORCPT ); Thu, 24 Oct 2019 09:07:13 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1571922432; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iqMbBKNFFm9xU6vDXXB3AgHKcot1wlVfLwjUAzgtL3A=; b=KQnGUrHKVRJyo7PpFO3BZMhHEmGQyKZ+PxQc1bzYvFUWnKupVWWt6vqnCLsE8s96a1Djq9 Uo7HhLJ2QvupFWf7DTHxqA6VPecFWsX6trvSGh7+Sfg+zhU90pU3iyBsjerZuUBjib/3/A n62Dh6PTgcdirGvXgWkh/b9BAEA/N2M= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-206-QI-8RY-pPf6VPTQLgr-OMQ-1; Thu, 24 Oct 2019 09:07:07 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id DB55280183D; Thu, 24 Oct 2019 13:07:06 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTP id E05E454560; Thu, 24 Oct 2019 13:07:05 +0000 (UTC) From: Andrew Jones To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, Andre Przywara Subject: [PULL 02/10] arm: gic: Split variable output data from test name Date: Thu, 24 Oct 2019 15:06:53 +0200 Message-Id: <20191024130701.31238-3-drjones@redhat.com> In-Reply-To: <20191024130701.31238-1-drjones@redhat.com> References: <20191024130701.31238-1-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: QI-8RY-pPf6VPTQLgr-OMQ-1 X-Mimecast-Spam-Score: 0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Andre Przywara For some tests we mix variable diagnostic output with the test name, which leads to variable test line, confusing some higher level frameworks. Split the output to always use the same test name for a certain test, and put diagnostic output on a separate line using the INFO: tag. Signed-off-by: Andre Przywara Reviewed-by: Andrew Jones Signed-off-by: Andrew Jones --- arm/gic.c | 45 ++++++++++++++++++++++++++------------------- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/arm/gic.c b/arm/gic.c index 2ec4070fbaf9..02d292807c9b 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -353,8 +353,8 @@ static void test_typer_v2(uint32_t reg) { int nr_gic_cpus = ((reg >> 5) & 0x7) + 1; - report("all %d CPUs have interrupts", nr_cpus == nr_gic_cpus, - nr_gic_cpus); + report_info("nr_cpus=%d", nr_cpus); + report("all CPUs have interrupts", nr_cpus == nr_gic_cpus); } #define BYTE(reg32, byte) (((reg32) >> ((byte) * 8)) & 0xff) @@ -370,16 +370,21 @@ static void test_typer_v2(uint32_t reg) static void test_byte_access(void *base_addr, u32 pattern, u32 mask) { u32 reg = readb(base_addr + 1); + bool res; - report("byte reads successful (0x%08x => 0x%02x)", - reg == (BYTE(pattern, 1) & (mask >> 8)), - pattern & mask, reg); + res = (reg == (BYTE(pattern, 1) & (mask >> 8))); + report("byte reads successful", res); + if (!res) + report_info("byte 1 of 0x%08x => 0x%02x", pattern & mask, reg); pattern = REPLACE_BYTE(pattern, 2, 0x1f); writeb(BYTE(pattern, 2), base_addr + 2); reg = readl(base_addr); - report("byte writes successful (0x%02x => 0x%08x)", - reg == (pattern & mask), BYTE(pattern, 2), reg); + res = (reg == (pattern & mask)); + report("byte writes successful", res); + if (!res) + report_info("writing 0x%02x into bytes 2 => 0x%08x", + BYTE(pattern, 2), reg); } static void test_priorities(int nr_irqs, void *priptr) @@ -399,15 +404,16 @@ static void test_priorities(int nr_irqs, void *priptr) pri_mask = readl(first_spi); reg = ~pri_mask; - report("consistent priority masking (0x%08x)", + report("consistent priority masking", (((reg >> 16) == (reg & 0xffff)) && - ((reg & 0xff) == ((reg >> 8) & 0xff))), pri_mask); + ((reg & 0xff) == ((reg >> 8) & 0xff)))); + report_info("priority mask is 0x%08x", pri_mask); reg = reg & 0xff; for (pri_bits = 8; reg & 1; reg >>= 1, pri_bits--) ; - report("implements at least 4 priority bits (%d)", - pri_bits >= 4, pri_bits); + report("implements at least 4 priority bits", pri_bits >= 4); + report_info("%d priority bits implemented", pri_bits); pattern = 0; writel(pattern, first_spi); @@ -452,9 +458,9 @@ static void test_targets(int nr_irqs) /* Check that bits for non implemented CPUs are RAZ/WI. */ if (nr_cpus < 8) { writel(0xffffffff, targetsptr + GIC_FIRST_SPI); - report("bits for %d non-existent CPUs masked", - !(readl(targetsptr + GIC_FIRST_SPI) & ~cpu_mask), - 8 - nr_cpus); + report("bits for non-existent CPUs masked", + !(readl(targetsptr + GIC_FIRST_SPI) & ~cpu_mask)); + report_info("%d non-existent CPUs", 8 - nr_cpus); } else { report_skip("CPU masking (all CPUs implemented)"); } @@ -465,8 +471,10 @@ static void test_targets(int nr_irqs) pattern = 0x0103020f; writel(pattern, targetsptr + GIC_FIRST_SPI); reg = readl(targetsptr + GIC_FIRST_SPI); - report("register content preserved (%08x => %08x)", - reg == (pattern & cpu_mask), pattern & cpu_mask, reg); + report("register content preserved", reg == (pattern & cpu_mask)); + if (reg != (pattern & cpu_mask)) + report_info("writing %08x reads back as %08x", + pattern & cpu_mask, reg); /* The TARGETS registers are byte accessible. */ test_byte_access(targetsptr + GIC_FIRST_SPI, pattern, cpu_mask); @@ -505,9 +513,8 @@ static void gic_test_mmio(void) test_readonly_32(gic_dist_base + GICD_IIDR, false)); reg = readl(idreg); - report("ICPIDR2 is read-only (0x%08x)", - test_readonly_32(idreg, false), - reg); + report("ICPIDR2 is read-only", test_readonly_32(idreg, false)); + report_info("value of ICPIDR2: 0x%08x", reg); test_priorities(nr_irqs, gic_dist_base + GICD_IPRIORITYR); From patchwork Thu Oct 24 13:06:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 11209521 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2E29413BD for ; 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bh=ySh5FzLv3PhiEYiCeAga8oLpZp/gEcCTnNgFcAQ1J1c=; b=g0t+af7f7DQFsJxaidSUBT9rmkZd/YLqE6XaDmoGZMYnXfX+PgFvVDkL67dfJ/OUyUUqWM R3OnP0+DBrYsUIxuCX/PMnYGtzDfrmWO2LoEzteT+HBfcD1tN0KghpJZ6IY5IeunlXYBlw EXlOdqfBgyBtZSaqc6Ndk07fM3pEZBk= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-314-4sc6jEfqNC6G1w1G4tay6w-1; Thu, 24 Oct 2019 09:07:09 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 2CE05801E5F; Thu, 24 Oct 2019 13:07:08 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTP id 2F9715D712; Thu, 24 Oct 2019 13:07:07 +0000 (UTC) From: Andrew Jones To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, Andre Przywara Subject: [PULL 03/10] arm: timer: Split variable output data from test name Date: Thu, 24 Oct 2019 15:06:54 +0200 Message-Id: <20191024130701.31238-4-drjones@redhat.com> In-Reply-To: <20191024130701.31238-1-drjones@redhat.com> References: <20191024130701.31238-1-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: 4sc6jEfqNC6G1w1G4tay6w-1 X-Mimecast-Spam-Score: 0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Andre Przywara For some tests we mix variable diagnostic output with the test name, which leads to variable test line, confusing some higher level frameworks. Split the output to always use the same test name for a certain test, and put diagnostic output on a separate line using the INFO: tag. Signed-off-by: Andre Przywara Reviewed-by: Andrew Jones Signed-off-by: Andrew Jones --- arm/timer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arm/timer.c b/arm/timer.c index f2f60192ba62..0b808d5da9da 100644 --- a/arm/timer.c +++ b/arm/timer.c @@ -249,7 +249,8 @@ static void test_timer(struct timer_info *info) local_irq_enable(); left = info->read_tval(); report("interrupt received after TVAL/WFI", info->irq_received); - report("timer has expired (%d)", left < 0, left); + report("timer has expired", left < 0); + report_info("TVAL is %d ticks", left); } static void test_vtimer(void) From patchwork Thu Oct 24 13:06:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 11209531 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DC5FD112C for ; Thu, 24 Oct 2019 13:07:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BBE352166E for ; Thu, 24 Oct 2019 13:07:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="LGuab+SI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393529AbfJXNHT (ORCPT ); Thu, 24 Oct 2019 09:07:19 -0400 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:35116 "EHLO us-smtp-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2393527AbfJXNHR (ORCPT ); Thu, 24 Oct 2019 09:07:17 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1571922437; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pn1bwJ9+9AINZi93Ccf5bbrwslVAPOtF64W9cwOY830=; b=LGuab+SIL/1TedpsfLvXpyHO/pEHmnod3DpwijUFls6+XUwugDBvCvfGjrCrasQxyrvVzM xsrstqFQ5nk8Us21UCCcCT7yAjgNj+FzBx1qCV1BMQY+Bcdg67ecPC+AKxmFWw6btYPbP7 Z5Lwk81bhD6LOZF5OMAqFECkN0LrANc= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-118-aYeMZeFWNliVRQGCS6-ZIQ-1; Thu, 24 Oct 2019 09:07:10 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 6F7481800E04; Thu, 24 Oct 2019 13:07:09 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTP id 74C855D70E; Thu, 24 Oct 2019 13:07:08 +0000 (UTC) From: Andrew Jones To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, Andre Przywara Subject: [PULL 04/10] arm: selftest: Split variable output data from test name Date: Thu, 24 Oct 2019 15:06:55 +0200 Message-Id: <20191024130701.31238-5-drjones@redhat.com> In-Reply-To: <20191024130701.31238-1-drjones@redhat.com> References: <20191024130701.31238-1-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: aYeMZeFWNliVRQGCS6-ZIQ-1 X-Mimecast-Spam-Score: 0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Andre Przywara For some tests we mix variable diagnostic output with the test name, which leads to variable test line, confusing some higher level frameworks. Split the output to always use the same test name for a certain test, and put diagnostic output on a separate line using the INFO: tag. Signed-off-by: Andre Przywara Reviewed-by: Andrew Jones Signed-off-by: Andrew Jones --- arm/selftest.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arm/selftest.c b/arm/selftest.c index 28a17f7a7531..a0c1ab8180bc 100644 --- a/arm/selftest.c +++ b/arm/selftest.c @@ -43,13 +43,16 @@ static void check_setup(int argc, char **argv) phys_addr_t memsize = PHYS_END - PHYS_OFFSET; phys_addr_t expected = ((phys_addr_t)val)*1024*1024; - report("size = %" PRIu64 " MB", memsize == expected, - memsize/1024/1024); + report("memory size matches expectation", + memsize == expected); + report_info("found %" PRIu64 " MB", memsize/1024/1024); ++nr_tests; } else if (strcmp(argv[i], "smp") == 0) { - report("nr_cpus = %d", nr_cpus == (int)val, nr_cpus); + report("number of CPUs matches expectation", + nr_cpus == (int)val); + report_info("found %d CPUs", nr_cpus); ++nr_tests; } From patchwork Thu Oct 24 13:06:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 11209527 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 27B0613BD for ; Thu, 24 Oct 2019 13:07:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0650F21906 for ; Thu, 24 Oct 2019 13:07:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="R6ZYQmvj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393541AbfJXNHR (ORCPT ); Thu, 24 Oct 2019 09:07:17 -0400 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:27299 "EHLO us-smtp-delivery-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2393527AbfJXNHQ (ORCPT ); Thu, 24 Oct 2019 09:07:16 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1571922435; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=90nJ7SduaEl/Ta4vW3TrQn+5ds5ba8O0P0WMbTveFi0=; b=R6ZYQmvjw9Ywi5lQCu+jUByI9/EO8xyXHdDqi5/Ctvc13EcxfBZNDhsHvYUXh7yd5Rovtw zHfGRMPvpRfhRlUFnX+qGoGgLIOF3u0jy/ipKRzWUW8hsn458CXUx6VhqFyJTzvuyTFi4N xDspu3BZiuQGKSLs0fFj/kM1NWacx0Y= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-134--9aE3u-SM8aHHNzbQEdgUQ-1; Thu, 24 Oct 2019 09:07:11 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id B414E100550E; Thu, 24 Oct 2019 13:07:10 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTP id B8AAE62A66; Thu, 24 Oct 2019 13:07:09 +0000 (UTC) From: Andrew Jones To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, Andre Przywara Subject: [PULL 05/10] arm: selftest: Make MPIDR output stable Date: Thu, 24 Oct 2019 15:06:56 +0200 Message-Id: <20191024130701.31238-6-drjones@redhat.com> In-Reply-To: <20191024130701.31238-1-drjones@redhat.com> References: <20191024130701.31238-1-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: -9aE3u-SM8aHHNzbQEdgUQ-1 X-Mimecast-Spam-Score: 0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Andre Przywara At the moment the smp selftest outputs one line for each vCPU, with the CPU number and its MPIDR printed in the same test result line. For automated test frameworks this has the problem of including variable output in the test name, also the number of tests varies, depending on the number of vCPUs. Fix this by only generating a single line of output for the SMP test, which summarises the result. We use two cpumasks, to let each vCPU report its result and completion of the test (code stolen from the GIC test). For informational purposes we keep the one line per CPU, but prefix it with an INFO: tag, so that frameworks can ignore it. Signed-off-by: Andre Przywara Reviewed-by: Andrew Jones Signed-off-by: Andrew Jones --- arm/selftest.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arm/selftest.c b/arm/selftest.c index a0c1ab8180bc..e9dc5c0cab28 100644 --- a/arm/selftest.c +++ b/arm/selftest.c @@ -17,6 +17,8 @@ #include #include +static cpumask_t ready, valid; + static void __user_psci_system_off(void) { psci_system_off(); @@ -341,8 +343,11 @@ static void cpu_report(void *data __unused) uint64_t mpidr = get_mpidr(); int cpu = smp_processor_id(); - report("CPU(%3d) mpidr=%010" PRIx64, - mpidr_to_cpu(mpidr) == cpu, cpu, mpidr); + if (mpidr_to_cpu(mpidr) == cpu) + cpumask_set_cpu(smp_processor_id(), &valid); + smp_wmb(); /* Paired with rmb in main(). */ + cpumask_set_cpu(smp_processor_id(), &ready); + report_info("CPU%3d: MPIDR=%010" PRIx64, cpu, mpidr); } int main(int argc, char **argv) @@ -371,6 +376,11 @@ int main(int argc, char **argv) report("PSCI version", psci_check()); on_cpus(cpu_report, NULL); + while (!cpumask_full(&ready)) + cpu_relax(); + smp_rmb(); /* Paired with wmb in cpu_report(). */ + report("MPIDR test on all CPUs", cpumask_full(&valid)); + report_info("%d CPUs reported back", nr_cpus); } else { printf("Unknown subtest\n"); From patchwork Thu Oct 24 13:06:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 11209525 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E9BFB112C for ; Thu, 24 Oct 2019 13:07:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C7B1D20659 for ; Thu, 24 Oct 2019 13:07:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="P/5vJLbK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393538AbfJXNHQ (ORCPT ); Thu, 24 Oct 2019 09:07:16 -0400 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:51908 "EHLO us-smtp-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2393536AbfJXNHP (ORCPT ); Thu, 24 Oct 2019 09:07:15 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1571922434; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iriwzjYTJKLukOOoYgMkAJzxOyOd26UcbojrjnQjMwQ=; b=P/5vJLbKoJdeqP7re1oU/QPqujjMzEoGCS1Dkth3Xj50O7ZA0WyCSHFWwr1hmvIBoz6XAH pCJAJ2gUQYpOiCrtOrRoqkNOgeJdpG0KC6NjnvEWa1Iztz0tRmCR+QQrhSEVWeU3QY92su hNgGyNCYxXPUmOBCinFHsCdqIdEUtRE= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-244-0RbiYxizOuynws5Q0-hp4A-1; Thu, 24 Oct 2019 09:07:12 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 08A9A80183D; Thu, 24 Oct 2019 13:07:12 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTP id 07E2562A66; Thu, 24 Oct 2019 13:07:10 +0000 (UTC) From: Andrew Jones To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, Andre Przywara Subject: [PULL 06/10] arm: Add missing test name prefix calls Date: Thu, 24 Oct 2019 15:06:57 +0200 Message-Id: <20191024130701.31238-7-drjones@redhat.com> In-Reply-To: <20191024130701.31238-1-drjones@redhat.com> References: <20191024130701.31238-1-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: 0RbiYxizOuynws5Q0-hp4A-1 X-Mimecast-Spam-Score: 0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Andre Przywara When running the unit tests in TAP mode (./run_tests.sh -t), every single test result is printed. This works fine for most tests which use the reporting prefix feature to indicate the actual test name. However psci and pci were missing those names, so the reporting left people scratching their head what was actually tested: ... ok 74 - invalid-function ok 75 - affinity-info-on ok 76 - affinity-info-off ok 77 - cpu-on Push a "psci" prefix before running those tests to make those report lines more descriptive. While at it, do the same for pci, even though it is less ambigious there. Also the GIC ITARGETSR test was missing a report_prefix_pop(). Signed-off-by: Andre Przywara Reviewed-by: Andrew Jones Signed-off-by: Andrew Jones --- arm/gic.c | 2 ++ arm/pci-test.c | 2 ++ arm/psci.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/arm/gic.c b/arm/gic.c index 02d292807c9b..adb6aa464513 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -480,6 +480,8 @@ static void test_targets(int nr_irqs) test_byte_access(targetsptr + GIC_FIRST_SPI, pattern, cpu_mask); writel(orig_targets, targetsptr + GIC_FIRST_SPI); + + report_prefix_pop(); } static void gic_test_mmio(void) diff --git a/arm/pci-test.c b/arm/pci-test.c index cf128ac1b032..7c3836e5cd63 100644 --- a/arm/pci-test.c +++ b/arm/pci-test.c @@ -19,6 +19,8 @@ int main(void) return report_summary(); } + report_prefix_push("pci"); + pci_print(); ret = pci_testdev(); diff --git a/arm/psci.c b/arm/psci.c index 5cb4d5c7c233..536c9b742033 100644 --- a/arm/psci.c +++ b/arm/psci.c @@ -126,6 +126,8 @@ int main(void) { int ver = psci_invoke(PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0); + report_prefix_push("psci"); + if (nr_cpus < 2) { report_skip("At least 2 cpus required"); goto done; From patchwork Thu Oct 24 13:06:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 11209533 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B908813BD for ; Thu, 24 Oct 2019 13:07:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8AE8920659 for ; Thu, 24 Oct 2019 13:07:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="h/HpqGsg" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393557AbfJXNHU (ORCPT ); Thu, 24 Oct 2019 09:07:20 -0400 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:55737 "EHLO us-smtp-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2393548AbfJXNHS (ORCPT ); Thu, 24 Oct 2019 09:07:18 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1571922438; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zTSzgalkw9qlrrhqQs428qBy292FUf7dpnq5c4qJjf4=; b=h/HpqGsg3jPbyKJghcBqzjPVY4K6RsjM8+ijK78UpVOQ9NLS6d5R9SuaR9/TW5/m1ST5+e dHXSbhjYu02Lnrbsk/ZSAdS8qSkY69BHlQdltly3dr8TINRYIQOkPqAWC9LsS3Mn2ovlMZ D/HWgg48qAOdIRcqYUFQubSu93IFVQc= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-362-2YTHzEIQP1ukgN4dWbdFIA-1; Thu, 24 Oct 2019 09:07:14 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 48D691005512; Thu, 24 Oct 2019 13:07:13 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTP id 4CD815D70E; Thu, 24 Oct 2019 13:07:12 +0000 (UTC) From: Andrew Jones To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, Alexandru Elisei Subject: [PULL 07/10] lib: arm64: Add missing ISB in flush_tlb_page Date: Thu, 24 Oct 2019 15:06:58 +0200 Message-Id: <20191024130701.31238-8-drjones@redhat.com> In-Reply-To: <20191024130701.31238-1-drjones@redhat.com> References: <20191024130701.31238-1-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: 2YTHzEIQP1ukgN4dWbdFIA-1 X-Mimecast-Spam-Score: 0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Alexandru Elisei Linux commit d0b7a302d58a made it abundantly clear that certain CPU implementations require an ISB after a DSB. Add the missing ISB to flush_tlb_page. No changes are required for flush_tlb_all, as the function already had the ISB. Reviewed-by: Andrew Jones Signed-off-by: Alexandru Elisei Signed-off-by: Andrew Jones --- lib/arm64/asm/mmu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/arm64/asm/mmu.h b/lib/arm64/asm/mmu.h index fa554b0c20ae..72d75eafc882 100644 --- a/lib/arm64/asm/mmu.h +++ b/lib/arm64/asm/mmu.h @@ -24,6 +24,7 @@ static inline void flush_tlb_page(unsigned long vaddr) dsb(ishst); asm("tlbi vaae1is, %0" :: "r" (page)); dsb(ish); + isb(); } static inline void flush_dcache_addr(unsigned long vaddr) From patchwork Thu Oct 24 13:06:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 11209537 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 748A0112C for ; Thu, 24 Oct 2019 13:07:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5424E2166E for ; Thu, 24 Oct 2019 13:07:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="iLDLZCpq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2502320AbfJXNH1 (ORCPT ); Thu, 24 Oct 2019 09:07:27 -0400 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:25614 "EHLO us-smtp-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2502289AbfJXNH1 (ORCPT ); Thu, 24 Oct 2019 09:07:27 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1571922446; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=p6Add7eq6f12eyAWq2019g8AK0b1v262zSXSWVC4y7I=; b=iLDLZCpq3XSSyhS5xvlwUt+Z9IxgGBgNyV2plVYY4c56gYb00ZtIwL4m/6MmXs5j8ngqYQ Pc9w9/jsZl04qzK+GaBtKZaB3NXqPBNHGxqQRDM3IZawmUM7AMIDW51PjcADjRNRvIyiFs IWA+HJku8l7b489NWieQPJLRvwvHQyM= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-104-g84IGUXJML-ENdnVB2CdPg-1; Thu, 24 Oct 2019 09:07:17 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id A11325E9; Thu, 24 Oct 2019 13:07:16 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTP id 904E761F27; Thu, 24 Oct 2019 13:07:13 +0000 (UTC) From: Andrew Jones To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, Alexandru Elisei Subject: [PULL 08/10] lib: arm/arm64: Add function to clear the PTE_USER bit Date: Thu, 24 Oct 2019 15:06:59 +0200 Message-Id: <20191024130701.31238-9-drjones@redhat.com> In-Reply-To: <20191024130701.31238-1-drjones@redhat.com> References: <20191024130701.31238-1-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: g84IGUXJML-ENdnVB2CdPg-1 X-Mimecast-Spam-Score: 0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Alexandru Elisei The PTE_USER bit (AP[1]) in a page entry means that lower privilege levels (EL0, on arm64, or PL0, on arm) can read and write from that memory location [1][2]. On arm64, it also implies PXN (Privileged execute-never) when is set [3]. Add a function to clear the bit which we can use when we want to execute code from that page or the prevent access from lower exception levels. Make it available to arm too, in case someone needs it at some point. [1] ARM DDI 0406C.d, Table B3-6 [2] ARM DDI 0487E.a, table D5-28 [3] ARM DDI 0487E.a, table D5-33 Reviewed-by: Andrew Jones Signed-off-by: Alexandru Elisei Signed-off-by: Andrew Jones --- lib/arm/asm/mmu-api.h | 1 + lib/arm/mmu.c | 15 +++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/lib/arm/asm/mmu-api.h b/lib/arm/asm/mmu-api.h index df3ccf7bc7e0..8fe85ba31ec9 100644 --- a/lib/arm/asm/mmu-api.h +++ b/lib/arm/asm/mmu-api.h @@ -22,4 +22,5 @@ extern void mmu_set_range_sect(pgd_t *pgtable, uintptr_t virt_offset, extern void mmu_set_range_ptes(pgd_t *pgtable, uintptr_t virt_offset, phys_addr_t phys_start, phys_addr_t phys_end, pgprot_t prot); +extern void mmu_clear_user(unsigned long vaddr); #endif diff --git a/lib/arm/mmu.c b/lib/arm/mmu.c index 3d38c8397f5a..78db22e6af14 100644 --- a/lib/arm/mmu.c +++ b/lib/arm/mmu.c @@ -217,3 +217,18 @@ unsigned long __phys_to_virt(phys_addr_t addr) assert(!mmu_enabled() || __virt_to_phys(addr) == addr); return addr; } + +void mmu_clear_user(unsigned long vaddr) +{ + pgd_t *pgtable; + pteval_t *pte; + + if (!mmu_enabled()) + return; + + pgtable = current_thread_info()->pgtable; + pte = get_pte(pgtable, vaddr); + + *pte &= ~PTE_USER; + flush_tlb_page(vaddr); +} From patchwork Thu Oct 24 13:07:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 11209535 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 83EC213BD for ; Thu, 24 Oct 2019 13:07:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 59E222166E for ; Thu, 24 Oct 2019 13:07:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="Z4u4yq5O" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2502287AbfJXNHZ (ORCPT ); Thu, 24 Oct 2019 09:07:25 -0400 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:31276 "EHLO us-smtp-1.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2393550AbfJXNHZ (ORCPT ); Thu, 24 Oct 2019 09:07:25 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1571922443; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WKtAWgOxEavjB22GAtw5S7DQVmQPf7uiXWd5oT2CWYM=; b=Z4u4yq5Ovd1JJY/2uLRgScXRQCgbZL+2bHz9IGf8JZ1TvrOp8EzCszQVc6mo/EFYfGQnb1 OCsZFX8JCwKjT9cf8grbkwuh4eP9B06ZqVwkItgYfbbCTWxeuGJcPlr9DrhFzmNEImy6aS DOZrQ8ghaRI31fshPL6ppB4GB3hAcVQ= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-20-9veaiJwKM1WCo7BaMch8aQ-1; Thu, 24 Oct 2019 09:07:21 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 7A6B01800E00; Thu, 24 Oct 2019 13:07:19 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTP id E809261F21; Thu, 24 Oct 2019 13:07:16 +0000 (UTC) From: Andrew Jones To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, Alexandru Elisei Subject: [PULL 09/10] arm64: Add cache code generation test Date: Thu, 24 Oct 2019 15:07:00 +0200 Message-Id: <20191024130701.31238-10-drjones@redhat.com> In-Reply-To: <20191024130701.31238-1-drjones@redhat.com> References: <20191024130701.31238-1-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: 9veaiJwKM1WCo7BaMch8aQ-1 X-Mimecast-Spam-Score: 0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Alexandru Elisei Caches are a misterious creature on arm64, requiring a more hands-on approach from the programmer than on x86. When generating code, two cache maintenance operations are generally required: an invalidation for the stale instruction and a clean to the PoU (Point of Unification) for the new instruction. Fortunately, the ARM architecture has features to alleviate some of this overhead, which are advertised via the IDC and DIC bits in CTR_EL0: if IDC is 1, then the dcache clean is not required, and if DIC is 1, the icache invalidation can be absent. KVM exposes these bits to the guest. Until Linux v4.16.1, KVM performed an icache invalidation each time a stage 2 page was mapped. This was then optimized so that the icache invalidation was performed when the guest tried to execute code from the page for the first time. And that was optimized again when support for the DIC bit was added to KVM. The interactions between a guest that is generating code, the stage 2 tables and the IDC and DIC bits can be subtle, especially when KVM optimizations come into play. Let's add a test that generates a few instructions and checks that KVM indeed honors those bits. Reviewed-by: Andrew Jones Signed-off-by: Alexandru Elisei Signed-off-by: Andrew Jones --- arm/Makefile.arm64 | 1 + arm/cache.c | 122 +++++++++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 6 +++ 3 files changed, 129 insertions(+) create mode 100644 arm/cache.c diff --git a/arm/Makefile.arm64 b/arm/Makefile.arm64 index 35de5ea333b4..6d3dc2c4a464 100644 --- a/arm/Makefile.arm64 +++ b/arm/Makefile.arm64 @@ -25,6 +25,7 @@ OBJDIRS += lib/arm64 # arm64 specific tests tests = $(TEST_DIR)/timer.flat tests += $(TEST_DIR)/micro-bench.flat +tests += $(TEST_DIR)/cache.flat include $(SRCDIR)/$(TEST_DIR)/Makefile.common diff --git a/arm/cache.c b/arm/cache.c new file mode 100644 index 000000000000..2939b85a8c9a --- /dev/null +++ b/arm/cache.c @@ -0,0 +1,122 @@ +#include +#include +#include +#include + +#define NTIMES (1 << 16) + +#define CTR_DIC (1UL << 29) +#define CTR_IDC (1UL << 28) + +#define CLIDR_LOC_SHIFT 24 +#define CLIDR_LOC_MASK (7UL << CLIDR_LOC_SHIFT) +#define CLIDR_LOUU_SHIFT 27 +#define CLIDR_LOUU_MASK (7UL << CLIDR_LOUU_SHIFT) +#define CLIDR_LOUIS_SHIFT 21 +#define CLIDR_LOUIS_MASK (7UL << CLIDR_LOUIS_SHIFT) + +#define RET 0xd65f03c0 +#define MOV_X0(x) (0xd2800000 | (((x) & 0xffff) << 5)) + +#define clean_dcache_pou(addr) \ + asm volatile("dc cvau, %0\n" :: "r" (addr) : "memory") +#define inval_icache_pou(addr) \ + asm volatile("ic ivau, %0\n" :: "r" (addr) : "memory") + +typedef int (*fn_t)(void); + +static inline void prime_icache(u32 *code, u32 insn) +{ + *code = insn; + /* This is the sequence recommended in ARM DDI 0487E.a, page B2-136. */ + clean_dcache_pou(code); + dsb(ish); + inval_icache_pou(code); + dsb(ish); + isb(); + + ((fn_t)code)(); +} + +static void check_code_generation(bool dcache_clean, bool icache_inval) +{ + u32 fn[] = {MOV_X0(0x42), RET}; + u32 *code = alloc_page(); + unsigned long sctlr; + int i, ret; + bool success; + + /* Make sure we can execute from a writable page */ + mmu_clear_user((unsigned long)code); + + sctlr = read_sysreg(sctlr_el1); + if (sctlr & SCTLR_EL1_WXN) { + sctlr &= ~SCTLR_EL1_WXN; + write_sysreg(sctlr, sctlr_el1); + isb(); + /* SCTLR_EL1.WXN is permitted to be cached in a TLB. */ + flush_tlb_all(); + } + + for (i = 0; i < ARRAY_SIZE(fn); i++) { + *(code + i) = fn[i]; + clean_dcache_pou(code + i); + dsb(ish); + inval_icache_pou(code + i); + } + dsb(ish); + isb(); + + /* Sanity check */ + ((fn_t)code)(); + + success = true; + for (i = 0; i < NTIMES; i++) { + prime_icache(code, MOV_X0(0x42)); + *code = MOV_X0(0x66); + if (dcache_clean) + clean_dcache_pou(code); + if (icache_inval) { + if (dcache_clean) + dsb(ish); + inval_icache_pou(code); + } + dsb(ish); + isb(); + + ret = ((fn_t)code)(); + success &= (ret == 0x66); + } + + report("code generation", success); +} + +int main(int argc, char **argv) +{ + u64 ctr, clidr; + bool dcache_clean, icache_inval; + + report_prefix_push("IDC-DIC"); + + ctr = read_sysreg(ctr_el0); + dcache_clean = !(ctr & CTR_IDC); + icache_inval = !(ctr & CTR_DIC); + + if (dcache_clean) { + clidr = read_sysreg(clidr_el1); + if ((clidr & CLIDR_LOC_MASK) == 0) + dcache_clean = false; + if ((clidr & CLIDR_LOUU_MASK) == 0 && + (clidr & CLIDR_LOUIS_MASK) == 0) + dcache_clean = false; + } + + if (dcache_clean) + report_info("dcache clean to PoU required"); + if (icache_inval) + report_info("icache invalidation to PoU required"); + + check_code_generation(dcache_clean, icache_inval); + + return report_summary(); +} diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 6d3df92a4e28..daeb5a09ad39 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -142,3 +142,9 @@ smp = 2 groups = nodefault,micro-bench accel = kvm arch = arm64 + +# Cache emulation tests +[cache] +file = cache.flat +arch = arm64 +groups = cache From patchwork Thu Oct 24 13:07:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 11209541 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 255EF13BD for ; Thu, 24 Oct 2019 13:07:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E549D21928 for ; Thu, 24 Oct 2019 13:07:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="Q7GTwPLY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2502336AbfJXNHx (ORCPT ); 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Thu, 24 Oct 2019 13:07:20 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTP id C29FE5D70E; Thu, 24 Oct 2019 13:07:19 +0000 (UTC) From: Andrew Jones To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, Alexander Graf Subject: [PULL 10/10] arm: Add PL031 test Date: Thu, 24 Oct 2019 15:07:01 +0200 Message-Id: <20191024130701.31238-11-drjones@redhat.com> In-Reply-To: <20191024130701.31238-1-drjones@redhat.com> References: <20191024130701.31238-1-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: 5bqa73AKOvCW58CxXP9b2g-1 X-Mimecast-Spam-Score: 0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Alexander Graf This patch adds a unit test for the PL031 RTC that is used in the virt machine. It just pokes basic functionality. I've mostly written it to familiarize myself with the device, but I suppose having the test around does not hurt, as it also exercises the GIC SPI interrupt path. Signed-off-by: Alexander Graf Reviewed-by: Andrew Jones --- arm/Makefile.common | 1 + arm/pl031.c | 262 ++++++++++++++++++++++++++++++++++++++++++++ lib/arm/asm/gic.h | 1 + 3 files changed, 264 insertions(+) create mode 100644 arm/pl031.c diff --git a/arm/Makefile.common b/arm/Makefile.common index f0c4b5d7620c..b8988f214d3b 100644 --- a/arm/Makefile.common +++ b/arm/Makefile.common @@ -11,6 +11,7 @@ tests-common += $(TEST_DIR)/pmu.flat tests-common += $(TEST_DIR)/gic.flat tests-common += $(TEST_DIR)/psci.flat tests-common += $(TEST_DIR)/sieve.flat +tests-common += $(TEST_DIR)/pl031.flat tests-all = $(tests-common) $(tests) all: directories $(tests-all) diff --git a/arm/pl031.c b/arm/pl031.c new file mode 100644 index 000000000000..5672f36f5fc2 --- /dev/null +++ b/arm/pl031.c @@ -0,0 +1,262 @@ +/* + * Verify PL031 functionality + * + * This test verifies whether the emulated PL031 behaves correctly. + * + * Copyright 2019 Amazon.com, Inc. or its affiliates. + * Author: Alexander Graf + * + * This work is licensed under the terms of the GNU LGPL, version 2. + */ +#include +#include +#include +#include +#include + +struct pl031_regs { + uint32_t dr; /* Data Register */ + uint32_t mr; /* Match Register */ + uint32_t lr; /* Load Register */ + union { + uint8_t cr; /* Control Register */ + uint32_t cr32; + }; + union { + uint8_t imsc; /* Interrupt Mask Set or Clear register */ + uint32_t imsc32; + }; + union { + uint8_t ris; /* Raw Interrupt Status */ + uint32_t ris32; + }; + union { + uint8_t mis; /* Masked Interrupt Status */ + uint32_t mis32; + }; + union { + uint8_t icr; /* Interrupt Clear Register */ + uint32_t icr32; + }; + uint32_t reserved[1008]; + uint32_t periph_id[4]; + uint32_t pcell_id[4]; +}; + +static u32 cntfrq; +static struct pl031_regs *pl031; +static int pl031_irq; +static void *gic_ispendr; +static void *gic_isenabler; +static volatile bool irq_triggered; + +static int check_id(void) +{ + uint32_t id[] = { 0x31, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; + int i; + + for (i = 0; i < ARRAY_SIZE(id); i++) + if (id[i] != readl(&pl031->periph_id[i])) + return 1; + + return 0; +} + +static int check_ro(void) +{ + uint32_t offs[] = { offsetof(struct pl031_regs, ris), + offsetof(struct pl031_regs, mis), + offsetof(struct pl031_regs, periph_id[0]), + offsetof(struct pl031_regs, periph_id[1]), + offsetof(struct pl031_regs, periph_id[2]), + offsetof(struct pl031_regs, periph_id[3]), + offsetof(struct pl031_regs, pcell_id[0]), + offsetof(struct pl031_regs, pcell_id[1]), + offsetof(struct pl031_regs, pcell_id[2]), + offsetof(struct pl031_regs, pcell_id[3]) }; + int i; + + for (i = 0; i < ARRAY_SIZE(offs); i++) { + uint32_t before32; + uint16_t before16; + uint8_t before8; + void *addr = (void*)pl031 + offs[i]; + uint32_t poison = 0xdeadbeefULL; + + before8 = readb(addr); + before16 = readw(addr); + before32 = readl(addr); + + writeb(poison, addr); + writew(poison, addr); + writel(poison, addr); + + if (before8 != readb(addr)) + return 1; + if (before16 != readw(addr)) + return 1; + if (before32 != readl(addr)) + return 1; + } + + return 0; +} + +static int check_rtc_freq(void) +{ + uint32_t seconds_to_wait = 2; + uint32_t before = readl(&pl031->dr); + uint64_t before_tick = get_cntvct(); + uint64_t target_tick = before_tick + (cntfrq * seconds_to_wait); + + /* Wait for 2 seconds */ + while (get_cntvct() < target_tick) ; + + if (readl(&pl031->dr) != before + seconds_to_wait) + return 1; + + return 0; +} + +static bool gic_irq_pending(void) +{ + uint32_t offset = (pl031_irq / 32) * 4; + + return readl(gic_ispendr + offset) & (1 << (pl031_irq & 31)); +} + +static void gic_irq_unmask(void) +{ + uint32_t offset = (pl031_irq / 32) * 4; + + writel(1 << (pl031_irq & 31), gic_isenabler + offset); +} + +static void irq_handler(struct pt_regs *regs) +{ + u32 irqstat = gic_read_iar(); + u32 irqnr = gic_iar_irqnr(irqstat); + + gic_write_eoir(irqstat); + + if (irqnr == pl031_irq) { + report(" RTC RIS == 1", readl(&pl031->ris) == 1); + report(" RTC MIS == 1", readl(&pl031->mis) == 1); + + /* Writing any value should clear IRQ status */ + writel(0x80000000ULL, &pl031->icr); + + report(" RTC RIS == 0", readl(&pl031->ris) == 0); + report(" RTC MIS == 0", readl(&pl031->mis) == 0); + irq_triggered = true; + } else { + report_info("Unexpected interrupt: %d\n", irqnr); + return; + } +} + +static int check_rtc_irq(void) +{ + uint32_t seconds_to_wait = 1; + uint32_t before = readl(&pl031->dr); + uint64_t before_tick = get_cntvct(); + uint64_t target_tick = before_tick + (cntfrq * (seconds_to_wait + 1)); + + report_info("Checking IRQ trigger (MR)"); + + irq_triggered = false; + + /* Fire IRQ in 1 second */ + writel(before + seconds_to_wait, &pl031->mr); + +#ifdef __aarch64__ + install_irq_handler(EL1H_IRQ, irq_handler); +#else + install_exception_handler(EXCPTN_IRQ, irq_handler); +#endif + + /* Wait until 2 seconds are over */ + while (get_cntvct() < target_tick) ; + + report(" RTC IRQ not delivered without mask", !gic_irq_pending()); + + /* Mask the IRQ so that it gets delivered */ + writel(1, &pl031->imsc); + report(" RTC IRQ pending now", gic_irq_pending()); + + /* Enable retrieval of IRQ */ + gic_irq_unmask(); + local_irq_enable(); + + report(" IRQ triggered", irq_triggered); + report(" RTC IRQ not pending anymore", !gic_irq_pending()); + if (!irq_triggered) { + report_info(" RTC RIS: %x", readl(&pl031->ris)); + report_info(" RTC MIS: %x", readl(&pl031->mis)); + report_info(" RTC IMSC: %x", readl(&pl031->imsc)); + report_info(" GIC IRQs pending: %08x %08x", readl(gic_ispendr), readl(gic_ispendr + 4)); + } + + local_irq_disable(); + return 0; +} + +static void rtc_irq_init(void) +{ + gic_enable_defaults(); + + switch (gic_version()) { + case 2: + gic_ispendr = gicv2_dist_base() + GICD_ISPENDR; + gic_isenabler = gicv2_dist_base() + GICD_ISENABLER; + break; + case 3: + gic_ispendr = gicv3_dist_base() + GICD_ISPENDR; + gic_isenabler = gicv3_dist_base() + GICD_ISENABLER; + break; + } +} + +static int rtc_fdt_init(void) +{ + const struct fdt_property *prop; + const void *fdt = dt_fdt(); + struct dt_pbus_reg base; + int node, len; + u32 *data; + int ret; + + node = fdt_node_offset_by_compatible(fdt, -1, "arm,pl031"); + if (node < 0) + return -1; + + prop = fdt_get_property(fdt, node, "interrupts", &len); + assert(prop && len == (3 * sizeof(u32))); + data = (u32 *)prop->data; + assert(data[0] == 0); /* SPI */ + pl031_irq = SPI(fdt32_to_cpu(data[1])); + + ret = dt_pbus_translate_node(node, 0, &base); + assert(!ret); + pl031 = ioremap(base.addr, base.size); + + return 0; +} + +int main(int argc, char **argv) +{ + cntfrq = get_cntfrq(); + rtc_irq_init(); + if (rtc_fdt_init()) { + report_skip("Skipping PL031 tests. No device present."); + return 0; + } + + report("Periph/PCell IDs match", !check_id()); + report("R/O fields are R/O", !check_ro()); + report("RTC ticks at 1HZ", !check_rtc_freq()); + report("RTC IRQ not pending yet", !gic_irq_pending()); + check_rtc_irq(); + + return report_summary(); +} diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h index f6dfb907a7d5..1fc10a096259 100644 --- a/lib/arm/asm/gic.h +++ b/lib/arm/asm/gic.h @@ -41,6 +41,7 @@ #include #define PPI(irq) ((irq) + 16) +#define SPI(irq) ((irq) + GIC_FIRST_SPI) #ifndef __ASSEMBLY__ #include